Beamformer integrated circuit, wireless communication device, and inspection system

Abstract

To provide a beamformer integrated circuit, a wireless communication device, and an inspection system that can perform inspection without increasing time and cost even when a plurality of memories are provided.SOLUTION: A beamformer integrated circuit includes a plurality of memories 13 that store setting values of at least one of the phase and intensity of signals supplied to a plurality of antenna elements or signals supplied from the plurality of antenna elements, and a determination circuit 73 that determines whether values simultaneously read out from specific addresses of the plurality of memories 13 all match.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a beamformer integrated circuit, a wireless communication device, and a test system. [Background technology]

[0002] In recent years, wireless communication using high-frequency signals such as millimeter waves, quasi-millimeter waves, and microwaves has been attracting attention. In particular, in wireless communication using high-frequency signals with frequencies higher than the quasi-millimeter wave band, beamforming is required because the directionality of radio waves increases. A wireless communication device that performs beamforming is equipped with a phased array antenna module having multiple antenna elements and a beamformer integrated circuit.

[0003] The beamformer integrated circuit includes a plurality of phase controllers corresponding to a plurality of antenna elements, a memory that stores phase setting values ​​to be set in the plurality of phase controllers, and a setting circuit that reads the setting values ​​stored in the memory and sets them in the phase controller. In addition, the beamformer integrated circuit may also have intensity controllers corresponding to a plurality of antenna elements. In such a case, the intensity setting value to be set in the intensity controller is also stored in the memory. A required beam pattern is formed by setting appropriate setting values ​​in the phase controller and intensity controller and adjusting the phases and intensities of a plurality of signals supplied from (or to) a plurality of antenna elements. Patent Document 1 below discloses an example of a conventional phased array antenna module. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-212947 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, the above-mentioned inspection of the beamformer integrated circuit is often performed by writing a predetermined value into the memory of the beamformer integrated circuit and checking whether the value read from the memory matches the value written into the memory. If the beamformer integrated circuit is provided with multiple memories, the above-mentioned inspection must be repeated for each memory, which increases the time and cost required for the inspection.

[0006] The present invention has been made in consideration of the above circumstances, and aims to provide a beamformer integrated circuit, a wireless communication device, and an inspection system that can perform inspection without increasing time and cost even when multiple memories are provided. [Means for solving the problem]

[0007] In order to solve the above problems, a beamformer integrated circuit (10) according to a first aspect of the present invention comprises a plurality of memories (13) for storing setting values ​​of at least one of the phase and intensity of signals supplied to a plurality of antenna elements (21) or signals supplied from the plurality of antenna elements, and a judgment circuit (73) for judging whether values ​​simultaneously read out from specific addresses of the plurality of memories all match.

[0008] In the beamformer integrated circuit according to the first aspect of the present invention, a judgment circuit judges whether values ​​simultaneously read from specific addresses of multiple memories all match, thereby enabling testing to be performed without increasing time and cost compared to testing multiple memories sequentially.

[0009] A beamformer integrated circuit according to a second aspect of the present invention is a beamformer integrated circuit according to the first aspect of the present invention, further comprising a switching circuit (75) that switches between outputting the decision result of the decision circuit to the outside, or outputting one of the values ​​simultaneously read out from specific addresses of the plurality of memories to the outside.

[0010] A beamformer integrated circuit according to a third aspect of the present invention is a beamformer integrated circuit according to the second aspect of the present invention, further comprising a selection circuit (76) which selects which of the values ​​simultaneously read out from specific addresses of the plurality of memories is to be output to the outside when the switching circuit is switched to outputting one of the values ​​simultaneously read out from specific addresses of the plurality of memories to the outside.

[0011] A beamformer integrated circuit according to a fourth aspect of the present invention is a beamformer integrated circuit according to any one of the first to third aspects of the present invention, comprising a first register (71) for holding values ​​to be written simultaneously to a plurality of the memories, and a second register (72) for holding the specific address for simultaneously writing to or reading from the plurality of the memories.

[0012] A wireless communication device (A) according to a first aspect of the present invention comprises a plurality of antenna elements (21) and a beamformer integrated circuit according to any one of the first to fourth aspects of the present invention that controls at least one of the phase and intensity of signals supplied to the plurality of antenna elements or signals supplied from the plurality of antenna elements using setting values ​​stored in the memory.

[0013] A wireless communication device (A) according to a second aspect of the present invention comprises a plurality of antenna elements (21), a beamformer integrated circuit according to a third aspect of the present invention, and a control device (2) that controls the switching circuit and the selection circuit so that the values ​​simultaneously read from specific addresses of the plurality of memories are sequentially output to the outside when the judgment result of the judgment circuit indicates that the values ​​simultaneously read from specific addresses of the plurality of memories do not all match.

[0014] An inspection system (IS) according to one aspect of the present invention is an inspection system for inspecting a beamformer integrated circuit according to the third aspect of the present invention, and includes a control device (100) that controls the switching circuit and the selection circuit so that the values ​​simultaneously read out from specific addresses of the multiple memories are sequentially output to the inspection system when the judgment result of the judgment circuit indicates that the values ​​simultaneously read out from specific addresses of the multiple memories do not all match. Effect of the Invention

[0015] According to the present invention, even if a plurality of memories are provided, it is possible to carry out an inspection without increasing time and cost. [Brief description of the drawings]

[0016] [Figure 1] 1 is a block diagram showing a configuration of a main part of a wireless communication device according to a first embodiment of the present invention. [Diagram 2] 1 is a block diagram showing a configuration of a main part of a beamformer integrated circuit according to a first embodiment of the present invention. [Diagram 3] 2 is a block diagram showing a configuration of a main part of an analog circuit section provided in the RF front end of a beamformer IC. FIG. [Figure 4] 1 is a block diagram showing a configuration of a main part of a test circuit used for testing a beamformer integrated circuit according to a first embodiment of the present invention. FIG. [Diagram 5] FIG. 11 is a block diagram showing the configuration of a main part of a test circuit used to test a beamformer integrated circuit according to a second embodiment of the present invention. [Figure 6] FIG. 11 is a block diagram showing the configuration of a main part of a test circuit used for testing a beamformer integrated circuit according to a third embodiment of the present invention. [Figure 7] 1 is a block diagram showing a configuration of a main part of an inspection system according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, a beamformer integrated circuit, a wireless communication device, and an inspection system according to embodiments of the present invention will be described in detail with reference to the drawings.

[0018] [First embodiment] <Wireless Communication Device> Fig. 1 is a block diagram showing the configuration of the main parts of a wireless communication device according to a first embodiment of the present invention. As shown in Fig. 1, a wireless communication device A of this embodiment includes a phased array antenna module 1 and a control device 2. Such a wireless communication device A performs wireless communication using, for example, a millimeter wave band, and is capable of beamforming that can freely change the beam pattern.

[0019] Phased array antenna module The phased array antenna module 1 has, for example, a plurality of ICs (Integrated Circuits) mounted on one side of a substrate such as a known printed circuit board, and an antenna array mounted on the other side. The plurality of ICs and the antenna array constituting the phased array antenna module are formed by using known materials and by using known methods.

[0020] As shown in Fig. 1, the phased array antenna module 1 includes eight beamformer ICs 10A-10H, an antenna array 20, and a frequency conversion IC 30. The phased array antenna module 1 is connected to a control device 2 via a signal line L1 and a control line L2. An RF signal at an IF (intermediate frequency) signal frequency is transmitted and received between the control device 2 and the phased array antenna module 1 via the signal line L1. A communication message related to control is transmitted and received between the control device 2 and the phased array antenna module 1 via the control line L2. Power is supplied from the control device 2 to the phased array antenna module 1 via a power line (not shown).

[0021] The beamformer ICs 10A to 10H (beamformer integrated circuits) are ICs that control the beam pattern of the antenna array 20. A plurality of antenna elements 21 that constitute the antenna array 20 are connected to each of the beamformer ICs 10A to 10H. For example, eight antenna elements 21 for horizontal polarization and eight antenna elements 21 for vertical polarization are connected to each of the beamformer ICs 10A to 10H. That is, the antenna array 20 is composed of a total of 128 antenna elements 21, including 64 antenna elements 21 for horizontal polarization and 64 antenna elements 21 for vertical polarization. The beamformer ICs 10A to 10H will be described in detail later.

[0022] The frequency conversion IC 30 is an IC that performs frequency conversion between an RF signal of an IF signal frequency and an RF signal of a frequency transmitted and received by the beamformer ICs 10A-10H and the antenna array 20. The frequency conversion IC 30 is connected to the beamformer ICs 10A-10H. Therefore, the RF signal output from the frequency conversion IC 30 is distributed to each of the beamformer ICs 10A-10H. In addition, the RF signals received by each of the beamformer ICs 10A-10H are combined and input to the frequency conversion IC 30.

[0023] <Beamformer Integrated Circuit> 2 is a block diagram showing the main configuration of a beamformer integrated circuit according to a first embodiment of the present invention. The eight beamformer ICs 10A-10H have the same configuration. Therefore, in the following description, only one of the beamformer ICs 10A-10H, i.e., the beamformer IC 10, may be described. Descriptions of the other seven beamformer ICs may be omitted.

[0024] The beamformer IC 10 includes 16 RF front ends 5A to 5P and a digital circuit 6. The 16 RF front ends 5A to 5P have the same configuration. Therefore, in the following description, one of the 16 RF front ends 5A to 5P, i.e., the RF front end 5, may be described. Descriptions of the other 15 RF front ends may be omitted.

[0025] 2, each of the 16 RF front-ends 5A-5P is connected to each of the 16 antenna elements 21A-21P such that there is a one-to-one correspondence between one antenna element 21 and one RF front-end 5. Of the 16 antenna elements 21A-21P, eight antenna elements (e.g., antenna elements 21A-21H) are antenna elements for horizontal polarization, and the remaining eight antenna elements (e.g., antenna elements 21I-21P) are antenna elements for vertical polarization.

[0026] The 16 antenna elements 21A-21P have the same or similar configurations. Therefore, in the following description, one of the 16 antenna elements 21A-21P, i.e., antenna element 21, may be described. Description of the other 15 antenna elements may be omitted. The antenna elements 21A-21P may have the same configurations. Regarding the configurations of the antenna elements 21A-21P, the configuration of the antenna element for horizontal polarization and the configuration of the antenna element for vertical polarization may be slightly different.

[0027] In this way, in one beamformer IC 10, the 16 RF front ends 5A-5P are connected to the 16 antenna elements 21A-21P in a one-to-one correspondence. Therefore, in the entire phased array antenna module 1 having eight beamformer ICs 10A-10H, each of the 128 antenna elements 21 constituting the antenna array 20 is connected to each of the 16 RF front ends 5A-5P in each of the eight beamformer ICs 10A-10H.

[0028] The 128 antenna elements 21 constituting the antenna array 20 are divided into 64 antenna elements 21 that transmit and receive horizontally polarized radio waves, and 64 antenna elements 21 that transmit and receive vertically polarized radio waves. Eight beamformer ICs 10A-10H control the transmission and reception of the horizontally polarized radio waves in the 64 antenna elements 21, and also control the transmission and reception of the vertically polarized radio waves in the 64 antenna elements 21. For each of the horizontally polarized radio waves and the vertically polarized radio waves, the beamformer ICs 10A-10H set the gain and phase of each of the 64 antenna elements so that the direction of the composite radio waves transmitted or received from the 64 antenna elements 21 is a predetermined direction.

[0029] 2, the RF front-end 5 includes a digital circuit unit 11 and an analog circuit unit 12. The digital circuit unit 11 transmits and receives communication messages related to control to and from the control device 2 via the control line L2 shown in Fig. 1. The digital circuit unit 11 controls the RF front-end 5 based on the communication messages transmitted from the control device 2.

[0030] In this embodiment, communication messages related to control are transmitted and received between the phased array antenna module 1 and the control device 2 through parallel communication. That is, the digital circuit unit 11 transmits and receives communication messages related to control between the control device 2 through parallel communication. Note that the communication between the phased array antenna module 1 and the control device 2 is not limited to parallel communication. It may be serial communication such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit).

[0031] The digital circuit unit 11 includes a memory 13. The memory 13 stores a beam table used for beamforming. The beam table is a lookup table that stores a plurality of combinations of phase-shift amount setting values ​​and gain setting values ​​that are set according to the beam pattern of the antenna array 20 to be controlled. In this embodiment, a beam table (beam table with 1024 items) that specifies 1024 combinations of phase-shift amount setting values ​​and gain setting values ​​is stored in the memory 13. The beam table is written to or read from a storage area using a 10-bit address.

[0032] The memory 13 is realized, for example, by using a static random access memory (SRAM). Although it is preferable that the memory 13 is realized by using an SRAM, the memory 13 may be realized by using a register, a dynamic random access memory (DRAM), a flash memory, or a read only memory (ROM).

[0033] Furthermore, the memory 13 may be realized using one SRAM or multiple SRAMs depending on the size of the beam table, the number of bits of the phase amount setting value, the number of bits of the gain setting value, etc. When the memory 13 is realized using multiple SRAMs, for example, the phase amount setting value of the beam table may be stored in a first SRAM, and the gain setting value of the beam table may be stored in a second SRAM.

[0034] The digital circuit unit 11 is connected to the digital circuit 6 by wiring inside the beamformer IC 10. The digital circuit 6 relays communication between the digital circuit unit 11 and the control device 2. Alternatively, the digital circuit 6 communicates with the digital circuit unit 11 based on the contents of a communication message transmitted from the control device 2. The digital circuit 6 also includes an inspection circuit used to inspect the beamformer IC 10. The details of this circuit will be described later.

[0035] The analog circuit unit 12 is a circuit that outputs an RF signal to the antenna element 21 connected to the RF front-end 5 and receives an RF signal output from the antenna element 21. Under the control of the digital circuit unit 11, the analog circuit unit 12 adjusts the gain and phase of the RF signal transmitted and received by the antenna element 21 connected to the RF front-end 5.

[0036] 3 is a block diagram showing the configuration of the main parts of an analog circuit section provided in an RF front end of a beamformer IC. The RF front ends 5A to 5P provided in the beamformer IC 10 have the same configuration. Therefore, in the following description, one of the analog circuit sections 12 provided in the 16 RF front ends 5A to 5P, i.e., the analog circuit section 12 provided in the RF front end 5, may be described. Descriptions of the analog circuit sections 12 provided in the other 15 RF front ends may be omitted.

[0037] 3, the analog circuit unit 12 includes a transmission circuit 61, a phase shifter 62, a variable gain amplifier 63, a power amplifier 64, a switch 65, a low noise amplifier 66, a variable gain amplifier 67, a phase shifter 68, and a reception circuit 69. Note that in FIG. 3, the memory 13 provided in the digital circuit unit 11 of the RF front end 5 is also shown.

[0038] The transmitting circuit 61, the phase shifter 62, the variable gain amplifier 63, and the power amplifier 64 are provided on the transmitting path R1, and the low noise amplifier 66, the variable gain amplifier 67, the phase shifter 68, and the receiving circuit 69 are provided on the receiving path R2. The transmitting path R1 is a path through which an RF signal output to the antenna element 21 passes, and the receiving path R2 is a path through which an RF signal input from the antenna element 21 passes. The switch 65 switches between connecting the transmitting path R1 or connecting the receiving path R2 to the antenna element 21 at a specified time interval. This allows the phased array antenna module 1 to transmit and receive high frequency signals as a time division multiplexing system.

[0039] The transmission circuit 61 is a circuit to which an RF signal (a signal to be transmitted as radio waves from the antenna element 21) output from the frequency conversion IC 30 (see FIG. 1) is input. The phase shifter 62 adjusts the phase shift amount of the RF signal passing through the transmission path R1 according to the phase shift amount setting value of the beam table read from the memory 13. The variable gain amplifier 63 adjusts the intensity of the RF signal passing through the transmission path R1 according to the gain setting value of the beam table read from the memory 13. The power amplifier 64 amplifies the RF signal passing through the transmission path R1 by a predetermined amplification factor. By adjusting the phase shift amount and intensity of the RF signal passing through the transmission path R1, the beam pattern of the radio waves transmitted from the phased array antenna module 1 can be changed.

[0040] The low noise amplifier 66 amplifies the RF signal input from the switch 65 at a predetermined amplification factor. The variable gain amplifier 67 adjusts the intensity of the RF signal passing through the receiving path R2 according to the gain setting value of the beam table read from the memory 13. The phase shifter 68 adjusts the phase shift amount of the RF signal passing through the receiving path R2 according to the phase shift amount setting value of the beam table read from the memory 13. The receiving circuit 69 receives the RF signal passing through the receiving path R2 and outputs it to the frequency conversion IC 30 (see FIG. 1). By adjusting the phase shift amount and intensity of the RF signal passing through the receiving path R2, the beam pattern of the radio waves received by the phased array antenna module 1 can be changed.

[0041] Fig. 4 is a block diagram showing the main configuration of a test circuit used to test the beamformer integrated circuit according to the first embodiment of the present invention. Fig. 4 also shows the RF front-end 5 provided in the beamformer IC 10 and the memory 13 provided therein. As shown in Fig. 4, the test circuit is provided in the digital circuit 6 shown in Fig. 2, and includes a register 71 (first register), a register 72 (second register), a decision circuit 73, and a register 74. This test circuit is a circuit used when testing whether all of the memories 13 of the RF front-end 5 provided in the beamformer IC 10 operate normally.

[0042] The register 71 is a register that holds values ​​to be simultaneously written to the multiple memories 13 when the beamformer IC 10 is inspected. The register 72 is a register that holds addresses for simultaneously writing to or reading from the multiple memories 13 when the beamformer IC 10 is inspected. The values ​​held in the register 71 and the addresses held in the register 72 are output from the control device 2 when the beamformer IC 10 is inspected.

[0043] The judgment circuit 73 is a circuit that judges whether or not the values ​​simultaneously read from the multiple memories 13 all match. When the judgment circuit 73 judges that the values ​​simultaneously read from the multiple memories 13 all match (when all memories 13 are operating normally), it outputs "1". In contrast, when the judgment circuit 73 judges that the values ​​simultaneously read from the multiple memories 13 all do not match (when there is a memory 13 that is not operating normally), it outputs "0". The register 74 is a register that holds the judgment result of the judgment circuit 73. The judgment result held in the register 74 is read out to the control device 2.

[0044] <Method of Inspecting Beamformer Integrated Circuit> The inspection of the beamformer IC 10 can be performed at any timing. For example, it can be performed before shipping of the wireless communication device A, when performing maintenance on the wireless communication device A, or at other timings. The wireless communication device A shown in FIG. 1 is provided with eight beamformer ICs 10, and the inspection of these eight beamformer ICs 10 may be performed in parallel or sequentially. The following describes the inspection performed on any one of the eight beamformer ICs 10.

[0045] When the inspection of the beamformer IC 10 is started, first, the control device 2 outputs a communication message to the beamformer IC 10, instructing the values ​​to be simultaneously written to the multiple memories 13 and the addresses to which the values ​​are to be simultaneously written to the multiple memories 13. This communication message is input to the digital circuit 6 of the beamformer IC 10 via the control line L2, and the values ​​to be simultaneously written to the multiple memories 13 are held in the register 71, and the addresses to which the values ​​are to be simultaneously written to the multiple memories 13 are held in the register 72.

[0046] Next, the control device 2 outputs a communication message to the beamformer IC 10 to instruct it to write to the memory 13. When this communication message is input to the digital circuit 6 of the beamformer IC 10 via the control line L2, the value held in the register 71 is simultaneously written to the addresses held in the registers 72 of the memories 13 provided in all of the RF front ends 5.

[0047] Next, the control device 2 outputs a communication message to the beamformer IC 10 to instruct it to read the values ​​written in the memories 13. When this communication message is input to the digital circuit 6 of the beamformer IC 10 via the control line L2, the values ​​written in the addresses held in the registers 72 are simultaneously read from the memories 13 provided in all of the RF front ends 5. The simultaneously read values ​​are input to the determination circuit 73, which determines whether or not all the values ​​match.

[0048] When it is determined that all the values ​​simultaneously read from the multiple memories 13 match, the determination circuit 73 outputs "1". On the other hand, when it is determined that all the values ​​simultaneously read from the multiple memories 13 do not match, the determination circuit 73 outputs "0". The value output from the determination circuit 73 is held in a register 74. The value held in this register 74 is output to the control device 2 via a control line L2.

[0049] The control device 2 performs one or more inspections while sequentially changing addresses for simultaneous writing or reading from the multiple memories 13. The control device 2 may change values ​​to be simultaneously written to the multiple memories 13 along with the addresses for simultaneous writing or reading. If all values ​​obtained from the beamformer IC 10 are "1" until the inspection of the beamformer IC 10 is completed, the control device 2 can determine that all memories 13 provided in the beamformer IC 10 are operating normally. On the other hand, if values ​​obtained from the beamformer IC 10 include "0" until the inspection of the beamformer IC 10 is completed, the control device 2 can determine that a memory 13 that is not operating normally exists in the beamformer IC 10.

[0050] As described above, in this embodiment, the beamformer IC 10 includes a plurality of memories 13 that store setting values ​​of at least one of the phase and intensity (gain) of signals supplied to the plurality of antenna elements 21 or signals supplied from the plurality of antenna elements 21, and a determination circuit 73 that determines whether or not all values ​​simultaneously read out from the memories 13 match. This allows the plurality of memories 13 to be inspected simultaneously, so inspection can be performed without increasing time and cost compared to the case where the plurality of memories 13 are inspected sequentially.

[0051] Second Embodiment Next, a second embodiment of the present invention will be described. The wireless communication device of this embodiment has the same configuration as the wireless communication device A according to the first embodiment described with reference to Fig. 1. The beamformer integrated circuit (beamformer IC) of this embodiment has a configuration generally similar to the beamformer IC 10 described with reference to Figs. 2 and 3, but the internal configuration of the digital circuit 6 is slightly different.

[0052] The determination circuit 73 in the first embodiment described above determines whether all values ​​simultaneously read from the multiple memories 13 match, and outputs "1" if it is determined that all match, and outputs "0" if it is determined that all do not match. When such a determination circuit 73 is used, there is a possibility that an erroneous determination occurs in which the determination circuit 73 outputs "1" even if a memory 13 that is not operating normally exists. For example, there is a case where multiple memories 13 are broken in the same way, and even if a value "1111" is written to a specific address of the multiple memories 13, all values ​​read from the specific address of the multiple memories 13 are "0000". In this embodiment, even if such an erroneous determination occurs, the control device 2 can determine whether or not a memory 13 that is not operating normally exists in the beamformer IC 10.

[0053] 5 is a block diagram showing the main configuration of an inspection circuit used to inspect a beamformer integrated circuit according to a second embodiment of the present invention. In FIG. 5, the same components as those shown in FIG. 4 are denoted by the same reference numerals. As shown in FIG. 5, the inspection circuit of this embodiment is configured by adding a switching circuit 75 to the inspection circuit shown in FIG. 4. The switching circuit 75 is a circuit that switches between outputting the judgment result of the judgment circuit 73 to the outside or outputting one of the values ​​simultaneously read out from the multiple memories 13 to the outside under the control of the control device 2. In addition, it is optional whether one of the values ​​simultaneously read out from the multiple memories 13 is output to the outside.

[0054] Inspection of the beamformer IC 10 in this embodiment is basically performed in the same manner as in the first embodiment. However, every time the value held in the register 74 (the determination result of the determination circuit 73) is output to the control device 2 via the control line L2, a communication message instructing the switching circuit 75 to be switched is transmitted from the control device 2. Then, after any one of the values ​​simultaneously read out from the multiple memories 13 is held in the register 74, it is output to the control device 2 via the control line L2. When any one of the values ​​simultaneously read out from the multiple memories 13 is output to the control device 2, a communication message instructing the switching circuit 75 to be switched is transmitted again from the control device 2, and the switching circuit 75 is switched.

[0055] As described above, this embodiment includes a switching circuit 75 that switches between outputting the determination result of the determination circuit 73 to the outside, or outputting to the outside one of the values ​​simultaneously read from the multiple memories 13. As a result, even if a malfunction occurs in which the determination circuit 73 outputs "1" despite the presence of a memory 13 that is not operating normally, the control device 2 can determine that the beamformer IC 10 includes a memory 13 that is not operating normally.

[0056] Third Embodiment Next, a third embodiment of the present invention will be described. The wireless communication device of this embodiment has the same configuration as the wireless communication device A according to the first embodiment described with reference to Fig. 1. The beamformer integrated circuit (beamformer IC) of this embodiment has a configuration generally similar to the beamformer IC 10 described with reference to Figs. 2 and 3, but the internal configuration of the digital circuit 6 is slightly different, as in the second embodiment.

[0057] In the second embodiment described above, even if an erroneous judgment is made by the judgment circuit 73, the control device 2 can determine that a malfunctioning memory 13 exists in the beamformer IC 10. In contrast, in the present embodiment, when "0" is output from the judgment circuit 73, the control device 2 can identify the fault location by reading all values ​​simultaneously read from the multiple memories 13.

[0058] Fig. 6 is a block diagram showing the main configuration of an inspection circuit used to inspect a beamformer integrated circuit according to a third embodiment of the present invention. In Fig. 6, the same components as those shown in Figs. 4 and 5 are given the same reference numerals. As shown in Fig. 6, the inspection circuit of this embodiment is configured by adding a selection circuit 76 to the inspection circuit shown in Fig. 5. The selection circuit 76 is a circuit that selects one of the values ​​simultaneously read from the multiple memories 13 as a value to be output to the outside under the control of the control device 2. The selection circuit 76 is controlled when the switching circuit 75 switches to output one of the values ​​simultaneously read from the multiple memories 13 to the outside.

[0059] Inspection of the beamformer IC 10 in this embodiment is basically performed in the same manner as in the first embodiment. However, when "0" is output from the judgment circuit 73 and this judgment result is stored in the register 74 and then output to the control device 2 via the control line L2, the control device 2 transmits a communication message instructing the switching circuit 75 to switch. Then, the control device 2 sequentially outputs a communication message for controlling the selection circuit 76, and one of the values ​​simultaneously read from the multiple memories 13 is sequentially selected as a value to be output to the outside and stored in the register 74, and then sequentially output to the control device 2 via the control line L2.

[0060] For example, among values ​​simultaneously read from the memories 13 provided in the 16 RF front-ends 5A to 5P, the value read from the memory 13 provided in the RF front-end 5A is selected first and output to the control device 2. Next, the value read from the memory 13 provided in the RF front-end 5B is selected and output to the control device 2. Subsequently, the values ​​read from the memories 13 provided in the RF front-ends 5C to 5O are sequentially selected and output to the control device 2. Then, when the value read from the memory 13 provided in the RF front-end 5P is selected and output to the control device 2, the control of the selection circuit 76 ends. Note that when the control of the selection circuit 76 ends, a communication message instructing the switching circuit 75 to be switched is again transmitted from the control device 2, and the switching circuit 75 is switched.

[0061] As described above, in this embodiment, in addition to the switching circuit 75 in the second embodiment, a selection circuit 76 is provided that selects one of the values ​​simultaneously read from the multiple memories 13 as a value to be output to the outside. This allows the control device 2 to read all the values ​​simultaneously read from the multiple memories 13 when "0" is output from the determination circuit 73, thereby making it possible to identify the location of the failure.

[0062] Other embodiments Fig. 7 is a block diagram showing the main configuration of an inspection system according to an embodiment of the present invention. In Fig. 7, the same components as those shown in Fig. 2 are given the same reference numerals. As shown in Fig. 7, the inspection system IS of this embodiment includes a control device 100, which is connected to a beamformer IC10 via a control line L10 and inspects the beamformer IC10. The control device 100 inspects the beamformer IC10 by carrying out the same control as the control device 2 in the first to third embodiments described above.

[0063] For example, consider the case where the digital circuit 6 provided in the beamformer IC 10 to be inspected has the configuration shown in Fig. 6 (the case of the third embodiment). In this case, when the determination circuit 73 outputs "0", the control device 100 controls the switching circuit 75 and the selection circuit 76 so that values ​​simultaneously read out from the multiple memories 13 are output sequentially to the inspection system.

[0064] In the inspection system IS of this embodiment, the control device 100 inspects the beamformer IC 10 by performing the same control as the control device 2 in the first to third embodiments described above. This allows the inspection of the beamformer IC 10 to be performed without increasing time and cost. Furthermore, even if a malfunction occurs in which the determination circuit 73 outputs "1" despite the presence of a memory 13 that is not operating normally, the control device 2 can determine that the beamformer IC 10 includes a memory 13 that is not operating normally. Furthermore, when the determination circuit 73 outputs "0", the control device 2 can read all values ​​that are simultaneously read from the multiple memories 13, and therefore can identify the location of the malfunction.

[0065] The beamformer integrated circuit, the wireless communication device, and the inspection system according to the embodiment of the present invention have been described above, but the present invention is not limited to the above embodiment and can be freely modified within the scope of the present invention. For example, in the above embodiment, an example in which the inspection is performed in units of eight memories 13 has been described, but the inspection may be performed in units of fewer than eight memories 13 or in units of more than eight memories 13. Alternatively, the eight memories 13 to be inspected may be divided into a plurality of parts, and the inspection may be performed in units of the parts. For example, ten memories 13 may be divided into seven memories 13 and three memories 13, and the inspection may be performed in units of seven memories 13, and the inspection may be performed in units of three memories 13. The number of parts is not limited to two, and may be three or more.

[0066] The phased array antenna module described in the above embodiment is for a time division multiplexing system. However, the phased array antenna module of the present invention may be for a frequency division multiplexing system.

[0067] In the above-described embodiment, an example has been described in which one antenna element 21 is connected to one RF front end 5 in a one-to-one correspondence. However, in the present invention, two front ends may be connected to a dual-polarized antenna element having a connection terminal for horizontal polarization and a connection terminal for vertical polarization. [Explanation of symbols]

[0068] 2...control device, 10...beamformer IC, 13...memory, 21...antenna element, 71...register, 72...register, 73...determination circuit, 75...switching circuit, 76...selection circuit, 100...control device, A...wireless communication device, IS...inspection system

Claims

1. A plurality of memories for storing at least one of a phase and intensity of a signal supplied to a plurality of antenna elements or a signal supplied from the plurality of antenna elements; a determination circuit for determining whether or not values ​​simultaneously read from specific addresses of the plurality of memories are all the same; 1. A beamformer integrated circuit comprising:

2. 2. The beamformer integrated circuit of claim 1, further comprising a switching circuit that switches between outputting the judgment result of the judgment circuit to the outside or outputting one of the values ​​simultaneously read out from specific addresses of the multiple memories to the outside.

3. 3. The beamformer integrated circuit of claim 2, further comprising a selection circuit that selects which of the values ​​simultaneously read from specific addresses of the plurality of memories is to be output to the outside when the switching circuit switches to outputting one of the values ​​simultaneously read from specific addresses of the plurality of memories to the outside.

4. a first register for holding values ​​to be simultaneously written to the plurality of memories; a second register for holding the specific address for simultaneously writing or reading from the plurality of memories; 2. The beamformer integrated circuit of claim 1 comprising:

5. A plurality of antenna elements; 5. The beamformer integrated circuit according to claim 1, wherein at least one of a phase and an intensity of a signal supplied to the plurality of antenna elements or a signal supplied from the plurality of antenna elements is controlled using a setting value stored in the memory; A wireless communication device comprising:

6. A plurality of antenna elements; A beamformer integrated circuit according to claim 3; a control device that controls the switching circuit and the selection circuit so that the values ​​simultaneously read from the specific addresses of the plurality of memories are sequentially output to the outside when the determination result of the determination circuit indicates that all of the values ​​simultaneously read from the specific addresses of the plurality of memories are not the same; A wireless communication device comprising:

7. 4. A test system for testing a beamformer integrated circuit according to claim 3, comprising: An inspection system comprising a control device that controls the switching circuit and the selection circuit so that values ​​read simultaneously from specific addresses of multiple memories are output to an inspection system when the judgment result of the judgment circuit indicates that the values ​​read simultaneously from specific addresses of multiple memories are not all identical.

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