Electronic control device

Abstract

To provide an electronic control device for a vehicle that is capable of performing appropriate communication while suppressing power consumption.SOLUTION: An electronic control device 10 includes SoCs 30 to 32 and a memory unit 33, and a communication switch 40. The SoCs 30 to 32 and the memory unit 33 are compatible with a predetermined communication protocol, and the communication switch 40 is configured to be applicable to the predetermined communication protocol. When communication between the SoCs 30 and 31 is capable of faster communication than communication between combinations of other devices, the electronic control device is configured to perform direct communication only between the SoCs 30 and 31. The electronic control device is also configured to be able to perform communication via the communication switch 40 between devices other than between the SoCs 30 and 31 that perform direct communication. A communication speed for communication through the communication switch 40 is slower than a speed of direct communication between the SoCs 30 and 31.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an electronic control device. [Background technology]

[0002] In recent years, vehicle systems have integrated functions such as normal vehicle control and autonomous driving functions into an integrated ECU (Electronics Control Unit). An integrated ECU is equipped with multiple SoCs (System On Chip), which communicate with each other while controlling the vehicle. To accommodate such multi-SoCs and improve connectivity with peripheral devices, there are an increasing number of cases where communication between devices is performed via a communication switch.

[0003] On the other hand, in the consumer field, a communication method based on the PCIe (Peripheral Component Interconnect express) standard is provided as a high-speed communication method between devices (see, for example, Patent Document 1). PCIe has a high transfer rate and a high degree of freedom in bus width. It is expected that applying this type of technology to vehicle systems will enable flexible response when updating or expanding the functions of integrated ECUs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-119498 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology using PCIe described in the Background section, devices are generally connected via a single communication switch. In this configuration, even if only some devices require faster communication speeds than other devices, a communication switch compatible with the maximum speed used by those units must be used, resulting in a high-cost and over-specified system.

[0006] In addition, because communication switches perform high-speed transmission and reception processing according to a specific communication protocol, the amount of processing increases as the corresponding communication speed increases, resulting in higher power consumption. Because high-power switches are required for communication between limited devices, more heat is generated, and the required power circuitry must be increased in size.

[0007] An object of the present disclosure is to provide an electronic control device for a vehicle that is capable of performing appropriate communication while suppressing system costs and power consumption. [Means for solving the problem]

[0008] According to the invention of claim 1, the system includes three or more devices and a communication switch. The three or more devices are compatible with a predetermined communication protocol. The communication switch is configured to be applicable to the predetermined communication protocol. When communication between at least two of the devices is faster than communication between other combinations of devices, the system is configured to allow direct communication between at least two devices. In addition, the system is configured to allow communication between devices other than the two devices that directly communicate with each other via the communication switch.

[0009] The communication speed through a communication switch is slower than the speed of direct communication between two devices. As a result, direct communication between two devices allows high-speed communication. In addition, other combinations of devices can communicate via a communication switch, so there is no need to use a communication switch that supports high-speed communication, and appropriate communication can be performed while suppressing system costs and power consumption. [Brief description of the drawings]

[0010] [Figure 1] Electrical configuration block diagram of an electronic control device in a first embodiment [Diagram 2] Correspondence between PCIe transfer speed and fundamental frequency in the first embodiment [Diagram 3] FIG. 1 is an electrical block diagram of an electronic control device according to a comparative example. [Figure 4] Electrical configuration block diagram of an electronic control device in a second embodiment [Diagram 5] Flowchart 1 for explaining the operation in the second embodiment [Figure 6] Flowchart 2 for explaining the operation in the second embodiment [Figure 7] Electrical configuration block diagram of an electronic control device in a third embodiment [Figure 8] Frequency characteristic diagram of substrate transmission loss in the third embodiment [Figure 9] FIG. 13 is a diagram comparing eye patterns before and after waveform shaping in the third embodiment. [Figure 10] Electrical configuration block diagram of an electronic control device in a fourth embodiment [Figure 11] 11 is a flowchart for explaining an outline of the operation in the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, several embodiments of the electronic control device will be described with reference to the drawings. In each embodiment described below, components that perform the same or similar operations are denoted by the same or similar reference numerals, and descriptions thereof will be omitted as necessary.

[0012] (First embodiment) The first embodiment will be described with reference to Figures 1 and 2. As shown in Figure 1, an electronic control device 10 is equipped with a base substrate 11, a first extension substrate 21, a second extension substrate 22, and a third extension substrate 23. The base substrate 11, the first extension substrate 21, the second extension substrate 22, and the third extension substrate 23 are each formed of a resin build-up substrate using, for example, FR4 as a base material.

[0013] The electronic control device 10 constitutes an integrated electronic control device equipped with various functions related to vehicle control. Although the integrated electronic control device 10 will be described here, it may be applied to an electronic control device 10 for a vehicle equipped with some of the vehicle control functions. The integrated electronic control device 10 is equipped with SoCs 30 to 32, a memory unit 33 (corresponding to three or more devices), and a communication switch 40.

[0014] The base substrate 11 is equipped with some functional components for vehicle control functions, and as part of these functional components, an SoC 30 and a communication switch 40 are mounted. SoC is an abbreviation for System On Chip.

[0015] The SoC 30 is configured by integrating a processor 30a, a memory 30b, a communication unit 30c, and other peripheral circuits (not shown) into one chip. The memory 30b is configured by a non-transient real recording medium such as a volatile memory and a non-volatile memory. The processor 30a includes a processing unit that performs data calculation and conversion, program execution, control of other devices, and the like, among the components of a computer. Typically, the processor 30a includes a CPU (Central Processing Unit) that controls the entire computer, or an MPU (Micro Processing unit) that integrates some functions of the CPU. The communication unit 30c supports a predetermined communication protocol that complies with, for example, the PCIe (Peripheral Component Interconnect express) standard, and supports the fifth generation (Gen5) of the PCIe standard.

[0016] The PCIe standard has backward compatibility. A SoC30 that supports Gen5 can communicate at Gen5, and can also communicate normally at communication speeds specified by the fourth generation (Gen4) and third generation (Gen3).

[0017] As shown in FIG. 2, the communication speed of the PCIe standard is specified as Gen3 → maximum 8GT / s, Gen4 → maximum 16GT / s, and Gen5 → maximum 32GT / s. T / s is also referred to as bits per second (bps). The fundamental frequency of the communication pulse is 4 GHz for Gen3, 8 GHz for Gen4, and 16 GHz for Gen5. Here, a case where PCIe is applied to the bus of the electronic control device 10 will be described. However, this is not limited to this, and the present disclosure can be applied to various other bus communication methods of the PCIe standard.

[0018] The SoC 30 of this embodiment has a function of executing a program stored in a memory 30b by a processor 30a, and receiving sense data from a group of sensors 45 such as a peripheral camera, LiDAR, and millimeter wave radar by a communication unit 30c, and quickly processing images, etc.

[0019] The communication switch 40 is configured with a bus switch compatible with a predetermined communication protocol conforming to, for example, the PCIe standard. The communication switch 40 includes a switch core and a plurality of input / output ports. The communication switch 40 is configured with a bus switch compatible with, for example, Gen3 of the PCIe standard, which is slower than the maximum speed. A normal transfer path P2 compatible with Gen3 of the PCIe standard is configured between the communication unit 30c of the SoC 30 and the input / output port of the communication switch 40.

[0020] The first extension board 21 and the second extension board 22 are each equipped with functional components for expanding the functions of the vehicle, and among those functional components, SoC 31 and SoC 32 are respectively mounted. The SoC 31 is also implemented with a processor 31a, a memory 31b, a communication unit 31c, and other peripheral circuits (not shown) mounted on a single chip. The SoC 32 is also implemented with a processor 32a, a memory 32b, a communication unit 32c, and other peripheral circuits (not shown) mounted on a single chip.

[0021] The SoC 31 of this embodiment realizes, for example, an advanced driver assistance system (ADAS) by executing a program stored in the memory 31b by the processor 31a, and executes driving assistance or automatic driving of the vehicle. Examples of driving assistance include lane keeping assistance, automatic braking, parking assistance, and cruise control. For example, when the SoC 31 executes driving assistance or automatic driving control of the vehicle, it detects the presence or absence of obstacles or pedestrians around the vehicle based on the image processing data processed by the SoC 30, and controls the driving conditions of the vehicle (for example, forward / reverse, driving speed, left / right steering).

[0022] It is desirable that SoC30 and SoC31 are able to control each other in real time. There is an increasing need for high-speed data communication between SoC30 and SoC31, and this is of high importance. For this reason, a high-speed transfer compatible path P1 is configured between SoC30 and SoC31.

[0023] The image processing data processed by the SoC 30 is data used solely for driving assistance or automatic driving control. For this reason, in this embodiment, direct communication is possible only between the SoC 30 and the SoC 31, and a high-speed transfer compatible path P1 that supports, for example, Gen5, the highest speed of the PCIe standard, is configured. The SoC 30 does not have a high-speed transfer compatible path P1 between itself and another SoC 32 or the memory unit 33.

[0024] The SoC 32 of this embodiment executes various controls of the vehicle other than the above-mentioned advanced driving assistance system, for example, controls related to a so-called HMI (Human Machine Interface) that controls display on a display such as a meter or a head-up display, by executing a program stored in the memory 32b by the processor 32a. Note that the SoC 32 has little need for high-speed communication with other SoCs 30 and SoC 32 when controlling various control devices. For this reason, the SoC 32 has a normal transfer path P2 compatible with Gen3 of the PCIe standard between the input / output port of the communication switch 40. This allows the SoC 32 to communicate with other devices at a slow Gen3 communication speed.

[0025] The third extension board 23 is equipped with a memory unit 33 as one of its functional components. The memory unit 33 includes a memory 33b such as a flash storage (e.g., SSD: Solid State Drive) capable of communicating according to the NVMe communication protocol, and a communication unit 33c. The memory unit 33 is used, for example, as a data logger for ensuring the safety of the driver and for recording when an abnormality occurs. NVMe is an abbreviation for Non-Volatile Memory Express, and is a standard for a communication protocol that defines the procedure for communication between different devices.

[0026] The communication unit 33c of the memory unit 33 supports a predetermined communication protocol conforming to the PCIe standard, and supports the third generation (Gen3) of the PCIe standard, which is slower than the maximum speed. A normal transfer path P2 conforming to the Gen3 of the PCIe standard is configured between the memory unit 33 and the input / output port of the communication switch 40. This allows the memory unit 33 to communicate with other devices at the slow Gen3 communication speed.

[0027] When the communication switch 40 receives data from one input / output port, it processes the received signal for each layer according to a predetermined communication protocol and transfers it to another input / output port. Since the communication switch 40 requires processing according to the communication protocol, the latency is likely to be relatively large.

[0028] Among the PCIe standards, Gen5, Gen4, and Gen3 have different processing contents, but when the maximum communication speed is relatively high, such as in Gen5, the amount of processing increases compared to Gen4, Gen3, etc., and the delay time and power consumption tend to increase. The communication switch 40 of this embodiment uses a bus switch compatible with Gen3, so it is possible to reduce the delay time and power consumption.

[0029] In this way, high-speed communication is possible between SoC 30 and SoC 31, and mutual communication is possible between SoC 31, 32 and memory unit 33. Note that between devices other than between SoC 30 and SoC 31, for example, between SoC 30 and SoC 32, between SoC 30 and memory unit 33, and between SoC 32 and memory unit 33, communication is possible by Gen3 via normal transfer path P2 through communication switch 40.

[0030] In a vehicle capable of driving assistance or automatic driving control, it is important to link with indicators such as meters and head-up displays and to acquire data logs as quickly as possible in order to ensure the safety of the driver and to immediately respond to abnormalities. For this reason, in this embodiment, SoC31 that executes automatic driving control, SoC32 that executes control of the indicators, and memory unit 33 that acts as a data logger are communicatively linked.

[0031] The amount of data transferred per unit time for data mutually communicated between SoCs 31, 32 and memory unit 33 is smaller than the image / video data communicated via the above-mentioned high-speed transfer path P1. Therefore, although the communication speed between SoC 30 and memory unit 33 and between SoC 32 and memory unit 33 is slower than the communication speed of Gen5 for direct communication between SoC 30 and SoC 31, the configuration is sufficiently practical. In this embodiment, communication can be performed between SoC31 and SoC32, and between SoC31 and SoC33 through the communication switch 40 via SoC30.

[0032] <Comparative Example> 3, if a communication switch 40a is provided between the SoC 30 and all other devices (i.e., the SoC 31, the SoC 32, and the memory unit 33), the communication switch 40a must be capable of maximum high-speed communication. For example, even if the communication speed of the SoC 30 is limited to only some functions, the communication switch 40a, which is a repeater, must also be capable of maximum speed. In addition, the latency increases by passing through the communication switch 40a, and the effective transfer rate decreases.

[0033] <Summary of this embodiment> According to this embodiment, only between the devices of SoC30 and SoC31 that require high-speed transfer, direct communication is possible through the high-speed transfer compatible path P1 without going through the communication switch 40. This allows high-speed communication only between SoC30 and SoC31. Other device combinations can communicate via a low-spec communication switch 40 that corresponds to the required communication speed. By setting the compatible generation of the communication switch 40 to Gen3, the same as that of the SoC32 and the memory unit 33, the performance of PCIe can be reduced, and power consumption and circuit size can be reduced. Furthermore, the size of the power supply circuit for supplying power and heat generated by components can be reduced, and the cost of components used can be reduced. In addition, since communication is not performed through the communication switch 40 in the high-speed transfer compatible path P1, latency can be reduced. As a result, appropriate communication can be performed while suppressing system costs.

[0034] Second embodiment The second embodiment will be described with reference to Figs. 4 to 6. Differences from the first embodiment will be described. As shown in Fig. 4, an electronic control device 210 replacing the electronic control device 10 has a multiplexer 50 mounted on a base substrate 11. A high-speed transfer compatible path P1 is configured between the SoC 30 and the input / output port of the multiplexer 50, and a high-speed transfer compatible path P1 is also configured between the input / output port of the multiplexer 50 and the SoC 31. The high-speed transfer compatible path P1 can also communicate data at the Gen3 communication speed, and can therefore also function as a normal transfer path P2. A normal transfer path P2 is also configured between the input / output port of the communication switch 40 and the input / output port of the multiplexer 50.

[0035] The multiplexer 50 switches between the input / output ports, thereby switching between a high-speed transfer path P1 for direct communication between the SoC30 and the SoC31 and a normal transfer path P2 for communication via the communication switch 40. The SoC30 and the SoC31 are connected to a control terminal of the multiplexer 50, and the connection between the input / output ports of the multiplexer 50 can be switched based on a control signal from the SoC30 or the SoC31.

[0036] The multiplexer 50 is a passive switch that simply switches the connection destination, and executes the same function and the same processing regardless of the communication speed, so that the power consumption is not easily dependent on the communication speed. The multiplexer 50 is structured to simply selectively switch the input in an analog manner and output it. Therefore, the latency is, for example, about several tens of ps, which is significantly smaller than the latency of the communication switch 40. Even if the multiplexer 50 is provided on the route along the high-speed transfer compatible path P1, it will have almost no adverse effect on the communication speed.

[0037] Next, a method of switching the multiplexer 50 and a method of transmitting data will be described. For example, as shown in Fig. 5, a case where SoC 30 transmits data to another device will be described. When SoC 30 transmits data to SoC 31 as a destination in S1, it determines YES in S1. In this case, SoC 30 determines whether the data requires high-speed transfer in S5.

[0038] If SoC 30 determines that the data requires high-speed transfer, for example, that the data requires real-time processing such as image data, it outputs a control signal for multiplexer 50 in S6, and switches the input of multiplexer 50 to high-speed transfer compatible path P1 in S7. Then, SoC 30 transmits the data to destination SoC 31 in S4.

[0039] Conversely, if the SoC 30 determines in S5 that the data does not require high-speed transfer, it determines NO. The SoC 30 outputs a control signal for the multiplexer 50 in S2, and switches the input of the multiplexer 50 to the normal transfer path P2 in S3. Then, the SoC 30 transmits the data to the destination SoC 31 in S4.

[0040] Furthermore, if SoC 30 determines in S1 that SoC 31 is not the destination, that is, that SoC 32 or memory unit 33 is the destination of the data, SoC 30 outputs a control signal for multiplexer 50 in S2 to switch the input of multiplexer 50 to normal transfer path P2. Then, SoC 30 transmits the data to the destination in S4.

[0041] Next, a case will be described where the SoC 31 transmits data to another device as shown in Fig. 6. When the SoC 31 transmits data to the SoC 30 as the destination in S1, the result of the determination in S1 is YES. In this case, the SoC 31 determines in S5 whether the data requires high-speed transfer.

[0042] When the SoC 31 determines that the data requires high-speed transfer, for example, data requiring high-speed processing such as image signal reception response data related to autonomous driving, the SoC 31 outputs a control signal for the multiplexer 50 in S6a, and switches the input of the multiplexer 50 to the high-speed transfer compatible path P1 in S7a. Then, the SoC 31 transmits the data to the destination SoC 30 in S4.

[0043] Conversely, if the SoC 31 determines in S5 that the data does not require high-speed transfer, it determines NO in S5. The SoC 31 outputs a control signal for the multiplexer 50 in S2a, and switches the input of the multiplexer 50 to the normal transfer path P2 in S3a. Then, the SoC 31 transmits the data to the destination SoC 30 in S4.

[0044] Furthermore, if SoC31 determines in S1 that SoC30 is not the destination, that is, that SoC32 or memory unit 33 is the destination of data, SoC31 outputs a control signal for multiplexer 50 in S2 to switch the input of multiplexer 50 to normal transfer path P2. Then, SoC31 transmits data to the destination in S4. This allows both SoC30 and SoC31 to transmit data to other devices at an appropriate communication speed.

[0045] According to this embodiment, a multiplexer 50 is provided, and the multiplexer 50 switches between the normal transfer path P2 and the high-speed transfer compatible path P1. With this configuration, as in the above-described embodiment, high-speed communication is possible only between specific SoCs 30 and 31, and the communication switch 40a capable of high-speed communication between all devices can be eliminated. In addition, since the multiplexer 50 is disposed on the side of the base substrate 11, the interface with the first extension substrate 21 can be changed by adding a control signal for the multiplexer 50, and the number of steps required for improvement can be reduced as much as possible.

[0046] In addition, in the case where the data destination is a device capable of high-speed communication and the data requires high-speed transfer, the SoC 30 or SoC 31 selects the high-speed transfer compatible path P1 by the multiplexer 50, and otherwise selects the normal transfer path P2 by the multiplexer 50. By controlling to select the normal transfer path P2 except when high-speed transfer is required, power consumption can be reduced.

[0047] According to this embodiment, a normal transfer path P2 via the communication switch 40 is provided, and high-speed communication / normal communication can be switched, thereby improving the accessibility of the SoC 31 to other devices. For example, the SoC 31 that supports high-speed transfer can also communicate with the SoC 32 or the memory unit 33 via the normal transfer path P2 via the communication switch 40. Communication between the SoC 31 and the SoC 32 or the memory unit 33 can be performed without using the SoC 30, and the processing load of the SoC 30 can be reduced.

[0048] Furthermore, communication between other devices can also be achieved through the communication switch 40 that is not compliant with the PCIe standard Gen5, which reduces component costs and suppresses heat generation, thereby enabling the configuration size of the power supply circuit to be reduced.

[0049] Third embodiment The third embodiment will be described with reference to Fig. 7 to Fig. 9. The same parts as those in the second embodiment are given the same reference numerals and their explanations are omitted, and only the different parts will be described. Fig. 7 shows the electrical configuration of electronic control device 310 that replaces electronic control device 210, and Fig. 8 shows the board transmission characteristics of base board 20 and first extension board 21.

[0050] 8, in the case of PCIe, as the generation progresses from Gen3 to Gen5, the fundamental frequency of the communication pulse increases, and the insertion loss also increases, so that the transmission loss during transmission through the base substrate 20 tends to increase. Furthermore, as the path length L becomes longer, the insertion loss also increases, and the transmission loss during transmission through the base substrate 20 and the first extension substrate 21 becomes larger. For example, in the case of PCIe Gen5, the fundamental frequency of the communication pulse is 16 GHz, and the path length L is a short distance L1 or a medium distance L2, and if it is a relatively short distance, it meets the criteria of the standard, but if it is transmitted over a long distance L3, there is a risk that the insertion loss criteria will not be met (see column A).

[0051] 7, it is desirable to configure the high-speed transfer compatible path P1 between the SoC 30 and the multiplexer 50 to include a re-driver 60 as a signal attenuation correction unit. In particular, the high-speed transfer compatible path P1 is likely to have a longer transmission distance between the SoC 30 and the SoC 31 than the path that passes through the communication switch 40. For this reason, signal attenuation can be dealt with by inserting the re-driver 60 on the route of the high-speed transfer compatible path P1.

[0052] The redriver 60 is composed of a driver IC having an analog filter called a CTLE (Continuous Time Linear Equalizer), a function of amplifying only a specific frequency band, and a function of correcting the waveform of a high-speed signal. For example, in PCIe Gen5, the fundamental frequency is 16 GHz, so it is advisable to provide the redriver 60 so as to amplify only the 16 GHz band, which has large attenuation. As a result, even if the communication distance between SoC30 and SoC31 becomes long, inserting the redriver 60 can also support long-distance L3 data transmission.

[0053] The latency of the re-driver 60 and the multiplexer 50 is significantly smaller than the latency of the communication switch 40. Therefore, even if the re-driver 60 and the multiplexer 50 are provided on the high-speed transfer compatible path P1, there is almost no effect on the communication speed.

[0054] Moreover, it is desirable to place the re-driver 60 at a position where the transmission path loss of the base substrate 20 from the SoC 30 side, which is the high-speed transmission device, does not exceed a predetermined value. This is because even if the re-driver 60 is provided after the occurrence of a transmission path loss exceeding the predetermined value, no waveform correction effect can be obtained. The predetermined value is a criterion (criterion for judgment) for the substrate transmission loss characteristics.

[0055] 8 and employing a system for communicating by PCIe Gen5, it is desirable to place the redriver 60 within a predetermined medium distance L2 from the data transmission end of the SoC 30. This is because even if it is placed away by the long distance L3, the insertion loss becomes large and the effect cannot be fully enjoyed.

[0056] Furthermore, in the PCIe standard, when communication exceeds 10 GT / s such as Gen4 / 5, signal loss in the board transmission path becomes large and long-distance communication becomes impossible. In the configuration of the comparative example shown in Fig. 3 described above, the communication switch 40a serves as a repeater, but there is a risk that signals will continue to attenuate between the SoC 30 and the SoC 31 and long-distance communication will become impossible. As in this embodiment, the effect can be reliably obtained by limiting the placement location to a location where the transmission path loss is smaller than a predetermined value.

[0057] FIG. 9 shows an example of eye patterns before and after the redriver 60. When the communication unit 30c of the SoC 30 transmits a transmission signal through the board wiring of the base board 20, the redriver 60 amplifies the transmission signal and the signal reaches the communication unit 31c of the SoC 31 through the board wiring. At this time, as shown in FIG. 9, although a large amount of jitter occurs at the input of the redriver 60, the redriver 60 can open the eye pattern by shaping the waveform. In addition, the SoC 31 can obtain the transmission data by amplifying the input signal and shaping the data into a rectangular waveform. This makes it possible to minimize the error rate of the transmission data, and to transmit a signal with high signal quality even when performing long-distance L3 communication.

[0058] In this embodiment, the redriver 60 is described as a signal attenuation correction unit, but a retimer or other unit that requires a similar effect may be placed. In addition to the functions of the redriver 60, the retimer has a function of correcting data-dependent jitter components by CDR (Clock Data Recovery). As a result, the eye pattern after passing through the retimer has less jitter than when the signal passes through the redriver 60, and a signal with higher signal quality can be transmitted.

[0059] In addition, as a method for reducing the transmission loss of the board, it is also effective to use a base material with a lower dielectric constant than FR4. In fact, in servers and other devices where high-speed transmission of PCIe Gen4 or higher is frequently used, loss is addressed by adopting low-dielectric base materials such as Megtron4 and Megtron6. For example, in automotive applications, it may be sufficient to make only some paths high-speed, and it is not realistic to use a low-dielectric material only for those paths. Therefore, it is preferable to address this issue by using a redriver 60 rather than changing the base material from FR4.

[0060] (Fourth embodiment) The fourth embodiment will be described with reference to Figs. 10 and 11. The same parts as those in the third embodiment are denoted by the same reference numerals, and the description will be omitted, and the different parts will be described. Fig. 10 shows the configuration of an electronic control device 410 that replaces the electronic control device 310. The redriver 60 is provided with a startup / shutdown terminal, and is configured so that the SoC 30 can stop the power supply to the redriver 60 by sending a shutdown signal to the startup / shutdown terminal of the redriver 60. Also, the SoC 30 can input power to the redriver 60 by sending a startup signal to the startup / shutdown terminal of the redriver 60. The other configurations are the same as those in the third embodiment, and therefore the description will be omitted.

[0061] A flowchart replacing Fig. 5 is shown in Fig. 11. For example, when the SoC 30 selects the normal transfer path P2 and communicates by Gen3 through the normal transfer path P2, the SoC 30 inputs a shutdown signal to the startup / shutdown terminal of the redriver 60 as shown in S10 before switching to the normal transfer path P2 in S3 of Fig. 11. This desirably stops the operation of the redriver 60. When the normal transfer path P2 is selected, the redriver 60 is in an unused state, and therefore, by stopping the operation of the redriver 60, standby power can be reduced.

[0062] For example, when the SoC30 selects the high-speed transfer compatible path P1 and communicates by Gen5 through the high-speed transfer compatible path P1, the SoC30 inputs a startup signal to the startup / shutdown terminal of the redriver 60 in S11 before switching to the high-speed transfer compatible path P1 in S7 of Fig. 11. Starting up the redriver 60 enables high-speed communication with good signal quality between the SoC30 and the SoC31. This allows the standby power of the redriver 60 to be reduced without impairing the communication function, and allows the power consumption to be reduced.

[0063] (Other embodiments) The present invention is not limited to the above-described embodiment, and the following modifications and extensions are possible. The multiple devices shown in the present disclosure may each be, for example, an electronic circuit, a block of an electronic control circuit, an integrated circuit device, or a memory, and are not limited to the SoCs 30 to 32 and memory unit 33 exemplified in the above-described embodiment.

[0064] In addition, while the embodiment has been described in which the SoCs 30 to 32 and the memory unit 33 are mounted on different substrates, i.e., the base substrate 20, the first extension substrate 21, the second extension substrate 22, and the third extension substrate 23, the present invention is not limited to this. A plurality of devices may be mounted on the same substrate. For example, the present invention may be applied to a configuration in which the SoCs 30 and 31 are mounted on the same base substrate 20. Although the embodiment has been described in which the PCIe is adopted, the communication protocol is not limited to this example.

[0065] The techniques described in the present disclosure may be implemented by a special purpose computer provided by configuring a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the techniques described in the present disclosure may be implemented by a special purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the techniques described in the present disclosure may be implemented by one or more special purpose computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured with one or more hardware logic circuits. Also, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions executed by the computer.

[0066] Although the present disclosure has been described based on the above-mentioned embodiment, it is understood that the present disclosure is not limited to the embodiment or the structure described in the embodiment. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0067] In the drawings, 10, 210, 310, and 410 indicate electronic control devices, 30 to 32 indicate SoCs (devices), 33 indicates a memory device (device), 40 indicates a communication switch, 50 indicates a multiplexer, and 60 indicates a re-driver (signal attenuation correction unit).

Claims

1. Three or more devices (30, 31, 32, 33) compatible with a predetermined communication protocol; a communication switch (40) capable of applying the predetermined communication protocol; When communication between at least two of the plurality of devices is possible at a higher speed than communication between other combinations of devices, direct communication is performed only between the at least two devices; The communication switch is configured to allow communication between devices other than the two devices that directly communicate with each other, An electronic control device, wherein the communication speed through the communication switch is slower than the speed of direct communication between the two devices.

2. 2. The electronic control device according to claim 1, further comprising a multiplexer (50) for switching between a high-speed transfer compatible path for direct communication between the two devices and a normal transfer path for communication via the communication switch.

3. 3. The electronic control device according to claim 2, further comprising a signal attenuation correction unit (60) between the multiplexer and a transmitting device that transmits through the high-speed transfer compatible path.

4. 4. The electronic control device according to claim 3, wherein the signal attenuation correction unit is disposed at a position where a board transmission path loss from the transmitting device side does not exceed a predetermined value.

5. At least one of the two devices is a device capable of high-speed communication with respect to a data transmission destination, and 3. The electronic control device according to claim 2, wherein said multiplexer switches so as to select said high-speed transfer compatible path in the case of data requiring high-speed transfer, and selects said normal transfer path in the other cases.

6. 4. The electronic control device according to claim 3, wherein at least one of the two devices stops operation of the signal attenuation correction unit when the normal transfer path is selected.

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