Phase control device and phase control method

Abstract

To provide a phase control device and a phase control method capable of correcting the residual frequency offset and the phase offset of a phase-modulated received signal accurately and quickly.SOLUTION: An APC 812 provided in a receiving portion of a wireless communication device includes a normalization unit 91 that normalizes the amplitude of a phase-modulated received signal, a hard decision unit 93 that performs hard decision processing on the normalized received signal and outputs a hard decision signal, a subtraction unit 94 that calculates an error in the received signal from the difference between the hard decision signal and the normalized received signal, an LMS 95 that generates and updates tap coefficients on the basis of the error of the received signal, and a multiplication unit 97 that corrects the residual frequency offset and the phase offset of the received signal on the basis of the tap coefficients.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a phase control device and a phase control method for correcting a residual frequency offset and a phase offset of a phase-modulated received signal. [Background technology]

[0002] In digital communication, one of the methods for improving the efficiency of frequency band utilization and increasing the speed of data communication is to multi-value digital modulation and demodulation using a modulation method that uses phase information to identify data, such as quadrature amplitude modulation (QAM) and phase shift keying (PSK). In a wireless communication system using such a modulation method, a frequency error occurs in a local signal used for frequency shifting between a transmitter and a receiver, and a frequency offset and a phase offset are added to a received signal. The frequency offset is corrected by AFC (Automatic Frequency Control) of the wireless receiving device, but a residual frequency offset often occurs due to an estimation error at that time. A wireless receiving device equipped with APC (Automatic Phase Control) is known to correct this residual frequency offset and phase offset (see, for example, Patent Document 1).

[0003] For example, the LMS (Least Mean Square) algorithm is used to correct the residual frequency offset and phase offset by the APC. The LMS algorithm calculates correction weights (tap coefficients) by multiplying the input signal to the APC with a signal obtained by subtracting the output signal of the APC from a signal obtained by hard-deciding the output signal of the APC. The APC multiplies the input signal by the tap coefficients to correct the residual frequency offset and phase offset of the received signal.

[0004] However, the tap coefficients calculated by the LMS algorithm shift the received signal not only in the phase direction but also in the amplitude direction, so if a received signal with ideal symbol points arranged on multiple envelopes, such as 16APSK (amplitude and phase-shift keying), is received in a low CNR (career-to-noise ratio) state and processed by APC, incorrect correction will be performed in the amplitude direction.

[0005] In order to solve the above problems, a method of normalizing the amplitude of the tap coefficients is known (see, for example, Patent Document 2). Fig. 9 shows an example of an APC using normalization of the amplitude of the tap coefficients, and Fig. 10 shows an LMS processing unit of the APC 100 shown in Fig. 9. The APC 100 includes a hard decision unit 101, a subtraction unit 102, an LMS 103, a conjugate transformation unit (conj) 104, and a multiplication unit 105.

[0006] The hard decision section 101 extracts the coordinate values ​​of the symbol points from the output signal (received signal) of the APC 100, performs hard decision on the extracted coordinate values ​​of the symbol points, and outputs a hard decision signal in which the coordinate values ​​of the symbol points are corrected to the coordinate values ​​that should be taken based on the hard decision result. Here, hard decision refers to a process of deciding the ideal coordinate values ​​that should be taken based on the coordinate values ​​of the judged symbol point, which is the symbol point to be judged. The subtraction section 102 subtracts the output signal of the APC 100 from the hard decision signal to find the error e(n) of the output signal, and outputs it to the LMS 103.

[0007] The LMS 103 includes a conjugate conversion unit (conj) 1031, a multiplication unit 1032, an addition unit 1033, and a delay adjustment unit (Z -1 The multiplication unit 1032 multiplies an input signal (received signal) x(n) of the APC 100 by an error e(n) converted to a complex conjugate number by the conjugate conversion unit 1031 by μ, which is an update coefficient for the tap coefficient, and outputs the result to an addition unit 1033. The addition unit 1033 adds the output signal of the multiplication unit 1032 and a tap coefficient w(n) output from the LMS 103, and outputs the tap coefficient w(n+1) to the delay adjustment unit 1034. The delay adjustment unit 1034 performs delay adjustment on the tap coefficient w(n+1) and outputs the tap coefficient w(n) to the normalization unit 1035. The normalization unit 1035 normalizes the amplitude of the tap coefficient w(n) and outputs it to the conjugate transformation unit 104 of the APC 100.

[0008] Multiplication section 105 of APC 100 multiplies input signal (received signal) x(n) by tap coefficient w(n) converted to a conjugate complex number by conjugate conversion section 104, and outputs a received signal (output signal) in which the residual frequency offset and phase offset have been corrected. In this way, by normalizing the amplitude of the tap coefficient within the feedback loop of the LMS algorithm, erroneous correction in the amplitude direction of the received signal can be suppressed. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2004-364157 A [Patent Document 2] JP 2007-028161 A Summary of the Invention [Problem to be solved by the invention]

[0010] To speed up the above APC processing, it has been considered to implement the APC in an FPGA (Field Programmable Gate Array). However, because the normalization of the amplitude of the tap coefficient requires calculation of the amplitude of the input signal and division processing, if the FPGA operating clock is fast, it becomes difficult to perform the normalization processing in the feedback loop of the LMS algorithm within one FPGA clock, and a timing error occurs. As a countermeasure to the timing error, a pipeline can be inserted, but this distorts the calculation formula of the LMS algorithm and causes it to not operate correctly.

[0011] SUMMARY OF THE PRESENT EMBODIMENTS An object of the present invention is to provide a phase control device and a phase control method capable of correcting the residual frequency offset and phase offset of a phase-modulated received signal accurately and at high speed. [Means for solving the problem]

[0012] In order to solve the above problem, the invention described in claim 1 is a phase control device comprising: normalization means for normalizing the amplitude of a phase-modulated received signal; hard decision means for performing hard decision processing on the normalized received signal to output a hard decision signal; error calculation means for calculating an error in the received signal from a difference between the hard decision signal and the normalized received signal; tap coefficient generation means for generating and updating tap coefficients based on the error of the received signal; and correction means for correcting a residual frequency offset and a phase offset of the received signal based on the tap coefficients.

[0013] The invention described in claim 2 is a phase control method characterized by normalizing the amplitude of a phase-modulated received signal, performing hard decision processing on the normalized received signal to output a hard decision signal, calculating an error of the received signal from a difference between the hard decision signal and the normalized received signal, generating and updating tap coefficients based on the error of the received signal, and correcting a residual frequency offset and a phase offset of the received signal based on the tap coefficients. Effect of the Invention

[0014] According to the inventions described in claims 1 and 2, since the normalization process is performed outside the feedback loop of the LMS algorithm, it is possible to implement it in an FPGA with a high-speed operating clock. [Brief description of the drawings]

[0015] [Figure 1] 1 is a diagram showing a schematic configuration of a wireless communication system according to an embodiment of the present invention; [Diagram 2] 2 is a functional block diagram showing a schematic configuration of a transmission unit of the wireless communication device shown in FIG. [Diagram 3] 2 is a functional block diagram showing a schematic configuration of a receiving section of the wireless communication device shown in FIG. [Figure 4] 3 is a diagram showing a frame structure of a data frame transmitted from a transmitting unit shown in FIG. 2. [Diagram 5] FIG. 2 is a diagram showing a constellation of symbol points of a received signal modulated with 16APSK. [Figure 6] FIG. 4 is a block diagram showing a schematic configuration of an APC812 shown in FIG. [Figure 7] FIG. 7 is a block diagram showing a schematic configuration of the LMS shown in FIG. 6. [Figure 8] This is a constellation of symbol points showing the normalized amplitude of a received signal modulated with 16APSK. [Figure 9] FIG. 1 is a block diagram showing a schematic configuration of a conventional APC that normalizes tap coefficients within the feedback of an LMS. [Figure 10] FIG. 10 is a block diagram showing a schematic configuration of the LMS shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention will be described below based on the embodiments shown in the drawings. Note that, in the following, only the characteristic configuration of the present invention will be described, and a description of the same mechanism as the conventional one for performing wireless communication will be omitted.

[0017] 1 is a diagram showing a schematic configuration of a wireless communication system 1 using a wireless communication device (wireless receiving device) 2 according to an embodiment of the present invention. A wireless communication device 2 and an antenna 3 are arranged in each of wireless communication transmitting and receiving stations constituting the wireless communication system 1. The wireless communication devices 2 are connected to each other by a wireless line 4 via the antenna 3. Note that a communication satellite or the like may be used as a relay station in the wireless line 4.

[0018] First, in this embodiment, a schematic configuration of a wireless communication device 2 equipped with a phase control device according to the present invention will be described.

[0019] The wireless communication device 2 includes an interface unit 5, a transmitter 6, a splitter 7, and a receiver 8 (see the lower part of FIG. 1).

[0020] Here, the wireless communication device 2 is a device that is equipped with a transmission mechanism and a reception mechanism and transmits and receives data. In the following description, the wireless communication device 2 when performing processing related to transmission using the transmission mechanism is referred to as the "transmitting side," and the wireless communication device 2 when performing processing related to reception using the reception mechanism is referred to as the "receiving side."

[0021] The interface unit 5 mainly includes a data circuit-terminating device 51 (including devices called data communication devices and data circuit devices). The interface unit 5 receives transmission data to be transmitted, and outputs the transmission data to the transmitting unit 6 via the data circuit-terminating device 51.

[0022] The transmitter 6 receives the transmission data output from the interface 5, generates a data frame by combining a data signal obtained by mapping the transmission data with an alternating signal used to correct a clock error, and further superimposes a carrier signal of a predetermined frequency on the data frame to perform digital modulation. Note that the modulation method used in the wireless communication system 1 is not limited to a specific method, but 16APSK, for example, is used.

[0023] The transmitter 6 converts the digitally modulated data frame into an analog signal, converts the signal into a high-frequency signal having a frequency higher than a predetermined frequency, amplifies the signal with a power amplifier, and outputs the signal as a transmission signal. The transmission signal is guided from the transmitter 6 via the splitter 7 to the antenna 3, and is then transmitted in a burst as radio waves from the antenna 3 via the wireless line 4 to the antenna 3 of the other wireless communication device 2 (in other words, the receiving side in this communication).

[0024] In addition, when a transmission signal is transmitted in bursts as radio waves from the antenna 3 of the other wireless communication device 2 (in other words, the transmitting side in this communication) to the antenna 3 of the wireless communication device 2 (in other words, the receiving side in this communication) via wireless line 4, the antenna 3 converts the received radio waves into an electrical signal (received signal) and outputs it.

[0025] The received signal output from the antenna 3 is guided to the receiving unit 8 via the branching filter 7. The receiving unit 8 receives the received signal, passes it through a channel filter that passes only signals in a predetermined frequency band, and converts it into a signal with a frequency lower than the high frequency. The receiving unit 8 further converts the frequency-converted received signal into a digital signal and outputs it.

[0026] The receiver 8 performs quadrature detection processing (demodulation) on the digital received signal to generate an in-phase component (Ich) baseband signal and a quadrature component (Qch) baseband signal, the phases of which are orthogonal to each other. In the following explanation, the in-phase component and the quadrature component will not be particularly distinguished from each other and will be explained as being common to both, except when it is necessary to focus on the in-phase component and the quadrature component separately, and in the drawings, the in-phase component signal and the quadrature component signal are represented by a single signal line.

[0027] The receiver 8 performs burst detection based on the demodulated baseband signal. When the arrival of a data frame is detected by this burst detection, the receiver 8 performs frequency offset correction, clock error correction, phase correction, etc. on the received data frame. The receiver 8 then separates the alternating signal from the data frame that has been subjected to various corrections, performs demapping on the data signal to generate transmission data, and outputs it to the interface 5.

[0028] In the burst detection according to the present embodiment, a data frame to which an alternating signal is added as a preamble signal is burst-transmitted from the wireless communication device 2 on the transmitting side, and the arrival of the data frame is detected by detecting the alternating signal from the receiving means that receives and outputs the data frame. This eliminates the need to add a CW signal for burst signal detection to the data frame, thereby improving the throughput of burst communication.

[0029] 2 is a functional block diagram showing a schematic configuration of the transmission unit 6. The transmission unit 6 includes a FIFO memory 61, a mapping unit 62, an alternating signal generation unit 63, a combining unit 64, a transmission ROF 65, a quadrature modulation unit 66, a DAC (Digital Analog Converter) 67, a mixer 68, a local oscillator 69, and a power amplifier 610.

[0030] The FIFO memory 61 is a memory that temporarily stores the transmission data output from the interface unit 5 and outputs it to the mapping unit 62, and transfers the transmission data to the mapping unit 62 on a so-called first-in first-out basis.

[0031] The mapping unit 62 performs mapping processing on the binary data string of the transmission data so as to form a predetermined signal point arrangement, generates a data signal consisting of a symbol string, and outputs the data signal to the combining unit 64. The alternating signal generating unit 63 generates an alternating signal used to correct the clock error, and outputs the alternating signal to the combining unit 64.

[0032] The combiner 64 combines the alternating signal input from the alternating signal generator 63 with the beginning of the data signal input from the mapping unit 62 to generate a data frame DF (see FIG. 4 ) and outputs it to the transmission ROF 65. The transmission ROF 65 has a roll-off filter function and is connected to the combiner 64. The data frame DF input from the input section 63 is subjected to band limiting processing and output to the quadrature modulation section 66 .

[0033] The quadrature modulation unit 66 superimposes a carrier signal of a predetermined frequency on the data frame DF input from the transmission ROF 65, digitally modulates it, and outputs it to the DAC 67. Note that the modulation method used in the quadrature modulation unit 66 is not limited to a specific method, but for example, quadrature amplitude modulation is used.

[0034] The DAC 67 converts the data frame DF input from the quadrature modulation unit 66 into an analog transmission signal and outputs it to the mixer 68. The local oscillator 69 generates a local oscillation signal having a predetermined fixed frequency and outputs the generated local oscillation signal to the mixer 68. The mixer 68 mixes the local oscillation signal with the transmission signal input from the DAC 67 to convert it into a signal with a higher frequency than the predetermined frequency.

[0035] The power amplifier 610 amplifies the transmission signal frequency-converted by the mixer 68 and outputs it to the antenna 3. The antenna 3 transmits the transmission signal amplified by the power amplifier 610 as a radio wave to the antenna 3 of the other wireless communication device 2 (in other words, the receiving side in this communication). Although not shown, a splitter 7 is connected between the power amplifier 610 and the antenna 3.

[0036] As shown in FIG. 4, the transmitting unit 6 of this embodiment transmits a data frame DF consisting of an alternating signal and a data signal, thereby improving the throughput of burst communication compared to the conventional case in which a CW signal is added.

[0037] 3 is a functional block diagram showing a schematic configuration of the receiving unit 8. The receiving unit 8 includes a channel filter 81, a mixer 82, a local oscillator 83, a variable ATT (attenuator) 84, an ADC (Analog Digital Converter) 85, a quadrature detection unit 86, a burst detection unit 87, a timing control unit 88, an AFC (Automatic frequency control) 89, a receiving ROF 810, a symbol recovery unit 811, an APC (Automatic Phase Control) 812, a separator 813, a demapping unit 814, an AGC 815, and a DAC 816.

[0038] The antenna 3 converts the received radio waves into an electric signal (received signal) and outputs it to the channel filter 81. The splitter 7 is connected between the antenna 3 and the channel filter 81. The channel filter 81 passes a predetermined frequency band of the received signal input from the antenna 3 and outputs it to the mixer 82. The local oscillator 83 generates a local oscillation signal having a predetermined fixed frequency and outputs the generated local oscillation signal to the mixer 82. The mixer 82 mixes the local oscillation signal with the received signal input from the channel filter 81 to convert it into a signal with a frequency lower than the predetermined frequency, and outputs it to the variable ATT 84.

[0039] The variable ATT 84 includes an attenuator, and adjusts the attenuation amount of the received signal output from the mixer 82 in response to an external signal to attenuate the signal and output the attenuated signal to the ADC 85. The attenuation amount in the variable ATT 84 changes based on a control signal of the AGC 815 supplied via the DAC 816.

[0040] The ADC 85 converts into a digital signal the received signal input from the variable ATT 84. The quadrature detection unit 86 performs quadrature detection processing on the received signal to generate an in-phase component (Ich) baseband signal and a quadrature component (Qch) baseband signal whose phases are orthogonal to each other.

[0041] FIG. 5 is a diagram showing a constellation of the 16APSK baseband signal generated by the quadrature detection unit 85 on an IQ plane (a coordinate plane with Ich on the horizontal axis and Qch on the vertical axis). The 16APSK baseband signal is centered on the intersection of Ich and Qch. Sixteen signal points (symbols) are arranged on a double circular envelope.

[0042] The burst detection unit 87 performs burst detection from the baseband signal input from the quadrature detection unit 86. When the burst detection unit 87 detects the arrival of a data frame DF by burst detection, it outputs a detection flag to the timing control unit 88. The timing control unit 88, to which the detection flag has been input, outputs an enable signal to each module to cause it to process the data frame DF.

[0043] In response to an enable signal from the timing control unit 88, the AFC 89 performs frequency offset correction on the data frame DF of the baseband signal and outputs the result to the receive ROF 810. The receive ROF 810 has a roll-off filter function, and performs band limiting processing on the baseband signal input from the AFC 89 and outputs the result to the symbol recovery unit 811.

[0044] The symbol recovery unit 811 corrects the clock error using an alternating signal included in the data frame DF of the baseband signal input from the reception ROF 810, and outputs the corrected signal to an APC (phase control device) 812. The APC 812 corrects the residual frequency offset and phase offset of the data frame DF of the baseband signal input from the symbol recovery unit 811, and outputs the corrected signal to a separation unit 813.

[0045] The separator 813 separates the data signal from the data frame DF and outputs the data signal to the demapping unit 814. The demapping unit 814 performs demapping processing (decoding processing) on ​​the signal (each of the in-phase component and the quadrature component) consisting of the symbol sequence data input from the separator 813, converts the symbol sequence data into transmission data of a binary data sequence, and outputs the transmission data to the interface unit 5.

[0046] Fig. 6 is a block diagram showing the functional configuration of the APC 812, and Fig. 7 shows the LMS processing unit of the APC 812. The APC 812 includes a normalization unit (normalization means) 91, a multiplication unit 92, a hard decision unit (hard decision means) 93, a subtraction unit (error calculation means) 94, an LMS (tap coefficient generation means) 95, a conjugate conversion unit (conj) 96, and a multiplication unit (correction means) 97.

[0047] The normalization unit 91 normalizes the amplitude of the received signal (input signal) input from the symbol recovery unit 811 and outputs the normalized signal to the multiplication unit 92. The received signal whose amplitude has been normalized changes from a state in which 16 symbol points are arranged on a double envelope as shown in Fig. 5 to a state in which 12 symbol points are arranged on a single envelope as shown in Fig. 8. The multiplication unit 92 multiplies the received signal x(n) whose amplitude has been normalized by the tap coefficient w(n) input from the conjugate transformation unit 96, and outputs the result to the hard decision unit 93.

[0048] The hard decision unit 93 extracts the coordinate values ​​of the symbol point from the output signal x(n) from the multiplication unit 92, performs hard decision on the extracted coordinate values ​​of the symbol point, and outputs a hard decision signal in which the coordinate values ​​of the symbol point are corrected to the coordinate values ​​of the ideal symbol point that they should be based on the hard decision result. Note that for the ideal symbol point used in the hard decision, mapping normalized by the normalization unit 91 is used, as shown in FIG. 8. The subtraction unit 94 subtracts the output signal x(n) from the multiplication unit 92 from the hard decision signal to obtain an error e(n) of the output signal, and outputs it to the LMS 95.

[0049] The LMS 95 includes a conjugate conversion unit (conj) 951, a multiplication unit 952, an addition unit 953, and a delay adjustment unit (Z -1 ) 954 and is equipped with.

[0050] The multiplication unit 952 multiplies the normalized received signal x(n), the error e(n) converted to a conjugate complex number by the conjugate conversion unit 951, and μ, which is an update coefficient for the tap coefficient, and outputs the result to the addition unit 955. The adder 953 adds the output signal of the multiplier 952 and the tap coefficient w(n) output from the LMS 95, and outputs the tap coefficient w(n+1) to a delay adjuster 954. The delay adjuster 954 performs delay adjustment on the tap coefficient w(n+1), and outputs the tap coefficient w(n) to the conjugate transformer 96 of the APC 812.

[0051] The multiplier 97 of the APC 812 multiplies the input signal before normalization (the state shown in FIG. 5 ) by the tap coefficient w(n) converted to a conjugate complex number by the conjugate converter 96, and outputs the received signal (output signal) in which the residual frequency offset and phase offset have been corrected to the separator 813.

[0052] According to the wireless communication device 2 of the present embodiment, normalization processing is performed outside the feedback loop of the LMS95 algorithm, so that it can be implemented in an FPGA with a high-speed operating clock.

[0053] Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above embodiment, and even if there are design changes and the like within the scope of the gist of the present invention, they are included in the present invention. [Explanation of symbols]

[0054] 1. Wireless communication systems 2. Wireless communication devices 5. Transmitter 8 Receiving section 812 APC (Phase Control Device) 91 Normalization unit (normalization means) 92 Multiplication section 93 Hard decision section (hard decision means) 94 Subtraction section (error calculation means) 95 LMS (tap coefficient generation means) 951 Conjugate conversion unit 952 Multiplication section 953 Addition section 954 Delay Adjustment Unit 96 Conjugate conversion section 97 Multiplication unit (correction means)

Claims

1. a normalization means for normalizing the amplitude of the phase modulated received signal; a hard decision means for performing a hard decision process on the normalized received signal and outputting a hard decision signal; an error calculation means for calculating an error of the received signal from a difference between the hard decision signal and the normalized received signal; a tap coefficient generating means for generating and updating tap coefficients based on an error of the received signal; a correction means for correcting a residual frequency offset and a phase offset of the received signal based on the tap coefficients; A phase control device comprising:

2. Normalize the amplitude of the phase modulated received signal; performing a hard decision process on the normalized received signal to output a hard decision signal; Calculating an error of the received signal from a difference between the hard decision signal and the normalized received signal; generating and updating tap coefficients based on the error of the received signal; correcting a residual frequency offset and a phase offset of the received signal based on the tap coefficients; A phase control method comprising:

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