Phase synchronizing device, communication apparatus and phase synchronizing method

Abstract

To provide a phase synchronizing device, etc., capable of suppressing the occurrence of Wander in an output clock signal.SOLUTION: A phase synchronizing device comprises: a phase comparison section for comparing phases between a frequency divided reference clock signal, for which a frequency of a reference clock signal is divided, and an output frequency divided signal for which a frequency of a fed-back output clock signal is divided; a random number generation section for generating a random number value within a range of fluctuation of a non-principal portion which is a portion of a value indicated by a result of the comparison of phases less than a predetermined value; an addition section for performing addition processing in which, in a case where the non-principal portion is more than the random number value, the predetermined value is added to a principal portion of the value indicated by the result of the comparison of phases equal to or more than the predetermined value and in a case where the non-principal portion is equal to or less than the random number value, the predetermined value is not added to the principal portion in the result of the comparison of phases; and an output section for outputting the output clock signal generated using a rectangular wave generated using a value of the principal portion on which the addition processing is performed as a value representing a duty.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a phase synchronization device, a communication device, and a phase synchronization method. [Background technology]

[0002] In digital PLL (Phase Locked Loop) circuits, the phase difference between the master clock and the slave clock is generally expressed by the number of counted pulses of the divided clock, which can cause various problems.

[0003] Patent Document 1 discloses a digital PLL circuit in which the pull-in operation is not affected by the range limit of the phase difference detection value representing the number of pulses described above. The phase difference detector of the PLL circuit of Patent Document 1 outputs a phase difference detection value whose length takes a value within a range of 2π. The correction unit corrects the phase difference detection value to a phase value that is not limited to the range. The slave clock generation unit generates a slave clock according to the phase value output by the correction unit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-199815 A Summary of the Invention [Problem to be solved by the invention]

[0005] In a digital PLL circuit, the duty (usage) of a square wave is controlled according to the result of the phase difference comparison. This duty represents, for example, the time that the high state continues in the square wave. However, digital errors occur in the process from the digital calculation of the phase difference in the phase comparator to the generation of a square wave by duty control using the result of the digital calculation.

[0006] Specifically, the value representing the phase difference is represented by, for example, the number of pulses. If the phase difference is not divisible by the length of the pulse and includes a portion that is a multiple of the length of one pulse and a fractional portion that is less than one pulse, the fractional portion is, for example, truncated and not used for DUTY control. As a result, the output of the phase difference output device representing the phase difference between the master clock (in other words, the reference clock signal) and the slave clock (in other words, the output clock signal) described above is not necessarily constant. In other words, a positive error of the fraction is accumulated, and when the accumulated error exceeds the length of one pulse, the phase difference increases by 1. Then, the error is reduced by adding a negative error of the fraction, and when the accumulated error falls below the length of one pulse, the phase difference decreases by 1. In this way, the increase and decrease of the phase difference are repeated slowly. As a result, wander occurs in the output clock signal. This wander is a periodic increase and decrease in the duration of the rectangular wave of the output clock signal in a high state.

[0007] The technology of Patent Document 1 can suppress the influence of the pull-in operation due to the range limit of the phase difference detection value. However, in the technology of Patent Document 1, the number of phase difference pulses is used as it is to generate the slave clock. Therefore, the technology of Patent Document 1 cannot suppress the occurrence of wander in the output clock signal.

[0008] An object of the present disclosure is to provide a phase synchronization device, a communication device, and a phase synchronization method that can suppress the occurrence of wander in an output clock signal. [Means for solving the problem]

[0009] A phase synchronization device according to one aspect of the present disclosure includes a phase comparison unit that compares the phase of a divided reference clock signal obtained by dividing a reference clock signal with an output divided signal obtained by dividing a fed-back output clock signal; a random number generation unit that generates a random value within the range of variation of a non-major part, which is a part of a value indicated by a result of the phase comparison that is less than a predetermined value; an addition unit that performs an addition process in which, if the non-major part is larger than the random value, the predetermined value is added to a major part, which is a part of the value indicated by the result of the phase comparison that is equal to or greater than the predetermined value, and if the non-major part is equal to or less than the random value, the predetermined value is not added to the major part of the result of the phase comparison; and an output unit that outputs the output clock signal generated using a rectangular wave generated using the value of the major part subjected to the addition process as a value representing a duty.

[0010] A phase synchronization method according to one aspect of the present disclosure performs an addition process in which a divided reference clock signal obtained by dividing a reference clock signal and an output divided signal obtained by dividing a fed-back output clock signal are compared in phase, a random number value is generated within a range of variation of a non-major part of a value indicated by the result of the phase comparison that is less than a predetermined value, and if the non-major part is greater than the random number value, the predetermined value is added to a major part of the value indicated by the result of the phase comparison that is greater than or equal to the predetermined value, and if the non-major part is less than or equal to the random number value, the predetermined value is not added to the major part of the result of the phase comparison, and an output clock signal generated using a rectangular wave generated using the value of the major part subjected to the addition process as a value representing a duty is output. Effect of the Invention

[0011] The present disclosure has an effect of suppressing the occurrence of wander in an output clock signal. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a digital phase-locked loop according to an embodiment of the present disclosure. [Diagram 2]FIG. 2 is a diagram illustrating an example of the configuration of a digital phase-locked loop according to a comparative example of the present disclosure. [Diagram 3] FIG. 3 is a diagram illustrating a schematic diagram of signals in a digital phase-locked loop according to a comparative example of the present disclosure. [Figure 4] FIG. 4 is a block diagram illustrating an example of a configuration of a communication system according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram illustrating a schematic diagram of signals in a digital phase-locked loop according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a block diagram illustrating an example of the configuration of a phase synchronization device according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a flowchart illustrating an example of the operation of the phase synchronization device according to the embodiment of the present disclosure. [Figure 8] FIG. 8 is a block diagram illustrating an example of the configuration of a phase synchronization device according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a flowchart illustrating an example of the operation of the phase synchronization device according to the embodiment of the present disclosure. [Figure 10] FIG. 10 is a flowchart illustrating an example of the operation of the phase synchronization device according to the embodiment of the present disclosure. [Figure 11] FIG. 11 is a flowchart illustrating the operation of the addition process of the phase synchronization device according to the embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram illustrating an example of a hardware configuration of a computer capable of realizing a phase synchronization device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Before describing the embodiments of the present disclosure, comparative examples of the present disclosure will be described in detail below with reference to the drawings.

[0014] <Comparative Example> FIG. 2 is a diagram illustrating an example of the configuration of a digital phase-locked loop according to a comparative example of the present disclosure.

[0015] A digital phase-locked loop (hereinafter also referred to as a digital PLL circuit) according to a comparative example of the present disclosure will be described below with reference to FIG.

[0016] In the example shown in FIG. 2, the digital PLL circuit of this comparative example includes two frequency dividers 1, a phase comparator 2, a rectangular wave generator 3, an analog LPF (Low-Pass Filter) 4, and a VCO (Voltage-Controlled Oscillator) 5.

[0017] A reference clock signal (hereinafter also referred to as reference clock) to be tracked and an output clock signal (hereinafter also referred to as output clock) are input to the two frequency dividers 1, respectively. The frequency divider 1 to which the reference clock is input divides the frequency of the input reference clock to generate a divided reference clock signal, which is a divided signal obtained by dividing the frequency of the reference clock. The frequency divider 1 to which the output clock is input divides the frequency of the input output clock signal to generate a divided output clock signal, which is a divided signal obtained by dividing the frequency of the output clock signal. The division ratios of the two frequency dividers 1 are the same.

[0018] The phase comparator 2 compares the phase of the frequency-divided reference clock signal with the phase between the frequency-divided output clock signals. Specifically, the phase comparator 2 calculates the phase difference between the frequency-divided reference clock signal and the frequency-divided output clock signal by digital calculation. The phase comparator 2 outputs the phase difference, which is expressed as a real number between the phase of the frequency-divided reference clock signal and the phase between the frequency-divided output clock signals, as the phase difference and rounds it to an integer. The process of rounding the phase difference by the phase comparator 2 is, for example, any of predetermined processes among rounding down, rounding up, and rounding up.

[0019] The square wave generator 3 generates a square signal, which is a square wave signal, from the calculated phase difference. Specifically, the square wave generator 3 generates a square wave whose DUTY (also written as duty) is a value according to the calculated phase difference. DUTY is a value indicating the time during which a state in which the signal value in the square wave is high continues. The DUTY value may be, for example, a value obtained by multiplying the phase difference value by a predetermined coefficient.

[0020] The analog LPF 4 smoothes the generated rectangular signal by suppressing high frequency components, thereby converting the rectangular signal into a voltage.

[0021] The VCO 5 generates, from the signal output from the analog LPF 4, an output clock signal having a frequency that corresponds to the voltage level of the signal.

[0022] In order to make the output clock follow the reference clock, the square wave generator 3 controls the duty of the square wave using the phase difference resulting from the phase comparison. The unit of the phase difference may be appropriately determined. For example, a real number multiple such as "degrees" or "radians" may be the unit of the phase difference in the description of the present disclosure (i.e., the phase difference represented by 1 in the description of the present disclosure). For example, the integer part of the phase difference is used as this phase difference. In this case, the phase difference is, for example, an integer phase difference obtained by rounding a phase difference that is not actually limited to an integer. In other words, the fractional part less than 1 is a phase difference that has been truncated. In other words, the phase difference resulting from the phase comparison is a phase difference that includes an error (i.e., a digital error) less than 1 that occurs by rounding the phase difference. This digital error is, for example, an error that occurs between the phase difference considered to be an integer and the actual phase difference by considering the phase difference as an integer.

[0023] In the process in which the square wave generator 3 generates a square wave by duty control using the result of the digital calculation of the phase comparator 2 (i.e., the phase difference), the square wave is affected by the digital error generated by the digital calculation. The difference between the actual phase difference and the phase difference to be output (i.e., the above-mentioned digital error) is accumulated. In other words, it is added to the digital error to be calculated next. If the actual phase difference is larger than the integer phase difference output by the phase comparator 2, the actual digital error increases. If the value of the increased digital error exceeds 1, the output phase difference increases by 1. If the actual phase difference is smaller than the integer phase difference output by the phase comparator 2, the digital error decreases. If the decreased digital error falls below 0, the output phase difference decreases by 1. In this way, the increase and decrease of the phase difference are repeated slowly. This causes wander in the output clock signal. This wander is the periodic repetition of high and low states of the frequency of the output clock signal.

[0024] FIG. 3 is a diagram illustrating a schematic diagram of signals in a digital phase-locked loop according to a comparative example of the present disclosure.

[0025] "Reference clock (divider output)" in Figure 3 represents the waveform of the divided reference clock signal. "Output clock (divider output)" represents the waveform of the divided output clock signal. "Phase comparator output (DUTY) control" is a value representing the phase difference output by phase comparator 2. "Square wave" is the waveform of the square wave output by square wave generator 3. The LPF output represents the voltage transition of the signal output from analog LPF 4. When the duty of the square wave output by square wave generator 3 increases, the LPF output increases slowly due to smoothing by analog LPF 4. Also, when the duty of the square wave output by square wave generator 3 decreases, the LPF output decreases slowly due to smoothing by analog LPF 4. This causes wander in the output clock signal.

[0026] In the example shown in FIG. 3, wander occurs in which a time period during which an output clock signal with a frequency when the phase difference is 8 is output and a time period during which an output clock signal with a frequency when the phase difference is 9 are output alternately.

[0027] <First embodiment> Next, a first embodiment of the present disclosure will be described in detail with reference to the drawings.

[0028] <Configuration> FIG. 1 is a diagram illustrating an example of the configuration of a digital phase-locked loop according to an embodiment of the present disclosure.

[0029] Hereinafter, the configuration of a digital phase-locked loop according to a first embodiment of the present disclosure will be described with reference to FIG.

[0030] 1, the digital PLL circuit includes two frequency dividers 10, a phase comparator 20, a square wave generator 30, an analog LPF 40, and a VCO 50. The digital PLL circuit further includes a random number generator 60, a correction determiner 70, and an adder 80 between the phase comparator 20 and the square wave generator 30. In FIG. 1, the part indicated by "+1" is the adder 80.

[0031] A reference clock signal (also referred to as reference clock as described above) to be tracked and an output clock signal (also referred to as output clock as described above) are input to the two frequency dividers 10, respectively. Frequency divider 10 to which the reference clock is input divides the frequency of the input reference clock to generate a frequency-divided reference clock signal, which is a frequency-divided signal obtained by dividing the frequency of the reference clock. Frequency divider 10 to which the output clock is input divides the frequency of the input output clock signal to generate a frequency-divided output clock signal, which is a frequency-divided signal obtained by dividing the frequency of the output clock signal.

[0032] The phase comparator 20 compares the phase of the frequency-divided reference clock signal with the phase between the frequency-divided output clock signals. Specifically, the phase comparator 20 calculates the phase difference between the frequency-divided reference clock signal and the frequency-divided output clock signal by digital calculation. The phase comparator 20 outputs a portion of the phase difference that is used to generate a square wave (hereinafter also referred to as a major portion) to the adder 80. The phase comparator 20 outputs a portion of the phase difference that is not used to generate a square wave (hereinafter also referred to as a minor portion) to the correction determiner 70. The value of the phase difference calculated by the phase comparator 20 is represented by the sum of the value of the major portion and the value of the minor portion.

[0033] The main part is, for example, a value represented by a predetermined number of upper bits of a bit string of a predetermined bit length representing the value of the phase difference. In other words, the main part is represented by a bit string of a predetermined bit length in which the bit string of the predetermined number of upper bits is the same as the bit string of the predetermined number of upper bits in the bit string representing the value of the phase difference, and the value of each bit of the lower bit string except for the predetermined number of upper bits is 0. In further other words, the main part is a value represented by bits (the predetermined bit and bits higher than the predetermined bit) equal to or higher than the predetermined bit (the bit the above-mentioned predetermined number of bits from the top) of the bit string representing the value of the phase difference.

[0034] The non-major part is, for example, a value represented by a lower bit string excluding a predetermined number of upper bits of a bit string of a predetermined bit length representing the value of the phase difference. In other words, the non-major part is represented by a bit string of a predetermined bit length in which the value of each bit of the bit string of the predetermined number of upper bits is 0, and the lower bit string excluding the predetermined number of upper bits is the same as the lower bit string in the bit string representing the value of the phase difference. In further other words, the non-major part is a value represented by bits lower than a predetermined bit (the bit the above-mentioned predetermined number of bits from the upper bit) of the bit string representing the value of the phase difference.

[0035] In other words, the major part is the part of the phase difference value that is equal to or greater than a predetermined value. And the minor part is the part of the phase difference value that is less than the predetermined value. This predetermined value is, for example, a value represented by a bit string of a predetermined bit length in which the bit a predetermined number of bits from the most significant bit is 1 and the other bits are 0. This predetermined value corresponds, for example, to the unit of the DUTY of the square wave generated by the square wave generator 30. The unit of the DUTY is the minimum value of change in the DUTY value. For example, if the unit of the DUTY value is 1, when the phase difference value changes by a predetermined value, the DUTY value changes by 1.

[0036] When the bit string representing the phase difference is expressed by a fixed-point number, the major part is the integer part. In this case, the minor part is the decimal part. In this case, the above-mentioned predetermined value is 1. Hereinafter, this predetermined value is also referred to as an additional value.

[0037] The random number generator 60 generates random numbers in the same range as the variable range of the value of the non-major part (in other words, the range of values ​​that the value of the non-major part can take). The random number generator 60 may generate pseudo-random numbers as the random numbers described above. The frequency with which the random number generator 60 generates random numbers may be, for example, the same as the frequency with which the phase comparator 20 compares phases (i.e., calculates a phase difference). The frequency with which the random number generator 60 generates random numbers may be, for example, higher than the frequency with which the phase comparator 20 compares phases (i.e., calculates a phase difference). The random number generator 60 outputs the generated random numbers (specifically, data representing the values ​​of the random numbers) to the correction determiner 70.

[0038] The correction determiner 70 compares the random number generated by the random number generator 60 (i.e., the value of the random number) with the minor part of the phase difference (specifically, the value of the minor part) output from the phase comparator 20. When the minor part is larger than the value of the random number, the correction determiner 70 controls the adder 80 to add the additional value to the major part of the phase difference (i.e., the value represented by the major part). When the minor part of the phase difference is equal to or smaller than the value of the random number, the correction determiner 70 controls the adder 80 not to add the additional value to the major part of the phase difference (i.e., the value represented by the major part).

[0039] The adder 80, under the control of the correction determiner 70, adds the above-mentioned predetermined value (i.e., the added value) to the major part of the phase difference (i.e., the value represented by the major part) when the minor part is greater than the value of the random number. When the major part is an integer part of the phase difference and the minor part is a decimal part of the phase difference, this added value is 1. In this case, the adder 80 outputs a signal indicating the major part of the phase difference to which the added value has been added (i.e., a value representing the sum of the major part of the phase difference and the added value) to the square wave generator 30. When the minor part of the phase difference is equal to or less than the value of the random number under the control of the correction determiner 70, the adder 80 does not add the added value to the major part of the phase difference (i.e., the value represented by the major part). In this case, the adder 80 outputs a signal indicating the major part of the phase difference (i.e., the value of the major part of the phase difference) to the square wave generator 30.

[0040] The square wave generator 30 generates a square signal, which is a square wave signal, from the value of the phase difference (also written as the corrected phase difference) output by the adder 80. As described above, the value of the phase difference (i.e., the corrected phase difference) output by the adder 80 is the major part of the phase difference to which the added value has been added (i.e., a value representing the sum of the major part of the phase difference output by the phase comparator 20 and the added value) when the minor part is greater than the value of the random number. The value of the phase difference output by the adder 80 is the value of the major part of the phase difference (i.e., the major part of the phase difference output by the phase comparator 20) when the minor part of the phase difference is equal to or less than the value of the random number.

[0041] Specifically, the square wave generator 30 generates a square wave whose DUTY (also written as duty) is a value corresponding to the value of the phase difference output from the adder 80. As described above, DUTY is a value indicating the time during which the signal value in the square wave remains high. In this embodiment, the value of DUTY may be, for example, a value obtained by multiplying the value of the phase difference (i.e., the corrected phase difference) output from the adder 80 by a predetermined coefficient.

[0042] The analog LPF 40 smoothes the generated rectangular signal to suppress high frequency components, thereby converting the rectangular signal into a voltage.

[0043] From the signal output from the analog LPF 40, the VCO 50 generates, as an output clock signal, a clock signal having a frequency according to the voltage level of the signal.

[0044] By the above process, the probability that the addition value is added to the major part of the phase difference generated by the phase comparator 20 is the ratio of the value of the minor part of the phase difference (e.g., the decimal part of the phase difference) to the above-mentioned predetermined value (i.e., the addition value). When the minor part is the decimal part of the phase difference, the addition value is 1. This probability is the ratio of the value of the minor part of the phase difference to the addition value, which is 1, that is, the value of the minor part of the phase difference. The duty of the square wave input to the analog LPF 40 is shifted on average at the ratio of the value of the minor part of the phase difference (e.g., the decimal part of the phase difference) to the above-mentioned predetermined value (i.e., the addition value, for example, 1). In this case, the shift of the duty of the square wave input to the analog LPF 40 means that the duty of the square wave changes from the duty determined by the major part of the phase difference to the duty determined by the sum of the major part of the phase difference and the addition value. The output of the analog LPF 40 is smoothed to a voltage determined by the value of the phase difference (that is, the sum of the major and minor parts of the phase difference).

[0045] FIG. 5 is a diagram illustrating a schematic diagram of signals in a digital phase-locked loop according to an embodiment of the present disclosure.

[0046] The reference clock (divider output) in FIG. 5 represents the waveform of the divided reference clock signal. The output clock (divider output) represents the waveform of the divided output clock signal. The phase comparator output (DUTY) control is a value representing the phase difference output by the phase comparator 20. The square wave is a square wave waveform output by the square wave generator 30. The LPF output represents the voltage transition of the signal output from the analog LPF 40. In the example shown in FIG. 5, the LPF output is a voltage determined by the value of the phase difference (i.e., the sum of the major and minor parts of the phase difference) due to smoothing by the analog LPF 40. In the example shown in FIG. 5, no wander occurs in the output clock signal.

[0047] <Effects> The above-described embodiment has an effect of suppressing the occurrence of wander in the output clock signal. The reason is that the adder 80 adds the addition value to the major part of the phase difference when the minor part is greater than the value of the random number, and does not add the addition value to the major part of the phase difference when the minor part of the phase difference is equal to or less than the value of the random number. This reduces the possibility that the output of the analog LPF 40 shifts at the timing of multiple consecutive pulses of the output clock signal. The output of the analog LPF 40 becomes a voltage corresponding to the sum of the major part and the minor part by smoothing. Then, the frequency of the clock signal output by the VCO 50 is suppressed from becoming higher than the fundamental frequency in multiple consecutive pulses. This fundamental frequency is the frequency of the output clock signal when the value of the phase difference input to the square wave generator 30 is the value of the major part of the phase difference. In other words, the occurrence of wander in the output clock signal is suppressed.

[0048] <Modification of the first embodiment> FIG. 4 is a block diagram illustrating an example of a configuration of a communication system according to an embodiment of the present disclosure.

[0049] The communication system shown in Fig. 4 includes a GPS (Global Positioning System) receiver 101 and a communication device 102. The communication device 102 includes a digital PLL circuit 103 and a signal processing circuit unit 104. The digital PLL circuit 103 is the digital PLL circuit according to the first embodiment.

[0050] The GPS receiver 101 outputs a clock signal to a digital PLL circuit 103 in a communication device 102 .

[0051] The digital PLL circuit 103 receives, as a reference clock signal, a clock signal from the GPS receiver 101. The digital PLL circuit 103 outputs an output clock signal to the signal processing circuit unit 104.

[0052] The signal processing circuit unit 104 receives the output clock signal from the digital PLL circuit 103 as a clock signal, and performs predetermined signal processing using the received clock signal.

[0053] <Second embodiment> A second embodiment of the present disclosure will be described below, which represents a main part of the first embodiment.

[0054] <Configuration> Fig. 6 is a block diagram illustrating an example of the configuration of a phase synchronization device according to an embodiment of the present disclosure. The phase synchronization device in Fig. 6 is, for example, a digital PLL circuit (phase locked loop circuit).

[0055] First, a phase synchronization device according to a second embodiment of the present disclosure will be described with reference to Fig. 6. The phase synchronization device of this embodiment is realized as a digital phase locked loop (that is, a digital PLL circuit).

[0056] In the example shown in FIG. 6, the phase synchronization device 100A includes a phase comparison section 120, a random number generation section 160, an addition section 180, and an output section 192.

[0057] The phase comparator section 120 compares the phase of a frequency-divided reference clock signal obtained by dividing the frequency of the reference clock signal with that of an output frequency-divided signal obtained by dividing the frequency of the fed-back output clock signal.

[0058] The random number generating section 160 generates a random number value (that is, a random value value) within the range of variation of the non-major portion, which is the portion of the value indicated by the result of the phase comparison that is less than a predetermined value.

[0059] When the non-major part is greater than the random number value, the addition unit 180 adds a predetermined number to the major part, which is the part of the value indicated by the result of the phase comparison that is equal to or greater than a predetermined value, and when the non-major part is equal to or less than the random number value, the addition unit 180 does not add the predetermined number to the major part of the result of the phase comparison.

[0060] The output unit 192 outputs the output clock signal generated using a square wave generated using the value of the main part subjected to the addition process as a value representing a duty. The method of generating the output clock signal is the same as the method of generating the output clock signal in the first embodiment.

[0061] The phase comparator 120, the random number generator 160, and the adder 180 of this embodiment are the same as the phase comparator 20, the random number generator 60, and the adder 80 of the first embodiment, respectively. The phase comparator 120, the random number generator 160, and the adder 180 of this embodiment operate in the same manner as the phase comparator 20, the random number generator 60, and the adder 80 of the first embodiment, respectively. The output unit 192 of this embodiment corresponds to the signal line through which the VCO 50 of the first embodiment outputs an output signal.

[0062] <Operation> FIG. 7 is a flowchart illustrating an example of the operation of the phase synchronization device according to the embodiment of the present disclosure.

[0063] The operation of the phase synchronization device 100A according to this embodiment will be described below with reference to FIG.

[0064] 7, the phase comparator 120 compares the phase of the frequency-divided reference clock signal with that of the output frequency-divided signal (step S11). Next, the random number generator 160 generates a random number within the range of variation of a non-major portion, which is a portion of the value indicated by the phase comparison result that is less than a predetermined value (step S12).

[0065] If the non-major part is equal to or smaller than the random value (YES in step S13), the adder 180 adds a predetermined value to the major part, which is the part of the value indicated by the phase comparison result that is equal to or larger than the predetermined value (step S14). If the non-major part is larger than the random value (NO in step S13), the adder 180 does not perform the operation of step S14.

[0066] Then, the output section 192 outputs the output clock signal generated using a square wave generated using the value of the main part as a value representing the duty (step S15).

[0067] <Effects> This embodiment has the same effect as the first embodiment. The reason is that the adder 180 performs an addition process in which, if the non-major part is greater than the random number, a predetermined number is added to the major part of the phase comparison result, and, if the non-major part is equal to or less than the random number, the adder 180 does not add the predetermined number to the major part of the phase comparison result. As described above, the non-major part is a part of the value indicated by the phase comparison result that is less than a predetermined value. The major part is a part of the value indicated by the phase comparison result that is equal to or greater than a predetermined value. And, the output unit 192 outputs an output clock signal generated using a rectangular wave generated using the value of the major part subjected to the addition process as a value representing the duty. This suppresses the occurrence of wander in the output clock signal, for example, as described in the description of the effect of the first embodiment.

[0068] <Third embodiment> The third embodiment of the present disclosure will be described in detail with reference to the drawings. This embodiment is a schematic representation of the first embodiment.

[0069] FIG. 8 is a block diagram illustrating an example of the configuration of a phase synchronization device according to an embodiment of the present disclosure.

[0070] Hereinafter, a phase synchronization device 100 according to a third embodiment of the present disclosure will be described with reference to FIG.

[0071] The phase synchronization device 100 shown in FIG. 8 includes a frequency division section 110A, a frequency division section 110B, a phase comparison section 120, a rectangular wave generation section 130, an analog LPF section 140, a VCO section 150, a random number generation section 160, a correction determination section 170, an addition section 180, a receiving section 191, and an output section 192.

[0072] The frequency division unit 110A and the frequency division unit 110B of this embodiment correspond to the two frequency dividers 10 of the first embodiment. The phase comparison unit 120, the square wave generation unit 130, the analog LPF unit 140, the VCO unit 150, the random number generation unit 160, the correction determination unit 170, and the addition unit 180 of this embodiment are the same as the phase comparator 20, the square wave generator 30, the analog LPF 40, the VCO 50, the random number generator 60, the correction determination unit 70, and the adder 80 of the first embodiment, respectively. The receiving unit 191 of this embodiment corresponds to the signal line in the first embodiment through which the reference clock signal is input to the frequency divider 1. The output unit 192 of this embodiment corresponds to the signal line in the first embodiment through which the output clock signal is output from the VCO 50.

[0073] <Receiving unit 191> The receiving unit 191 receives a reference clock signal.

[0074] <Frequency dividing section 110A> The frequency dividing unit 110A divides the reference clock signal by a predetermined division ratio to generate a frequency-divided reference clock signal, which is a signal obtained by dividing the reference clock signal. The frequency dividing unit 110A is also referred to as a first frequency dividing unit.

[0075] <Frequency dividing section 110B> The frequency divider 110B divides the fed back output clock signal by a predetermined division ratio to generate a divided output clock signal, which is a signal obtained by dividing the fed back output clock signal. The division ratio of the frequency divider 110B is the same as that of the frequency divider 110A. The frequency divider 110A is also referred to as a second frequency divider.

[0076] <Phase comparison section 120> The phase comparator section 120 compares the phase of a frequency-divided reference clock signal obtained by dividing the frequency of the reference clock signal with that of an output frequency-divided signal obtained by dividing the frequency of the fed-back output clock signal. The phase comparator 120 calculates the phase difference between the frequency-divided reference clock signal and the output frequency-divided signal as a result of the phase comparison. The phase comparator 120 outputs the value of the main part of the phase difference to the adder 180. The phase comparator 120 outputs the value of the non-main part of the phase difference to the correction determination unit 170.

[0077] The minor part is a part of the value representing the phase difference that is less than a predetermined value. And the major part is a part of the value representing the phase difference that is equal to or greater than a predetermined value. The minor part may be a value represented by a bit lower than a predetermined bit in a bit string representing a value representing the phase difference. The major part may be a value represented by a predetermined bit and a bit higher than the predetermined bit in a bit string representing a value representing the phase difference. The minor part may be a part less than 1 of the value representing the phase difference (i.e., a decimal part of the value representing the phase difference). The major part may be an integer part of the value representing the phase difference.

[0078] <Random number generator 160> The random number generator 160 generates a random number value within the range of variation of the non-major portion, which is the portion of the value indicated by the phase comparison result that is less than a predetermined value. The range of variation of the non-major portion is provided to the random number generator 160 in advance.

[0079] <Correction determination unit 170> The correction determination section 170 determines whether or not the minor portion of the phase difference is equal to or smaller than a random number value.

[0080] <Rectangular Wave Generation Unit 130> The rectangular wave generation unit 130 uses the value of the main part (i.e., the corrected main part) where the addition process is performed as the value representing DUTY to generate the rectangular wave. The frequency of the rectangular wave generated by the rectangular wave generation unit 130 may be predetermined. In this case, the value representing duty represents the duty ratio.

[0081] <Analog LPF Unit 140> The analog LPF unit 140 (also referred to as a low-pass filter unit) generates a voltage signal from the rectangular wave by applying a low-pass filter to the rectangular wave generated by the rectangular wave generation unit 130. The frequency of the rectangular wave generated by the rectangular wave generation unit 130 and the frequency band that the analog LPF unit 140 allows to pass are configured such that when the duty ratio of the rectangular wave is constant, the generated voltage signal is considered to be constant based on a predetermined standard.

[0082] <VCO Unit 150> The VCO unit 150 (also referred to as a voltage-controlled oscillation unit) generates an output clock signal with a frequency corresponding to the voltage indicated by the voltage signal. The VCO unit 150 sends the generated output clock signal to the output unit 192. The VCO unit 150 further sends the generated output clock signal to the frequency division unit 110B (in other words, feeds it back).

[0083] <Output Unit 192> The output unit 192 outputs the generated output clock signal.

[0084] <Operation> FIG. 9 and FIG. 10 are flowcharts showing examples of the operation of the phase synchronization device according to the embodiment of the present disclosure.

[0085] Hereinafter, the operation of the phase synchronization device 100 of the present disclosure will be described with reference to FIGS. 9 and 10.

[0086] In the example shown in FIGS. 9 and 10, first, the receiving unit 191 receives a reference clock signal (step S101).

[0087] Next, frequency division unit 110A divides the reference clock signal to generate a divided reference clock signal (step S102).Furthermore, frequency division unit 110B divides the fed back output clock signal to generate a divided output clock signal (step S103).The operation of step S102 and the operation of step S103 are performed in parallel.

[0088] The phase comparison section 120 compares the phase of the frequency-divided reference clock signal with that of the frequency-divided output clock signal, and calculates the phase difference (step S104).

[0089] The random number generator 160 generates a random number value within the range of variation of the non-major portion, which is the portion of the value indicated by the phase comparison result that is less than a predetermined value (step S105).

[0090] Next, the phase synchronization device 100 performs an addition process (step S106). The addition process will be described in detail later.

[0091] The square wave generating unit 130 generates a square wave using the value of the main part that has been subjected to the addition process (step S107).

[0092] Next, the analog LPF unit 140 generates a voltage signal by applying a low-pass filter to the generated square wave (step S108).

[0093] VCO unit 150 generates an output clock signal having a frequency corresponding to the voltage indicated by the voltage signal (step S109). VCO unit 150 feeds back the output clock signal to frequency division unit 110B (step S110) and also sends the output clock signal to output unit 192.

[0094] The output unit 192 outputs the output clock signal (step S111).

[0095] FIG. 11 is a flowchart illustrating the operation of the addition process of the phase synchronization device according to the embodiment of the present disclosure.

[0096] Hereinafter, the operation of the phase synchronization device 100 according to the second embodiment of the present disclosure will be described with reference to FIG.

[0097] In the example shown in FIG. 11, first, the correction determination unit 170 compares the value of the non-major portion with a random number value (step S121).

[0098] If the non-major portion is equal to or less than the random value (YES in step S122), the adder 180 adds a predetermined value to the major portion, which is the portion of the value indicated by the phase comparison result that is equal to or greater than the predetermined value (step S123).

[0099] If the non-major portion is greater than the random value (NO in step S122), the phase synchronization device 100 does not perform the operation of step S123.

[0100] <Effects> The present embodiment described above has the same effects as those of the second embodiment, for the same reasons as those for the effects of the second embodiment.

[0101] <Other embodiments> The phase synchronization circuit and the phase synchronization device according to the embodiment of the present disclosure can be realized by a computer including a processor that executes a program loaded in a memory. The phase synchronization circuit and the phase synchronization device according to the embodiment of the present disclosure can also be realized by dedicated hardware such as a circuit. The phase synchronization circuit and the phase synchronization device according to the embodiment of the present disclosure can also be realized by a combination of the above-mentioned computer and dedicated hardware such as a circuit. Hereinafter, the phase synchronization circuit is also referred to as a phase synchronization device.

[0102] FIG. 12 is a diagram illustrating an example of a hardware configuration of a computer 1000 that can realize a phase synchronization device according to an embodiment of the present disclosure. In the example illustrated in FIG. 12, the computer 1000 includes a processor 1001, a memory 1002, a storage device 1003, and an I / O (Input / Output) interface 1004. The computer 1000 can also access a storage medium 1005. The memory 1002 and the storage device 1003 are, for example, storage devices such as a RAM (Random Access Memory) and a hard disk. The storage medium 1005 is, for example, a storage device such as a RAM or a hard disk, a ROM (Read Only Memory), or a portable storage medium. The storage device 1003 may be the storage medium 1005. The processor 1001 can read and write data and programs from and to the memory 1002 and the storage device 1003. The processor 1001 can access other devices via the I / O interface 1004. The processor 1001 can access the storage medium 1005. The storage medium 1005 stores a program that causes the computer 1000 to operate as a phase synchronization device according to an embodiment of the present disclosure.

[0103] The processor 1001 loads a program stored in the storage medium 1005, which causes the computer 1000 to operate as a phase synchronization device according to an embodiment of the present disclosure, into the memory 1002. Then, the processor 1001 executes the program loaded into the memory 1002, causing the computer 1000 to operate as a phase synchronization device according to an embodiment of the present disclosure.

[0104] The frequency divider 10, phase comparator 20, square wave generator 30, analog LPF 40, VCO 50, random number generator 60, correction determiner 70, and adder 80 can be realized, for example, by a processor 1001 that executes a program loaded into a memory 1002. The frequency divider 110, phase comparator 120, square wave generator 130, analog LPF 140, VCO 150, random number generator 160, correction determiner 170, adder 180, receiver 191, and output unit 192 can be realized, for example, by the processor 1001 that executes a program loaded into the memory 1002.

[0105] Some or all of the frequency divider 10, phase comparator 20, square wave generator 30, analog LPF 40, VCO 50, random number generator 60, correction determiner 70, and adder 80 can be realized by dedicated circuits that realize their functions. Some or all of the frequency divider 110, phase comparator 120, square wave generator 130, analog LPF 140, VCO 150, random number generator 160, correction determiner 170, adder 180, receiver 191, and output unit 192 can be realized by dedicated circuits that realize their functions.

[0106] Furthermore, some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0107] (Appendix 1) a phase comparator that compares the phase of a frequency-divided reference clock signal obtained by dividing a reference clock signal with a phase of an output frequency-divided signal obtained by dividing a fed-back output clock signal; a random number generator for generating random numbers within a range of variation of a non-major portion, which is a portion of the result of the phase comparison that is less than a predetermined value; an addition unit that performs an addition process in which, when the non-major part is greater than the random value, the predetermined value is added to a major part of the result of the phase comparison that is equal to or greater than the predetermined value, and, when the non-major part is equal to or less than the random value, the predetermined value is not added to the major part of the result of the phase comparison; an output section that outputs the output clock signal generated using a rectangular wave generated using the value of the main part that has been subjected to the addition process as a value representing a duty; A phase synchronization device comprising:

[0108] (Appendix 2) The phase comparator calculates a phase difference between the frequency-divided reference clock signal and the output frequency-divided signal as a result of the phase comparison. 2. A phase synchronizer as claimed in claim 1.

[0109] (Appendix 3) the non-major portion being a portion of the value representing the phase difference that is less than the predetermined value, The main portion is a portion of the value representing the phase difference that is equal to or greater than the predetermined value. 3. A phase synchronizer as claimed in claim 2.

[0110] (Appendix 4) the minor portion is a value represented by bits lower than a predetermined bit in a bit string representing a value representing the phase difference, The main part is a value represented by the predetermined bit and bits higher than the predetermined bit in a bit string representing a value representing the phase difference. 3. A phase synchronizer as claimed in claim 2.

[0111] (Appendix 5) the minor portion being a portion of the value representing the phase difference that is less than 1; The major portion is an integer portion of a value representing the phase difference. 3. A phase synchronizer as claimed in claim 2.

[0112] (Appendix 6) a square wave generating unit that generates the square wave by using the value of the main portion after the addition process as a value representing the duty; 3. The phase synchronization device according to claim 1 or 2, further comprising:

[0113] (Appendix 7) The square wave generating unit generates the square wave by using the value of the main portion after the addition process as a value representing a time during which the higher of the two levels of the square wave continues. 7. A phase synchronisation device as claimed in claim 6.

[0114] (Appendix 8) a receiving unit for receiving the reference clock signal; a first frequency division unit that generates the frequency-divided reference clock signal by dividing the frequency of the reference clock signal; a second frequency divider unit that generates the output frequency-divided signal by dividing the frequency of the output clock signal that is fed back; a correction determination unit that determines whether the non-major portion is equal to or smaller than the random value; a square wave generating unit that generates the square wave by using the value of the main part after the addition process as a value representing the duty; a low-pass filter unit that generates a voltage signal from the rectangular wave by applying a low-pass filter to the rectangular wave; a voltage controlled oscillator that generates the output clock signal having a frequency corresponding to the voltage indicated by the voltage signal; 3. The phase synchronization device according to claim 1 or 2, further comprising:

[0115] (Appendix 9) A phase synchronizing device according to claim 1 or 2, The phase synchronization device receives a clock signal from a GPS (Global Positioning System) receiver as the reference clock signal, The output clock signal is used as the clock signal. Communication equipment.

[0116] (Appendix 10) comparing the phase of a frequency-divided reference clock signal obtained by dividing the reference clock signal with a frequency-divided output clock signal obtained by dividing the fed-back output clock signal; generating a random number within a range of variation of a non-major portion of the phase comparison result that is less than a predetermined value; performing an addition process in which, if the non-major part is greater than the random value, the predetermined value is added to the major part of the result of the phase comparison, which is a part of the value that is equal to or greater than the predetermined value, and, if the non-major part is equal to or less than the random value, the predetermined value is not added to the major part of the result of the phase comparison; outputting the output clock signal generated using a rectangular wave generated using the value of the main part subjected to the addition process as a value representing a duty; Phase synchronization method.

[0117] (Appendix 11) Calculating a phase difference between the divided reference clock signal and the output divided signal as a result of the phase comparison 11. A phase synchronization method as recited in claim 10.

[0118] (Appendix 12) the non-major portion being a portion of the value representing the phase difference that is less than the predetermined value, The main portion is a portion of the value representing the phase difference that is equal to or greater than the predetermined value. 12. A phase synchronization method as described in claim 11.

[0119] (Appendix 13) the minor portion is a value represented by bits lower than a predetermined bit in a bit string representing a value representing the phase difference, The main part is a value represented by the predetermined bit and bits higher than the predetermined bit in a bit string representing a value representing the phase difference. 12. A phase synchronization method as described in claim 11.

[0120] (Appendix 14) the minor portion being a portion of the value representing the phase difference that is less than 1; The major portion is an integer portion of a value representing the phase difference. 12. A phase synchronization method as described in claim 11.

[0121] (Appendix 15) The value of the main portion after the addition process is used as a value representing the duty to generate the square wave. 12. The phase synchronization method according to claim 10 or 11.

[0122] (Appendix 16) generating said square wave using the value of said main portion after said summing process as a value representing the duration of the higher of the two levels of said square wave; 16. A phase synchronization method as recited in claim 15.

[0123] (Appendix 17) receiving the reference clock signal; generating the divided reference clock signal by dividing the reference clock signal; generating the output divided signal by dividing the fed back output clock signal; determining whether the minor portion is less than or equal to the random value; generating the square wave using the value of the main portion after the addition process as a value representing the duty; generating a voltage signal from the square wave by applying a low pass filter to the square wave; generating the output clock signal having a frequency corresponding to the voltage indicated by the voltage signal; 12. The phase synchronization method according to claim 10 or 11.

[0124] (Appendix 18) The phase synchronization method according to claim 10 or 11, The phase synchronization method includes receiving a clock signal from a GPS (Global Positioning System) receiver as the reference clock signal; The output clock signal is used as the clock signal. Communication methods.

[0125] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above embodiments. Various modifications that can be understood by a person skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. [Explanation of symbols]

[0126] 1 frequency divider 2 phase comparator 3 Square wave generator 4 Analog LPF 5 VCO 10 divider 20 Phase comparator 30 Square wave generator 40 Analog LPF 50 VCO 60 Random Number Generator 70 Correction judger 80 Adder 100 phase synchronizer 100A phase synchronizer 101 GPS receiver 102 Communication equipment 103 Digital PLL circuit 104 Signal processing circuit section 110 frequency divider 110A frequency divider 110B Frequency divider 120 Phase comparator 130 Square wave generator 140 Analog LPF section 150 VCO section 160 Random Number Generator 170 Correction judgment section 180 Addition section 191 Receiving section 192 Output section 1000 Computers 1001 Processor 1002 Memory 1003 Storage device 1004 I / O Interface 1005 Storage medium

Claims

1. a phase comparator that compares the phase of a frequency-divided reference clock signal obtained by dividing a reference clock signal with a phase of an output frequency-divided signal obtained by dividing a fed-back output clock signal; a random number generator for generating random numbers within a range of variation of a non-major portion, which is a portion of the result of the phase comparison that is less than a predetermined value; an addition unit that performs an addition process in which, when the non-major part is greater than the random value, the predetermined value is added to a major part of the result of the phase comparison that is equal to or greater than the predetermined value, and, when the non-major part is equal to or less than the random value, the predetermined value is not added to the major part of the result of the phase comparison; an output section that outputs the output clock signal generated using a rectangular wave generated using the value of the main part that has been subjected to the addition process as a value representing a duty; A phase synchronization device comprising:

2. The phase comparator calculates a phase difference between the frequency-divided reference clock signal and the output frequency-divided signal as a result of the phase comparison.

2. The phase synchronizer according to claim 1.

3. the non-major portion being a portion of the value representing the phase difference that is less than the predetermined value, The main portion is a portion of the value representing the phase difference that is equal to or greater than the predetermined value.

3. The phase synchronizer according to claim 2.

4. the minor portion is a value represented by bits lower than a predetermined bit in a bit string representing a value representing the phase difference, The main part is a value represented by the predetermined bit and bits higher than the predetermined bit in a bit string representing a value representing the phase difference.

3. The phase synchronizer according to claim 2.

5. the minor portion being a portion of the value representing the phase difference that is less than 1; The major portion is an integer portion of a value representing the phase difference.

3. The phase synchronizer according to claim 2.

6. a square wave generating unit that generates the square wave by using the value of the main portion after the addition process as a value representing the duty; The phase synchronization device according to claim 1 or 2, further comprising:

7. The square wave generating unit generates the square wave by using the value of the main portion after the addition process as a value representing a time during which the higher of the two levels of the square wave continues.

7. The phase synchronizer according to claim 6.

8. a receiving unit for receiving the reference clock signal; a first frequency division unit that generates the frequency-divided reference clock signal by dividing the frequency of the reference clock signal; a second frequency divider that generates the output frequency-divided signal by dividing the frequency of the output clock signal that is fed back; a correction determination unit that determines whether the non-major portion is equal to or smaller than the random value; a square wave generating unit that generates the square wave by using the value of the main part after the addition process as a value representing the duty; a low-pass filter unit that generates a voltage signal from the rectangular wave by applying a low-pass filter to the rectangular wave; a voltage controlled oscillator that generates the output clock signal having a frequency corresponding to the voltage indicated by the voltage signal; The phase synchronization device according to claim 1 or 2, further comprising:

9. A phase synchronization device according to claim 1 or 2, The phase synchronization device receives a clock signal from a GPS (Global Positioning System) receiver as the reference clock signal, The output clock signal is used as the clock signal. Communication equipment.

10. comparing the phase of a frequency-divided reference clock signal obtained by dividing the reference clock signal with a frequency-divided output clock signal obtained by dividing the fed-back output clock signal; generating a random number within a range of variation of a non-major portion of the phase comparison result that is less than a predetermined value; performing an addition process in which, if the non-major part is greater than the random value, the predetermined value is added to the major part of the result of the phase comparison, which is a part of the value that is equal to or greater than the predetermined value, and, if the non-major part is equal to or less than the random value, the predetermined value is not added to the major part of the result of the phase comparison; outputting the output clock signal generated using a rectangular wave generated using the value of the main part subjected to the addition process as a value representing a duty; Phase synchronization method.

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