Display device

Abstract

To reduce sub-pixel defects.SOLUTION: A display device according to an embodiment of the present description includes a display panel in which a plurality of sub-pixels is defined, a first light-emitting element arranged in each of the plurality of sub-pixels, a second light-emitting element connected in series to the first light-emitting element, a first control transistor connected in parallel to the first light-emitting element and turned on by a first control signal, and a second control transistor connected in parallel to the second light-emitting element and turned on by a second control signal. Thus, the first light-emitting element and the second light-emitting element can be independently controlled using the first control transistor and the second control transistor connected in parallel to the first light-emitting element and the second light-emitting element, respectively.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present specification relates to a display device, and more particularly to a display device using LEDs (Light Emitting Diodes). [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide variety of applications, including not only computer monitors and TVs but also personal portable devices. Research is currently underway into display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs (Light Emitting Diodes) have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, and therefore have excellent reliability and a longer lifespan than LCDs and OLEDs. LEDs not only light up quickly, but also have excellent luminous efficiency, strong impact resistance, excellent stability, and can display high brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of reducing dark spot defects in sub-pixels.

[0006] Another problem to be solved by the present specification is to provide a display device capable of reducing defects in a sub-pixel by arranging a plurality of light-emitting elements in the sub-pixel.

[0007] Another problem to be solved by the present specification is to provide a display device capable of displaying a high-resolution image by arranging a plurality of light-emitting elements in a sub-pixel.

[0008] Another problem to be solved by the present invention is to provide a display device capable of normally driving the remaining light emitting elements even if an open circuit or short circuit occurs in one of a plurality of light emitting elements connected in series.

[0009] Another problem to be solved by the present disclosure is to provide a display device capable of providing a path through which a driving current can flow in a detouring manner when some light emitting elements are defective.

[0010] Another problem to be solved by the present specification is to provide a display device capable of controlling a plurality of light emitting elements by adding a minimum number of transistors.

[0011] The subject of the present specification is not limited to the subject mentioned above, and other subjects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0012] A display device according to an embodiment of the present specification includes a display panel in which a plurality of sub-pixels are defined, a first light-emitting element arranged in each of the plurality of sub-pixels, a second light-emitting element connected in series to the first light-emitting element, a first control transistor connected in parallel to the first light-emitting element and turned on by a first control signal, and a second control transistor connected in parallel to the second light-emitting element and turned on by a second control signal. Thus, the first light-emitting element and the second light-emitting element can be independently controlled using the first control transistor and the second control transistor connected in parallel to the first light-emitting element and the second light-emitting element, respectively.

[0013] A display device according to another embodiment of the present specification includes a substrate, an adhesive layer disposed on the substrate, a first light-emitting element disposed on the adhesive layer and including a first anode and a first cathode, a second light-emitting element disposed on the adhesive layer and including a second anode and a second cathode, and a plurality of reflective electrodes disposed between the substrate and the adhesive layer, the plurality of reflective electrodes including a first reflective electrode electrically connected to the first anode, a second reflective electrode electrically connected to the first cathode and the second anode, and a third reflective electrode electrically connected to the second cathode. Thus, the first light-emitting element and the second light-emitting element can be connected in series using the plurality of reflective electrodes.

[0014] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0015] The present specification can reduce dark spot defects in sub-pixels and improve the reliability of the display device.

[0016] In the present specification, a plurality of light-emitting elements are arranged in a sub-pixel, making it possible to display an image with higher resolution.

[0017] In the present specification, a plurality of light emitting elements are arranged in a sub-pixel, and when some of the light emitting elements are defective, the remaining light emitting elements can be used to normally drive the sub-pixel.

[0018] In the present specification, even if some of the light emitting devices among a plurality of light emitting devices connected in series become defective, the remaining light emitting devices can be normally driven by using a transistor through which a driving current flows in a detouring manner.

[0019] In the present specification, a control transistor is connected in parallel to each of a plurality of light-emitting elements, and when some of the light-emitting elements are defective, a path through which the driving current flows can be provided to bypass the defective light-emitting elements.

[0020] In the present specification, a control transistor is connected in parallel to each of a plurality of light emitting elements, so that the light emitting elements can be individually controlled.

[0021] The present invention makes it possible to control multiple light emitting elements by adding a minimum number of transistors.

[0022] The effects of the present specification are not limited to the above-mentioned examples, and various other effects are included in the present specification. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic diagram illustrating a configuration of a display device according to an embodiment of the present specification. [Figure 2a] 1 is a partial cross-sectional view of a display device according to an embodiment of the present specification. [Figure 2b] FIG. 1 is a perspective view of a tiling display device according to an embodiment of the present specification. [Diagram 3] FIG. 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification. [Figure 4a] 11 is a driving timing diagram of a sub-pixel of a display device according to an embodiment of the present disclosure, when a first light emitting element emits light. [Figure 4b] FIG. 4 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification, illustrating a flow of a driving current when a first light-emitting element emits light. [Figure 5a] 11 is a driving timing diagram of a sub-pixel of a display device according to an embodiment of the present specification when a second light emitting element emits light. [Figure 5b] FIG. 11 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification, illustrating a flow of a driving current when a second light-emitting element emits light. [Figure 6] FIG. 2 is a plan view of a sub-pixel of a display device according to an embodiment of the present specification. [Figure 7] 7A and 7B are cross-sectional views taken along lines VIIa-VIIa' and VIIb-VIIb' in FIG. [Figure 8] 2 is a diagram illustrating a configuration of a gate driver of a display device according to an embodiment of the present specification; [Figure 9] 1 is a circuit diagram of a control signal generating circuit of a display device according to an embodiment of the present specification. [Figure 10]1 is a drive timing diagram of a control signal generating circuit of a display device according to an embodiment of the present specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The advantages and features of the present specification, and the methods for achieving them, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided solely to ensure that the disclosure of the present specification is complete and to fully convey the scope of the specification to those skilled in the art to which the present specification pertains.

[0025] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, and the specification is not limited to the matters illustrated. The same reference symbols refer to the same components throughout the specification. In addition, when explaining this specification, if it is determined that a specific description of related known technology may unnecessarily cloud the gist of this specification, the detailed description will be omitted. When "including," "having," "made," etc. are used in this specification, other parts may be added since "only" is not used. When a component is expressed in the singular, it may include a plural unless otherwise explicitly stated.

[0026] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0027] When describing a positional relationship, for example when describing the positional relationship between two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., one or more other parts may be located between the two parts, so long as "immediately" or "directly" is not used.

[0028] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0029] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of this specification.

[0030] Like reference numbers refer to like elements throughout the specification.

[0031] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0032] The features of the various embodiments of this specification may be combined or combined with each other, either partially or in whole, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0033] In the following, the present specification will be described with reference to the drawings.

[0034] Fig. 1 is a schematic diagram of a display device according to an embodiment of the present specification. Fig. 2a is a partial cross-sectional view of a display device according to an embodiment of the present specification. Fig. 2b is a perspective view of a tiling display device according to an embodiment of the present specification. For convenience of explanation, Fig. 1 shows only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC among various components of the display device 100.

[0035] Referring to FIG. 1, a display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD for supplying various signals to the display panel PN, and a timing controller TC for controlling the gate driver GD and the data driver DD.

[0036] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided from a timing controller TC. Although one gate driver GD is shown to be disposed at a distance from one side of the display panel PN in FIG. 1, the number and arrangement of the gate driver GD are not limited thereto.

[0037] The data driver DD converts image data input from the timing controller TC into a data voltage Vdata using a reference gamma voltage in response to a plurality of data control signals provided from the timing controller TC, and supplies the converted data voltage Vdata to a plurality of data lines DL.

[0038] The timing controller TC aligns externally input image data and supplies it to the data driver DD. The timing controller TC can generate gate control signals and data control signals using externally input synchronous signals, for example, a dot clock signal, a data enable signal, and a horizontal / vertical synchronous signal. The timing controller TC can then supply the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0039] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL cross each other in the display panel PN, and each of the sub-pixels SP is connected to the scan lines SL and the data lines DL. In addition, although not shown in the drawing, each of the sub-pixels SP may be connected to a high potential power supply line VDD, a low potential power supply line VSS, a reference line RL, etc.

[0040] A display area AA and a non-display area NA surrounding the display area AA can be defined in the display panel PN.

[0041] The display area AA is an area where an image is displayed on the display device 100. A plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be arranged in the display area AA. The plurality of sub-pixels SP are the minimum units constituting the display area AA, and n sub-pixels SP may form one pixel PX. A light-emitting element LED and a thin film transistor for driving the light-emitting element LED may be arranged in each of the plurality of sub-pixels SP. The plurality of light-emitting elements LED may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting element LED may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0042] In the display area AA, a plurality of wirings are arranged to transmit various signals to the sub-pixels SP. For example, the plurality of wirings may include a plurality of data wirings DL that supply a data voltage Vdata to each of the sub-pixels SP, a plurality of scan wirings SL that supply a scan signal to each of the sub-pixels SP, etc. The plurality of scan wirings SL may extend from the display area AA in one direction and be connected to the sub-pixels SP, and the plurality of data wirings DL may extend from the display area AA in a direction different from the one direction and be connected to the sub-pixels SP. In addition, a low potential power supply wiring VSS, a high potential power supply wiring VDD, etc. may be further arranged in the display area AA, but are not limited thereto.

[0043] The non-display area NA is an area where no image is displayed, and may be defined as an area extending from the display area AA. Link wiring and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, driving ICs such as gate driver ICs and data driver ICs, etc. may be arranged in the non-display area NA.

[0044] However, the non-display area NA may be located on the rear surface of the display panel PN, i.e., on a surface without sub-pixels SP, or may be omitted, and is not limited to what is shown in the drawings.

[0045] Meanwhile, drivers such as the gate driver GD, the data driver DD, and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-display area NA in a GIP (Gate In Panel) manner, or in the display area AA between a plurality of sub-pixels SP in a GIA (Gate In Active Area) manner. For example, the data driver DD and the timing controller TC can be formed on a separate flexible film and printed circuit board, and the data driver DD and the timing controller TC can be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0046] If the gate driver GD is implemented in the GIP method and the data driver DD and the timing controller TC transmit signals to the display panel PN through pad electrodes in the non-display area NA, the area of ​​the non-display area NA for arranging the gate driver GD and the pad electrodes needs to be at a certain level or more, which may increase the bezel.

[0047] Alternatively, if the gate driver GD is mounted inside the display area AA in the GIA manner, and a side wiring SRL is formed to connect the signal wiring on the front side of the display panel PN to the pad electrode on the rear side of the display panel PN, and a flexible film and a printed circuit board are bonded to the rear side of the display panel PN, the non-display area NA on the front side of the display panel PN can be minimized. That is, if the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN in the above manner, it may be possible to implement a zero bezel, which is essentially a bezel-free display.

[0048] 2a and 2b, a plurality of pad electrodes for transmitting various signals to a plurality of sub-pixels SP are arranged in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 for transmitting signals to the plurality of sub-pixels SP is arranged in the non-display area NA on the front side of the display panel PN, and a second pad electrode PAD2 electrically connected to driving components such as a flexible film and a printed circuit board is arranged in the non-display area NA on the rear side of the display panel PN. That is, only the pad area where the first pad electrode PAD1 is arranged may be formed to a minimum in the non-display area NA on the front side of the display panel PN where an image is displayed.

[0049] In this case, although not shown in the drawing, various signal wirings connected to multiple subpixels SP, such as scan wirings SL and data wirings DL, may extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0050] Also, side wirings SRL are arranged along the side surfaces of the display panel PN. The side wirings SRL can electrically connect a first pad electrode PAD1 on the front surface of the display panel PN to a second pad electrode PAD2 on the rear surface of the display panel PN. Thus, signals from driving components on the rear surface of the display panel PN can be transmitted to the sub-pixels SP through the second pad electrode PAD2, the side wirings SRL and the first pad electrode PAD1. Thus, a signal transmission path between the side surface and rear surface is formed on the front surface of the display panel PN, and the area of ​​the non-display region NA on the front surface of the display panel PN can be minimized.

[0051] 2b, a tiled display device TD having a large screen can be implemented by connecting a plurality of display devices 100. In this case, as shown in FIG 2a, when the tiled display device TD is implemented using the display device 100 with a minimized bezel, a seam area between the display devices 100 where no image is displayed can be minimized, thereby improving display quality.

[0052] For example, a plurality of sub-pixels SP may form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another adjacent display device 100 may be implemented as the same as a distance D1 between pixels PX within one display device 100. Therefore, the distance D1 between pixels PX may be configured to be constant between display devices 100, thereby minimizing seam areas.

[0053] However, FIG. 2a and FIG. 2b are merely illustrative, and the display device 100 according to an embodiment of the present specification may be a general display device having a bezel, and is not limited thereto.

[0054] FIG. 3 is a circuit diagram of a subpixel of a display device according to an embodiment of the present specification. FIG. 4a is a driving timing diagram of a subpixel of a display device according to an embodiment of the present specification when a first light-emitting element emits light. FIG. 4b is a circuit diagram of a subpixel of a display device according to an embodiment of the present specification for explaining a flow of a driving current when a first light-emitting element emits light. FIG. 5a is a driving timing diagram of a subpixel of a display device according to an embodiment of the present specification for explaining a flow of a driving current when a second light-emitting element emits light. FIG. 5b is a circuit diagram of a subpixel of a display device according to an embodiment of the present specification for explaining a flow of a driving current when a second light-emitting element emits light.

[0055] Referring to FIG. 3, a subpixel SP of a display device 100 according to one embodiment of this specification includes a circuit including a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first control transistor LET1, a second control transistor LET2, a first capacitor C1, a second capacitor C2 and a third capacitor, and a first light-emitting element LED1 and a second light-emitting element LED2 connected to the circuit.

[0056] Each of the sub-pixels SP is connected to the first scan line SL1, the second scan line SL2, the data line DL, the emission control line EML, the reference line RL, the high potential power supply line VDD, and the low potential power supply line VSS.

[0057] Meanwhile, the plurality of transistors of the plurality of sub-pixels SP may be made of transistors of different types. For example, one of the plurality of transistors may be a transistor having an oxide semiconductor as an active layer. Since an oxide semiconductor material has a low off-current, it is suitable for a switching transistor that has a short turn-on time and maintains a long turn-off time. As another example, the other of the plurality of transistors may be a transistor having a low temperature polysilicon (LTPS) as an active layer. Since a polysilicon material has high mobility, low power consumption, and excellent reliability, it may be suitable for a driving transistor DT, etc.

[0058] The multiple transistors arranged in each of the multiple subpixels SP may be N-type transistors or P-type transistors. In an N-type transistor, the carriers are electrons, so that electrons can flow from the source electrode to the drain electrode, and a current can flow from the drain electrode to the source electrode. In a P-type transistor, the carriers are holes, so that holes can flow from the source electrode to the drain electrode, and a current can flow from the source electrode to the drain electrode. For example, one of the multiple transistors may be an N-type transistor, and another of the multiple transistors may be a P-type transistor.

[0059] In the following description, it is assumed that the multiple transistors are P-type transistors; however, the multiple transistors may be N-type transistors or may include both P-type and N-type transistors, and is not limited thereto.

[0060] The driving transistor DT is a transistor that controls a driving current based on a data voltage Vdata. The driving gate electrode DGE of the driving transistor DT is connected to a second node N2, the driving source electrode DSE is connected to a third node N3, and the driving drain electrode DDE is connected to a fourth node N4. The driving transistor DT can control the driving current applied to the light emitting element LED by the gate-source voltage Vgs.

[0061] The first transistor T1 is a transistor for transmitting a data voltage Vdata to the sub-pixel SP. The first gate electrode GE1 of the first transistor T1 is connected to the first scan line SL1, the first source electrode SE1 is connected to the data line DL, and the first drain electrode DE1 is connected to the first node N1. The first transistor T1 is turned on by a first scan signal SCAN1 to transmit the data voltage Vdata from the data line DL to the first node N1.

[0062] The second transistor T2 is a transistor for sampling and compensating the threshold voltage of the driving transistor DT. The second gate electrode GE2 of the second transistor T2 is connected to the first scan line SL1, and the second source electrode SE2 and the second drain electrode DE2 are connected to the second node N2 and the fourth node N4. The second transistor T2 is turned on by the first scan signal SCAN1, and can connect the driving gate electrode DGE and the driving drain electrode DDE of the driving transistor DT. Therefore, when the second transistor T2 is turned on, the driving transistor DT can be in a diode connection state in which the driving gate electrode DGE and the driving drain electrode DDE are shorted and operate like a diode.

[0063] The third transistor T3 is a transistor for initializing the first node N1 to a reference voltage. The third gate electrode GE3 of the third transistor T3 is connected to the emission control line EML, the third source electrode SE3 is connected to the reference line RL, and the third drain electrode DE3 is connected to the first node N1. The third transistor T3 is turned on by the emission control signal EM and can transmit the reference voltage to the first node N1.

[0064] The fourth transistor T4 is a transistor for controlling the flow of the driving current. The fourth gate electrode GE4 of the fourth transistor T4 is connected to the light emission control wiring EML, the fourth source electrode SE4 is connected to the fourth node N4, and the fourth drain electrode DE4 is connected to the low potential power supply wiring VSS. The fourth transistor T4 is turned on by the light emission control signal EM, and can connect the fourth node N4 and the low potential power supply wiring VSS, so that the driving current can flow from the high potential power supply wiring VDD side to the low potential power supply wiring VSS side.

[0065] The fifth transistor T5 is a transistor for initializing the fourth node N4 to a reference voltage. The fifth gate electrode GE5 of the fifth transistor T5 is connected to the second scan line SL2, the fifth source electrode SE5 is connected to the reference line RL, and the fifth drain electrode DE5 is connected to the fourth node N4. The fifth transistor T5 is turned on by the second scan signal SCAN2 and can transmit the reference voltage to the fourth node N4. Therefore, the voltage of the driving drain electrode DDE of the driving transistor DT can be initialized to the reference voltage by the fifth transistor T5.

[0066] The first control transistor LET1 is a transistor for controlling whether the first light emitting element LED1 emits light or not. The first control gate electrode EGE1 of the first control transistor LET1 is connected to the first control wiring LEL1, the first control source electrode ESE1 is connected to the first anode AD1 of the first light emitting element LED1 and the high potential power supply wiring VDD, and the first control drain electrode EDE1 is the first cathode CD1 of the first light emitting element LED1 and is connected to the fifth node N5. The first control transistor LET1 and the first light emitting element LED1 can be connected in parallel.

[0067] The first control transistor LET1 is turned on by the first control signal LE1 of the first control line LEL1, so that the driving current can flow to the first control transistor LET1 instead of the first light emitting element LED1. That is, when the first control transistor LET1 is turned on, the driving current can be bypassed to flow to the turned-on first control transistor LET1 instead of flowing toward the first light emitting element LED1. When the first control transistor LET1 is turned on, the driving current can be bypassed to flow from the first control source electrode ESE1 to the first control drain electrode EDE1 of the first control transistor LET1. Conversely, when the first control transistor LET1 is turned off, the driving current can flow from the first anode AD1 to the first cathode CD1 of the first light emitting element LED1. Therefore, the first light emitting element LED1 can emit light only when the first control transistor LET1 is turned off.

[0068] The second control transistor LET2 is a transistor for controlling whether the second light-emitting element LED2 emits light or not. The second control gate electrode EGE2 of the second control transistor LET2 is connected to the second control wiring LEL2, the second control source electrode ESE2 is connected to the second anode AD2 of the second light-emitting element LED2 and the fifth node N5, and the second control drain electrode EDE2 is the second cathode CD2 of the second light-emitting element LED2 and is connected to the third node N3. The second control transistor LET2 and the second light-emitting element LED2 may be connected in parallel.

[0069] The second control transistor LET2 is turned on by a second control signal LE2 on the second control line LEL2, so that the driving current can flow to the second control transistor LET2 instead of the second light-emitting element LED2. When the second control transistor LET2 is turned on, the driving current can be bypassed and flow from the second control source electrode ESE2 to the second control drain electrode EDE2 of the second control transistor LET2. When the second control transistor LET2 is turned off, the driving current can flow from the second anode AD2 to the second cathode CD2 of the second light-emitting element LED2. Therefore, the second light-emitting element LED2 can emit light only when the second control transistor LET2 is turned off.

[0070] A first capacitor C1 is connected between the first node N1 and the second node N2. The first capacitor C1 includes a plurality of first capacitors C1. Some of the plurality of first capacitors C1 are connected to the first node N1, and the remaining are connected to the second node N2. The first capacitor C1 is charged with a data voltage Vdata reflecting a threshold voltage of the driving transistor DT, and while the first light-emitting element LED1 or the second light-emitting element LED2 emits light, the voltage applied to the driving gate electrode DGE of the driving transistor DT is fixed, so that a constant driving current can be supplied to the first light-emitting element LED1 or the second light-emitting element LED2 during one frame.

[0071] The second capacitor C2 is connected between the second node N2 and the third node N3. The second capacitor C2 includes a plurality of second capacitors C2. Some of the plurality of second capacitors C2 are connected to the second node N2, and the remaining are connected to the third node N3. The second capacitor C2 may be connected between the driving gate electrode DGE and the driving source electrode DSE of the driving transistor DT.

[0072] Meanwhile, when the voltage at the first node N1 fluctuates, the voltage at the second node N2 may also fluctuate due to the coupling characteristics of the first capacitor C1. At this time, the second capacitor C2 connected in series with the first capacitor C1 is in a coupled state with the first capacitor C1, and the transfer rate at which the voltage at the first node N1 is transferred to the voltage at the second node N2 may change depending on the ratio of the capacitances of the first capacitor C1 and the second capacitor C2. Therefore, when the light emitting element LED is configured as a micro LED having a steep IV curve slope, the transfer rate of the data voltage Vdata transferred from the first node N1 to the second node N2 can be reduced by connecting the second capacitor C2 to the first capacitor C1, thereby enabling more delicate gray scale expression.

[0073] The third capacitor is a capacitor formed between the high potential power supply line VDD and the third node N3, and may be a kind of parasitic capacitor. The third capacitor may be a capacitor formed between existing components without forming a separate electrode. For example, the third capacitor may be formed by overlapping at least a part of the components connected to the high potential power supply line VDD and at least a part of the components connected to the third node N3. The third capacitor may increase the capacitance inherent to the light emitting element LED, thereby allowing the light emitting element LED to emit light of higher brightness.

[0074] The first light emitting element LED1 includes a first anode AD1 and a first cathode CD1. The first anode AD1 of the first light emitting element LED1 is connected to the high potential power supply line VDD, and the first cathode CD1 is connected to the fifth node N5. The first light emitting element LED1 can emit light by receiving a set driving current through the driving transistor DT that is turned on while the first control transistor LET1 is turned off.

[0075] The second light emitting element LED2 is connected in series to the first light emitting element LED1 and includes a second anode AD2 and a second cathode CD2. The second anode AD2 of the second light emitting element LED2 is connected to the fifth node N5, and the second cathode CD2 is connected to the third node N3. The second light emitting element LED2 can emit light by receiving a set driving current through the driving transistor DT that is turned on while the second control transistor LET2 is turned off.

[0076] The first light-emitting element LED1 and the second light-emitting element LED2 may be driven alternately. The first light-emitting element LED1 and the second light-emitting element LED2 may emit light in different frames or different horizontal periods. For example, the first light-emitting element LED1 may emit light in the n-th frame, and the second light-emitting element LED2 may emit light in the m-th frame. For example, the first light-emitting element LED1 may emit light in the n-th horizontal period, and the second light-emitting element LED2 may emit light in the m-th horizontal period. In this case, the first control transistor LET1 and the second control transistor LET2 may also be turned on alternately. That is, the first control transistor LET1 and the second control transistor LET2 may be turned on in different frames, and the first light-emitting element LED1 and the second light-emitting element LED2 may be controlled to emit light in different periods.

[0077] Therefore, in the display device 100 according to an embodiment of the present specification, the first light emitting element LED1 and the second light emitting element LED2 are connected in series to each of the sub-pixels SP, the first control transistor LET1 connected in parallel to the first light emitting element LED1, and the second control transistor LET2 connected in parallel to the second light emitting element LED2 are formed, so that even if a defect occurs in the sub-pixel SP, the sub-pixel SP can be seen to be normally driven. For example, when an open defect occurs in which a part of the first anode AD1 and the first cathode CD1 of the first light emitting element LED1 is not connected to the circuit, or a short defect occurs in which the first anode AD1 and the first cathode CD1 of the first light emitting element LED1 are electrically connected to each other, the driving current can be bypassed and flowed to the first control transistor LET1 and supplied to the second light emitting element LED2, and the second light emitting element LED2 can be normally driven. Similarly, even if an open defect or a short defect occurs in the second light emitting element LED2, the second control transistor LET2 can form a current path between the driving transistor DT and the first light emitting element LED1. That is, when the second light emitting element LED2 fails, the driving current can be diverted to the second control transistor LET2, and the first light emitting element LED1 can be driven normally. Therefore, in the display device 100 according to an embodiment of the present specification, even if a failure occurs in one of the plurality of light emitting elements LED arranged in each of the plurality of sub-pixels SP, the sub-pixel SP can be driven using the remaining light emitting element LED, thereby minimizing dark spot failures and improving the reliability of the display device 100.

[0078] As described above, the first light-emitting element LED1 and the second light-emitting element LED2 can emit light alternately in units of frames or horizontal periods. If the first light-emitting element LED1 is defective and cannot emit light, the second light-emitting element LED2 emits light in another frame or another horizontal period, so that the sub-pixel SP does not appear as a dark spot. In particular, when the display device 100 is driven at a high frequency, the length of one frame or the length of the horizontal period is very short, so that the user is unlikely to recognize the non-emission defect of the first light-emitting element LED1 or the second light-emitting element LED2. Therefore, the first light-emitting element LED1 and the second light-emitting element LED2 emit light alternately, and even if one light-emitting element LED does not emit light due to a defect, the remaining light-emitting element LED can emit light to display a normal image.

[0079] Hereinafter, a driving process of the sub-pixel SP will be described in detail on the assumption that the first light emitting element LED1 and the second light emitting element LED2 are alternately driven in frame units.

[0080] 4a and 4b, a second scan signal SCAN2 of a low level is output to the second scan line SL2 at time A. The second scan signal SCAN2 of a low level turns on the fifth transistor T5, and a reference voltage can be applied to the fourth node N4, that is, the driving drain electrode DDE of the driving transistor DT. Therefore, at time A, the voltage of the driving drain electrode DDE of the driving transistor DT can be initialized to the reference voltage.

[0081] Next, a first scan signal SCAN1 of low level is output to the first scan line SL1 in a period between time points B and C. The first transistor T1 is turned on by the first scan signal SCAN1 of low level, and the data voltage Vdata can be transmitted to the first node N1. The second transistor T2 is turned on by the first scan signal SCAN1 of low level, and the drive gate electrode DGE and the drive drain electrode DDE of the drive transistor DT can be connected to each other.

[0082] Then, in the period between time B and time C, the first control signal LE1 and the second control signal LE2 of low level are output to both the first control line LEL1 and the second control line LEL2. At time B, the high potential power supply line VDD and the driving source electrode DSE of the driving transistor DT may be electrically connected. At time B, the high potential power supply line VDD is connected to the driving source electrode DSE of the driving transistor DT which is in a diode-connected state by the second transistor T2, so that a current can flow through the driving transistor DT and the threshold voltage of the driving transistor DT can be sampled. Therefore, the threshold voltage of the driving transistor DT may be sampled and reflected to the second node N2, and the data voltage Vdata reflecting the threshold voltage of the driving transistor DT may be charged to the first capacitor C1.

[0083] Next, the light emission control signal EM of low level is output to the light emission control line EML at time D. The light emission control signal EM of low level turns on the third transistor T3, and the reference voltage may be applied to the first node N1.

[0084] The low-level light emitting control signal EM turns on the fourth transistor T4, electrically connecting the driving transistor DT to the low potential power supply wiring VSS, allowing a driving current to flow to the first light emitting element LED1 or the second light emitting element LED2.

[0085] 4a and 4b, when it is the turn of the first light emitting element LED1 to emit light among the first light emitting element LED1 and the second light emitting element LED2, a first control signal LE1 of high level is output to the first control line LEL1, and a second control signal LE2 of low level is output to the second control line LEL2. That is, the first control signal LE1 for turning off the first control transistor LET1 is output to the first control line LEL1, and the second control signal LE2 for turning on the second control transistor LET2 is output to the second control line LEL2.

[0086] By turning off the first control transistor LET1, the driving current can flow toward the first light-emitting element LED1 connected in parallel with the first control transistor LET1. And, by turning on the second control transistor LET2, the driving current can flow toward the second control transistor LET2. Therefore, between the high-potential power supply wiring VDD and the fifth node N5, the first control transistor LET1 is turned off, and the driving current can flow to the first light-emitting element LED1 connected in parallel with the first control transistor LET1, and between the fifth node N5 and the third node N3, the second control transistor LET2 is turned on, and the driving current can flow to the second control transistor LET2. Therefore, when the first control transistor LET1 is turned off and the second control transistor LET2 is turned on, the first light-emitting element LED1 emits light, and the second light-emitting element LED2 does not emit light.

[0087] 5a and 5b, when it is the turn of the second light emitting element LED2 to emit light among the first light emitting element LED1 and the second light emitting element LED2, a first control signal LE1 of low level is output to the first control line LEL1, and a second control signal LE2 of high level is output to the second control line LEL2. That is, the first control signal LE1 for turning on the first control transistor LET1 is output to the first control line LEL1, and the second control signal LE2 for turning off the second control transistor LET2 is output to the second control line LEL2.

[0088] By turning on the first control transistor LET1, the driving current can be bypassed and flow to the first control transistor LET1. And, by turning off the second control transistor LET2, the driving current can flow toward the second light-emitting element LED2. Therefore, between the high-potential power supply wiring VDD and the fifth node N5, the first control transistor LET1 is turned on, and the driving current can flow to the first control transistor LET1, and between the fifth node N5 and the third node N3, the second control transistor LET2 is turned off, and the driving current can flow to the second light-emitting element LED2 connected in parallel to the second control transistor LET2. Therefore, when the first control transistor LET1 is turned on and the second control transistor LET2 is turned off, the first light-emitting element LED1 does not emit light, and the second light-emitting element LED2 can emit light.

[0089] Therefore, in the display device 100 according to an embodiment of the present specification, the first light-emitting element LED1 and the second light-emitting element LED2 are connected in parallel to the first control transistor LET1 and the second control transistor LET2, respectively, so that it is possible to easily control whether the first light-emitting element LED1 and the second light-emitting element LED2 emit light. The first light-emitting element LED1 and the first control transistor LET1 are connected in parallel, and when the first control transistor LET1 is turned off, the driving current flows to the first light-emitting element LED1 side, and the first light-emitting element LED1 can emit light. Conversely, when the first control transistor LET1 is turned on, the driving current flows detouring to the first control transistor LET1 side, so that the first light-emitting element LED1 does not emit light. The second light-emitting element LED2 can also emit light only when the second control transistor LET2 connected in parallel to the first light-emitting element LED1 is turned off. Therefore, the first light-emitting element LED1 and the second light-emitting element LED2 can be selectively emitted by using the first control transistor LET1 and the second control transistor LET2 connected in parallel to the first light-emitting element LED1 and the second light-emitting element LED2, respectively. In addition, in order to independently control the first light-emitting element LED1 and the second light-emitting element LED2, only the first control transistor LET1 and the second control transistor LET2 are added to the minimum instead of a complex circuit, so that the configuration of the sub-pixel SP can be simplified.

[0090] In addition, in the display device 100 according to an embodiment of the present specification, the first control transistor LET1 and the second control transistor LET2 are formed in parallel with the first light-emitting element LED1 and the second light-emitting element LED2, respectively, so that even if a defect occurs in one light-emitting element LED, the remaining light-emitting element LED can be normally driven. For example, if an open defect occurs in the first light-emitting element LED1 of the first light-emitting element LED1 and the second light-emitting element LED2 connected in series, it may be difficult for a driving current to flow to the second light-emitting element LED2. However, in the display device 100 according to an embodiment of the present specification, the first control transistor LET1 connected in parallel with the first light-emitting element LED1 can be turned on to form a path through which the driving current flows in a detour, so that the driving current can be normally supplied to the second light-emitting element LED2. Therefore, even if a defect occurs in some of the light-emitting elements LED, the driving current can be normally supplied to the remaining light-emitting elements LED by using the control transistor connected in parallel with the light-emitting element LED.

[0091] In the display device 100 according to an embodiment of the present specification, a high-resolution image can be easily displayed by arranging a plurality of light-emitting element LEDs in one sub-pixel SP. For example, a high-resolution image can be displayed by arranging only one light-emitting element LED in each of the plurality of sub-pixels SP and increasing the number of the plurality of sub-pixels SP. In this case, the area allocated to each of the plurality of sub-pixels SP is reduced, and designing the sub-pixels SP may become difficult. In contrast, in the display device 100 according to an embodiment of the present specification, a high-resolution image can be displayed without increasing the number of the plurality of sub-pixels SP by arranging a plurality of light-emitting element LEDs in each of the plurality of sub-pixels SP. That is, an effect similar to an increase in the number of the light-emitting element LEDs and an increase in the number of the plurality of sub-pixels SP can be achieved. In this case, the number of the sub-pixels SP is the same, and only the number of the light-emitting element LEDs is increased, so that an area in which each of the sub-pixels SP can be designed can be secured, and the sub-pixels SP can be more easily designed.

[0092] Meanwhile, referring to Fig. 4a, when the first light emitting element LED1 emits light, the first control signal LE1 applied to the first control line LEL1 may have the same waveform as the first scan signal SCAN1. And, referring to Fig. 5a, when the second light emitting element LED2 emits light, the second control signal LE2 applied to the second control line LEL2 may have the same waveform as the first scan signal SCAN1. In the display device 100 according to an embodiment of the present specification, a control signal generating circuit LEC is connected to each of a plurality of first stages ST1 that generate the first scan signal SCAN1, and one of the first control signal LE1 and the second control signal LE2 can be output in the same waveform as the first scan signal SCAN1, which will be described in more detail later with reference to Figs. 8 to 10.

[0093] Hereinafter, the structure of the sub-pixel SP of the display device 100 according to an embodiment of the present specification will be described with reference to FIGS.

[0094] Fig. 6 is a plan view of a subpixel of a display device according to an embodiment of the present specification. Fig. 7 is a cross-sectional view taken along lines VIIa-VIIa' and VIIb-VIIb' in Fig. 6. For ease of explanation, Fig. 6 omits the illustration of a plurality of reflective electrodes RE, a first light-emitting element LED1, a second light-emitting element LED2, a plurality of connection electrodes CE, and a bank BB.

[0095] 6 and 7, a display device 100 according to an embodiment of the present specification includes a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a first passivation layer 114a, a second passivation layer 114b, a first planarization layer 115a, a second planarization layer 115b, a third planarization layer 115c, an adhesive layer 116, a bank BB, a protective layer 117, a light-shielding layer LS, a plurality of transistors, a plurality of capacitors, a plurality of wirings, a plurality of reflective electrodes RE, a plurality of connection electrodes CE, and a plurality of light-emitting elements LED.

[0096] First, the substrate 110 is a component for supporting various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. The substrate 110 may also be made of a material including a polymer or plastic and having flexibility.

[0097] A light blocking layer LS is disposed in each of the sub-pixels SP on the substrate 110. The light blocking layer LS blocks light incident on a driving active layer DACT of the driving transistor DT, which will be described later, under the substrate 110. The light blocking layer LS blocks light incident on the driving active layer DACT of the driving transistor DT, thereby minimizing leakage current. The light blocking layer LS may be made of an opaque conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0098] A buffer layer 111 is disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be composed of, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, and is not limited thereto.

[0099] The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes a driving active layer DACT, a driving gate electrode DGE, a driving source electrode DSE, and a driving drain electrode DDE.

[0100] The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0101] A gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer for electrically insulating the driving active layer DACT and the driving gate electrode DGE, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0102] A drive gate electrode DGE is disposed on the gate insulating layer 112. The drive gate electrode DGE may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0103] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the driving gate electrode DGE. Contact holes are formed in the first interlayer insulating layer 113a and the second interlayer insulating layer 113b for connecting the driving source electrode DSE and the driving drain electrode DDE to the driving active layer DACT, respectively. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are insulating layers for protecting the lower components, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0104] A driving source electrode DSE and a driving drain electrode DDE electrically connected to the driving active layer DACT are disposed on the second interlayer insulating layer 113b. The driving source electrode DSE and the driving drain electrode DDE may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0105] The first transistor T1 is disposed on the buffer layer 111. The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0106] A first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0107] A gate insulating layer 112 is disposed on the first active layer ACT1, and a first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 may be integrated with the first scan line SL1 and electrically connected to the first scan line SL1. The first gate electrode GE1 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0108] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the first gate electrode GE1, and a first source electrode SE1 and a first drain electrode DE1 electrically connected to the first active layer ACT1 are disposed on the second interlayer insulating layer 113b. The first source electrode SE1 is integrated with the data line DL and electrically connected to the data line DL. The first drain electrode DE1 may be electrically connected to a first-second capacitor electrode C1b of a first capacitor C1, which will be described later, through a contact hole in the second interlayer insulating layer 113b. The first source electrode SE1 and the first drain electrode DE1 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0109] The second transistor T2 is disposed on the buffer layer 111. The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0110] A second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0111] A gate insulating layer 112 is disposed on the second active layer ACT2, and a second gate electrode GE2 is disposed on the gate insulating layer 112. The second gate electrode GE2 may be integrated with the first scan line SL1 and electrically connected to the first scan line SL1. The second gate electrode GE2 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0112] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the second gate electrode GE2, and a second source electrode SE2 and a second drain electrode DE2 electrically connected to the second active layer ACT2 are disposed on the second interlayer insulating layer 113b. The second source electrode SE2 is a driving gate electrode DGE and is electrically connected to the 1-1 capacitor electrode C1a of the first capacitor C1. The second drain electrode DE2 is electrically connected to the fourth source electrode SE4 of the fourth transistor T4, the fifth drain electrode DE5 of the fifth transistor T5, and the driving drain electrode DDE. The second source electrode SE2 and the second drain electrode DE2 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0113] The third transistor T3 is disposed on the buffer layer 111. The third transistor T3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0114] A third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0115] A gate insulating layer 112 is disposed on the third active layer ACT3, and a third gate electrode GE3 is disposed on the gate insulating layer 112. The third gate electrode GE3 is integrated with the emission control wiring EML and is electrically connected to the emission control wiring EML. The third gate electrode GE3 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0116] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the third gate electrode GE3, and a third source electrode SE3 and a third drain electrode DE3 electrically connected to the third active layer ACT3 are disposed on the second interlayer insulating layer 113b. The third source electrode SE3 is electrically connected to the fifth source electrode SE5 and the reference line RL, and the third drain electrode DE3 is electrically connected to the first-second capacitor electrode C1b of the first capacitor C1 and the first drain electrode DE1 of the first transistor T1. The third source electrode SE3 and the third drain electrode DE3 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0117] The fourth transistor T4 is disposed on the buffer layer 111. The fourth transistor T4 includes a fourth active layer ACT4, a fourth gate electrode GE4, a fourth source electrode SE4, and a fourth drain electrode DE4.

[0118] The fourth active layer ACT4 is disposed on the buffer layer 111. The fourth active layer ACT4 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0119] A gate insulating layer 112 is disposed on the fourth active layer ACT4, and a fourth gate electrode GE4 is disposed on the gate insulating layer 112. The fourth gate electrode GE4 may be integrated with the light emission control wiring EML and electrically connected to the light emission control wiring EML. The fourth gate electrode GE4 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0120] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the fourth gate electrode GE4, and a fourth source electrode SE4 and a fourth drain electrode DE4 electrically connected to the fourth active layer ACT4 are disposed on the second interlayer insulating layer 113b. The fourth source electrode SE4 is electrically connected to the driving drain electrode DDE, the fifth drain electrode DE5 and the second drain electrode DE2 of the fifth transistor T5, and the fourth drain electrode DE4 is electrically connected to the low potential power supply wiring VSS. At this time, the low potential power supply wiring VSS and the fourth drain electrode DE4 may be made of the same material in the same layer and may be integrated. The fourth source electrode SE4 and the fourth drain electrode DE4 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0121] The fifth transistor T5 is disposed on the buffer layer 111. The fifth transistor T5 includes a fifth active layer ACT5, a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0122] A fifth active layer ACT5 is disposed on the buffer layer 111. The fifth active layer ACT5 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0123] A gate insulating layer 112 is disposed on the fifth active layer ACT5, and a fifth gate electrode GE5 is disposed on the gate insulating layer 112. The fifth gate electrode GE5 is electrically connected to the second scan line SL2. The fifth gate electrode GE5 may be formed of the same material in the same layer as the second scan line SL2 and may be integrated with the second scan line SL2. The fifth gate electrode GE5 may be formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0124] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the fifth gate electrode GE5, and a fifth source electrode SE5 and a fifth drain electrode DE5 electrically connected to the fifth active layer ACT5 are disposed on the second interlayer insulating layer 113b. The fifth source electrode SE5 is electrically connected to the reference line RL and the third source electrode SE3, and the fifth drain electrode DE5 is connected to the driving drain electrode DDE, the fourth source electrode SE4, and the second drain electrode DE2. The fifth source electrode SE5 and the fifth drain electrode DE5 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0125] The first control transistor LET1 is disposed on the buffer layer 111. The first control transistor LET1 includes a first control active layer EACT1, a first control gate electrode EGE1, a first control source electrode ESE1, and a first control drain electrode EDE1.

[0126] A first control active layer EACT1 is disposed on the buffer layer 111. The first control active layer EACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0127] A gate insulating layer 112 is disposed on the first control active layer EACT1, and a first control gate electrode EGE1 is disposed on the gate insulating layer 112. The first control gate electrode EGE1 may be integrated with the first control wiring LEL1 and electrically connected to the first control wiring LEL1. The first control gate electrode EGE1 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0128] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the first control gate electrode EGE1, and a first control source electrode ESE1 and a first control drain electrode EDE1 electrically connected to the first control active layer EACT1 are disposed on the second interlayer insulating layer 113b. The first control source electrode ESE1 is electrically connected to a high potential power supply wiring VDD, and the first control drain electrode EDE1 is electrically connected to a second control source electrode ESE2 of the second control transistor LET2. The first control source electrode ESE1 and the first drain electrode DE1 may be connected in parallel to the first light emitting element LED1 through a first reflective electrode RE1 and a second reflective electrode RE2, which will be described later. The first control source electrode ESE1 and the first control drain electrode EDE1 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0129] The second control transistor LET2 is disposed on the buffer layer 111. The second control transistor LET2 includes a second control active layer EACT2, a second control gate electrode EGE2, a second control source electrode ESE2, and a second control drain electrode EDE2.

[0130] A second control active layer EACT2 is disposed on the buffer layer 111. The second control active layer EACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0131] A gate insulating layer 112 is disposed on the second control active layer EACT2, and a second control gate electrode EGE2 is disposed on the gate insulating layer 112. The second control gate electrode EGE2 may be integrated with the second control wiring LEL2 and electrically connected to the second control wiring LEL2. The second control gate electrode EGE2 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0132] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are disposed on the second control gate electrode EGE2, and a second control source electrode ESE2 and a second control drain electrode EDE2 electrically connected to the second control active layer EACT2 are disposed on the second interlayer insulating layer 113b. The second control source electrode ESE2 is integrated with the first control drain electrode EDE1 and electrically connected to the first control drain electrode EDE1. The second control source electrode ESE2 may be electrically connected to the second anode AD2 of the second light-emitting element LED2 through a second reflective electrode RE2 described later. The second control drain electrode EDE2 may extend from the second control active layer EACT2 toward the driving active layer DACT and be connected to the driving active layer DACT. And the second control drain electrode EDE2 may be electrically connected to the driving source electrode DSE through the driving active layer DACT. Also, the second control drain electrode EDE2 may be electrically connected to the second cathode CD2 of the second light emitting element LED2 through the driving source electrode DSE and the third reflective electrode RE3. Therefore, the second control source electrode ESE2 and the second control drain electrode EDE2 may be connected in parallel to the second light emitting element LED2 through the second reflective electrode RE2 and the third reflective electrode RE3. The second control source electrode ESE2 and the second control drain electrode EDE2 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0133] Next, the first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a 1-1 capacitor electrode C1a and a 1-2 capacitor electrode C1b. The 1-1 capacitor electrode C1a and the 1-2 capacitor electrode C1b may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0134] The 1-1 capacitor electrode C1a is disposed on the gate insulating layer 112. The 1-1 capacitor electrode C1a may be integrated with the driving gate electrode DGE. Therefore, the 1-1 capacitor electrode C1a may be electrically connected to the driving gate electrode DGE and a second source electrode SE2 connected to the driving gate electrode DGE.

[0135] The 1-2 capacitor electrode C1b is disposed on the first interlayer insulating layer 113a. The 1-2 capacitor electrode C1b is disposed so as to overlap the 1-1 capacitor electrode C1a with the first interlayer insulating layer 113a interposed therebetween. The 1-2 capacitor electrode C1b may be electrically connected to the first drain electrode DE1 and the third drain electrode DE3.

[0136] A second capacitor C2 is disposed on the substrate 110. The second capacitor C2 includes a 2-1 capacitor electrode C2a, a 2-2 capacitor electrode C2b, and a 2-3 capacitor electrode C2c. The second capacitor C2 includes a 2-1 capacitor electrode C2a, a 2-2 capacitor electrode C2b, and a 2-3 capacitor electrode C2c. The second capacitor C2 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0137] The 2-1st capacitor electrode C2a is disposed on the substrate 110. The 2-1st capacitor electrode C2a is an extended portion from the light-shielding layer LS and may be integrated with the light-shielding layer LS. In this case, the 2-1st capacitor electrode C2a may be electrically connected to the driving source electrode DSE through the auxiliary electrode AE. The auxiliary electrode AE ​​is disposed on the gate insulating layer 112 and may electrically connect the driving source electrode DSE and the 2-1st capacitor electrode C2a to each other.

[0138] A 2-2 capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2 capacitor electrode C2b may be integrated with the driving gate electrode DGE and the 1-1 capacitor electrode C1a. Therefore, the 2-1 capacitor electrode C2a may be electrically connected to the driving gate electrode DGE, the 1-1 capacitor electrode C1a, and the second source electrode SE2.

[0139] The 2-3 capacitor electrode C2c is disposed on the first interlayer insulating layer 113a. The 2-3 capacitor electrode C2c may include a first electrode layer C2c1 and a second electrode layer C2c2. The first electrode layer C2c1 of the 2-3 capacitor electrode C2c may be formed in the same layer and made of the same material as the 1-2 capacitor electrode C1b, but may be patterned in an island shape separated from the 1-2 capacitor electrode C1b. The first layer may be disposed to overlap the 2-1 capacitor electrode C2a and the 2-2 capacitor electrode C2b with the first interlayer insulating layer 113a sandwiched therebetween.

[0140] The second electrode layer C2c2 of the 2-3 capacitor electrode C2c is disposed on the second interlayer insulating layer 113b. The second electrode layer C2c2 may be integrated with the driving source electrode DSE. The second electrode layer C2c2 may be electrically connected to the first electrode layer C2c1 through a contact hole in the second interlayer insulating layer 113b.

[0141] Next, a plurality of wirings are arranged on the substrate 110. The plurality of wirings include a first scan wiring SL1, a second scan wiring SL2, a light emission control wiring EML, a first control wiring LEL1, a second control wiring LEL2, a reference wiring RL, a data wiring DL, a high potential power supply wiring VDD, and a low potential power supply wiring VSS.

[0142] First, the first scan line SL1, the second scan line SL2, the emission control line EML, the first control line LEL1, and the second control line LEL2 are disposed on the gate insulating layer 112. The first scan line SL1, the second scan line SL2, the emission control line EML, the first control line LEL1, and the second control line LEL2 may extend in the row direction and be electrically connected to other components of the subpixel SP. For example, the first scan line SL1 may be connected to the first transistor T1 and the second transistor T2, and the second scan line SL2 may be connected to the fifth transistor T5. The emission control line EML may be connected to the third transistor T3 and the fourth transistor T4, and the first control line LEL1 and the second control line LEL2 may be connected to the first control transistor LET1 and the second control transistor LET2. The first scan line SL1, the second scan line SL2, the light emission control line EML, the first control line LEL1 and the second control line LEL2 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0143] Next, a reference line RL and a high potential power supply line VDD are disposed on the first interlayer insulating layer 113a. The reference line RL and the high potential power supply line VDD may extend in the row direction and be electrically connected to other components of the subpixel SP. For example, the reference line RL may be connected to the fifth transistor T5, and the high potential power supply line VDD may be connected to the first control transistor LET1. The reference line RL and the high potential power supply line VDD may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0144] The data line DL and the low potential power line VSS are disposed on the second interlayer insulating layer 113b. The data line DL and the low potential power line VSS may extend in the column direction and cross other lines extending in the row direction. The data line DL and the low potential power line VSS may be electrically connected to other components of the subpixel SP. For example, the data line DL may be connected to the first transistor T1, and the low potential power line VSS may be connected to the fourth transistor T4. The data line DL and the low potential power line VSS may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0145] Next, a first passivation layer 114a is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the first control transistor LET1, the second control transistor LET2, the first capacitor C1, and the second capacitor C2. The first passivation layer 114a is an insulating layer for protecting the components below the first passivation layer 114a, and may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0146] A first planarization layer 115a is disposed on the first passivation layer 114a. The first planarization layer 115a can planarize the upper portion of the substrate 110 including the driving transistor DT. The first planarization layer 115a can be configured as a single layer or multiple layers, and can be made of, for example, but not limited to, a photoresist, benzocyclobutene, or an acryl-based organic material.

[0147] A plurality of reflective electrodes RE are disposed on the first planarization layer 115a. The plurality of reflective electrodes RE are configured to reflect light emitted from the plurality of light-emitting elements LED to the upper portion of the substrate 110, and may be disposed to cover most of the areas of the plurality of sub-pixels SP. The plurality of reflective electrodes RE may be used as electrodes that reflect light emitted from the light-emitting elements LED and electrically connect the plurality of light-emitting elements LED to other components of the sub-pixels SP. The plurality of reflective electrodes RE may include various conductive layers in consideration of light reflection efficiency and resistance. For example, the reflective electrode RE may be made of an opaque conductive layer having high reflectivity, such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof. The reflective electrode RE may further include a transparent conductive layer, such as ITO (Indium Tin Oxide), to improve resistance.

[0148] The multiple reflective electrodes RE include a first reflective electrode RE1, a second reflective electrode RE2, and a third reflective electrode RE3.

[0149] The first reflective electrode RE1 is an electrode for electrically connecting the first control source electrode ESE1 and the first light-emitting element LED1. The first reflective electrode RE1 may be electrically connected to the first control source electrode ESE1 through a contact hole formed in the first planarization layer 115a and the first passivation layer 114a. The first reflective electrode RE1 may be electrically connected to the first anode AD1 of the first light-emitting element LED1 through a first anode AD1 connection electrode CE described below. Therefore, the first control source electrode ESE1 of the first control transistor LET1 and the first anode AD1 of the first light-emitting element LED1 may be electrically connected to each other through the first reflective electrode RE1.

[0150] The second reflective electrode RE2 is an electrode for electrically connecting the first control drain electrode EDE1 and the first light-emitting element LED1 and at the same time electrically connecting the second control source electrode ESE2 and the second light-emitting element LED2. The second reflective electrode RE2 may be electrically connected to the first control drain electrode EDE1 and the second control source electrode ESE2 through contact holes formed in the first planarization layer 115a and the first passivation layer 114a. The second reflective electrode RE2 may be electrically connected to the first cathode CD1 of the first light-emitting element LED1 through a first cathode CD1 connection electrode CE described later. And, the second reflective electrode RE2 may be electrically connected to the second anode AD2 of the second light-emitting element LED2 through a second anode AD2 connection electrode CE described later. Therefore, the first control drain electrode EDE1 of the first control transistor LET1 and the first cathode CD1 of the first light-emitting element LED1 may be electrically connected to each other through the second reflective electrode RE2. The second control source electrode ESE2 of the second control transistor LET2 and the second anode AD2 of the second light emitting element LED2 may be electrically connected to each other through the second reflective electrode RE2.

[0151] The third reflective electrode RE3 is an electrode for electrically connecting the second light-emitting element LED2 to the driving source electrode DSE and the second control drain electrode EDE2. The third reflective electrode RE3 may be electrically connected to the driving source electrode DSE through a contact hole formed in the first planarization layer 115a and the first passivation layer 114a. At this time, the driving source electrode DSE and the second control drain electrode EDE2 of the second control transistor LET2 are electrically connected to each other through the driving active layer DACT. Therefore, the third reflective electrode RE3 may also be electrically connected to the second control drain electrode EDE2. And the third reflective electrode RE3 may be electrically connected to the second cathode CD2 of the second light-emitting element LED2 through a second cathode CD2 connection electrode CE described later. Therefore, the second control drain electrode EDE2 and the driving source electrode DSE and the second cathode CD2 of the second light-emitting element LED2 may be electrically connected to each other through the third reflective electrode RE3.

[0152] Next, a second passivation layer 114b is disposed on the plurality of reflective electrodes RE. The second passivation layer 114b is an insulating layer for protecting the structure below the second passivation layer 114b, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0153] An adhesive layer 116 is disposed on the second passivation layer 114b. The adhesive layer 116 is formed on the front surface of the substrate 110, and can fix a plurality of light-emitting elements LEDs disposed on the adhesive layer 116. The adhesive layer 116 can be made of a photo-curable adhesive material that can be cured by light. For example, the adhesive layer 116 can be made of an acrylic-based material containing a photosensitive agent, but is not limited thereto.

[0154] A plurality of light emitting elements LED are disposed on the adhesive layer 116. The plurality of light emitting elements LED are elements that emit light by current, and may be, for example, light emitting elements LED (Light Emitting Diode) or micro LEDs. The plurality of light emitting elements LED may include a red light emitting element LED that emits red light, a green light emitting element LED that emits green light, and a light emitting element LED that emits blue light, and light of various hues including white may be realized by combining these. The first light emitting element LED1 and the second light emitting element LED2 disposed in the same subpixel SP and connected in series may be light emitting elements LED that emit light of the same hue.

[0155] The first light-emitting element LED1 and the second light-emitting element LED2 may be formed to have substantially the same structure. The first semiconductor layer NL, the light-emitting layer EL, the second semiconductor layer PL, the first anode AD1, the first cathode CD1, and the sealing film PAS of the first light-emitting element LED1 may have substantially the same configuration as the first semiconductor layer NL, the light-emitting layer EL, the second semiconductor layer PL, the second anode AD2, the second cathode CD2, and the sealing film PAS of the second light-emitting element LED2.

[0156] First, the first light emitting element LED1 includes a first semiconductor layer NL, a light emitting layer EL, a second semiconductor layer PL, a first anode AD1, a first cathode CD1, and a sealing film PAS.

[0157] A first semiconductor layer NL is disposed on the adhesive layer 116, and a second semiconductor layer PL is disposed on the first semiconductor layer NL. The first semiconductor layer NL and the second semiconductor layer PL may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer NL and the second semiconductor layer PL may be layers formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with n-type and p-type impurities. The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited thereto.

[0158] The light emitting layer EL is disposed between the first semiconductor layer NL and the second semiconductor layer PL. The light emitting layer EL can emit light by receiving holes and electrons from the first semiconductor layer NL and the second semiconductor layer PL. The light emitting layer EL can have a single layer or a multi-quantum well (MQW) structure and can be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0159] A first cathode CD1 is disposed on the first semiconductor layer NL. The first cathode CD1 may be disposed on an upper surface of the first semiconductor layer NL exposed from the light emitting layer EL and the second semiconductor layer PL. In this case, the first semiconductor layer NL electrically connected to the first cathode CD1 may be a semiconductor layer doped with n-type impurities. The first cathode CD1 may be electrically connected to the second anode AD2 of the second light emitting element LED2, the first control drain electrode EDE1 of the first control transistor LET1, and the second control source electrode ESE2 of the second control transistor LET2 through the first cathode CD1 connection electrode CE and the second reflective electrode RE2. The first cathode CD1 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0160] A first anode AD1 is disposed on the second semiconductor layer PL. The first anode AD1 may be disposed on an upper surface of the second semiconductor layer PL. The second semiconductor layer PL electrically connected to the first anode AD1 may be a semiconductor layer doped with p-type impurities. The first anode AD1 may be electrically connected to a high potential power supply line VDD and a first control source electrode ESE1 of the first control transistor LET1 through a first anode AD1 connection electrode CE and a first reflective electrode RE1. The first anode AD1 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0161] Next, a sealing film PAS is disposed to surround the first semiconductor layer NL, the light emitting layer EL, the second semiconductor layer PL, the first anode AD1, and the first cathode CD1. The sealing film PAS is made of an insulating material and can protect the first semiconductor layer NL, the light emitting layer EL, and the second semiconductor layer PL. Contact holes exposing the first anode AD1 and the first cathode CD1 are formed in the sealing film PAS, and the first anode AD1 and the first cathode CD1 can be electrically connected to the first anode AD1 connection electrode CE and the first cathode CD1 connection electrode CE, respectively.

[0162] Meanwhile, a part of the side of the first semiconductor layer NL may be exposed from the sealing film PAS. The light-emitting element LED manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, a part of the sealing film PAS may be peeled off during the process of separating the light-emitting element LED from the wafer. For example, a part of the sealing film PAS adjacent to the lower edge of the first semiconductor layer NL of the light-emitting element LED may be peeled off during the process of separating the light-emitting element LED from the wafer, and a part of the lower side of the first semiconductor layer NL may be exposed to the outside. However, even if the lower part of the light-emitting element LED is exposed from the sealing film PAS, the first anode AD1 connection electrode CE and the first cathode CD1 connection electrode CE are formed after forming the second planarization layer 115b and the third planarization layer 115c that cover the side of the first semiconductor layer NL, so that short-circuit defects can be reduced.

[0163] Next, the second light-emitting element LED2 includes a first semiconductor layer NL, a light-emitting layer EL, a second semiconductor layer PL, a second anode AD2, a second cathode CD2, and a sealing film PAS. The first semiconductor layer NL, the light-emitting layer EL, the second semiconductor layer PL, and the sealing film PAS of the second light-emitting element LED2 are formed of substantially the same structure and material as the first semiconductor layer NL, the light-emitting layer EL, the second semiconductor layer PL, and the sealing film PAS of the first light-emitting element LED1.

[0164] The second cathode CD2 of the second light emitting element LED2 may be disposed on the first semiconductor layer NL like the first cathode CD1 of the first light emitting element LED1, and may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. The second cathode CD2 may be electrically connected to the driving source electrode DSE of the driving transistor DT and the second drain electrode DE2 of the second control transistor LET2 through the second cathode CD2 connection electrode CE and the third reflective electrode RE3.

[0165] The second anode AD2 of the second light-emitting element LED2 is disposed on the second semiconductor layer PL like the first anode AD1 of the first light-emitting element LED1, and may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. The second anode AD2 may be electrically connected to the first cathode CD1 of the first light-emitting element LED1, the first control drain electrode EDE1 of the first control transistor LET1, and the second control source electrode ESE2 of the second control transistor LET2 through the second anode AD2 connection electrode CE and the second reflective electrode RE2.

[0166] Next, the second planarization layer 115b and the third planarization layer 115c are disposed on the adhesive layer 116 and the light-emitting element LED.

[0167] The second planarization layer 115b overlaps with a part of the side surface of the light-emitting elements LED to fix and protect the light-emitting elements LED. The second planarization layer 115b can cover the part where the sealing film PAS protecting the side surface of the first semiconductor layer NL of the light-emitting element LED has been peeled off. This can prevent contact and short circuit defects between the connection electrode CE and the first semiconductor layer NL later.

[0168] The third planarization layer 115c is formed to cover the second planarization layer 115b and an upper portion of the light emitting element LED. The third planarization layer 115c may have contact holes formed therein to expose the first anode AD1 and the first cathode CD1 of the first light emitting element LED1 and the second anode AD2 and the second cathode CD2 of the second light emitting element LED2. The first anode AD1, the first cathode CD1, the second anode AD2, and the second cathode CD2 are exposed from the third planarization layer 115c, but the third planarization layer 115c is partially disposed in the region between the first anode AD1 and the first cathode CD1 of the first light emitting element LED1 and the region between the second anode AD2 and the second cathode CD2 of the second light emitting element LED2, thereby reducing short circuit defects. The second planarization layer 115b and the third planarization layer 115c may be configured as a single layer or multiple layers, and may be made of, for example, photoresist, benzocyclobutene, or an acryl-based organic material, but are not limited thereto.

[0169] A plurality of connection electrodes CE are disposed on the third planarization layer 115c. The plurality of connection electrodes CE are electrodes for electrically connecting the plurality of light-emitting elements LED and other components of the sub-pixel SP. The plurality of connection electrodes CE include a first cathode CD1 connection electrode CE, a first anode AD1 connection electrode CE, a second cathode CD2 connection electrode CE, and a second anode AD2 connection electrode CE. The plurality of connection electrodes CE may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but are not limited thereto.

[0170] First, the first cathode CD1 connection electrode CE may be electrically connected to the second reflective electrode RE2 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. And, the first cathode CD1 connection electrode CE may be electrically connected to the first cathode CD1 of the first light-emitting element LED1 through the contact hole of the third planarization layer 115c. Thus, the first cathode CD1 and the second reflective electrode RE2 may be electrically connected to each other through the first cathode CD1 connection electrode CE.

[0171] The first anode AD1 connection electrode CE may be electrically connected to the first reflective electrode RE1 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. The first anode AD1 connection electrode CE may be electrically connected to the first anode AD1 of the first light-emitting element LED1 through a contact hole in the third planarization layer 115c. Thus, the first anode AD1 and the first reflective electrode RE1 may be electrically connected to each other through the first anode AD1 connection electrode CE.

[0172] The second cathode CD2 connection electrode CE may be electrically connected to the third reflective electrode RE3 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. And, the second cathode CD2 connection electrode CE may be electrically connected to the second cathode CD2 of the second light-emitting element LED2 through the contact hole of the third planarization layer 115c. Thus, the second cathode CD2 and the third reflective electrode RE3 may be electrically connected to each other through the second cathode CD2 connection electrode CE.

[0173] The second anode AD2 connection electrode CE may be electrically connected to the second reflective electrode RE2 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. The second anode AD2 connection electrode CE may be electrically connected to the second anode AD2 of the second light-emitting element LED2 through a contact hole in the third planarization layer 115c. Thus, the second anode AD2 and the second reflective electrode RE2 may be electrically connected to each other through the second anode AD2 connection electrode CE.

[0174] Meanwhile, the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE may both be connected to the second reflective electrode RE2. In the drawings, the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE are shown spaced apart from each other on the second reflective electrode RE2, but the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE may be connected to each other and integrally formed, and are not limited thereto.

[0175] Next, a bank BB is disposed on the second planarization layer 115b. The bank BB may be disposed at a certain interval from the light-emitting element LED, and may overlap at least a portion with the plurality of reflective electrodes RE. The bank BB may be disposed so as to cover at least a portion of the plurality of connection electrodes CE. The bank BB may be made of an opaque material to reduce color mixing between the plurality of sub-pixels SP, for example, but is not limited to, a black resin.

[0176] A protective layer 117 is disposed on the connection electrodes CE and the bank BB. The protective layer 117 is a layer for protecting the structure below the protective layer 117. The protective layer 117 may be configured as a single layer or multiple layers, and may be made of, for example, but not limited to, benzocyclobutene, a light-transmitting epoxy, a photoresist, or an acrylic organic material.

[0177] Meanwhile, the display device 100 according to an embodiment of the present specification may include a gate driver GD and a data driver DD as described above to drive a plurality of sub-pixels SP of a display panel PN. At this time, the gate driver GD may generate a first scan signal SCAN1, a second scan signal SCAN2, and an emission control signal EM and apply them to the first scan line SL1, the second scan line SL2, and the emission control line EML. The gate driver GD may further generate a first control signal LE1 and a second control signal LE2 and apply them to the first control line LEL1 and the second control line LEL2. In particular, since one of the first control signal LE1 and the second control signal LE2 has the same waveform as the first scan signal SCAN1, the first scan signal SCAN1 generated by the gate driver GD may be used as one of the first control signal LE1 and the second control signal LE2. Therefore, in the display device 100 according to one embodiment of the present specification, a control signal generating circuit LEC for further generating a first control signal LE1 and a second control signal LE2 may be formed in the gate driver GD including a plurality of first stages ST1 for generating a first scan signal SCAN1.

[0178] In the following, the control signal generating circuit LEC will be described in detail with reference to FIGS.

[0179] Fig. 8 is a configuration diagram of a gate driver of a display device according to an embodiment of the present specification. Fig. 9 is a circuit diagram of a control signal generating circuit of a display device according to an embodiment of the present specification. Fig. 10 is a driving timing diagram of the control signal generating circuit of a display device according to an embodiment of the present specification.

[0180] First, the gate driver GD includes a plurality of first stages ST1 for generating a first scan signal SCAN1. The plurality of first stages ST1 are connected in series and can generate the first scan signal SCAN1 based on a start signal VST or a first scan signal SCAN1 output from a front first stage ST1. For example, the top first stage ST1 can receive the start signal VST and output the first scan signal SCAN1 to the top first scan line SL1. And the n-th first stage ST1 can receive the first scan signal SCAN1 from the front n-1-th first stage ST1 and output the first scan signal SCAN1 to the n-th first scan line SL1.

[0181] A control signal generating circuit LEC is connected to the output terminals of each of the first stages ST1. The control signal generating circuit LEC includes a first circuit LEC1 and a second circuit LEC2, and each of the first circuit LEC1 and the second circuit LEC2 can generate a first control signal LE1 and a second control signal LE2 upon receiving the first scan signal SCAN1 output from the first stage ST1.

[0182] 9, the first circuit LEC1 is a circuit that generates a first control signal LE1 and a second control signal LE2 when the first light emitting element LED1 emits light. The first circuit LEC1 can generate the first control signal LE1 having the same waveform as the first scan signal SCAN1 and the second control signal LE2 having a turn-on level. The first circuit LEC1 includes a first connecting transistor CT1, a second connecting transistor CT2, a first auxiliary transistor Tbv1, and a first boosting capacitor Cb1.

[0183] First, the first connection transistor CT1 is a transistor for selectively connecting the output terminal of the first stage ST1 and the first control line LEL1. The gate electrode of the first connection transistor CT1 is connected to the drain electrode of the first auxiliary transistor Tbv1 and the Q1 node Q1, the source electrode is connected to the output terminal of the first stage ST1, and the drain electrode is connected to the first control line LEL1. The first connection transistor CT1 can be turned on or off based on the first enable signal EN1 transmitted through the first auxiliary transistor Tbv1. The turned-on first connection transistor CT1 can connect the output terminal of the first stage ST1 and the first control line LEL1, and the first scan signal SCAN1 from the first stage ST1 can be transmitted to the first control line LEL1 through the first connection transistor CT1. Therefore, the first scan signal SCAN1 is transmitted directly to the first control line LEL1, so that the first scan signal SCAN1 and the first control signal LE1 can have the same waveform.

[0184] The second connection transistor CT2 is a transistor for selectively connecting the gate low line and the second control line LEL2. The gate electrode of the second connection transistor CT2 is the drain electrode of the first auxiliary transistor Tbv1 and is connected to the Q1 node Q1, the source electrode is connected to the gate low line, and the drain electrode is connected to the second control line LEL2. The second connection transistor CT2 can be turned on or off based on the first enable signal EN1 transmitted through the first auxiliary transistor Tbv1. The turned-on second connection transistor CT2 can connect the gate low line and the second control line LEL2, and the gate low voltage VGL of the gate low line can be transmitted to the second control line LEL2 through the second connection transistor CT2. Therefore, the gate low voltage VGL becomes a low-level second control signal LE2 and can be output to the second control line LEL2.

[0185] The first auxiliary transistor Tbv1 is connected between the first enable line and the Q1 node Q1. The gate electrode of the first auxiliary transistor Tbv1 is connected to the gate low line, the source electrode is connected to the first enable line, and the drain electrode is connected to the Q1 node Q1. The first auxiliary transistor Tbv1, whose gate electrode is connected to the gate low line, may be always turned on and may electrically connect the first enable line and the Q1 node Q1.

[0186] The first boosting capacitor Cb1 is connected between the Q1 node Q1 and the first control line LEL1. The voltage of the Q1 node Q1 may momentarily become lower than the first enable voltage due to the bootstrapping of the first boosting capacitor Cb1, and the first connection transistor CT1 may stably maintain a turn-on state. Therefore, the first boosting capacitor Cb1 may help the first scan signal SCAN1 to be output to the first control signal LE1 without distortion or delay.

[0187] Next, the second circuit LEC2 is a circuit that generates the first control signal LE1 and the second control signal LE2 when the second light emitting element LED2 emits light. The second circuit LEC2 can generate the first control signal LE1 of a turn-on level and the second control signal LE2 having the same waveform as the first scan signal SCAN1. The second circuit LEC2 includes a third connecting transistor CT3, a fourth connecting transistor CT4, a second auxiliary transistor Tbv2, and a second boosting capacitor Cb2.

[0188] The third connection transistor CT3 is a transistor for selectively connecting the output terminal of the first stage ST1 and the second control line LEL2. The gate electrode of the third connection transistor CT3 is connected to the drain electrode of the second auxiliary transistor Tbv2 and the Q2 node Q2, the source electrode is connected to the output terminal of the first stage ST1, and the drain electrode is connected to the second control line LEL2. The third connection transistor CT3 can be turned on or off based on the second enable signal EN2 transmitted through the second auxiliary transistor Tbv2. The turned-on third connection transistor CT3 can connect the output terminal of the first stage ST1 and the second control line LEL2, and the first scan signal SCAN1 from the first stage ST1 can be transmitted to the second control line LEL2 through the third connection transistor CT3. Therefore, the first scan signal SCAN1 is transmitted directly to the second control line LEL2, so that the first scan signal SCAN1 and the second control signal LE2 can have the same waveform.

[0189] The fourth connection transistor CT4 is a transistor for selectively connecting the gate low line and the first control line LEL1. The gate electrode of the fourth connection transistor CT4 is connected to the drain electrode of the second auxiliary transistor Tbv2 and the Q2 node Q2, the source electrode is connected to the gate low line, and the drain electrode is connected to the first control line LEL1. The fourth connection transistor CT4 can be turned on or off based on the second enable signal EN2 transmitted through the second auxiliary transistor Tbv2. The turned-on fourth connection transistor CT4 can connect the gate low line and the first control line LEL1, and the gate low voltage VGL of the gate low line can be transmitted to the first control line LEL1 through the fourth connection transistor CT4. Therefore, the gate low voltage VGL becomes a first control signal LE1 of low level and can be output to the first control line LEL1.

[0190] The second auxiliary transistor Tbv2 is connected between the second enable line and the Q2 node Q2. The gate electrode of the second auxiliary transistor Tbv2 is connected to the gate low line, the source electrode is connected to the second enable line, and the drain electrode is connected to the Q2 node Q2. The second auxiliary transistor Tbv2, whose gate electrode is connected to the gate low line, may be always turned on and may electrically connect the second enable line and the Q2 node Q2.

[0191] The second boosting capacitor Cb2 is connected between the Q2 node Q2 and the second control line LEL2. The voltage of the Q2 node Q2 can be lower than the second enable voltage by bootstrapping of the second boosting capacitor Cb2, and the third connection transistor CT3 can stably maintain a turn-on state. Therefore, the second boosting capacitor Cb2 can help the first scan signal SCAN1 to be output to the second control signal LE2 without distortion or delay.

[0192] Next, referring to both Figures 9 and 10, the period from time A to time B is the period during which the first light-emitting element LED1 is driven, and the period from time C to time D is the period during which the second light-emitting element LED2 is driven.

[0193] First, during a period between time A and time B, the first circuit LEC1 may generate and output the first control signal LE1 and the second control signal LE2 so that only the first light emitting element LED1 emits light.

[0194] During the period between time A and time B, the first enable signal EN1 of low level is output to the first enable wire, and the second enable signal EN2 of high level is output to the second enable wire. At this time, the first enable signal EN1 and the second enable signal EN2 are signals of opposite phase. For example, if the first enable signal EN1 is at high level, the second enable signal EN2 may be at low level, and if the first enable signal EN1 is at low level, the second enable signal EN2 may be at high level. Therefore, the turn-on period of the first connection transistor CT1 and the second connection transistor CT2, whose gate electrodes are applied with the first enable signal EN1, and the turn-on period of the third connection transistor CT3 and the fourth connection transistor CT4, whose gate electrodes are applied with the second enable signal EN2, may be configured alternately.

[0195] In the first circuit LEC1, a first enable signal EN1 of a low level may be applied to the Q1 node Q1 through the first auxiliary transistor Tbv1. The first connection transistor CT1 and the second connection transistor CT2 may be turned on by the first enable signal EN1 of a low level applied to the Q1 node Q1. The turned-on first connection transistor CT1 may connect the output terminal of the first stage ST1 to the first control line LEL1, and a first control signal LE1 having the same waveform as the first scan signal SCAN1 may be output to the first control line LEL1. The turned-on second connection transistor CT2 may connect the gate low line to the second control line LEL2, and a second control signal LE2 of a low level having the same voltage as the gate low voltage VGL may be output. Therefore, the first control signal LE1 having the same waveform as the first scan signal SCAN1 may be output to the first control line LEL1, and a second control signal LE2 of a low level may be output to the second control line LEL2. Therefore, during the period in which the first light emitting element LED1 emits light, the second control transistor LET2 maintains the turned-on state, so that the second light emitting element LED2 does not emit light.

[0196] During the period between time A and time B, the high-level second enable signal EN2 output to the second enable line may be transmitted to the Q2 node Q2 of the second circuit LEC2. The third connection transistor CT3 and the fourth connection transistor CT4 of the second circuit LEC2 may be turned off by the high-level second enable signal EN2, so that the first scan signal SCAN1 may be output to the second control line LEL2 or the gate low voltage VGL may not be output to the first control line LEL1.

[0197] Next, during the period between time C and time D, the first enable signal EN1 of high level is output to the first enable line, and the second enable signal EN2 of low level is output to the second enable line.

[0198] In the first circuit LEC1, a first enable signal EN1 of high level can be applied to the Q1 node Q1 through the first auxiliary transistor Tbv1. The first connection transistor CT1 and the second connection transistor CT2 can be turned off by the first enable signal EN1 of high level applied to the Q1 node Q1. Therefore, the first circuit LEC1 can prevent signals from being output to the first control line LEL1 and the second control line LEL2.

[0199] In the second circuit LEC2, a low-level second enable signal EN2 may be applied to the Q2 node Q2 through the second auxiliary transistor Tbv2. The third connection transistor CT3 and the fourth connection transistor CT4 may be turned on by the low-level second enable signal EN2 applied to the Q2 node Q2. The turned-on third connection transistor CT3 may connect the output terminal of the first stage ST1 to the second control line LEL2, and the second control signal LE2 having the same waveform as the first scan signal SCAN1 may be output to the second control line LEL2. The turned-on fourth connection transistor CT4 may connect the gate low line to the first control line LEL1, and the low-level first control signal LE1 having the same voltage as the gate low voltage VGL may be output. Therefore, the low-level first control signal LE1 may be output to the first control line LEL1, and the second control signal LE2 having the same waveform as the first scan signal SCAN1 may be output to the second control line LEL2. Therefore, during the period in which the second light emitting element LED2 emits light, the first control transistor LET1 maintains the turned-on state, so that the first light emitting element LED1 does not emit light.

[0200] Therefore, in the display device 100 according to an embodiment of the present specification, the control signal generating circuit LEC is connected to the output terminals of the first stages ST1 of the gate driver GD, so that the first control signal LE1 and the second control signal LE2 can be easily generated. First, the control signal generating circuit LEC includes a first circuit LEC1 and a second circuit LEC2. When the first light emitting element LED1 emits light, the first circuit LEC1 can generate the first control signal LE1 having the same waveform as the first scan signal SCAN1 and apply it to the first control line LEL1. When the first light emitting element LED1 emits light, the first circuit LEC1 can generate the second control signal LE2 having a turn-on level that can turn on the second control transistor LET2 so that the second light emitting element LED2 does not emit light and apply it to the second control line LEL2. For example, the first circuit LEC1 can output the first scan signal SCAN1 input from the first stage ST1 to the first control line LEL1 as the first control signal LE1, and output the second control signal LE2 having a low level to the second control line LEL2. Therefore, during a frame or horizontal period in which the first light emitting element LED1 emits light, the first control signal LE1 and the second control signal LE2 can be generated using the first circuit LEC1.

[0201] The second circuit LEC2 can generate a first control signal LE1 of a turn-on level that can turn on the first control transistor LET1 so that the first light emitting element LED1 does not emit light when the second light emitting element LED2 emits light, and apply the first control signal LE1 to the first control line LEL1. When the second light emitting element LED2 emits light, the second circuit LEC2 can generate a second control signal LE2 of the same waveform as the first scan signal SCAN1 and apply the second control signal LE2 to the second control line LEL2. For example, the second circuit LEC2 can output the first scan signal SCAN1 input from the first stage ST1 to the second control line LEL2 as the second control signal LE2, and output the first control signal LE1 of a low level to the first control line LEL1. Therefore, when it is a frame or horizontal period in which the second light emitting element LED2 emits light, the first control signal LE1 and the second control signal LE2 can be generated using the second circuit LEC2. Therefore, the conventional first scan signal SCAN1 and gate low voltage VGL are used as the first control signal LE1 and the second control signal LE2, thereby simplifying the structure of the gate driver GD.

[0202] An embodiment of the present invention can also be described as follows.

[0203] According to an aspect of the present invention, a display device includes a display panel having a plurality of sub-pixels defined therein, a first light-emitting element arranged in each of the plurality of sub-pixels, a second light-emitting element connected in series to the first light-emitting element, a first control transistor connected in parallel to the first light-emitting element and turned on by a first control signal, and a second control transistor connected in parallel to the second light-emitting element and turned on by a second control signal.

[0204] According to another feature herein, the first light emitting element and the second light emitting element can alternately emit light.

[0205] According to still another feature of the present disclosure, while the first light emitting element emits light, the first control transistor may be turned off and the second control transistor may be turned on.

[0206] According to still another feature of the present disclosure, while the first light emitting element emits light, a driving current can flow from the first light emitting element to the second control transistor.

[0207] According to still another feature of the present disclosure, while the second light emitting element emits light, the first control transistor may be turned on and the second control transistor may be turned off.

[0208] According to still another feature of the present disclosure, while the second light emitting element emits light, a driving current can flow from the first control transistor to the second light emitting element.

[0209] According to another feature of the present specification, the display device may further include a gate driver electrically connected to the display panel and outputting a first scan signal, a first control signal and a second control signal to the plurality of sub-pixels, wherein the gate driver may include a plurality of first stages generating the first scan signals, and a plurality of control signal generating circuits connected to output terminals of the plurality of first stages generating the first control signals and the second control signals and outputting them to the first control wiring and the second control wiring.

[0210] According to another feature of the present specification, each of the multiple control signal generating circuits includes a first circuit that outputs a first control signal and a second control signal to a first control wiring and a second control wiring while a first light-emitting element emits light, and a second circuit that outputs a first control signal and a second control signal to the first control wiring and the second control wiring while a second light-emitting element emits light, wherein the first circuit outputs a first scan signal to the first control signal and outputs a gate low voltage to the second control signal, and the second circuit outputs the gate low voltage to the first control signal and outputs the first scan signal to the second control signal.

[0211] According to another feature of the present specification, the first circuit includes a first connection transistor having a gate electrode connected to a Q1 node and a source electrode and a drain electrode connected between output terminals of the plurality of first stages and a first control wiring, a second connection transistor having a gate electrode connected to the Q1 node and a source electrode and a drain electrode connected between a gate low wiring and a second control wiring, and a first auxiliary transistor transmitting a first enable signal to the Q1 node, and the second circuit includes a third connection transistor having a gate electrode connected to a Q2 node and a source electrode and a drain electrode connected between output terminals of the plurality of first stages and the second control wiring, a fourth connection transistor having a gate electrode connected to the Q2 node and a source electrode and a drain electrode connected between the gate low wiring and the first control wiring, and a second auxiliary transistor transmitting a second enable signal to the Q2 node.

[0212] According to yet another feature of the present disclosure, the first enable signal and the second enable signal may be opposite phase signals.

[0213] According to still another aspect of the present disclosure, turn-on periods of the first and second connection transistors may be arranged to alternate with turn-on periods of the third and fourth connection transistors.

[0214] According to another aspect of the present invention, a display device includes a substrate, an adhesive layer disposed on the substrate, a first light-emitting element disposed on the adhesive layer and including a first anode and a first cathode, a second light-emitting element disposed on the adhesive layer and including a second anode and a second cathode, and a plurality of reflective electrodes disposed between the substrate and the adhesive layer, the plurality of reflective electrodes including a first reflective electrode electrically connected to the first anode, a second reflective electrode electrically connected to the first cathode and the second anode, and a third reflective electrode electrically connected to the second cathode.

[0215] According to another feature of the present specification, the pixel may further include a first control transistor including a first control source electrode disposed between the substrate and the plurality of reflective electrodes and electrically connected to a high potential power supply wiring, a second control transistor including a second control source electrode disposed between the substrate and the plurality of reflective electrodes and electrically connected to a first control drain electrode of the first control transistor, and a drive transistor including a drive source electrode disposed between the substrate and the plurality of reflective electrodes and electrically connected to a second control drain electrode of the second control transistor, wherein the first reflective electrode is electrically connected to the first control source electrode and the high potential power supply wiring, the second reflective electrode is electrically connected to the first control drain electrode and the second control source electrode, and the third reflective electrode is electrically connected to the second control drain electrode and the drive source electrode.

[0216] According to still another feature of the present specification, the light-emitting element further includes a planarization layer covering the first light-emitting element and the second light-emitting element, and a plurality of connection electrodes disposed on the planarization layer and electrically connecting the first light-emitting element and the second light-emitting element to the plurality of reflective electrodes through contact holes in the planarization layer, where the plurality of connection electrodes may include a first anode connection electrode electrically connecting the first anode and the first reflective electrode, a first cathode connection electrode electrically connecting the first cathode and the second reflective electrode, a second anode connection electrode electrically connecting the second anode and the second reflective electrode, and a second cathode connection electrode electrically connecting the second cathode and the third reflective electrode.

[0217] Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments, and various modifications can be made within the scope of the technical idea of ​​the present specification. Therefore, the embodiments disclosed in the present specification are for illustration purposes, not for limiting the technical idea of ​​the present specification, and the scope of the technical idea of ​​the present specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. a display panel having a plurality of sub-pixels defined therein; A first light-emitting element disposed in each of the plurality of sub-pixels; A second light emitting element connected in series to the first light emitting element; a first control transistor connected in parallel to the first light emitting device and turned on by a first control signal; a second control transistor connected in parallel to the second light emitting element and turned on by a second control signal.

2. The display device according to claim 1 , wherein the first light emitting element and the second light emitting element alternately emit light.

3. 3. The display device of claim 2, wherein the first control transistor is turned off and the second control transistor is turned on while the first light emitting element emits light.

4. The display device according to claim 3 , wherein while the first light emitting element emits light, a drive current flows from the first light emitting element to the second control transistor.

5. 3. The display device of claim 2, wherein the first control transistor is turned on and the second control transistor is turned off while the second light emitting element emits light.

6. The display device according to claim 5 , wherein a drive current flows from the first control transistor to the second light emitting element while the second light emitting element is emitting light.

7. a gate driver electrically connected to the display panel and outputting a first scan signal, the first control signal, and the second control signal to the plurality of sub-pixels; The gate driver includes: a plurality of first stages for generating the first scan signals; The display device according to claim 2, further comprising: a plurality of control signal generating circuits each connected to an output terminal of a corresponding one of the plurality of first stages, generating the first control signal and the second control signal and outputting them to a first control wiring and a second control wiring.

8. Each of the plurality of control signal generating circuits a first circuit that outputs the first control signal and the second control signal to the first control wiring and the second control wiring while the first light emitting element is emitting light; a second circuit that outputs the first control signal and the second control signal to the first control wiring and the second control wiring while the second light emitting element is emitting light; 8. The display device of claim 7, wherein the first circuit outputs the first scan signal to the first control signal and outputs a gate low voltage to the second control signal, and the second circuit outputs the gate low voltage to the first control signal and outputs the first scan signal to the second control signal.

9. The first circuit is a first connection transistor having a gate electrode connected to a first node (Q1) and a source electrode and a drain electrode connected between the output terminals of the first stages and the first control wiring; a second connection transistor having a gate electrode connected to the first node and a source electrode and a drain electrode connected between a gate row line and the second control line; a first auxiliary transistor transmitting a first enable signal to the first node; The second circuit is a third connection transistor having a gate electrode connected to a second node (Q2) and a source electrode and a drain electrode connected between an output terminal of a corresponding one of the first stages and the second control wiring; a fourth connection transistor having a gate electrode connected to the second node and a source electrode and a drain electrode connected between the gate row line and the first control line; The display device of claim 8 , further comprising: a second auxiliary transistor transmitting a second enable signal to the second node.

10. The display device according to claim 9 , wherein the first enable signal and the second enable signal are signals of opposite phases.

11. 11. The display device according to claim 10, wherein the turn-on periods of the first connection transistor and the second connection transistor are alternated with the turn-on periods of the third connection transistor and the fourth connection transistor.

12. the first circuit further includes a first boost capacitor connected between the first node and the first control wiring, The display device according to claim 9 , wherein the second circuit further includes a second boost capacitor connected between the second node and the second control wiring.

13. A substrate; an adhesive layer disposed on the substrate; a first light-emitting element disposed on the adhesive layer, the first light-emitting element including a first anode and a first cathode; a second light emitting element disposed on the adhesive layer, the second light emitting element including a second anode and a second cathode; a plurality of reflective electrodes disposed between the substrate and the adhesive layer; The plurality of reflective electrodes include a first reflective electrode electrically connected to the first anode; a second reflective electrode electrically connected to the first cathode and the second anode; a third reflective electrode electrically connected to the second cathode.

14. a first control transistor disposed between the substrate and the plurality of reflective electrodes and including a first control source electrode electrically connected to a high potential power supply line; a second control transistor disposed between the substrate and the plurality of reflective electrodes, the second control transistor including a second control source electrode electrically connected to a first control drain electrode of the first control transistor; a driving transistor disposed between the substrate and the plurality of reflective electrodes, the driving transistor including a driving source electrode electrically connected to a second control drain electrode of the second control transistor; 14. The display device of claim 13, wherein the first reflective electrode is electrically connected to the first control source electrode and the high potential power supply wiring, the second reflective electrode is electrically connected to the first control drain electrode and the second control source electrode, and the third reflective electrode is electrically connected to the second control drain electrode and the driving source electrode.

15. a planarization layer covering the first light emitting element and the second light emitting element; a plurality of connection electrodes disposed on the planarization layer and electrically connecting the first light emitting element and the second light emitting element to the plurality of reflective electrodes through contact holes in the planarization layer; The plurality of connection electrodes are a first anode connecting electrode that electrically connects the first anode and the first reflective electrode; a first cathode connecting electrode electrically connecting the first cathode and the second reflective electrode; a second anode connecting electrode that electrically connects the second anode and the second reflective electrode; The display device according to claim 14 , further comprising a second cathode connecting electrode that electrically connects the second cathode and the third reflective electrode.

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