Increased slew rate at source amplifier input

Abstract

To solve a problem that shortening of a settling time can be problematic for source amplifiers due to recent increase in display resolution and a frame rate of panel display devices.SOLUTION: A display driver includes a plurality of gamma bus lines and a drive leg configured to receive pixel data. The drive leg includes a decoder having first output and second output, a source amplifier having a set of pieces of input, and a source interpolation selector. The decoder electrically connects the first output to a first one of the gamma bus lines and electrically connects the second output to a second one of the gamma bus lines on the basis of the pixel data. The source interpolation selector provides electrical connection between the first output and second output of the decoder and the set of pieces of input of the source amplifier on the basis of the pixel data, and electrically connects the first output and second output of the decoder during a first period of a horizontal synchronization period.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present disclosure relates generally to an apparatus and method for driving a display panel, and more particularly to increasing the slew rate at a source amplifier input.

[0002] A display driver of a panel display device, such as a liquid crystal display (LCD) device, an organic light emitting diode (OLED) display device, or a micro light emitting diode (μLED) display device, may use a source amplifier to drive source lines of a display panel. In a typical implementation, the source amplifiers may be configured to receive one or more gamma voltages selected by a decoder based on pixel data, and generate data voltages corresponding to the pixel data from the received one or more gamma voltages. The data voltages generated by the source amplifiers may be output to source lines of the display panel and then supplied to selected pixels of the display panel to update or program the pixels.

[0003] Due to recent increases in display resolution and frame rate of panel display devices, shortening the settling time can be an issue for source amplifiers. The settling time here is the time required for the output to reach and remain within a given error range following an input stimulus. The source amplifier is sometimes designed to shorten the settling time, since shortening the settling time of the source amplifier can increase the operating speed of the display driver.

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below. It is not intended to necessarily identify key features or essential features of the present disclosure. The present disclosure may include various aspects and embodiments described below.

[0005] In an exemplary embodiment, the present disclosure provides a display driver comprising a plurality of gamma bus lines on which a plurality of gamma voltages are generated, and a drive leg configured to receive first pixel data and the plurality of gamma voltages. The drive leg comprises a decoder, a source amplifier, and a source interpolation selector. The decoder has a first output and a second output, and is configured to electrically connect the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data and to electrically connect the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data. The source amplifier has a set of inputs and is configured to provide data voltages to the display panel based on a set of input voltages at the set of inputs. The source interpolation selector is configured to provide an electrical connection between the first and second outputs of the decoder and the set of inputs of the source amplifier based on the first pixel data. The source interpolation selector is further configured to electrically connect the first and second outputs of the decoder during a first period of a horizontal synchronization period.

[0006] In another exemplary embodiment, the present disclosure provides a display device comprising a display panel and a display driver. The display driver comprises a plurality of gamma bus lines on which a plurality of gamma voltages are respectively generated, and a driving leg configured to receive first pixel data and the plurality of gamma voltages. The driving leg comprises a decoder, a source amplifier, and a source interpolation selector. The decoder has a first output and a second output, and is configured to electrically connect the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data, and to electrically connect the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data. The source amplifier has a set of inputs, and is configured to provide data voltages to the display panel based on a set of input voltages at the set of inputs. The source interpolation selector is configured to provide an electrical connection between the first and second outputs of the decoder and the set of inputs of the source amplifier based on the first pixel data. The source interpolation selector is further configured to electrically connect the first and second outputs of the decoder during a first period of a horizontal synchronization period.

[0007] In yet another exemplary embodiment, the present disclosure provides a method. The method includes generating a plurality of gamma voltages on a plurality of gamma bus lines, respectively. The method further includes electrically connecting a first output of the decoder to a first gamma bus line of the plurality of gamma bus lines based on first pixel data provided to the decoder, and electrically connecting a second output of the decoder to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data. The method further includes electrically connecting the first and second outputs of the decoder during a first one of the horizontal synchronization periods. The method further includes electrically connecting the first and second outputs of the decoder to a set of inputs of a source amplifier based on the first pixel data during a second one of the horizontal synchronization periods following the first one of the horizontal synchronization periods. The method further includes providing, by the source amplifier, data voltages to a display panel based on a set of input voltages at the set of inputs during the first and second periods.

[0008] Further features and aspects are described in more detail below with reference to the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 illustrates an exemplary partial configuration of a display driver including a source amplifier.

[0010] [Diagram 2] FIG. 2 illustrates an example configuration of a panel display device according to one or more embodiments.

[0011] [Figure 3A] FIG. 3A illustrates a partial example configuration of a display driver according to one or more embodiments.

[0012] [Figure 3B] FIG. 3B illustrates an example configuration of a gamma voltage generator according to one or more embodiments.

[0013] [Figure 4] FIG. 4 illustrates an example drive leg configuration according to one or more embodiments.

[0014] [Diagram 5] FIG. 5 illustrates an example of the operation of a driving leg according to one or more embodiments.

[0015] [Figure 6] FIG. 6 is a schematic diagram illustrating an example operation of a driving leg in accordance with one or more embodiments.

[0016] [Figure 7] FIG. 7 is an equivalent circuit diagram of selected gamma bus lines according to one or more embodiments.

[0017] [Figure 8] FIG. 8 is a schematic diagram illustrating an example operation of a driving leg in accordance with one or more embodiments.

[0018] [Figure 9] FIG. 9 illustrates an example of a display driver configuration according to another embodiment.

[0019] [Figure 10] FIG. 10 is a flowchart of an example process for driving a display panel according to one or more embodiments.

[0020] For ease of understanding, the same reference numbers are used, where possible, to designate identical elements common to the figures. It is anticipated that elements disclosed in one embodiment may be beneficially used in other embodiments without specific mention. Reference numbers may be subscripted to distinguish identical elements from one another. The drawings referred to herein should not be understood to be drawn to scale unless specifically noted. Also, for clarity of presentation and explanation, the drawings are often simplified and details or components are omitted. The drawings and discussion serve to explain the principles discussed below. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The following detailed description is exemplary in nature and is not intended to be limiting as to the disclosure and its application and uses, nor is there any intention to be bound by any expressed or implied theory presented in the preceding background, brief summary and drawings, or in the following detailed description.

[0022] In the following detailed description of the embodiments, many specific details are presented to provide a deeper understanding of the disclosed technology. However, it will be apparent to those skilled in the art that the disclosed technology can be implemented without using these specific details. In other instances, well-known configurations are not described in detail to avoid unnecessarily complicating the description.

[0023] The term "coupled" as used herein means directly connected or connected via one or more intervening components or circuits. Additionally, ordinal numbers (e.g., first, second, third, etc.) may be used throughout the application as adjectives of elements (i.e., any nouns in the application). The use of ordinal numbers is not intended to imply or create a particular ordering of any elements, nor is it intended to limit any element to only a single element, unless expressly disclosed, for example, by the use of "before," "after," "single," and other similar terms. Rather, the use of ordinal numbers is intended to distinguish elements. For example, a first element is distinct from a second element, and a first element may include more than one element and may follow (or precede) a second element in the ordering of elements.

[0024] As mentioned above, due to the recent increase in display resolution and frame rate of panel display devices, shortening the settling time can be an issue for source amplifiers. By shortening the settling time of the source amplifier, the operating speed of the display driver can be increased, so the source amplifier is sometimes designed to shorten the settling time.

[0025] This disclosure recognizes that one approach to shortening the settling time of a source amplifier is to improve or increase the slew rate of one or more inputs of the source amplifier. Slew rate, as used herein, is the rate of voltage change per unit time. By increasing the slew rate at the input of the source amplifier, the voltage at the input of the source amplifier will reach a desired voltage level more quickly when driven to that level, shortening the settling time of the source amplifier. The slew rate at the input of the source amplifier will be described below first.

[0026] Fig. 1 illustrates a partial configuration example of a display driver 100 including a source amplifier 120. In the configuration of Fig. 1, a decoder 110 is configured to select one gamma voltage from a plurality of gamma voltages generated by a gamma voltage generator 130 based on pixel data, and to supply the selected gamma voltage to a source amplifier 120. The source amplifier 120 is configured to generate a data voltage from the selected gamma voltage, and output the data voltage to a source output S[i] coupled to a pixel to be programmed.

[0027] The slew rate at the input of the source amplifier 120 depends on the RC time constant for the input of the source amplifier 120. In the configuration shown in FIG. 1, the RC time constant is the product of the input capacitance C_IN of the source amplifier 120 and the resistance of the path that supplies the selected gamma voltage from the gamma voltage generator 130 to the input of the source amplifier 120. The path includes the gamma bus line 135 that supplies the selected gamma voltage from the gamma voltage generator 130 to the decoder 110 and the series-connected switches in the decoder 110. The resistance of the path is the sum of the resistance R_gamma of the gamma bus line 135 and the on-resistance R_ON of the decoder. Here, the on-resistance R_ON is the sum of the on-resistances of the series-connected switches of the decoder 110. The slew rate at the input of the source amplifier 120 can be increased by reducing the effective resistance of the path that supplies the selected gamma voltage to the input of the source amplifier 120.

[0028] Based on this finding, the present disclosure provides various techniques for reducing the effective resistance of the path that provides the selected gamma voltage from the gamma voltage generator to the input of the source amplifier in the display driver. Various embodiments for increasing or enhancing the slew rate at the input of the source amplifier are described below.

[0029] FIG. 2 illustrates an example configuration of a display device 500 according to one or more embodiments. In the illustrated embodiment, the display device 500 is configured as a panel display device including a display panel 200 and a display driver 300. The display driver 300 is configured to drive the display panel 200 under the control of a host 400. Examples of the host 400 include application processors, central processing units (CPUs), and other processors and controllers suitable for controlling the display device 500. In one implementation, the display driver 300 is configured to generate data voltages based on pixel data received from the host 400 and output the data voltages from source outputs S[1]-S[n] to the display panel 200. The data voltages are supplied to pixels of the display panel 200 to program the pixels.

[0030] 3A illustrates an example of a partial configuration of a display driver 300 according to one or more embodiments. In the illustrated embodiment, the display driver 300 includes a set of drive legs 310-1 to 310-n, a gamma voltage generator 320, and a control circuit 370, where n is a natural number equal to or greater than 2. When the drive legs 310-1 to 310-n are not distinguished from one another, they may be collectively referred to simply as drive legs 310.

[0031] The driving legs 310-1 to 310-n are configured to generate data voltages based on pixel data D[1] to D[n] and output the data voltages to the source outputs S[1] to S[n], respectively. The pixel data D[1] to D[n] specify the grayscale of the pixel to be programmed with the data voltages output from the source outputs S[1] to S[n], respectively. The data voltages output from the source outputs S[1] to S[n] have voltage levels corresponding to the grayscale of the pixel data D[1] to D[n], respectively. In some implementations, the pixel data D[1] to D[n] may be generated by performing desired image processing (e.g., color adjustment, scaling, demurration, overshoot drive, contrast enhancement, gamma conversion, and other image processing) on ​​pixel data received from the host 400 (shown in FIG. 2). In other implementations, the pixel data received from the host 400 may be used as the pixel data D[1] to D[n] as is. The driving legs 310-1 to 310-n are configured to generate data voltages using a set of gamma voltages Vg[0] to Vg[m] received from a gamma voltage generator 320, where m is a natural number equal to or greater than 2. The gamma voltage generator 320 is configured to generate gamma voltages Vg[0] to Vg[m] and supply them to each of the driving legs 310-1 to 310-n via a gamma bus 330 having a set of gamma bus lines GL[0] to GL[m]. The gamma voltages Vg[0] to Vg[m] are generated on the gamma bus lines GL[0] to GL[m], respectively.

[0032] 3B illustrates an example configuration of a gamma voltage generator 320 according to one or more embodiments. In the illustrated embodiment, the gamma voltage generator 320 includes a gamma resistor string 322, a gamma top amplifier 324, a gamma bottom amplifier 326, and a set of gamma tap amplifiers 328-1 to 328-r (two shown), where r is a natural number equal to or greater than 1. The gamma top amplifier 324 outputs a gamma top voltage V TOP The gamma bottom amplifier 326 is configured to provide a gamma bottom voltage VBOTTOM The gamma tap amplifiers 328-1 to 328-r are configured to supply tap voltages V TAP1 ~V TAPr to a corresponding center tap of the gamma resistor string 322. The gamma bus line GL[0] is coupled to the first end 322a of the gamma resistor string 322, and thus the gamma voltage Vg[0] is coupled to the gamma top voltage V TOP The gamma bus line GL[m] is coupled to the second end 322b of the gamma resistor string 322, and thus the gamma voltage Vg[m] is equal to the gamma bottom voltage V BOTTOM The gamma bus lines GL[1] to GL[m-1] are coupled to the middle positions of the gamma resistor string 322, and the gamma voltages Vg[1] to Vg[m-1] are generated on the gamma bus lines GL[1] to GL[m-1] by voltage division using the gamma resistor string 322.

[0033] Returning to FIG. 3A, each driving leg 310 includes a decoder (DEC) 340, a source interpolation selector 350, and a source amplifier 360. The decoder 340 of each driving leg 310 has a set of inputs coupled to the gamma bus lines GL[0]-GL[m], respectively, and two outputs coupled to the source interpolation selector 350. The source amplifier 360 has a set of inputs coupled to the source interpolation selector 350. In the illustrated embodiment, the source amplifier 360 has three inputs. In other embodiments, the number of inputs of the source amplifier 360 may be two, four, or more. The source interpolation selector 350 is configured to provide an electrical connection between the output of the decoder 340 and the input of the source amplifier 360.

[0034] The display driver 300 further includes a control circuit 370 configured to generate and provide a shunt control signal to the source interpolation selector 350 of each drive leg 310. As will be discussed in detail below, the shunt control signal is used to instruct each source interpolation selector 350 to electrically connect the two outputs of the corresponding decoder 340, thereby shunting (shorting) the two outputs. The control circuit 370 may include a register 375 that stores a register value used to control the shunt control signal. The register value stored in the register 375 may indicate the duration of the period that the shunt control signal is held in an asserted state each time the shunt control signal is asserted. In one implementation, the register 375 is configured to be accessible by an entity external to the display driver 300, such as the host 400 illustrated in FIG. 1. In such an implementation, the external entity, such as the host 400, may be configured to program the register value stored in the register 375.

[0035] 4 illustrates an example configuration of each driving leg 310-i according to one or more embodiments. In the illustrated embodiment, the decoder 340 of the driving leg 310-i includes a switch array 342, a first output 344, and a second output 346. The switch array 342 is configured to select two of the gamma bus lines GL[0] to GL[m] based on the most significant p bits (the p bits from the top) of the pixel data D[i], and couple the two selected gamma bus lines to the first output 344 and the second output 346, respectively. Here, the pixel data D[i] is (p+q)-bit data. In an embodiment in which the pixel data D[i] is 10-bit data, p may be 8 and q may be 2, for example.

[0036] Source amplifier 360 has a set of inputs and is configured to drive source output S[i] based on input voltages at the inputs. In one implementation, source amplifier 360 may be configured to drive source output S[i] to a voltage that is a weighted average of the voltages at the outputs of source amplifier 360. In the illustrated embodiment, source amplifier 360 has three inputs 362-1, 362-2, and 362-3. In one implementation, weights assigned to inputs 362-1, 362-2, and 362-3 may be ¼, ¼, and ¼, respectively. In this case, the voltage V at source output S[i] may be OUT is expressed by the following formula (1). (1) V OUT =(1 / 4)V IN1 +(2 / 4)V IN2 +(1 / 4)V IN3 Here, V IN1 , V IN2 , V IN3 are the voltages at the inputs 362-1, 362-2, and 362-3, respectively. The voltage generated at the source output S[i] is used as a data voltage to program the selected pixel coupled to the source output S[i].

[0037] The source interpolation selector 350 is configured to operate in response to the least significant q bits (or the lowest q bits) of the (p+q)-bit pixel data D[i] and a shunt control signal received from the control circuit 370 (shown in FIG. 3A). The source interpolation selector 350 is configured to provide an electrical connection between the output of the decoder 340 and the input of the source amplifier 360 based on the least significant q bits of the (p+q)-bit pixel data D[i]. As will be discussed in detail later, the electrical connection in the source interpolation selector 350 is controlled based on the least significant q bits of the (p+q)-bit pixel data D[i] such that the source amplifier 360 provides a data voltage corresponding to the pixel data D[i] to the source output S[i]. Furthermore, the source interpolation selector 350 is configured to electrically connect the first output 344 and the second output 346 of the decoder 340 in response to the shunt control signal to shunt or short the first output 344 and the second output 346.

[0038] In the illustrated embodiment, the source interpolation selector 350 includes a first set of switches 352-1, 352-2, 352-3 and a second set of switches 354-1, 354-2, 354-3. The first set 352-1, 352-2, 352-3 are coupled between a first output 344 of the decoder 340 and inputs 362-1, 362-2, 362-3, respectively. The second set 354-1, 354-2, 354-3 are coupled between a second output 346 of the decoder 340 and inputs 362-1, 362-2, 362-3, respectively.

[0039] In one implementation, the source interpolation selector 350 has two modes, a select mode and a shunt mode. In the select mode, where the shunt control signal is deasserted, the source interpolation selector 350 is configured to electrically connect one of the first output 344 and the second output 346 of the decoder 340 to each of the inputs 362-1, 362-2, 362-3 based on the least significant q bits of the pixel data D[i]. More specifically, the source interpolation selector 350 is configured to close (turn on) one of the switches 352-1, 354-1 to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-1 of the source amplifier 360 based on the least significant q bits of the pixel data D[i]. The source interpolation selector 350 is further configured to close (turn on) one of the switches 352-2, 354-2 based on the least significant q bits of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-2 of the source amplifier 360. The source interpolation selector 350 is further configured to close (turn on) one of the switches 352-3, 354-3 based on the least significant q bits of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-3 of the source amplifier 360. It should be noted that in the selection mode, the source interpolation selector 350 electrically isolates the first output 344 and the second output 346 of the decoder 340 from each other.

[0040] In shunt mode when the shunt control signal is asserted, the source interpolation selector 350 closes (or turns on) all of the switches 352-1, 352-2, 352-3, 354-1, 354-2, 354-3 to shunt or short the first output 344 and the second output 346 of the decoder 340, and further electrically connects both the first output 344 and the second output 346 to the inputs 362-1, 362-2, 362-3, respectively, of the source amplifier 360. As will be discussed in detail later, by shunting (or shorting) the first output 344 and the second output 346 by the source interpolation selector 350, the effective resistance of the path supplying the selected gamma voltage from the gamma voltage generator 320 to the inputs 362-1, 362-2, and 362-3 of the source amplifier 360 is effectively reduced, thereby increasing the slew rate at the inputs 362-1, 362-2, and 362-3.

[0041] 5 illustrates an example of operation of the drive leg 310-i shown in FIG. 4 during horizontal synchronization periods 502 and 504, in accordance with one or more embodiments. At time t0, the horizontal synchronization signal used in the display driver 300 is asserted to begin the horizontal synchronization period 502. At the start of the horizontal synchronization period 502, the pixel data D[i] for the drive leg 310-i is Data[T-1], and the source output S[i] is at a voltage level V[T-1] corresponding to Data[T-1]. Si It is set to [T-1].

[0042] At time t1 in the horizontal synchronization period 502, the pixel data D[i] changes from Data[T-1] to Data[T]. When the pixel data D[i] changes, the selection of the gamma bus lines GL[0] to GL[m] by the decoder 340 (i.e., the selection of the gamma voltages Vg[0] to Vg[m]) changes, and as a result, the voltage at the source output S[i] changes to a voltage level V corresponding to Data[T], as shown by the solid line 510. Si[T]. Furthermore, the shunt control signal is asserted in synchronization with the change in pixel data D[i] at time t1. By asserting the shunt control signal at time t1, the source interpolation selector 350 is set to the shunt mode at the initial stage of the voltage change in the source output S[i].

[0043] FIG. 6 is a conceptual diagram illustrating an example of the operation of the driving leg 310-i during the period between time t1 and time t2 of the horizontal synchronization period 502, according to one or more embodiments. The decoder 340 selects two adjacent gamma bus lines GL[N] and GL[N-1] from the gamma bus 330 based on the most significant p bits of the pixel data D[i], which is Data[T] during the period between time t1 and time t2, where N is a natural number from 1 to m. Furthermore, the decoder 340 electrically connects the gamma bus line GL[N] to a first output 344 and electrically connects the gamma bus line GL[N-1] to a second output 346. It should be noted that the gamma bus lines GL[N] and GL[N-1] are used to supply gamma voltages Vg[N] and Vg[N-1], respectively, from the gamma voltage generator 320 to the decoder 340 of each driving leg 310, as also illustrated in FIG. 7. The decoder 340 detects the voltage level V Si The decoder 340 further electrically couples the selected gamma bus line GL[N] to a first output 344 and electrically couples the selected gamma bus line GL[N-1] to a second output 346.

[0044] The source interpolation selector 350 is set to the shunt mode in response to the assertion of the shunt control signal at time t1. In the shunt mode, the source interpolation selector 350 closes (or turns on) all of the switches 352-1 to 352-3 and 354-1 to 354-3. By closing the switches 352-1 to 352-3 and 354-1 to 354-3, the source interpolation selector 350 electrically connects both the first output 344 and the second output 346 of the decoder 340 to the inputs 362-1, 362-2, and 362-3 of the source amplifier 360, respectively. As a result, each of the inputs 362-1, 362-2, and 362-3 of the source amplifier 360 is driven toward a voltage between the gamma voltages Vg[N] and Vg[N-1], and the source amplifier 360 drives the source output S[i] toward that voltage.

[0045] On the other hand, by turning on the switches 352-1 to 352-3 and 354-1 to 354-3, the first output 344 and the second output 346 of the decoder 340 are electrically connected and shorted. As a result of the electrical connection between the first output 344 and the second output 346, the gamma bus line GL[N] and the gamma bus line GL[N-1] are electrically connected in parallel. More specifically, when the first output 344 and the second output 346 are electrically connected, a first path formed by a first set of series-connected switches in the decoder 340 between the gamma bus line GL[N] and the first output 344 and the gamma bus line GL[N], and a second path formed by a second set of series-connected switches in the decoder 340 between the gamma bus line GL[N-1] and the second output 346 and the gamma bus line GL[N-1] are electrically connected in parallel. Although the resistance of gamma bus lines GL[N] and GL[N-1] (denoted as "R_gamma" in FIG. 7) and the on-resistance of the series-connected switches in decoder 340 may be significant, connecting the first and second paths in parallel reduces the effective resistance of the path supplying the gamma voltage to each input of source amplifier 360, thereby reducing the RC time constant at each input of source amplifier 360. Reducing the RC time constant at each input of source amplifier 360 effectively increases the slew rate at each input of source amplifier 360.

[0046] Returning to FIG. 5, the shunt control signal is maintained asserted during the period from time t1 to time t2. In FIG. 5, the assertion duration of the shunt control signal, that is, the duration of the period from time t1 to time t2, is set to “T SH The assertion duration of the shunt control signal T SH (i.e., the time interval between time t1 and time t2) may be adjusted based on the characteristics of the display panel 200 and the display driver 300, such as the capacitance and / or resistance of the source lines of the display panel 200 and the driving capability of the source amplifier 360. In some embodiments, the display driver 300 may adjust the assertion duration T SHIn some embodiments, a register value stored in register 375 (shown in FIG. 3A ) determines the assertion duration T of the shunt control signal. SH In such an embodiment, the assertion duration T SH may be adjusted by programming the register value.

[0047] At time t2, the shunt control signal is deasserted to set the source interpolation selector 350 into the selection mode. In the illustrated embodiment, the shunt control signal remains deasserted until time t4 of the next horizontal sync period 504, which begins at time t3.

[0048] 8 is a conceptual diagram illustrating an example operation of the driving leg 310-i during a period between times t2 and t4, according to one or more embodiments. Because the source interpolation selector 350 is in a selection mode, the source interpolation selector 350 electrically decouples the first output 344 and the second output 346 of the decoder 340 from each other. Thus, the first output 344 is driven to the gamma voltage Vg[N] provided by the gamma bus line GL[N], and the second output 346 is driven to the gamma voltage Vg[N-1] provided by the gamma bus line GL[N-1].

[0049] Furthermore, the source interpolation selector 350 electrically connects the selected one of the first output 344 and the second output 346 of the decoder 340 to the inputs 361-1, 361-2, and 361-3 of the source amplifier 360 based on the lower q bits of the pixel data D[i], which is Data[T] during the period from time t2 to time t3. As a result, the gamma voltage Vg[N] or Vg[N-1] is supplied to each of the inputs 361-1, 361-2, and 361-3 of the source amplifier 360 based on the lower q bits of the pixel data D[i]. More specifically, the source interpolation selector 350 closes (or turns on) one of the switches 352-1 and 354-1 based on the lower q bits of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-1 of the source amplifier 360. As a result, the gamma voltage Vg[N] or Vg[N-1] is provided to the input 362-1 based on the lower q bits of the pixel data D[i]. The source interpolation selector 350 further closes (or turns on) one of the switches 352-2 and 354-2 based on the lower q bits of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-2 of the source amplifier 360. As a result, the gamma voltage Vg[N] or Vg[N-1] is provided to the input 362-2 based on the lower q bits of the pixel data D[i]. The source interpolation selector 350 further closes (or turns on) one of the switches 352-3 and 354-3 based on the lower q bits of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-3 of the source amplifier 360. As a result, the gamma voltage Vg[N] or Vg[N-1] is supplied to the input 362-3 based on the lowest q bits of the pixel data D[i].

[0050] Source amplifier 360 drives source output S[i] in response to the voltages at inputs 362-1, 362-2, and 362-3. In one implementation, source amplifier 360 drives source output S[i] to a voltage that is a weighted average of the voltages at inputs 362-1, 362-2, and 362-3. For example, in an embodiment where the weights assigned to inputs 362-1, 362-2, and 362-3 are ¼, ¼, and ¼, respectively, the voltage V generated at source output S[i] is OUT is expressed by the following formula (2): (2) V OUT =(1 / 4)V IN1 +(2 / 4)V IN2 +(1 / 4)V IN3 Here, V IN1 , V IN2 , V IN3 are the voltages at the inputs 362-1, 362-2 and 362-3, respectively. The voltage generated at the source output S[i] is used as a data voltage to program the selected pixel coupled to the source output S[i]. The combination of gamma voltages (Vg[N] or Vg[N-1]) provided to each input 362-1, 362-2 and 362-3 causes the voltage at the source output S[i] to reach a voltage level Vg[N] corresponding to Data[T]. Si It is determined to be driven by [T].

[0051] Returning to FIG. 5, the driving leg 310-i may operate in a similar manner in the next horizontal synchronization period 504 beginning at time t3. In the illustrated embodiment, at time t4 of the horizontal synchronization period 504, the pixel data D[i] changes from Data[T] to Data[T+1], and the shunt control signal is asserted in synchronization with the change in the pixel data D[i] at time t4. After time t4, the driving leg 310-i performs operations similar to those described above in connection with FIGS. 6-8, except that the pixel data D[i] changes from Data[T] to Data[T+1]. More specifically, the change in the pixel data D[i] causes the decoder 340 to change its selection of the gamma bus lines GL[0]-GL[m] (i.e., its selection of the gamma voltages Vg[0]-Vg[m]), causing the voltage at the source output S[i] to change to a voltage level V[T+1] corresponding to Data[T+1], as shown by solid line 510. Si [T+1]. Furthermore, the assertion of the shunt control signal places the source interpolation selector 350 in shunt mode to electrically couple the first output 344 and the second output 346 of the decoder 340. The shunt control signal remains asserted until time t5. The shunt control signal is then deasserted at time t5 to place the source interpolation selector 350 in select mode. In select mode, the source interpolation selector 350 provides one of the two selected gamma voltages to each of the inputs 362-1, 362-2, and 362-3 of the source amplifier 360. The source amplifier 360 adjusts the source output S[i] to a voltage level V corresponding to Data[T+1] in response to the voltages at the inputs 362-1, 362-2, and 362-3. Si Drive to [T+1].

[0052] Note that although FIG. 5 illustrates pixel data D[i] changing once each horizontal synchronization period, pixel data D[i] may change multiple times each horizontal synchronization period.

[0053] 5-8 effectively increases the slew rate at the input of the source amplifier 360 during the initial phase of the change in the voltage at the source output S[i], thereby achieving a reduction in the settling time of the source amplifier 360. An example of the reduction in the settling time is illustrated in FIG 5, where the solid line 510 shows an example of the change in the voltage at the source output S[i] when the first output 344 and the second output 346 of the decoder 340 are electrically connected during the initial phase, and the dashed lines 520 and 525 show an example of the change in the voltage at the source output S[i] when the first output 344 and the second output 346 are not electrically connected during the initial phase.

[0054] FIG. 9 illustrates an example configuration of a display driver 900 according to another embodiment. The display driver 900 is configured similarly to the display driver 300 illustrated in FIG. 3A and operates similarly to that illustrated in FIG. 5. One difference is that each drive leg 380-i includes a control circuit 390 that provides a shunt control signal to the source interpolation selector 350. The control circuit 390 controls the assertion duration of the shunt control signal ("T" illustrated in FIG. 5). SH The control circuit 390 for the driving leg 380-i is configured to generate and provide a shunt signal to the source interpolation selector 350 based on the pixel data D[i]. In one or more embodiments, the control circuit 390 for the driving leg 380-i is configured to control the assertion duration T SH The assertion duration T of the shunt control signal is adjusted. SH By using the pixel data D[i] to adjust the assertion duration T SH It may be possible to determine.

[0055] In various embodiments, the control circuit 390 of each drive leg 380-i determines the assertion duration T of the shunt control signal based on Data[T-1] and Data[T] when the pixel data D[i] changes from Data[T-1] to Data[T]. SH(shown in FIG. 5 ). Note that Data[T-1] is the previous pixel data provided to the decoder 340 before Data[T] is provided to the decoder 340. In some embodiments, the control circuit 390 of each drive leg 380-i may be configured to adjust the assertion duration T of the shunt control signal based on the difference between Data[T-1] and Data[T] (more specifically, the difference between the gray level specified by Data[T-1] and the gray level specified by Data[T]) when the pixel data D[i] changes from Data[T-1] to Data[T]. SH In one implementation, the assertion duration T of the shunt control signal may be adjusted. SH is adjusted to increase as the difference between Data[T-1] and Data[T] (or the difference between the gray scale specified by Data[T-1] and the gray scale specified by Data[T]) increases.

[0056] In some implementations, the control circuit 390 of each drive leg 380-i determines the assertion duration T of the shunt control signal based on one or more most significant bits of Data[T-1] and Data[T] when the pixel data D[i] changes from Data[T-1] to Data[T]. SH In an embodiment where Data[T-1] and Data[T] are (p+q)-bit data, the assertion duration T SH may be adjusted based on the most significant r bits of Data[T-1] and Data[T], where r is an integer less than p+q. By using only one or more most significant bits of Data[T-1] and Data[T], the circuit size of the control circuit 390 can be advantageously reduced. The control circuit 390 of each driving leg 380-i adjusts the assertion duration T of the shunt control signal based on the difference between one or more most significant bits of Data[T-1] and Data[T]. SH In one implementation, the control circuit 390 of each driving leg 380-i may be configured to adjust the assertion duration T of the shunt control signal based on the difference between the most significant bit (MSB) of Data[T-1] and the MSB of Data[T].SH may be configured to adjust

[0057] 10 is a flowchart of an example process for driving a display panel, according to one or more examples of the present disclosure. Process 1000 may be performed by the display driver 300 illustrated in FIG 3A or FIG 9. However, it will be recognized that a display driver having additional or fewer components than those illustrated in FIG 3A or FIG 9 may be used to perform process 1000, that any of the steps described below may be performed in any suitable order, and that process 1000 may be performed in any suitable environment.

[0058] The process 1000 includes, in step 1002, generating a plurality of gamma voltages (e.g., gamma voltages Vg[0] through Vg[m] illustrated in FIGS. 3A and 9) on a plurality of gamma bus lines (e.g., gamma bus lines GL[0] through GL“m”), respectively.

[0059] The process 1000 further includes, at step 1004, electrically connecting a first output of the decoder (e.g., the first output 344 shown in FIG. 4) to a first gamma bus line (e.g., the gamma bus line GL[N] shown in FIG. 6) of the plurality of gamma bus lines based on first pixel data (e.g., pixel data D[i] shown in FIGS. 3A, 6, and 9) provided to the decoder (e.g., the decoder 340). The process 1000 further includes, at step 1006, electrically connecting a second output of the decoder (e.g., the second output 346 shown in FIG. 4) to a second gamma bus line (e.g., the gamma bus line GL[N-1] shown in FIG. 6) of the plurality of gamma bus lines based on the first pixel data.

[0060] Process 1000 further includes, in step 1008, electrically connecting the first output and the second output of the decoder during a first period (e.g., the period between times t1 and t2 shown in FIG. 5) of a horizontal synchronization period (e.g., horizontal synchronization period 502 shown in FIG. 5).

[0061] Process 1000 further includes, in step 1010, providing electrical connections between a first output and a second output of the decoder and a pair of inputs of a source amplifier (e.g., source amplifier 360 shown in Figures 3A and 9) based on the first pixel data during a second period following the first period of the horizontal synchronization period (e.g., the period between times t2 and t3 in Figure 5).

[0062] Process 1000 further includes, in step 1012, supplying data voltages to a display panel (e.g., display panel 200 shown in FIG. 2) by the source amplifier based on a set of input voltages at the set of inputs during a first period and a second period.

[0063] The use of "a," "an," "the," "at least one," and similar reference words in the context of describing the present invention (particularly in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The use of the term "at least one" followed by a list of one or more items (e.g., "at least one of A and B") should be construed to mean one item selected from the listed items (A or B), or any combination of two or more of the listed items (A and B), unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "including" are to be construed as open-ended terms (i.e., meaning "including, but not limited to"), unless otherwise indicated. The recitation of ranges of values ​​herein is intended to merely serve as a shorthand method for individually referring to each individual value falling within the range, and each individual value is incorporated herein as if set forth individually herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. Any examples provided herein, or the use of exemplary language (e.g., "such as"), are intended merely to better illustrate the invention and do not limit the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.

[0064] Exemplary embodiments are described herein. Variations of those exemplary embodiments will become apparent to those skilled in the art upon reading the foregoing description. The inventors expect that those skilled in the art will adopt such variations as appropriate, and the inventors do not intend to practice the invention otherwise than as specifically described herein. Accordingly, this invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the invention unless otherwise indicated herein or otherwise clearly contradicted by context.

Claims

1. a plurality of gamma bus lines on which a plurality of gamma voltages are generated respectively; a drive leg configured to receive first pixel data and the plurality of gamma voltages; Equipped with The driving leg is a decoder having a first output and a second output, the decoder being configured to electrically connect the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data and to electrically connect the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; a source amplifier having a set of inputs and configured to provide data voltages to a display panel based on a set of input voltages at the set of inputs; a source interpolation selector configured to provide electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier based on the first pixel data, and to electrically connect the first and second outputs of the decoder during a first period of a horizontal synchronization period; Equipped Display driver.

2. The source interpolation selector is further configured to electrically connect each of the inputs of the source amplifier to the first output or the second output during a second period following the first period of the horizontal synchronization period.

2. A display driver as claimed in claim 1.

3. The source interpolation selector: a first set of switches respectively coupled between the first output of the decoder and the set of inputs of the source amplifier; a second set of switches respectively coupled between the second output of the decoder and the set of inputs of the source amplifier; Equipped 2. A display driver as claimed in claim 1.

4. electrically connecting the first output and the second output of the decoder during the first time period includes closing all of the first set of switches and all of the second set of switches during the first time period.

4. A display driver according to claim 3.

5. the source interpolation selector further configured to receive a shunt control signal; Electrically connecting the first output and the second output of the decoder during the first period of the horizontal synchronization period in response to the shunt control signal.

2. A display driver as claimed in claim 1.

6. the duration of the first period is programmable; 2. A display driver as claimed in claim 1.

7. and a control circuit configured to adjust the duration of the first period.

2. A display driver as claimed in claim 1.

8. Adjusting the duration of the first period is based on the first pixel data and second pixel data provided to the decoder before the first pixel data is provided to the decoder. A display driver according to claim 7.

9. Adjusting the duration of the first period is based on a difference between the first pixel data and second pixel data provided to the decoder before the first pixel data is provided to the decoder. A display driver according to claim 7.

10. Adjusting the duration of the first period is based on one or more most significant bits of the first pixel data and second pixel data provided to the decoder before the first pixel data is provided to the decoder. A display driver according to claim 7.

11. A display panel; A display driver; Equipped with The display driver a plurality of gamma bus lines on which a plurality of gamma voltages are generated respectively; a drive leg configured to receive first pixel data and the plurality of gamma voltages; Equipped with The driving leg is a decoder having a first output and a second output, the decoder being configured to electrically connect the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data and to electrically connect the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; a source amplifier having a set of inputs and configured to provide data voltages to the display panel based on a set of input voltages at the set of inputs; a source interpolation selector configured to provide electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier based on the first pixel data, and to electrically connect the first and second outputs of the decoder during a first period of a horizontal synchronization period; Display device.

12. The source interpolation selector is further configured to electrically connect each of the inputs of the source amplifier to the first output or the second output during a second period following the first period of the horizontal synchronization period. The display device according to claim 11.

13. The source interpolation selector: a first set of switches respectively coupled between the first output of the decoder and the set of inputs of the source amplifier; a second set of switches respectively coupled between the second output of the decoder and the set of inputs of the source amplifier; Equipped The display device according to claim 11.

14. electrically connecting the first output and the second output of the decoder during the first time period includes closing all of the first set of switches and all of the second set of switches during the first time period. The display device according to claim 13.

15. the source interpolation selector further configured to receive a shunt control signal; Electrically connecting the first output and the second output of the decoder during the first period of the horizontal synchronization period in response to the shunt control signal. The display device according to claim 11.

16. and a control circuit configured to adjust the duration of the first period. The display device according to claim 11.

17. Adjusting the duration of the first period is based on the first pixel data and second pixel data provided to the decoder before the first pixel data is provided to the decoder. The display device according to claim 16.

18. generating a plurality of gamma voltages on a plurality of gamma bus lines respectively; electrically connecting a first output of the decoder to a first gamma bus line of the plurality of gamma bus lines based on first pixel data provided to the decoder; electrically connecting a second output of the decoder to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; electrically connecting the first output and the second output of the decoder during a first period of a horizontal synchronization period; electrically connecting the first output and the second output of the decoder to a pair of inputs of a source amplifier based on the first pixel data during a second period following the first period of the horizontal synchronization period; supplying, by the source amplifier, data voltages to a display panel based on a set of input voltages at the set of inputs during the first time period and the second time period; Includes method.

19. a first set of switches respectively coupled between the first output of the decoder and the set of inputs of the source amplifier; a second set of switches respectively coupled between the second output of the decoder and the set of inputs of the source amplifier; Electrically connecting the first output and the second output of the decoder includes closing all of the first set of switches and all of the second set of switches during the first period of time.

20. The method of claim 18.

20. Further comprising adjusting a duration of the first period based on the first pixel data and second pixel data provided to the decoder before the first pixel data is provided to the decoder.

20. The method of claim 18.

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