Imaging device

Abstract

To provide an imaging device with an image processing function.SOLUTION: An imaging device includes a plurality of pixels. The pixel has a function of applying a first weight to image data acquired in an n-th frame (n is an integer of 2 or more) and generating first data in the n-th frame. The pixel has a function of applying a second weight to image data acquired in a (n-1)-th frame and generating first data in the (n-1)-th frame. The pixel also has a function of adding up the first data in the (n-1)-th fame and the first data in the n-th frame and generating second data.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification etc. relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, an operation method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Further, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device in which a transistor that includes an oxide semiconductor and has an extremely low off-state current is used in a pixel circuit.

[0005] Patent Document 2 discloses a technique for adding a calculation function to an imaging device. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2011-119711 A [Patent Document 2] JP 2016-123087 A Summary of the Invention [Problem to be solved by the invention]

[0007] Imaging devices mounted on portable devices and the like are generally equipped with a function for acquiring high-resolution images. In the next generation, imaging devices are required to be equipped with even more intelligent functions.

[0008] Currently, image data compression, image recognition, etc. are performed by extracting image data captured by an imaging device from the imaging device and processing the data. If such processing could be performed within the imaging device, linking with external devices would be faster, improving user convenience. In addition, the load and power consumption of peripheral devices could be reduced.

[0009] To express smooth movement in video, it is preferable to increase the frame rate. However, the greater the number of pixels, the shorter the horizontal period becomes, making it difficult to simply increase the frame rate. For this reason, technology is sometimes used to generate images that interpolate between frames of actual images (interpolated images). However, when the frame rate at which the actual images are acquired is relatively high, it can be difficult to secure the time to generate the interpolated images.

[0010] In view of the above, an object of one embodiment of the present invention is to provide an imaging device capable of performing image processing. Another object is to provide an imaging device capable of generating an image by interpolating between frames. Another object is to provide an imaging device capable of capturing a high-quality moving image. Another object is to provide an imaging device that functions as a part of a neural network. Another object is to provide an imaging device with low power consumption. Another object is to provide an imaging device with high reliability. Another object is to provide a novel imaging device or the like. Another object is to provide a method for driving the imaging device. Another object is to provide a novel semiconductor device or the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is an imaging device having a plurality of pixels. Each pixel has a function of applying a first weight to image data acquired in an n-th frame (n is an integer equal to or greater than 2) to generate first data for the n-th frame. Each pixel has a function of applying a second weight to image data acquired in an n-1-th frame to generate first data for the n-1-th frame. Each pixel also has a function of adding together the first data for the n-1-th frame and the first data for the n-th frame to generate second data.

[0013] One embodiment of the present invention is an imaging device having a plurality of pixels and a plurality of first circuits. The pixels are arranged in a matrix. The first circuit is electrically connected to a plurality of pixels arranged in a column direction. The pixel has a second circuit and a third circuit. One of the second circuit and the third circuit has a function of giving a first weight to image data acquired in an n-th frame (n is an integer of 2 or more) to generate first data of the n-th frame. The other of the second circuit and the third circuit has a function of giving a second weight to image data acquired in an n-1-th frame to generate first data of the n-1-th frame. Furthermore, the pixel has a function of adding the first data of the n-1-th frame and the first data of the n-th frame together to generate second data. The first circuit has a function of generating third data equivalent to the sum of the second data generated by each pixel.

[0014] In the imaging device described above, the pixel preferably has a photoelectric conversion device and a first transistor. The second circuit and the third circuit each have a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. One electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor. One of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor. The gate of the fourth transistor is electrically connected to one electrode of the first capacitor. The other electrode of the first capacitor is electrically connected to one of the source or drain of the fifth transistor. One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the first transistor is electrically connected to the first circuit.

[0015] In the imaging device described above, the other of the fifth transistor is preferably electrically connected to a first wiring, to which either a potential corresponding to the first weight or a potential corresponding to the second weight is supplied.

[0016] In the imaging device described above, the pixel preferably has a photoelectric conversion device and a first transistor. The second circuit and the third circuit each have a second transistor, a third transistor, a fourth transistor, and a first capacitor. One electrode of the photoelectric conversion device is electrically connected to one of the source or drain of the second transistor. The other of the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor. One of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor. The gate of the fourth transistor is electrically connected to one electrode of the first capacitor. One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the first transistor. The other of the source or drain of the first transistor is electrically connected to the first circuit. The fourth transistor has a back gate.

[0017] In the imaging device described above, it is preferable that the back gate is electrically connected to a first wiring, to which either a potential corresponding to the first weight or a potential corresponding to the second weight is supplied.

[0018] In the imaging device described above, the first circuit preferably includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor. One electrode of the second capacitor is electrically connected to a plurality of pixels. One electrode of the second capacitor is electrically connected to the sixth transistor. The other electrode of the second capacitor is electrically connected to one of the source or drain of the seventh transistor. One of the source or drain of the seventh transistor is electrically connected to the gate of the eighth transistor. One of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the ninth transistor. One of the source or drain of the ninth transistor is electrically connected to one of the source or drain of the tenth transistor.

[0019] In the imaging device, any one or more of the transistors included in the pixel and the first circuit preferably have a metal oxide in a channel formation region, the metal oxide including In, Zn, and an element M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0020] In the imaging device, it is preferable that one or more of the transistors included in the pixel and the first circuit have silicon in a channel formation region. Effect of the Invention

[0021] By using one embodiment of the present invention, it is possible to provide an imaging device capable of performing image processing. Or, it is possible to provide an imaging device capable of generating an image by interpolating between frames. Or, it is possible to provide an imaging device capable of capturing a high-quality moving image. Or, it is possible to provide an imaging device that functions as a part of a neural network. Or, it is possible to provide an imaging device with low power consumption. Or, it is possible to provide an imaging device with high reliability. Or, it is possible to provide a novel imaging device or the like. Or, it is possible to provide a method for driving the imaging device. Or, it is possible to provide a novel semiconductor device or the like. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a block diagram illustrating an imaging device. [Diagram 2] FIG. 2 is a diagram illustrating a pixel block and a circuit. [Diagram 3] FIG. 3 is a diagram illustrating a pixel block. [Figure 4] FIG. 4 is a diagram illustrating a pixel. [Diagram 5] FIG. 5 is a schematic diagram illustrating the operation of the imaging device. [Figure 6] FIG. 6 is a schematic diagram illustrating the operation of the imaging device. [Figure 7] FIG. 7 is a timing chart illustrating the operation of the pixel block and circuits. [Figure 8] FIG. 8 is a timing chart illustrating the operation of the pixel block and circuits. [Figure 9] FIG. 9 is a timing chart illustrating the operation of the pixel block and circuits. [Figure 10] FIG. 10 is a timing chart illustrating the operation of the pixel block and circuits. [Figure 11] FIG. 11 is a timing chart illustrating the operation of the pixel block and circuits. [Figure 12] FIG. 12 is a timing chart illustrating the operation of the pixel block and circuits. [Figure 13] FIG. 13 is a diagram illustrating a pixel. [Figure 14] 14A and 14B are diagrams for explaining the circuit. [Figure 15] FIG. 15 is a diagram illustrating a memory cell. [Figure 16] 16A and 16B are diagrams showing examples of the configuration of a neural network. [Figure 17] 17A to 17D are diagrams for explaining the configuration of a pixel of an imaging device. [Figure 18] 18A to 18C are diagrams illustrating the configuration of a photoelectric conversion device. [Figure 19] FIG. 19 is a cross-sectional view illustrating a pixel. [Figure 20] 20A to 20C are diagrams illustrating a Si transistor. [Figure 21] FIG. 21 is a cross-sectional view illustrating a pixel. [Figure 22] FIG. 22 is a cross-sectional view illustrating a pixel. [Diagram 23] FIG. 23 is a cross-sectional view illustrating a pixel. [Figure 24] 24A to 24D illustrate OS transistors. [Diagram 25] FIG. 25 is a cross-sectional view illustrating a pixel. [Figure 26] 26A to 26C are perspective views (cross-sectional views) illustrating a pixel. [Figure 27] 27A1 to 27A3 and 27B1 to 27B3 are perspective views of a package and a module that house an imaging device. [Figure 28] 28A to 28F are diagrams illustrating an electronic device. [Figure 29] FIG. 29 is a diagram illustrating an automobile. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate between different drawings.

[0024] Even if a circuit diagram shows a single element, the element may be configured as a plurality of elements as long as there is no functional problem. For example, a plurality of transistors operating as a switch may be connected in series or parallel. A capacitor may also be divided and placed in multiple positions.

[0025] A single conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Even if elements are shown as being directly connected to each other on a circuit diagram, the elements may actually be connected to each other via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0026] (Embodiment 1) In this embodiment, an imaging device capable of performing image processing will be described with reference to the drawings.

[0027] One aspect of the present invention is an imaging device with additional functions such as image processing. The imaging device has a function of storing analog data (image data) acquired during imaging in pixels and extracting data obtained by multiplying the analog data by an arbitrary weighting factor. The imaging device also has a function of adding up the data output from multiple pixels (product-sum calculation function).

[0028] Furthermore, the data extracted from the pixels can be input to a neural network or the like provided inside or outside the imaging device, thereby enabling processing such as image recognition. The imaging device according to one aspect of the present invention can store a huge amount of image data in the form of analog data in the pixels and perform calculations within the pixels, thereby enabling efficient processing.

[0029] One embodiment of the present invention is an imaging device having a function of generating an image (interpolated image) that interpolates between frames. In the imaging device, a pixel has a function of generating first data of the nth frame by applying an arbitrary weight to image data acquired by imaging the nth frame in an nth frame. The pixel also has a function of holding image data acquired by imaging the n-1th frame, and has a function of generating first data of the n-1th frame by applying an arbitrary weight to image data acquired in the n-1th frame in an nth frame. The pixel also has a function of generating second data by adding the first data of the n-1th frame and the first data of the nth frame together. The second data can be suitably used as image data that interpolates between frames, for example.

[0030] <Imaging device> 1 shows a block diagram of an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 300, a circuit 201, a circuit 302, a circuit 303, a circuit 304, and a circuit 305. Note that one or more of the circuit 201, the circuit 301, the circuit 302, the circuit 303, the circuit 304, and the circuit 305 may have an overlapping region with the pixel array 300. With this configuration, the area of ​​the imaging device can be reduced.

[0031] Note that in the imaging device of one embodiment of the present invention, a circuit having two or more of the functions of the circuit 201 and the circuits 301 to 305 may be used instead. Alternatively, circuits other than the circuit 201 and the circuits 301 to 305 may be used. Alternatively, one or more of the functions of the circuit 201 and the circuits 301 to 305 may be replaced by an operation performed by software. Alternatively, some of the circuits of the circuit 201 and the circuits 301 to 305 may be provided outside the imaging device.

[0032] The pixel array 300 can have an imaging function and a calculation function. Each of the circuits 201 and 301 can have a calculation function. The circuit 302 can have a calculation function or a data conversion function, and can output data to a wiring 311. Each of the circuits 303 and 304 can have a selection function. The circuit 305 can have a function of supplying a potential (such as a weight) to a pixel. Note that a shift register, a decoder, or the like can be used as a circuit having a selection function.

[0033] The pixel array 300 has a plurality of pixel blocks 200 arranged in a matrix. The circuit 201 is electrically connected to the plurality of pixel blocks 200 arranged in the column direction. Each pixel block 200 is electrically connected to the circuit 201 via a wiring 113.

[0034] A block diagram of the pixel block 200 is shown in FIG. 2, which also shows a circuit diagram of a circuit 201. The pixel block 200 has a plurality of pixels 100 arranged in a matrix, and each of the pixels 100 is electrically connected to the circuit 201 through a wiring 113. Note that the circuit 201 can also be provided within the pixel block 200.

[0035] The pixel 100 has a function of acquiring image data and generating data by adding the image data and a weighting coefficient. Note that, although the number of pixels 100 in the pixel block 200 is 3 rows and 3 columns in FIG. 2, this is not limited to this embodiment of the present invention. The number of pixels in the pixel block 200 may be, for example, 2 rows and 2 columns, or 4 rows and 4 columns. Alternatively, the number of pixels in the horizontal direction may be different from the number of pixels in the vertical direction. Also, some pixels may be shared between adjacent pixel blocks.

[0036] For example, the number of pixels 100 in the pixel block 200 can be changed by the configuration shown in Fig. 3. Fig. 3 shows a plurality of pixels 100 arranged in rows [q-1] to [q+1] and columns [p-1] to [p+1] (p and q are integers of 2 or more). A selection switch is provided in each pixel 100, and the selection switch is controlled to be "ON" or "OFF" by a selection signal supplied to row wirings RL[q-1] to RL[q+1]. The selection switch is electrically connected to any one of column wirings CL[p-1] to CL[p+1]. At least one of the column wirings is electrically connected to the circuit 201.

[0037] A conductive switch SW[p-1] is provided between the column wirings CL[p-1] and CL[p], and a conductive switch SW[p] is provided between the column wirings CL[p] and CL[p+1]. The conductive switch is controlled to be "ON" or "OFF" by a selection signal supplied to signal lines G1 and G2. When the selection switch is turned "ON," the adjacent column wirings can be made conductive.

[0038] For example, when a signal for turning on the selection switch is supplied to the row wirings RL[q-1] and RL[q] and a signal for turning on the conductive switch SW[p-1] is supplied to the signal line G1, the pixels 100 in the second row and second column (pixels 100[q-1,p-1], pixels 100[q-1,p], pixels 100[q,p-1], and pixels 100[q,p]) are selected. In addition, the column wirings CL[p-1] and CL[p] become conductive. Therefore, the pixels 100 in the second row and second column are electrically connected to the circuit 201.

[0039] Furthermore, when a signal to turn the selection switch “ON” is supplied to the row wiring RL[q+1] and a signal to turn the conductive switch SW[p] “ON” is supplied to the signal line G2, the pixels 100 in the 3rd row and 3rd column are electrically connected to the circuit 201.

[0040] The pixel block 200 and the circuit 201 can be operated as a multiply-accumulate circuit.

[0041] <Pixel circuit configuration example 1> 4 shows a circuit diagram of the pixel 100. The pixel 100 includes a photoelectric conversion device 101, a circuit 130a, a circuit 130b, and a transistor 108. The photoelectric conversion device 101 is electrically connected to the transistor 108 via the circuit 130a. The photoelectric conversion device 101 is also electrically connected to the transistor 108 via the circuit 130b.

[0042] A photodiode can be used as the photoelectric conversion device 101. When it is desired to increase the light detection sensitivity at low illuminance, an avalanche photodiode can be suitably used.

[0043] Each of the circuit 130a and the circuit 130b has a function of applying a weight to image data of an image acquired by the photoelectric conversion device 101 using a filter to generate first data and hold the first data. In the nth frame, one of the circuit 130a and the circuit 130b has a function of applying a weight to image data acquired in the nth frame (n is an integer of 2 or more) using a filter to generate first data for the nth frame. In the nth frame, the other of the circuit 130a and the circuit 130b has a function of applying a weight to the held image data of the n-1th frame using a filter to generate first data for the n-1th frame.

[0044] The imaging device according to one embodiment of the present invention can generate second data from first data of an n-th frame generated from image data acquired in an n-th frame and first data of an n-1-th frame generated from image data acquired in an n-1-th frame. The second data can be suitably used as image data for interpolating between frames, for example.

[0045] A conceptual diagram of the operation of an imaging device according to one embodiment of the present invention is shown in Fig. 5. Fig. 5 shows the operation for three frames, from the nth frame to the (n+2)th frame, as an example.

[0046] In the n-th frame, the photoelectric conversion device 101 is operated to generate image data IMn In the n-th frame, the circuit 130b acquires image data IM n is weighted using the second filter FL21, and the first data IM n In the n-th frame, the circuit 130a generates the image data IM*FL21 acquired in the (n-1)th frame. n-1 is weighted using the first filter FL11, and the first data IM n-1 *FL11 is generated. Then, the first data IM n-1 *FL11 contains the first data IM of the nth frame. n *FL21 is added and the second data (IM n-1 *FL11)+(IM n *FL21) is generated. The second data generated (IM n-1 *FL11)+(IM n *FL21) is output from pixel 100.

[0047] In the nth frame, the image data IM acquired in the nth frame n is weighted using a second filter FL21, and the image data IM n-1 is weighted using a first filter FL11.

[0048] In this specification and the like, the first data generated by applying a weight to image data using a filter may be indicated by using "*". For example, image data IM n The first data generated by weighting the first data IM n The second data generated from the first data is sometimes written as *FL11. The second data generated from the first data is sometimes written using "+". For example, the first data IM n *First data IM in FL11 n+1 *The second data generated by adding FL21 is called the second data (IM n *FL11)+(IM n+1 *It may be written as FL21).

[0049] In the (n+1)th frame, the photoelectric conversion device 101 is operated to generate image data IM n+1 In the n+1th frame, the circuit 130a acquires image data IM n+1 is weighted using the second filter FL21, and the first data IM n+1 In the n+1-th frame, the circuit 130b generates the image data IM*FL21 acquired in the n-th frame. n is weighted using the first filter FL11, and the first data IM n *FL11 is generated. Then, the first data of the nth frame, IM n *FL11 contains the first data IM of the n+1th frame. n+1 *FL21 is added and the second data (IM n *FL11)+(IM n+1 *FL21) is generated. The second data generated (IM n *FL11)+(IM n+1 *FL21) is output from pixel 100.

[0050] In the n+1th frame, the image data IM acquired in the n+1th frame n+1 is weighted using a second filter FL21, and the image data IM n is weighted using a first filter FL11.

[0051] In the (n+2)th frame, the photoelectric conversion device 101 is operated to generate image data IM n+2 In the n+2th frame, the circuit 130b acquires image data IM n+2 is weighted using the second filter FL21, and the first data IM n+2 In the n+2th frame, the circuit 130a generates the image data IM*FL21 acquired in the n+1th frame. n+1 is weighted using the first filter FL11, and the first data IM n+1 *FL11 is generated. Then, the first data IMn+1 *FL11 contains the first data IM of the n+2th frame. n+2 *FL21 is added and the second data (IM n+1 *FL11)+(IM n+2 *FL21) is generated. The second data generated (IM n+1 *FL11)+(IM n+2 *FL21) is output from pixel 100.

[0052] In the n+2th frame, the image data IM acquired in the n+2th frame n+2 is weighted using a second filter FL21, and the image data IM n+1 is weighted using a first filter FL11.

[0053] In any frame, the image data acquired in the frame is weighted using the second filter FL21, and the image data acquired in the previous frame is weighted using the first filter FL11.

[0054] For subsequent frames, the same operations as described above can be performed.

[0055] Here, the size (number of pixels) of the first filter FL11 and the second filter FL21 can be, for example, 2 rows and 2 columns, 3 rows and 3 columns, or 4 rows and 4 columns. The size (number of pixels) of the first filter FL11 and the second filter FL21 may be different in the horizontal direction and the vertical direction. The size (number of pixels) of the first filter FL11 and the second filter FL21 can be the same as the number of pixels of the pixel block 200. For example, when the number of pixels of the pixel block 200 is 3 rows and 3 columns, the first filter FL11 and the second filter FL21 having 3 rows and 3 columns can be used. In addition, the elements (weights) of the first filter FL11 and the second filter FL21 may be the same or different.

[0056] Although FIG. 5 illustrates an example in which one type of filter is used in each of the circuits 130a and 130b, one embodiment of the present invention is not limited to this. A plurality of types of filters may be used in each of the circuits 130a and 130b. When a plurality of types of filters are used, each of the filters may have different elements (weights). By using a plurality of types of filters with different elements (weights), a plurality of types of feature amounts can be extracted from the acquired image data, and highly accurate image processing can be performed. For example, by using the second data as image data for interpolating between frames, a smooth moving image can be obtained, and an imaging device capable of capturing a high-quality moving image can be obtained. Even when the frame frequency is particularly low, a smooth moving image can be obtained.

[0057] An example in which three types of filters are used in each of the circuits 130a and 130b is shown in Fig. 6. Fig. 6 shows an example of the operation for three frames from the nth frame to the n+2th frame.

[0058] In the n-th frame, the photoelectric conversion device 101 is operated to generate image data IM n In the n-th frame, the circuit 130b acquires image data IM n The first data IM is weighted by a second filter FL21, a fourth filter FL22, and a sixth filter FL23. n *FL21, first data IM n *FL22 and the first data IM n In the n-th frame, the circuit 130a generates the image data IM*FL23 acquired in the (n-1)th frame. n-1 The first data IM n-1 *FL11, first data IM n-1 *FL12 and the first data IM n-1 *Generate FL13.

[0059] The first data IM of the n-1th frame n-1*FL11 contains the first data IM of the nth frame. n *FL21 is added and the second data (IM n-1 *FL11)+(IM n *FL21) is generated. The first data IM of the n-1th frame n-1 *FL12 contains the first data IM of the nth frame. n *FL22 is added and the second data (IM n-1 *FL12)+(IM n *FL22) is generated. The first data IM of the n-1th frame n-1 *FL13 contains the first data IM of the nth frame. n *FL23 is added and the second data (IM n-1 *FL13)+(IM n *FL23) is generated. The second data (IM n-1 *FL11)+(IM n *FL21), the second data (IM n-1 *FL12)+(IM n *FL22), and the second data (IM n-1 *FL13)+(IM n *FL23) is output from pixel 100.

[0060] In the nth frame, the image data IM acquired in the nth frame n is weighted using a second filter FL21, a fourth filter FL22, and a sixth filter FL23, and image data IM acquired in the previous frame, that is, the n-1th frame, is n-1 is weighted using a first filter FL11, a third filter FL12, and a fifth filter FL13.

[0061] In the (n+1)th frame, the photoelectric conversion device 101 is operated to generate image data IM n+1 In the n+1th frame, the circuit 130a acquires image data IM n+1 The first data IM is weighted by a second filter FL21, a fourth filter FL22, and a sixth filter FL23. n+1 *FL21, first data IMn+1 *FL22 and the first data IM n+1 In the n+1-th frame, the circuit 130b generates the image data IM*FL23 acquired in the n-th frame. n The first data IM n *FL11, first data IM n *FL12 and the first data IM n *Generate FL13.

[0062] The first data of the nth frame, IM n *FL11 contains the first data IM of the n+1th frame. n+1 *FL21 is added and the second data (IM n *FL11)+(IM n+1 *FL21) is generated. The first data IM of the nth frame n *FL12 contains the first data IM of the n+1th frame. n+1 *FL22 is added and the second data (IM n *FL12)+(IM n+1 *FL22) is generated. The first data IM of the nth frame n *FL13 contains the first data IM of the n+1th frame. n+1 *FL23 is added and the second data (IM n *FL13)+(IM n+1 *FL23) is generated. The second data (IM n *FL11)+(IM n+1 *FL21), the second data (IM n *FL12)+(IM n+1 *FL22), and the second data (IM n *FL13)+(IM n+1 *FL23) is output from pixel 100.

[0063] In the n+1th frame, the image data IM acquired in the n+1th frame n+1is weighted using a second filter FL21, a fourth filter FL22, and a sixth filter FL23, and image data IM n is weighted using a first filter FL11, a third filter FL12, and a fifth filter FL13.

[0064] In the (n+2)th frame, the photoelectric conversion device 101 is operated to generate image data IM n+2 In the n+2th frame, the circuit 130b acquires image data IM n+2 The first data IM is weighted by a second filter FL21, a fourth filter FL22, and a sixth filter FL23. n+2 *FL21, first data IM n+2 *FL22 and the first data IM n+2 In the n+2th frame, the circuit 130a generates the image data IM*FL23 acquired in the n+1th frame. n+1 The first data IM n+1 *FL11, first data IM n+1 *FL12 and the first data IM n+1 *Generate FL13.

[0065] First data IM of the n+1th frame n+1 *FL11 contains the first data IM of the n+2th frame. n+2 *FL21 is added and the second data (IM n+1 *FL11)+(IM n+2 *FL12) is generated. The first data IM of the n+1th frame n+1 *FL12 contains the first data IM of the n+2th frame. n+2 *FL22 is added and the second data (IM n+1 *FL12)+(IM n+2 *FL12) is generated. The first data IM of the n+1th frame n+1 *FL13 contains the first data IM of the n+2th frame. n+2*FL23 is added and the second data (IM n+1 *FL13)+(IM n+2 *FL23) is generated. The second data (IM n+1 *FL11)+(IM n+2 *FL21), the second data (IM n+1 *FL12)+(IM n+2 *FL22), and the second data (IM n+1 *FL13)+(IM n+2 *FL23) is output from pixel 100.

[0066] In the n+2th frame, the image data IM acquired in the n+2th frame n+2 is weighted using a second filter FL21, a fourth filter FL22, and a sixth filter FL23, and image data IM acquired in the previous frame (n+1) is n+1 is weighted using a first filter FL11, a third filter FL12, and a fifth filter FL13.

[0067] In any frame, the image data acquired in that frame is weighted using the second filter FL21, the fourth filter FL22, and the sixth filter FL23, and the image data acquired in the previous frame is weighted using the first filter FL11, the third filter FL12, and the fifth filter FL13.

[0068] For subsequent frames, the same operations as described above can be performed.

[0069] The structures of the circuit 130a and the circuit 130b will be described with reference to FIG.

[0070] The circuit 130a includes a transistor 102a, a transistor 103a, a capacitor 104a, a transistor 105a, and a transistor 106a. One electrode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102a. The other of the source and drain of the transistor 102a is electrically connected to one of the source and drain of the transistor 103a, one electrode of the capacitor 104a, and the gate of the transistor 105a. One of the source and drain of the transistor 105a is electrically connected to one of the source and drain of the transistor 108. The other electrode of the capacitor 104a is electrically connected to one of the source and drain of the transistor 106b.

[0071] The other electrode of the photoelectric conversion device 101 is electrically connected to a wiring 114. The other of the source and the drain of the transistor 108 is electrically connected to a wiring 113. The gate of the transistor 108 is electrically connected to a wiring 122.

[0072] The gate of the transistor 102a is electrically connected to a wiring 116a. The other of the source and the drain of the transistor 103a is electrically connected to a wiring 115a. The gate of the transistor 103a is electrically connected to a wiring 117a. The other of the source and the drain of the transistor 105a is electrically connected to a wiring 119a. The other of the source and the drain of the transistor 106a is electrically connected to a wiring 111a. The gate of the transistor 106a is electrically connected to a wiring 112a.

[0073] Here, an electrical connection point between the other of the source or the drain of the transistor 102a, one of the source or the drain of the transistor 103a, one electrode of the capacitor 104a, and the gate of the transistor 105a is referred to as a node NDa.

[0074] The wiring 114 and the wiring 115a can each function as a power supply line. For example, the wiring 114 can function as a low-potential power supply line, and the wiring 115a can function as a high-potential power supply line. The wirings 112a, 116a, 117a, and 122 can function as signal lines that control the conduction of each transistor. The wiring 111a can function as a wiring that supplies a potential corresponding to a weighting coefficient to the pixel 100. The wiring 113 can function as a wiring that electrically connects the pixel 100 and the circuit 201. The wiring 119a can function as a low-potential power supply line (for example, a GND wiring).

[0075] Note that the wiring 113 may be electrically connected to an amplifier circuit or a gain adjustment circuit.

[0076] The transistor 102a can have a function of controlling the potential of the node NDa. The transistor 103a can have a function of initializing the potential of the node NDa. The transistor 105a can have a function of controlling a current flowing from the circuit 201 in accordance with the potential of the node NDa (a current flowing from the wiring 217 to the wiring 119a). The transistor 106a can have a function of supplying a potential corresponding to a weighting coefficient to the node NDa. The transistor 108 can have a function of selecting a pixel.

[0077] 4, the connection direction of a pair of electrodes of the photoelectric conversion device 101 may be reversed. In this case, the wiring 114 may function as a high potential power line, and the wiring 115a may function as a low potential power line.

[0078] The transistors 102a and 103a are preferably transistors using a metal oxide in a channel formation region (OS transistors). OS transistors have characteristics of extremely low off-state current. By using OS transistors for the transistors 102a and 103a, the period during which charge can be held at the node NDa can be extremely long. Furthermore, a global shutter system in which charge is accumulated simultaneously in all pixels can be applied without complicating the circuit configuration and operation method. Furthermore, while image data is held in the node NDa, multiple calculations can be performed using the image data.

[0079] On the other hand, it may be desirable for the transistor 105a to have excellent amplification characteristics. It may be preferable to use high-mobility transistors capable of high-speed operation as the transistors 106a and 108. Therefore, transistors using silicon for a channel formation region (Si transistors) may be used as the transistors 105a, 106a, and 108.

[0080] Note that the present invention is not limited to the above, and any combination of OS transistors and Si transistors may be used. All the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors. Examples of Si transistors include transistors having amorphous silicon and transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, and single crystal silicon).

[0081] The potential of the node NDa in the pixel 100 is determined by subtracting a potential (image data) generated by photoelectric conversion by the photoelectric conversion device 101 from a reset potential supplied from the wiring 115a. The potential of the node NDa is further determined by capacitively coupling a potential corresponding to a weighting factor supplied from the wiring 111a. Therefore, the transistor 105a can pass a current corresponding to data obtained by adding an arbitrary weighting factor to the image data. Note that, when the connection direction of the pair of electrodes of the photoelectric conversion device 101 is reversed from that of FIG. 4, the potential of the node NDa is determined by adding a potential (image data) generated by photoelectric conversion by the photoelectric conversion device 101 to a reset potential supplied from the wiring 115a.

[0082] The circuit 130b can have the same structure as the circuit 130a. The circuit 130b includes a transistor 102b, a transistor 103b, a capacitor 104b, a transistor 105b, and a transistor 106b. The transistors 102b, 103b, the capacitor 104b, 105b, and 106b can be described in the same manner as the transistors 102a, 103a, the capacitor 104a, the transistor 105a, and the transistor 106a, respectively, and therefore will not be described in detail here.

[0083] In this specification and the like, the transistors 102a and 102b may be collectively referred to as transistors 102. The transistors 103a and 103b may be collectively referred to as transistors 103. The capacitors 104a and 104b may be collectively referred to as capacitors 104. The transistors 105a and 105b may be collectively referred to as transistors 105. The transistors 106a and 106b may be collectively referred to as transistors 106. The circuits 130a and 130b may be collectively referred to as circuit 130.

[0084] The wiring 111b, the wiring 112b, the wiring 115b, the wiring 116b, the wiring 117b, and the wiring 119b can refer to the descriptions of the wiring 111a, the wiring 112a, the wiring 115a, the wiring 116a, the wiring 117a, and the wiring 119a, respectively, and therefore detailed descriptions thereof will be omitted. Similarly, the description of the node NDb can refer to the description of the node NDa, and therefore detailed descriptions thereof will be omitted. Note that the wiring 115a and the wiring 115b can be shared. Also, the wiring 119a and the wiring 119b can be shared. By sharing the wirings, the number of wirings can be reduced, and the area of ​​the wirings in a pixel can be reduced, thereby enabling a high-definition imaging device to be obtained.

[0085] <Circuit 201> 2, the pixels 100 are electrically connected to each other through wirings 113. The circuit 201 can perform calculations using the sum of currents flowing through the transistors 105 of the pixels 100.

[0086] The circuit 201 includes a capacitor 202, a transistor 203, a transistor 204, a transistor 205, a transistor 206, and a transistor 207. The transistor 207 functions as a voltage conversion circuit. A suitable analog potential (Bias) is applied to the gate of the transistor 207.

[0087] One electrode of the capacitor 202 is electrically connected to one of the source or drain of the transistor 203 and the gate of the transistor 204. One of the source or drain of the transistor 204 is electrically connected to one of the source or drain of the transistor 205 and one of the source or drain of the transistor 206. The other electrode of the capacitor 202 is electrically connected to the wiring 113 and one of the source or drain of the transistor 207.

[0088] Here, a point where one electrode of the capacitor 202, one of the source or drain of the transistor 203, and the gate of the transistor 204 are connected is referred to as a node C.

[0089] The other of the source and the drain of the transistor 203 is electrically connected to a wiring 218. The other of the source and the drain of the transistor 204 is electrically connected to a wiring 219. The other of the source and the drain of the transistor 205 is electrically connected to a reference power supply line such as a GND wiring. The other of the source and the drain of the transistor 206 is electrically connected to a wiring 212. The other of the source and the drain of the transistor 207 is electrically connected to a wiring 217. The gate of the transistor 203 is electrically connected to a wiring 216. The gate of the transistor 205 is electrically connected to a wiring 215. The gate of the transistor 206 is electrically connected to a wiring 213.

[0090] The wiring 217, the wiring 218, and the wiring 219 can each function as a power supply line. For example, the wiring 218 can function as a wiring that supplies a reset potential (Vr) for reading. The wiring 217 and the wiring 219 can each function as a high-potential power supply line. The wiring 213, the wiring 215, and the wiring 216 can each function as a signal line that controls the conduction of each transistor. The wiring 212 is an output line and can be electrically connected to, for example, the circuit 301 shown in FIG. 1.

[0091] The transistor 203 can have a function of resetting the potential of the node C to the potential of the wiring 218. The transistors 204 and 205 can function as source follower circuits. The transistor 206 can have a function of controlling reading. Note that the circuit 201 has a function as a correlated double sampling circuit (CDS circuit) and can be replaced with a circuit having the same function.

[0092] In one embodiment of the present invention, offset components other than the product of image data (X) and a weighting coefficient (W) are removed, and the product (WX) of image data (X) and a weighting coefficient (W) is extracted. WX can be calculated using data with exposure (with imaging) and without exposure (without imaging) acquired at the same pixel, and data when weights are applied to each of the data.

[0093] The current (I p ) is the sum of kΣ(-XV th ) 2 , the current (I p ) is the sum of kΣ(WXV th ) 2 In addition, the current (I ref ) is the sum of kΣ(0-V th ) 2 , the current (I ref ) is the sum of kΣ(WV th ) 2 Here, k is a constant, V th is the threshold voltage of transistor 105.

[0094] First, calculate the difference (data A) between the data with exposure and the data with weighting added to it. kΣ((-XV th ) 2 -(WXV th ) 2 )=kΣ(-W 2 +2W·X+2W·V th )

[0095] Next, calculate the difference (data B) between the data without exposure and the weighted data. kΣ((0-V th ) 2 -(WV th ) 2 )=kΣ(-W 2 +2W·V th )

[0096] Then, take the difference between data A and data B. kΣ(-W2 +2W·X+2W·V th -(-W 2 +2W·V th ))=kΣ(2W·X). In other words, it is possible to remove offset components other than the product of the image data (X) and the weighting coefficient (W).

[0097] The circuit 201 can read out data A and data B. Note that the difference between data A and data B can be calculated by the circuit 301, for example.

[0098] A case where the connection direction of a pair of electrodes of the photoelectric conversion device 101 is reversed to that in FIG. 4 will be described.

[0099] The current (I p ) is the sum of kΣ(XV th ) 2 , the current (I p ) is kΣ(W+XV th ) 2 In addition, the current (I ref ) is the sum of kΣ(0-V th ) 2 , the current (I ref ) is the sum of kΣ(WV th ) 2 It becomes.

[0100] First, calculate the difference (data A) between the data with exposure and the data with weighting added to the data with exposure. kΣ((XV th ) 2 -(W+XV th ) 2 )=kΣ(-W 2 -2W·X+2W·V th )

[0101] Next, calculate the difference (data B) between the data without exposure and the weighted data. kΣ((0-V th ) 2 -(WV th) 2 )=kΣ(-W 2 +2W·V th )

[0102] Then, take the difference between data A and data B. kΣ(-W 2 -2W·X+2W·V th -(-W 2 +2W·V th ))=kΣ(-2W X). Even if the connection direction of a pair of electrodes of the photoelectric conversion device 101 is reversed to that in FIG. 4, it is possible to remove offset components other than the product of the image data (X) and the weighting coefficient (W).

[0103] A transistor using a metal oxide for a channel formation region (OS transistor) is preferably used as the transistor 203. By using an OS transistor as the transistor 203, the period during which charge can be held at the node C can be significantly extended.

[0104] It may be preferable to use high-mobility transistors capable of high-speed operation as the transistors 204 and 205. Therefore, Si transistors may be used as the transistors 204 and 205.

[0105] Note that the above is not limiting, and any combination of OS transistors and Si transistors may be used. All the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors.

[0106] <Image capture operation 1> 7 is a timing chart for explaining the operation of calculating the difference (data A) between exposed data and weighted data in the pixel block 200 and the circuit 201. For convenience, the timing of conversion of each signal is shown together, but in practice it is preferable to shift the timing in consideration of delays within the circuit. In the following explanation, high potential is represented by "H" and low potential is represented by "L".

[0107] Here, the operation of the (n+1)th frame shown in FIG. 5 will be described with reference to FIG.

[0108] First, in a period T11, the potential of the wiring 116a is set to "H", the potential of the wiring 117a is set to "H", and the node NDa of the pixel 100 is set to a reset potential. In addition, the potential of the wirings 111a_1 to 111a_3 (the wirings 111a in the first to third rows) is set to "L", the potential of the wirings 112a_1 to 112a_3 (the wirings 112a in the first to third rows) is set to "H", and a weighting coefficient of 0 is written. Similarly, the potential of the wirings 111b_1 to 111b_3 (the wirings 111b in the first to third rows) is set to "L", the potential of the wirings 112b_1 to 112b_3 (the wirings 112b in the first to third rows) is set to "H", and a weighting coefficient of 0 is written.

[0109] In a period T12, the potential of the wiring 116a is set to "L" and the potential of the wiring 117a is set to "L", and the photoelectric conversion device 101 performs an exposure operation.

[0110] In a period T13, the potential of the wiring 116a is set to “H”, the potential generated by the photoelectric conversion device 101 is transferred, and the potential X n+1 The period T11 to the period T13 corresponds to a period for acquiring exposed data of the n+1th frame. Note that the node NDb is supplied with a potential X n (Image data) is stored.

[0111] In a period T14, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all the pixels 100 in the pixel block. Here, the wiring 122_1 indicates the wiring 122 of the pixel 100 in the first row, the wiring 122_2 indicates the wiring 122 of the pixel 100 in the second row, and the wiring 122_3 indicates the wiring 122 of the pixel 100 in the third row. At this time, the transistor 105a of each pixel 100 is supplied with a potential X n+1 A current corresponding to the potential X flows through the transistor 105b. nA current according to the potential flows. By setting the potential of the wiring 216 to "H", the potential Vr of the wiring 218 is written to the node C, and the potential of the node C is initialized to the potential Vr.

[0112] During period T15, the potential of wiring 111a_1 is set to a potential equivalent to weighting factor W11 (weighting to be added to the pixels in the first row) and the potential of wiring 112a_1 is set to “H”, so that the weighting factor W11 is added to node NDa of pixel 100 in the first row through capacitive coupling of capacitor 104a.

[0113] By setting the potential of the wiring 111a_2 to a potential equivalent to the weighting factor W12 (the weighting factor to be added to the pixel in the second row) and setting the potential of the wiring 112a_2 to “H”, the weighting factor W12 is added to the node NDa of the pixel 100 in the second row through the capacitive coupling of the capacitor 104a.

[0114] By setting the potential of the wiring 111a_3 to a potential equivalent to the weighting factor W13 (weighting added to the pixel in the third row) and setting the potential of the wiring 112a_3 to "H", the weighting factor W13 is added to the node NDa of the pixel 100 in the third row by the capacitive coupling of the capacitor 104a. Note that the weighting factor W11, the weighting factor W12, and the weighting factor W13 are elements of the first filter FL11.

[0115] By setting the potential of the wiring 111b_1 to a potential equivalent to the weighting factor W21 (the weighting factor to be added to the pixel in the first row) and setting the potential of the wiring 112b_1 to "H", the weighting factor W21 is added to the node NDb of the pixel 100 in the first row through the capacitive coupling of the capacitor 104b.

[0116] By setting the potential of the wiring 111b_2 to a potential equivalent to the weighting factor W22 (the weighting factor to be added to the pixel in the second row) and setting the potential of the wiring 112b_2 to “H”, the weighting factor W22 is added to the node NDb of the pixel 100 in the second row through the capacitive coupling of the capacitor 104b.

[0117] By setting the potential of the wiring 111b_3 to a potential equivalent to weighting factor W23 (weighting added to the pixel in the third row) and setting the potential of the wiring 112b_3 to "H", the weighting factor W23 is added to the node NDb of the pixel 100 in the third row by the capacitive coupling of the capacitor 104b. Note that the weighting factor W21, the weighting factor W22, and the weighting factor W23 are elements of the second filter FL21.

[0118] Continuing from the period T14, the potentials of the wirings 122_1, 122_2, and 122_3 are set to “H” to select all the pixels 100 in the pixel block 200. At this time, the transistors 105a of the pixels 100 in the first row are supplied with a potential W11+X n+1 A current corresponding to the potential W21+X flows through the transistor 105b. n In addition, a current corresponding to a potential W12+X flows through the transistor 105a of the pixel 100 in the second row. n+1 A current corresponding to the potential W22+X flows through the transistor 105b. n In addition, a current corresponding to a potential W13+X flows through the transistor 105a of the pixel 100 in the third row. n+1 A current corresponding to the potential W23+X flows through the transistor 105b. n A current according to the

[0119] Here, the potential of the other electrode of the capacitor 202 changes according to the current flowing through the wiring 113, and the change Y is added to the potential Vr of the node C by capacitive coupling. Therefore, the potential of the node C becomes "Vr+Y." If we consider Vr=0, then Y is the difference itself, and data A has been calculated.

[0120] The potential of the wiring 213 is set to “H” and the potential of the wiring 215 is set to “V bias By setting an appropriate analog potential such as "A" to "B", the circuit 201 can output a signal potential according to the data A of the pixel block 200 in the first row by a source follower operation (hereinafter, also referred to as reading out).

[0121] In FIG. 7, the wiring 213 included in the circuit 201 electrically connected to the pixel blocks 200 in the first column is denoted as wiring 213A, and the wiring 213 included in the circuit 201 electrically connected to the pixel blocks 200 in the second column is denoted as wiring 213B. The third column and subsequent columns are similar and are not illustrated. In the period T15, the wirings 213A, 213B, and the like are sequentially set to "H" to read out from each pixel block 200. Although FIG. 7 shows an example in which the wiring 213A and the wiring 213B are sequentially set to "H", one embodiment of the present invention is not limited thereto. Each wiring 213 may have a period during which it is set to "H" during the period T15.

[0122] In this specification and the like, the wiring 213A, the wiring 213B, and the like may be collectively referred to as the wiring 213.

[0123] The operation in period T15 corresponds to a period in which data A is generated based on captured data in the (n+1)th frame and data A is output to the circuit 301 (read out).

[0124] In a period T16, the potentials of the wirings 122_1, 122_2, 122_3, 112a_1, 112a_2, 112a_3, 112b_1, 112b_2, 112b_3, 213A, 213B, and 215 are set to "L".

[0125] This concludes the explanation of the operation of the n+1th frame.

[0126] Next, the operation of the n+2th frame shown in Fig. 5 will be described with reference to Fig. 7. Note that a description of the parts common to the above-mentioned n+1th frame (periods T11 to T16) will be omitted, and the different parts will be mainly described.

[0127] First, in a period T21, the potential of the wiring 116b is set to "H", the potential of the wiring 117b is set to "H", and the node NDb of the pixel 100 is set to a reset potential. In addition, the potentials of the wirings 111a_1 to 111a_3 are set to "L", the potentials of the wirings 112a_1 to 112a_3 are set to "H", and a weighting coefficient of 0 is written. Similarly, the potentials of the wirings 111b_1 to 111b_3 are set to "L", the potentials of the wirings 112b_1 to 112b_3 are set to "H", and a weighting coefficient of 0 is written.

[0128] In a period T22, the potential of the wiring 116b is set to "L", the potential of the wiring 117b is set to "L", and the photoelectric conversion device 101 performs an exposure operation.

[0129] In a period T23, the potential of the wiring 116b is set to “H”, the potential generated by the photoelectric conversion device 101 is transferred, and the potential X n+2 The period T21 to the period T23 corresponds to a period for acquiring exposed data of the n+2th frame. Note that the node NDa is supplied with a potential X n+1 (Image data) is stored.

[0130] In a period T24, the potentials of the wirings 122_1, 122_2, and 122_3 are set to “H” to select all the pixels 100 in the pixel block. At this time, the transistor 105a of each pixel 100 is supplied with a potential X n+1 A current corresponding to the potential X flows through the transistor 105b. n+2 A current according to the potential flows. By setting the potential of the wiring 216 to "H", the potential Vr of the wiring 218 is written to the node C, and the potential of the node C is initialized to the potential Vr.

[0131] During period T25, the potential of wiring 111a_1 is set to a potential equivalent to weighting factor W21 (weighting to be added to the pixels in the first row) and the potential of wiring 112a_1 is set to “H”, so that the weighting factor W21 is added to node NDa of pixel 100 in the first row through capacitive coupling of capacitor 104a.

[0132] By setting the potential of the wiring 111a_2 to a potential equivalent to the weighting factor W22 (the weighting factor to be added to the pixel in the second row) and setting the potential of the wiring 112a_2 to “H”, the weighting factor W22 is added to the node NDa of the pixel 100 in the second row through the capacitive coupling of the capacitor 104a.

[0133] By setting the potential of the wiring 111a_3 to a potential equivalent to weighting factor W23 (weighting to be added to the pixel in the third row) and setting the potential of the wiring 112a_3 to "H", the weighting factor W23 is added to the node NDa of the pixel 100 in the third row through the capacitive coupling of the capacitor 104a.

[0134] By setting the potential of the wiring 111b_1 to a potential equivalent to the weighting coefficient W11 (the weighting added to the pixel in the first row) and setting the potential of the wiring 112b_1 to "H", the weighting coefficient W11 is added to the node NDb of the pixel 100 in the first row through the capacitive coupling of the capacitor 104b.

[0135] By setting the potential of the wiring 111b_2 to a potential equivalent to the weighting factor W12 (the weighting factor to be added to the pixel in the second row) and setting the potential of the wiring 112b_2 to "H", the weighting factor W12 is added to the node NDb of the pixel 100 in the second row through the capacitive coupling of the capacitor 104b.

[0136] By setting the potential of wiring 111b_3 to a potential equivalent to weighting factor W13 (weighting to be added to the pixel in the third row) and setting the potential of wiring 112b_3 to "H", the weighting factor W13 is added to node NDb of pixel 100 in the third row through capacitive coupling of capacitor 104b.

[0137] Continuing from the period T24, the potentials of the wirings 122_1, 122_2, and 122_3 are set to “H” to select all the pixels 100 in the pixel block 200. At this time, the transistors 105a of the pixels 100 in the first row are supplied with a potential W21+X n+1 A current corresponding to the potential W11+X flows through the transistor 105b. n+2 In addition, a current corresponding to a potential W22+X flows through the transistor 105a of the pixel 100 in the second row. n+1 A current corresponding to the potential W12+X flows through the transistor 105b.n+2 In addition, a current corresponding to a potential W23+X flows through the transistor 105a of the pixel 100 in the third row. n+1 A current corresponding to the potential W13+X flows through the transistor 105b. n+2 A current according to the

[0138] Here, the potential of the other electrode of the capacitor 202 changes according to the current flowing through the wiring 113, and the change Y is added to the potential Vr of the node C by capacitive coupling. Therefore, the potential of the node C becomes "Vr+Y." If we consider Vr=0, then Y is the difference itself, and data A has been calculated.

[0139] The potential of the wiring 213 is set to “H” and the potential of the wiring 215 is set to “V bias By setting an appropriate analog potential such as "", the circuit 201 can output a signal potential according to the data A of the pixel block 200 in the first row by a source follower operation.

[0140] The operation in period T25 corresponds to a period in which data A is generated based on image-captured data in the (n+2)th frame and data A is output to the circuit 301 (read out).

[0141] In a period T26, the potentials of the wirings 122_1, 122_2, 122_3, 112a_1, 112a_2, 112a_3, 112b_1, 112b_2, 112b_3, 213A, 213B, and 215 are set to "L".

[0142] This concludes the explanation of the operation of the n+2th frame.

[0143] For subsequent frames, the same operations as described above can be performed.

[0144] 8 is a timing chart explaining the operation of calculating the difference (data B) between data without exposure and data with a weight applied thereto in pixel block 200 and circuit 201. Data B may be acquired as necessary. For example, if there is no change in the weight to be input, acquired data B may be stored in a memory and data B may be read out from the memory. A plurality of data B corresponding to a plurality of weights may be stored in the memory. Either data A or data B may be acquired first.

[0145] Here, the operation of the (n+1)th frame will be described with reference to Fig. 8. Note that a description of the parts common to the above-mentioned Fig. 7 will be omitted, and the different parts will be mainly described.

[0146] First, in the periods T11 to T13, the potentials of the wiring 116a and 117a are set to "H", and the node NDa of the pixel 100 is set to a reset potential. Similarly, the potentials of the wiring 116b and 117b are set to "H", and the node NDb of the pixel 100 is set to a reset potential. That is, during this period, the potentials of the nodes NDa and NDb are each the reset potential regardless of the operation of the photoelectric conversion device 101. At the end of the period T13, the potentials of the wirings 116a, 117a, 116b, and 117b are set to "L".

[0147] In a period T11, the potentials of the wirings 111a_1, 111a_2, and 111a_3 are set to "L", the potentials of the wirings 112a_1, 112a_2, and 112a_3 are set to "H", and the weighting coefficient is written as 0. This operation may be performed during a period in which the potential of the node NDa is the reset potential.

[0148] Similarly, the potentials of the wirings 111b_1, 111b_2, and 111b_3 are set to "L", the potentials of the wirings 112b_1, 112b_2, and 112b_3 are set to "H", and a weighting coefficient of 0 is written. This operation may be performed during a period in which the potential of the node NDb is the reset potential.

[0149] In a period T14, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all the pixels 100 in the pixel block 200. At this time, a current corresponding to the reset potential flows through the transistor 105a of each pixel 100. In addition, the potential of the wiring 216 is set to "H" to write the potential Vr of the wiring 218 to the node C. The operation in the period T14 corresponds to obtaining data without exposure, and the data is initialized to the potential Vr of the node C.

[0150] During period T15, the potential of wiring 111a_1 is set to a potential equivalent to weighting factor W11 (weighting to be added to the pixels in the first row) and the potential of wiring 112a_1 is set to “H”, so that the weighting factor W11 is added to node NDa of pixel 100 in the first row through capacitive coupling of capacitor 104a.

[0151] By setting the potential of the wiring 111a_2 to a potential equivalent to the weighting factor W12 (the weighting factor to be added to the pixel in the second row) and setting the potential of the wiring 112a_2 to “H”, the weighting factor W12 is added to the node NDa of the pixel 100 in the second row through the capacitive coupling of the capacitor 104a.

[0152] By setting the potential of the wiring 111a_3 to a potential equivalent to the weighting factor W13 (the weighting factor to be added to the pixel in the third row) and setting the potential of the wiring 112a_3 to “H”, the weighting factor W13 is added to the node NDa of the pixel 100 in the third row through the capacitive coupling of the capacitor 104a.

[0153] By setting the potential of the wiring 111b_1 to a potential equivalent to the weighting factor W21 (the weighting factor to be added to the pixel in the first row) and setting the potential of the wiring 112b_1 to "H", the weighting factor W21 is added to the node NDb of the pixel 100 in the first row through the capacitive coupling of the capacitor 104b.

[0154] By setting the potential of the wiring 111b_2 to a potential equivalent to the weighting factor W22 (the weighting factor to be added to the pixel in the second row) and setting the potential of the wiring 112b_2 to “H”, the weighting factor W22 is added to the node NDb of the pixel 100 in the second row through the capacitive coupling of the capacitor 104b.

[0155] By setting the potential of wiring 111b_3 to a potential equivalent to weighting factor W23 (weighting to be added to the pixel in the third row) and setting the potential of wiring 112b_3 to "H", the weighting factor W23 is added to node NDb of pixel 100 in the third row through capacitive coupling of capacitor 104b.

[0156] Continuing from the period T14, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all the pixels 100 in the pixel block 200. At this time, a current corresponding to a potential W11+0 flows through the transistor 105a of the pixels 100 in the first row, and a current corresponding to a potential W21+0 flows through the transistor 105b. A current corresponding to a potential W12+0 flows through the transistor 105a of the pixels 100 in the second row, and a current corresponding to a potential W22+0 flows through the transistor 105b. A current corresponding to a potential W13+0 flows through the transistor 105a of the pixels 100 in the third row, and a current corresponding to a potential W23+0 flows through the transistor 105b.

[0157] Here, the potential of the other electrode of the capacitor 202 changes according to the current flowing through the wiring 113, and the change Z is added to the potential Vr of the node C by capacitive coupling. Therefore, the potential of the node C becomes "Vr+Z." Here, if we consider Vr=0, Z is the difference itself, and data B has been calculated.

[0158] The potentials of the wiring 213A, the wiring 213B, etc. are sequentially set to “H”, and the potential of the wiring 215 is set to an appropriate analog potential (V bias ) the circuit 201 can output a signal potential according to the data B of the pixel block 200 in the first row by a source follower operation.

[0159] The operation in period T15 corresponds to a period in which data B is generated based on data without imaging and data B is output to the circuit 301 (read out).

[0160] In a period T16, the potentials of the wirings 122_1, 122_2, 122_3, 112a_1, 112a_2, 112a_3, 112b_1, 112b_2, 112b_3, 213A, 213B, and 215 are set to "L".

[0161] The data A and data B output from the circuit 201 by the above operation are input to the circuit 301. The circuit 301 performs a calculation to obtain the difference between the data A and the data B, and can remove unnecessary offset components other than the product of the image data (potential X) and the weighting coefficient (potential W). The circuit 301 may be configured to have a calculation circuit like the circuit 201, or may be configured to obtain the difference using a memory circuit and software processing.

[0162] In the above operation, the potential of node C of circuit 201 is initialized to the same potential "Vr" for both the operation of acquiring data A and the operation of acquiring data B. Then, in the subsequent difference calculation, "(Vr+Y)-(Vr+Z)"="YZ", and the potential "Vr" component is removed. As described above, other unnecessary offset components are also removed, so that the product of image data (potential X) and weighting coefficient (potential W) can be extracted.

[0163] This concludes the explanation of the operation of the n+1th frame.

[0164] Next, the operation of the n+2th frame will be described with reference to Fig. 8. Note that a description of the parts common to the above-mentioned n+1th frame (periods T11 to T16) will be omitted, and the different parts will be mainly described.

[0165] First, in the periods T21 to T23, the potential of the wiring 116a is set to "H", the potential of the wiring 117a is set to "H", and the node NDa of the pixel 100 is set to a reset potential. Similarly, the potential of the wiring 116b is set to "H", the potential of the wiring 117b is set to "H", and the node NDb of the pixel 100 is set to a reset potential. At the end of the period T23, the potentials of the wirings 116a, 117a, 116b, and 117b are set to "L".

[0166] In a period T21, the potentials of the wirings 111a_1, 111a_2, and 111a_3 are set to "L", the potentials of the wirings 112a_1, 112a_2, and 112a_3 are set to "H", and a weighting coefficient of 0 is written. Similarly, the potentials of the wirings 111b_1, 111b_2, and 111b_3 are set to "L", the potentials of the wirings 112b_1, 112b_2, and 112b_3 are set to "H", and a weighting coefficient of 0 is written.

[0167] In period T24, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all the pixels 100 in the pixel block 200. At this time, a current corresponding to the reset potential flows through the transistor 105b of each pixel 100. In addition, the potential of the wiring 216 is set to "H" to write the potential Vr of the wiring 218 to the node C. The operation in period T24 corresponds to obtaining data without exposure, and the data is initialized to the potential Vr of the node C.

[0168] During a period T25, the potential of the wiring 111a_1 is set to a potential corresponding to the weighting factor W21, and the potential of the wiring 112a_1 is set to "H," so that the weighting factor W21 is added to the node NDa of the pixel 100 in the first row by capacitive coupling of the capacitor 104a.

[0169] By setting the potential of the wiring 111a_2 to a potential corresponding to the weighting factor W22 and setting the potential of the wiring 112a_2 to "H", the weighting factor W22 is added to the node NDa of the pixel 100 in the second row by the capacitive coupling of the capacitor 104a.

[0170] By setting the potential of the wiring 111a_3 to a potential equivalent to the weighting factor W23 and setting the potential of the wiring 112a_3 to "H", the weighting factor W23 is added to the node NDa of the pixel 100 in the third row by the capacitive coupling of the capacitor 104a.

[0171] By setting the potential of the wiring 111b_1 to a potential corresponding to the weighting factor W11 and setting the potential of the wiring 112b_1 to "H", the weighting factor W11 is added to the node NDb of the pixel 100 in the first row by the capacitive coupling of the capacitor 104b.

[0172] By setting the potential of the wiring 111b_2 to a potential corresponding to the weighting factor W12 and setting the potential of the wiring 112b_2 to "H", the weighting factor W12 is added to the node NDb of the pixel 100 in the second row by the capacitive coupling of the capacitor 104b.

[0173] By setting the potential of the wiring 111b_3 to a potential equivalent to the weighting factor W13 and setting the potential of the wiring 112b_3 to "H", the weighting factor W13 is added to the node NDb of the pixel 100 in the third row by the capacitive coupling of the capacitor 104b.

[0174] Continuing from the period T24, the potentials of the wirings 122_1, 122_2, and 122_3 are set to "H" to select all the pixels 100 in the pixel block 200. At this time, a current corresponding to a potential W21+0 flows through the transistor 105a of the pixels 100 in the first row, and a current corresponding to a potential W11+0 flows through the transistor 105b. A current corresponding to a potential W22+0 flows through the transistor 105a of the pixels 100 in the second row, and a current corresponding to a potential W12+0 flows through the transistor 105b. A current corresponding to a potential W23+0 flows through the transistor 105a of the pixels 100 in the third row, and a current corresponding to a potential W13+0 flows through the transistor 105b.

[0175] Here, the potential of the other electrode of the capacitor 202 changes according to the current flowing through the wiring 113, and the change Z is added to the potential Vr of the node C by capacitive coupling. Therefore, the potential of the node C becomes "Vr+Z." Here, if we consider Vr=0, Z is the difference itself, and data B has been calculated.

[0176] The potentials of the wiring 213A, the wiring 213B, etc. are sequentially set to “H”, and the potential of the wiring 215 is set to an appropriate analog potential (V bias ) the circuit 201 can output a signal potential according to the data B of the pixel block 200 in the first row by a source follower operation.

[0177] The operation in period T25 corresponds to a period in which data B is generated based on data without imaging and data B is output to the circuit 301 (read out).

[0178] In a period T26, the potentials of the wirings 122_1, 122_2, 122_3, 112a_1, 112a_2, 112a_3, 112b_1, 112b_2, 112b_3, 213A, 213B, and 215 are set to "L".

[0179] The data A and data B output from the circuit 201 by the above operation are input to the circuit 301. The circuit 301 performs an operation to obtain the difference between the data A and the data B, and can remove unnecessary offset components other than the product of the image data (potential X) and the weighting coefficient (potential W).

[0180] This concludes the explanation of the operation of the n+2th frame.

[0181] For subsequent frames, the same operations as described above can be performed.

[0182] This operation corresponds to the initial operation in a neural network that performs inference, etc. Therefore, at least one calculation can be performed within the imaging device before a huge amount of image data is output to the outside, reducing the load of external calculations or data input / output, speeding up processing, and reducing power consumption.

[0183] As an operation different from the above, the potential of node C of circuit 201 may be initialized to different potentials in the operation of acquiring data A and the operation of acquiring data B. For example, assume that the potential is initialized to "Vr1" when acquiring data A, and to "Vr2" when acquiring data B. In this case, in the subsequent difference calculation, "(Vr1+Y)-(Vr2+Z)"="(Vr1-Vr2)+(YZ)". "YZ" is extracted as the product of image data (potential X) and weighting coefficient (potential W) as in the above operation, and "Vr1-Vr2" is further added. Here, "Vr1-Vr2" corresponds to a bias used as a threshold adjustment in the calculation of the intermediate layer of the neural network.

[0184] As an operation different from the above, the potential of the wiring 215 may be made different depending on whether imaging is performed or not. For example, when acquiring data A, the potential of the wiring 215 may be set to “V bias 1”, and when acquiring data B, the potential of the wiring 215 is set to “V bias 2”. Also, assume that node C is initialized to the same potential “Vr” during the acquisition operation of data A and during the acquisition operation of data B. In this case, in the subsequent difference calculation, “(Vr+YV bias 1)-(Vr+ZV bias 2)”=“(V bias 2-V bias 1)+(YZ)”. “YZ” is extracted as the product of the image data (electric potential X) and the weighting coefficient (electric potential W) in the same manner as in the above operation, and is further calculated as “V bias 2-V bias 1” is added. Here, “V bias 2-V bias 1" corresponds to the bias used as a threshold adjustment in the calculation of the intermediate layer of the neural network.

[0185] The weighting, for example, serves as a filter for a convolutional neural network (CNN), but may also serve to amplify or attenuate data. For example, if the weighting coefficient (W) during the acquisition operation of data A is the product of the filter processing amount and the amplification amount, data corrected to a bright image can be extracted. Data B is data without imaging, and can also be said to be black level data. Therefore, the operation of taking the difference between data A and data B can be said to be an operation for promoting the visualization of an image captured in a dark place. In other words, brightness correction using a neural network becomes possible.

[0186] As described above, in one aspect of the present invention, a bias can be generated by the operation of the imaging device. In addition, functional weights can be added within the imaging device. Therefore, the load of external calculations can be reduced and the imaging device can be used for various purposes. For example, in addition to subject inference, some of the processes such as resolution correction of image data, brightness correction, generation of color images from monochrome images, generation of three-dimensional images from two-dimensional images, restoration of missing information, generation of videos from still images, and correction of out-of-focus images can be performed within the imaging device.

[0187] <Image capture operation 2> An example in which three types of filters are used in each of the circuits 130a and 130b will be described with reference to FIGS.

[0188] 9 and 10 are timing charts for explaining the operation of calculating the difference (data A) between exposed data and weighted data in the pixel block 200 and the circuit 201. Note that explanations of parts common to the above-mentioned FIG. 7 will be omitted, and differences will be mainly explained.

[0189] The operation in the (n+1)th frame will be described with reference to Fig. 9. Note that Fig. 9 corresponds to the operation in the (n+1)th frame shown in Fig. 7.

[0190] For the periods T11 to T13, the description of FIG. 7 can be referred to, and therefore detailed description thereof will be omitted.

[0191] 7, detailed description of the periods T14_1 to T15_1 is omitted. During the periods T14_1 to T15_1, the image data IM acquired in the (n+1)th frame in the circuit 130a is n+1 is weighted by a first filter FL11, and the image data IM n is weighted using the second filter FL21. In the period T14_1 to the period T15_1, data A is calculated in the (n+1)th frame when the first filter FL11 and the second filter FL21 are used.

[0192] In a period T14_2, the potentials of the wirings 112a_1, 112a_2, 112a_3, 112b_1, 112b_2, and 112b_3 are set to “L”. At this time, the transistor 105a of each pixel 100 is supplied with a potential X n+1 A current corresponding to the potential X flows through the transistor 105b. n A current according to the potential flows. By setting the potential of the wiring 216 to "H", the potential Vr of the wiring 218 is written to the node C, and the potential of the node C is initialized to the potential Vr.

[0193] During period T15_2, the potential of the wiring 111a_1 is set to a potential equivalent to the weighting factor W31 (weighting to be added to the pixels in the first row) and the potential of the wiring 112a_1 is set to “H”, so that the weighting factor W31 is added to the node NDa of the pixels 100 in the first row through the capacitive coupling of the capacitor 104a.

[0194] By setting the potential of the wiring 111a_2 to a potential equivalent to the weighting factor W32 (the weighting factor to be added to the pixel in the second row) and setting the potential of the wiring 112a_2 to “H”, the weighting factor W32 is added to the node NDa of the pixel 100 in the second row through the capacitive coupling of the capacitor 104a.

[0195] By setting the potential of the wiring 111a_3 to a potential equivalent to the weighting factor W33 (weighting added to the pixel in the third row) and setting the potential of the wiring 112a_3 to "H", the weighting factor W33 is added to the node NDa of the pixel 100 in the third row by the capacitive coupling of the capacitor 104a. Note that the weighting factor W31, the weighting factor W32, and the weighting factor W33 are elements of the third filter FL12.

[0196] By setting the potential of the wiring 111b_1 to a potential equivalent to a weighting factor W41 (weighting to be added to the pixels in the first row) and setting the potential of the wiring 112b_1 to "H", the weighting factor W41 is added to the node NDb of the pixels 100 in the first row through the capacitive coupling of the capacitor 104b.

[0197] By setting the potential of the wiring 111b_2 to a potential equivalent to weighting factor W42 (weighting to be added to the pixel in the second row) and setting the potential of the wiring 112b_2 to "H", the weighting factor W42 is added to the node NDb of the pixel 100 in the second row through the capacitive coupling of the capacitor 104b.

[0198] By setting the potential of the wiring 111b_3 to a potential equivalent to the weighting factor W43 (weighting added to the pixels in the third row) and setting the potential of the wiring 112b_3 to "H", the weighting factor W43 is added to the node NDb of the pixel 100 in the third row by the capacitive coupling of the capacitor 104b. Note that the weighting factor W41, the weighting factor W42, and the weighting factor W43 are elements of the fourth filter FL22.

[0199] The transistor 105a of the pixel 100 in the first row is connected to a potential W31+X n+1 A current corresponding to the potential W41+X flows through the transistor 105b. n In addition, a current corresponding to a potential W32+X flows through the transistor 105a of the pixel 100 in the second row. n+1 A current corresponding to the potential W42+X flows through the transistor 105b. n In addition, a current corresponding to a potential W33+X flows through the transistor 105a of the pixel 100 in the third row. n+1 A current corresponding to the potential W43+X flows through the transistor 105b. n A current according to the

[0200] During the period T14_2 to the period T15_2, the image data IM acquired in the n+1th frame in the circuit 130a is n+1 is weighted by a third filter FL12, and the image data IM n is weighted using the fourth filter FL22. In the period T14_2 to the period T15_2, data A is calculated when the third filter FL12 and the fourth filter FL22 are used.

[0201] Similarly, in the period T14_3 to the period T15_3, the image data IM n+1 is weighted by a fifth filter FL13, and the image data IM acquired in the nth frame held in the circuit 130b is n is weighted by using the sixth filter FL23. In the period T14_3 to the period T15_3, data A is calculated when the fifth filter FL13 and the sixth filter FL23 are used.

[0202] For the period T16, the description in relation to FIG. 7 can be referred to, and therefore a detailed description thereof will be omitted.

[0203] This concludes the explanation of the operation of the n+1th frame.

[0204] The operation of the n+2th frame will be described with reference to Fig. 10. Fig. 10 corresponds to the operation of the n+2th frame shown in Fig. 7. Note that a description of the parts common to the above-mentioned n+1th frame (periods T11 to T16) will be omitted, and the different parts will be mainly described.

[0205] For the periods T21 to T23, the description of FIG. 7 can be referred to, and therefore detailed description thereof will be omitted.

[0206] 7, detailed description of the periods T24_1 to T25_1 will be omitted. During the periods T24_1 to T25_1, the image data IM acquired in the n+2th frame in the circuit 130b is n+2 The first filter FL11 is used to weight the image data IM acquired in the (n+1)th frame held in the circuit 130a. n+1 is weighted using the second filter FL21. In the period T24_1 to the period T25_1, data A is calculated in the (n+2)th frame when the first filter FL11 and the second filter FL21 are used.

[0207] In the period T24_2, the transistor 105a of each pixel 100 is supplied with a potential X n+1 A current corresponding to the potential X flows through the transistor 105b. n+2 A current according to the potential flows. By setting the potential of the wiring 216 to "H", the potential Vr of the wiring 218 is written to the node C, and the potential of the node C is initialized to the potential Vr.

[0208] During a period T25_2, the potential of the wiring 111a_1 is set to a potential corresponding to the weighting factor W41, and the potential of the wiring 112a_1 is set to "H," so that the weighting factor W41 is added to the node NDa of the pixel 100 in the first row by capacitive coupling of the capacitor 104a.

[0209] By setting the potential of the wiring 111a_2 to a potential corresponding to the weighting factor W42 and setting the potential of the wiring 112a_2 to "H", the weighting factor W42 is added to the node NDa of the pixel 100 in the second row by the capacitive coupling of the capacitor 104a.

[0210] By setting the potential of the wiring 111a_3 to a potential equivalent to the weighting factor W43 and setting the potential of the wiring 112a_3 to "H", the weighting factor W43 is added to the node NDa of the pixel 100 in the third row by the capacitive coupling of the capacitor 104a.

[0211] By setting the potential of the wiring 111b_1 to a potential corresponding to the weighting factor W31 and setting the potential of the wiring 112b_1 to "H", the weighting factor W31 is added to the node NDb of the pixel 100 in the first row by the capacitive coupling of the capacitor 104b.

[0212] By setting the potential of the wiring 111b_2 to a potential corresponding to the weighting factor W32 and setting the potential of the wiring 112b_2 to "H", the weighting factor W32 is added to the node NDb of the pixel 100 in the second row by the capacitive coupling of the capacitor 104b.

[0213] By setting the potential of the wiring 111b_3 to a potential equivalent to the weighting factor W33 and setting the potential of the wiring 112b_3 to "H", the weighting factor W33 is added to the node NDb of the pixel 100 in the third row by the capacitive coupling of the capacitor 104b.

[0214] The transistor 105a of the pixel 100 in the first row is connected to a potential W41+X n+1 A current corresponding to the potential W31+X flows through the transistor 105b. n+2 In addition, a current corresponding to a potential W42+X flows through the transistor 105a of the pixel 100 in the second row. n+1 A current corresponding to the potential W32+X flows through the transistor 105b. n+2 In addition, a current corresponding to a potential W43+X flows through the transistor 105a of the pixel 100 in the third row. n+1 A current corresponding to the potential W33+X flows through the transistor 105b. n+2 A current according to the

[0215] During the period T24_2 to the period T25_2, the image data IM acquired in the n+2th frame is n+2 The third filter FL12 is used to weight the image data IM acquired in the (n+1)th frame held in the circuit 130a. n+1 is weighted using the fourth filter FL22. In the period T24_2 to the period T25_2, data A is calculated when the third filter FL12 and the fourth filter FL22 are used.

[0216] Similarly, in the period T24_3 to the period T25_3, the image data IM acquired in the n+2th frame in the circuit 130b is n+2 The fifth filter FL13 is used to weight the image data IM acquired in the (n+1)th frame held in the circuit 130a. n+1 is weighted by using the sixth filter FL23. In the period T24_3 to the period T25_3, data A is calculated when the fifth filter FL13 and the sixth filter FL23 are used.

[0217] For the period T26, the description related to FIG. 7 can be referred to, and therefore a detailed description thereof will be omitted.

[0218] This concludes the explanation of the operation of the n+2th frame.

[0219] For subsequent frames, the same operations as described above can be performed.

[0220] 11 and 12 are timing charts for explaining the operation of calculating the difference (data B) between no-exposure data and weighted data in the pixel block 200 and the circuit 201. Note that explanations of parts common to the above-mentioned FIG. 8 will be omitted, and differences will be mainly explained.

[0221] The operation in the (n+1)th frame will be described with reference to Fig. 11. Note that Fig. 11 corresponds to the operation in the (n+1)th frame shown in Fig. 8.

[0222] For the periods T11 to T13, the description of FIG. 8 can be referred to, and therefore detailed description thereof will be omitted.

[0223] For the periods T14_1 to T15_1, the descriptions of the periods T14 to T15 in Fig. 8 can be referred to, and detailed description thereof will be omitted. In the periods T14_1 to T15_1, data B is calculated in the (n+1)th frame when the first filter FL11 and the second filter FL21 are used.

[0224] In a period T14_2, the potentials of the wirings 112a_1, 112a_2, 112a_3, 112b_1, 112b_2, and 112b_3 are set to "L". At this time, a current corresponding to the reset potential flows through the transistor 105a of each pixel 100. In addition, the potential of the wiring 216 is set to "H", so that the potential Vr of the wiring 218 is written to the node C. The operation in the period T14 corresponds to obtaining data without exposure, and the data is initialized to the potential Vr of the node C.

[0225] During a period T15_2, the potential of the wiring 111a_1 is set to a potential corresponding to the weighting coefficient W31, and the potential of the wiring 112a_1 is set to "H," so that the weighting coefficient W31 is added to the node NDa of the pixel 100 in the first row by capacitive coupling of the capacitor 104a.

[0226] By setting the potential of the wiring 111a_2 to a potential equivalent to the weighting factor W32 and setting the potential of the wiring 112a_2 to "H", the weighting factor W32 is added to the node NDa of the pixel 100 in the second row by the capacitive coupling of the capacitor 104a.

[0227] By setting the potential of the wiring 111a_3 to a potential equivalent to the weighting factor W33 and setting the potential of the wiring 112a_3 to "H", the weighting factor W33 is added to the node NDa of the pixel 100 in the third row by the capacitive coupling of the capacitor 104a.

[0228] By setting the potential of the wiring 111b_1 to a potential corresponding to the weighting factor W41 and setting the potential of the wiring 112b_1 to "H", the weighting factor W41 is added to the node NDb of the pixel 100 in the first row by the capacitive coupling of the capacitor 104b.

[0229] By setting the potential of the wiring 111b_2 to a potential equivalent to the weighting factor W42 and setting the potential of the wiring 112b_2 to "H", the weighting factor W42 is added to the node NDb of the pixel 100 in the second row by the capacitive coupling of the capacitor 104b.

[0230] By setting the potential of the wiring 111b_3 to a potential equivalent to the weighting factor W43 and setting the potential of the wiring 112b_3 to "H", the weighting factor W43 is added to the node NDb of the pixel 100 in the third row by the capacitive coupling of the capacitor 104b.

[0231] In the period T14_2 to the period T15_2, the data B is calculated when the third filter FL12 and the fourth filter FL22 are used.

[0232] Similarly, in the period T14_3 to the period T15_3, data B is calculated in the case where the fifth filter FL13 and the sixth filter FL23 are used.

[0233] For the period T16, the description in relation to FIG. 8 can be referred to, and therefore a detailed description thereof will be omitted.

[0234] This concludes the explanation of the operation of the n+1th frame.

[0235] The operation in the (n+2)th frame will be described with reference to Fig. 12. Fig. 12 corresponds to the operation in the (n+2)th frame shown in Fig. 8.

[0236] For the periods T21 to T23, the description of FIG. 8 can be referred to, and therefore detailed description thereof will be omitted.

[0237] For the periods T24_1 to T25_1, the descriptions of the periods T24 to T25 in Fig. 8 can be referred to, and detailed descriptions thereof will be omitted. In the periods T24_1 to T25_1, data B is calculated in the n+2-th frame when the first filter FL11 and the second filter FL21 are used.

[0238] In a period T24_2, the potentials of the wirings 112a_1, 112a_2, 112a_3, 112b_1, 112b_2, and 112b_3 are set to "L". At this time, a current corresponding to the reset potential flows through the transistor 105a of each pixel 100. In addition, the potential of the wiring 216 is set to "H", so that the potential Vr of the wiring 218 is written to the node C. The operation in the period T14 corresponds to obtaining data without exposure, and the data is initialized to the potential Vr of the node C.

[0239] During a period T25_2, the potential of the wiring 111a_1 is set to a potential corresponding to the weighting factor W41, and the potential of the wiring 112a_1 is set to "H," so that the weighting factor W41 is added to the node NDa of the pixel 100 in the first row by capacitive coupling of the capacitor 104a.

[0240] By setting the potential of the wiring 111a_2 to a potential corresponding to the weighting factor W42 and setting the potential of the wiring 112a_2 to "H", the weighting factor W42 is added to the node NDa of the pixel 100 in the second row by the capacitive coupling of the capacitor 104a.

[0241] By setting the potential of the wiring 111a_3 to a potential equivalent to the weighting factor W43 and setting the potential of the wiring 112a_3 to "H", the weighting factor W43 is added to the node NDa of the pixel 100 in the third row by the capacitive coupling of the capacitor 104a.

[0242] By setting the potential of the wiring 111b_1 to a potential corresponding to the weighting factor W31 and setting the potential of the wiring 112b_1 to "H", the weighting factor W31 is added to the node NDb of the pixel 100 in the first row by the capacitive coupling of the capacitor 104b.

[0243] By setting the potential of the wiring 111b_2 to a potential corresponding to the weighting factor W32 and setting the potential of the wiring 112b_2 to "H", the weighting factor W32 is added to the node NDb of the pixel 100 in the second row by the capacitive coupling of the capacitor 104b.

[0244] By setting the potential of the wiring 111b_3 to a potential equivalent to the weighting factor W33 and setting the potential of the wiring 112b_3 to "H", the weighting factor W33 is added to the node NDb of the pixel 100 in the third row by the capacitive coupling of the capacitor 104b.

[0245] In the period T24_2 to the period T25_2, the data B is calculated when the third filter FL12 and the fourth filter FL22 are used.

[0246] Similarly, in the period T24_3 to the period T25_3, data B is calculated in the case where the fifth filter FL13 and the sixth filter FL23 are used.

[0247] For the period T26, the description in relation to FIG. 8 can be referred to, and therefore a detailed description thereof will be omitted.

[0248] This concludes the explanation of the operation of the n+2th frame.

[0249] The same operation as described above can be performed for the subsequent frames. Note that although an example in which three types of filters are used in each of the circuits 130a and 130b is described here, one embodiment of the present invention is not limited to this. The number of types of filters used in each of the circuits 130a and 130b may be two or four or more. The number of types of filters used in each of the circuits 130a and 130b may be one.

[0250] <Pixel circuit configuration example 2> FIG. 13 shows an example of a configuration different from that of the pixel 100 shown in FIG.

[0251] The pixel 100 shown in FIG. 13 differs from the pixel 100 shown in FIG. 4 mainly in that the transistors 105a and 105b each have a back gate and in that the pixel 100 does not include the transistors 106a and 106b.

[0252] In the pixel 100 shown in FIG. 13, the back gate of the transistor 105a is electrically connected to the wiring 111a, and a potential corresponding to the weighting coefficient (W) is supplied from the wiring 111a. th ) is shifted to the negative side by the weighting factor (W), and the on-state current increases in the same way as when the weighting factor (W) is applied to the front gate. The back gate of the transistor 105b is electrically connected to the wiring 111b, and a potential equivalent to the weighting factor (W) is supplied from the wiring 111b. The threshold voltage (V th ) is shifted to the negative side by the weighting factor (W), and the on-current increases in the same way as when the weighting factor (W) is applied to the front gate. In the pixel 100 shown in FIG. 13, the difference between data A and data B is kΣ(2W·X), and offset components other than the product of image data (X) and weighting factor (W) can be removed. OS transistors can be suitably used for the transistor 105a and the transistor 105b having a back gate.

[0253] In the pixel 100 shown in FIG. 13, the other electrode of the capacitor 104a is electrically connected to the wiring 118a. The other electrode of the capacitor 104b is electrically connected to the wiring 118b. The wirings 118a and 118b each have a function of supplying a fixed potential. Note that the wiring 118a may be shared with one of the wirings 115a and 119b. For example, the other electrode of the capacitor 104a may be electrically connected to the wiring 115a. Similarly, the wiring 118b may be shared with one of the wirings 115b and 119b. For example, the other electrode of the capacitor 104b may be electrically connected to the wiring 115b. By sharing the wirings, the number of wirings can be reduced, and the area of ​​the wirings in the pixel can be reduced, thereby providing a high-definition imaging device.

[0254] As for the imaging operation, the description in relation to the above-mentioned Figs. 7 to 12 can be referred to, and therefore a detailed description thereof will be omitted.

[0255] <Circuit 301, circuit 302> 14A is a diagram for explaining circuits 301 and 302 connected to circuit 201. Data resulting from a multiply-and-accumulate operation output from circuit 201 is sequentially input to circuit 301. Circuit 301 may have various calculation functions in addition to the function of calculating the difference between data A and data B described above. For example, circuit 301 may have the same configuration as circuit 201. Alternatively, the function of circuit 301 may be replaced by software processing.

[0256] The circuit 301 may have a circuit that performs an activation function calculation. For example, a comparator circuit can be used for the circuit. The comparator circuit compares input data with a set threshold value and outputs the result as binary data. That is, the pixel block 200 and the circuit 301 can act as a part of a neural network.

[0257] The circuit 301 may include an A / D converter. Regardless of whether a product-sum operation is performed or not, when image data is output from the pixel block 200 to the outside, the circuit 301 can convert analog data into digital data.

[0258] For example, in a pixel block 200 having pixels 100 arranged in three rows and three columns, if the weights supplied to all pixels 100 are the same (e.g., 0) and the transistor 108 of the pixel from which data is to be output is made conductive, the sum of image data for the entire pixel block 200, the sum of image data for each row, or data for each pixel can be output from the pixel block 200.

[0259] The data output by the pixel block 200 corresponds to multi-bit image data, but if the data can be binarized by the circuit 301, it can be said that the image data is compressed.

[0260] Data output from the circuit 301 is sequentially input to the circuit 302. The circuit 302 can have a configuration including, for example, a latch circuit and a shift register. With this configuration, parallel-serial conversion can be performed, and data input in parallel can be output to the wiring 311 as serial data.

[0261] As shown in FIG. 14B, the circuit 302 may have a neural network. The neural network has memory cells arranged in a matrix, and each memory cell holds a weighting factor. Data output from the circuit 301 is input to each of the memory cells 320, and a multiply-and-accumulate operation can be performed. Note that the number of memory cells shown in FIG. 14B is an example and is not limited to this. Data after the multiply-and-accumulate operation can be output to a wiring 311.

[0262] 14A and 14B, there is no limitation on the connection destination of the wiring 311. For example, it can be connected to a neural network, a storage device, a communication device, etc.

[0263] The neural network shown in FIG. 14B has memory cells 320 and reference memory cells 325 arranged in a matrix, a circuit 330, a circuit 350, a circuit 360, and a circuit 370.

[0264] 15 shows an example of a memory cell 320 and a reference memory cell 325. The reference memory cell 325 is provided in an arbitrary column. The memory cell 320 and the reference memory cell 325 have the same configuration, and include a transistor 161, a transistor 162, and a capacitor 163.

[0265] One of the source or drain of the transistor 161 is electrically connected to the gate of the transistor 162. The gate of the transistor 162 is electrically connected to one electrode of the capacitor 163. Here, a point where one of the source or drain of the transistor 161, the gate of the transistor 162, and one electrode of the capacitor 163 are connected is referred to as a node NM.

[0266] A gate of the transistor 161 is electrically connected to the wiring WL. The other electrode of the capacitor 163 is electrically connected to the wiring RW. One of the source and the drain of the transistor 162 is electrically connected to a reference potential wiring such as a GND wiring.

[0267] In the memory cell 320, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WD. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BL.

[0268] In the reference memory cell 325, the other of the source and the drain of the transistor 161 is electrically connected to a wiring WDref. The other of the source and the drain of the transistor 162 is electrically connected to a wiring BLref.

[0269] The wiring WL is electrically connected to the circuit 330. The circuit 330 can be a decoder, a shift register, or the like.

[0270] The wiring RW is electrically connected to the circuit 301. Binary data output from the circuit 301 is written to each memory cell. Note that a sequential circuit such as a shift register may be provided between the circuit 301 and each memory cell.

[0271] The wiring WD and the wiring WDref are electrically connected to the circuit 350. The circuit 350 can be a decoder, a shift register, or the like. The circuit 350 may include a D / A converter and an SRAM. The circuit 350 can output the weighting coefficient written to the node NM.

[0272] The wiring BL and the wiring BLref are electrically connected to the circuit 360. The circuit 360 can have a structure similar to that of the circuit 201. The circuit 360 can provide a signal obtained by removing the offset component from the product-sum operation result.

[0273] The circuit 360 is electrically connected to the circuit 370. The circuit 370 can also be called an activation function circuit. The activation function circuit has a function of performing an operation to convert the signal input from the circuit 360 according to a predefined activation function. As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, etc. can be used. The signal converted by the activation function circuit is output to the outside as output data.

[0274] As shown in FIG. 16A, the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units). The intermediate layer HL may be one layer or two or more layers. A neural network having two or more intermediate layers HL can also be called a DNN (deep neural network). Learning using a deep neural network can also be called deep learning.

[0275] Input data is input to each neuron in the input layer IL. An output signal from a neuron in the previous or next layer is input to each neuron in the hidden layer HL. An output signal from a neuron in the previous layer is input to each neuron in the output layer OL. Each neuron may be connected to all neurons in the previous or next layer (full connection), or may be connected to only a portion of the neurons.

[0276] In the case of a convolutional neural network (CNN), the intermediate layer HL can be configured to have a layer that performs convolution processing (convolution layer), a layer that performs pooling processing (pooling layer), and a layer that performs fully connected processing (fully connected layer). In the convolution layer, feature extraction is performed by performing convolution processing. In addition, one or more weight filters can be used for the convolution processing. In addition to the above, the intermediate layer HL may include a normalization layer, etc. In the convolution processing, processing such as padding or stride may be combined.

[0277] FIG. 16B shows an example of a computation by a neuron. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N receives output x1 from a neuron in the previous layer and output x2 from a neuron in the previous layer. Neuron N then calculates the sum x1w1+x2w2 of the multiplication result (x1w1) of output x1 and weight w1 and the multiplication result (x2w2) of output x2 and weight w2, and then adds bias b as necessary to obtain value a=x1w1+x2w2+b. Value a is then transformed by activation function h, and output signal y=ah is output from neuron N.

[0278] In this way, the computation by a neuron includes the sum of the output of the previous layer neuron and the weight, that is, the sum of products (x1w1+x2w2 above). This sum of products may be performed by software using a program, or by hardware.

[0279] In one embodiment of the present invention, a multiply-and-accumulate circuit is used as hardware. When an analog circuit is used for the multiply-and-accumulate circuit, the circuit scale of the multiply-and-accumulate circuit can be reduced, or the number of accesses to a memory can be reduced, leading to improved processing speed and reduced power consumption.

[0280] The product-sum circuit preferably includes an OS transistor. Since an OS transistor has an extremely small off-state current, it is suitable as a transistor constituting an analog memory of the product-sum circuit. Note that the product-sum circuit may be configured using both a Si transistor and an OS transistor.

[0281] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0282] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0283] <Structure example> FIG. 17A is a diagram showing an example of the structure of a pixel of an imaging device, which can have a stacked structure of a layer 561 and a layer 563.

[0284] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 can include a layer 565a and a layer 565b as shown in Fig. 18A. Note that, in some cases, the layer may be referred to as a region.

[0285] 18A is a pn junction photodiode, and may use, for example, a p-type semiconductor for the layer 565a and an n-type semiconductor for the layer 565b. Alternatively, the layer 565a may be an n-type semiconductor, and the layer 565b may be a p-type semiconductor.

[0286] The pn junction photodiode can be typically formed using single crystal silicon. A photodiode using single crystal silicon as a photoelectric conversion layer has a relatively wide spectral sensitivity characteristic from ultraviolet light to near infrared light, and can detect light of various wavelengths by combining it with an optical conversion layer described later.

[0287] Alternatively, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode. Examples of the compound semiconductor include gallium arsenic phosphide (GaAsP), gallium phosphide (GaP), indium gallium arsenide (InGaAs), lead sulfur compound (PbS), lead selenium compound (PbSe), indium arsenide compound (InAs), indium antimony compound (InSb), and mercury cadmium telluride compound (HgCdTe).

[0288] The compound semiconductor is preferably a compound semiconductor having a Group 13 element (aluminum, gallium, indium, etc.) and a Group 15 element (nitrogen, phosphorus, arsenic, antimony, etc.) (also called a Group 3-5 compound semiconductor), or a compound semiconductor having a Group 12 element (magnesium, zinc, cadmium, mercury, etc.) and a Group 16 element (oxygen, sulfur, selenium, tellurium, etc.) (also called a Group 2-6 compound semiconductor).

[0289] Compound semiconductors allow the band gap to be changed depending on the combination of constituent elements and their atomic ratio, making it possible to form photodiodes that are sensitive to a wide range of wavelengths, from ultraviolet light to infrared light.

[0290] In addition, the wavelength of ultraviolet light can generally be defined as being around 0.01 μm to around 0.38 μm, the wavelength of visible light as being around 0.38 μm to around 0.75 μm, the wavelength of near-infrared light as being around 0.75 μm to around 2.5 μm, the wavelength of mid-infrared light as being around 2.5 μm to around 4 μm, and the wavelength of far-infrared light as being around 4 μm to around 1000 μm.

[0291] For example, to form a photodiode having photosensitivity from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from ultraviolet light to near infrared light, the above-mentioned silicon or GaAsP or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from near infrared light to mid-infrared light, PbS or InAs or the like can be used for the photoelectric conversion layer. To form a photodiode having photosensitivity from mid-infrared light to far-infrared light, PbSe, InSb, HgCdTe or the like can be used for the photoelectric conversion layer.

[0292] The photodiode using the compound semiconductor may have a pin junction instead of a pn junction. The pn junction and the pin junction are not limited to a homojunction structure, and may have a heterojunction structure.

[0293] For example, in a heterojunction, a first compound semiconductor can be used in one layer of a pn junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the other layer. Also, a first compound semiconductor can be used in one or two layers of a pin junction structure, and a second compound semiconductor different from the first compound semiconductor can be used in the remaining layers. Either the first compound semiconductor or the second compound semiconductor can be a simple semiconductor such as silicon.

[0294] Note that the photoelectric conversion layer of the photodiode may be formed using a different material for each pixel. By using this configuration, an imaging device having two or three types of pixels, such as pixels that detect ultraviolet light, pixels that detect visible light, and pixels that detect infrared light, can be formed.

[0295] The photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 566a, 566b, 566c, and 566d as shown in Fig. 18B. The photoelectric conversion device 101 shown in Fig. 18B is an example of an avalanche photodiode, in which the layers 566a and 566d correspond to electrodes, and the layers 566b and 566c correspond to a photoelectric conversion unit.

[0296] Layer 566a is preferably a low resistance metal layer, such as aluminum, titanium, tungsten, tantalum, silver, or a laminate of these.

[0297] The layer 566d is preferably a conductive layer having a high light-transmitting property to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 566d may be omitted.

[0298] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode with a photoelectric conversion layer made of, for example, a selenium-based material. It is preferable to use a selenium-based material, which is a p-type semiconductor, for the layer 566b, and a gallium oxide, which is an n-type semiconductor, for the layer 566c.

[0299] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In such photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. In addition, selenium-based materials have a high optical absorption coefficient, which offers the advantage of production in that the photoelectric conversion layer can be made as a thin film. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering methods.

[0300] As selenium-based materials, crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium can be used. These have photosensitivity from ultraviolet light to visible light. In addition, compounds of copper, indium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium (CIGS) can be used. These have photosensitivity from ultraviolet light to near infrared light.

[0301] The n-type semiconductor is preferably made of a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or a mixture of these oxides can be used. These materials also function as a hole injection blocking layer, and can reduce dark current.

[0302] The photoelectric conversion device 101 included in the layer 561 may be a laminate of layers 567a, 567b, 567c, 567d, and 567e as shown in Fig. 18C. The photoelectric conversion device 101 shown in Fig. 18C is an example of an organic photoconductive film, in which the layer 567a is a lower electrode, the layer 567e is a light-transmitting upper electrode, and the layers 567b, 567c, and 567d correspond to photoelectric conversion units.

[0303] One of the layers 567b and 567d of the photoelectric conversion portion can be a hole transport layer, and the other can be an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0304] For example, molybdenum oxide can be used as the hole transport layer. For example, C 60 , C 70 or derivatives thereof can be used.

[0305] A mixed layer (bulk heterojunction structure) of n-type and p-type organic semiconductors can be used as the photoelectric conversion layer. There are various types of organic semiconductors, and a material that has photosensitivity to the desired wavelength can be selected for the photoelectric conversion layer.

[0306] For example, a silicon substrate can be used as the layer 563 shown in FIG. 17A. The silicon substrate has Si transistors and the like. Using the Si transistors, in addition to pixel circuits, circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, neural networks, communication circuits, and the like can be formed. Also, memory circuits such as DRAMs (Dynamic Random Access Memory), CPUs (Central Processing Units), MCUs (Micro Controller Units), and the like may be formed. In this embodiment, the above circuits excluding the pixel circuits are called functional circuits.

[0307] For example, some or all of the transistors included in the pixel circuit (pixel 100) and the functional circuits (the circuit 201, the circuit 301, the circuit 302, the circuit 303, the circuit 304, the circuit 305, and the like) described in Embodiment 1 can be provided in the layer 563.

[0308] The layer 563 may be a laminate of multiple layers as shown in FIG. 17B. Although three layers, 563a, 563b, and 563c, are illustrated in FIG. 17B, two layers may be used. Alternatively, the layer 563 may be a laminate of four or more layers. These layers can be laminated using, for example, a bonding process. With this configuration, the pixel circuits and the functional circuits can be distributed among multiple layers and the pixel circuits and the functional circuits can be stacked, so that a small-sized, highly functional imaging device can be manufactured.

[0309] The pixel may have a stacked structure of a layer 561, a layer 562, and a layer 563 as shown in FIG. 17C.

[0310] The layer 562 can include an OS transistor. One or more of the functional circuits described above may be formed using an OS transistor. Alternatively, one or more of the functional circuits may be formed using a Si transistor included in the layer 563 and an OS transistor included in the layer 562. Alternatively, the layer 563 may be used as a supporting substrate such as a glass substrate, and a functional circuit may be formed using the OS transistor included in the layer 562.

[0311] For example, a normally-off CPU (also referred to as an Noff-CPU) can be realized by using OS transistors and Si transistors. Note that an Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an off state) even when the gate voltage is 0 V.

[0312] The Noff-CPU can stop the power supply to circuits in the Noff-CPU that are not required to operate, and put the circuits into a standby state. When the power supply is stopped and the circuits are in a standby state, no power is consumed. Thus, the Noff-CPU can minimize power consumption. The Noff-CPU can also retain information necessary for operation, such as setting conditions, for a long period of time even if the power supply is stopped. To return from the standby state, it is only necessary to resume the power supply to the circuit, and there is no need to rewrite the setting conditions, etc. In other words, high-speed return from the standby state is possible. In this way, the Noff-CPU can reduce power consumption without significantly reducing the operating speed.

[0313] Layer 562 may be a laminate of multiple layers as shown in Fig. 17D. Although two layers, layer 562a and layer 562b, are illustrated in Fig. 17D, layer 562 may be a laminate of three or more layers. These layers may be formed by stacking them on layer 563, for example. Alternatively, layer 562 may be formed by bonding a layer formed on layer 563 and a layer formed on layer 561.

[0314] As a semiconductor material used for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A representative example is an oxide semiconductor containing indium, for example, CAAC-OS or CAC-OS described later can be used. CAAC-OS has stable atoms constituting the crystal, and is suitable for transistors that emphasize reliability. In addition, CAC-OS has high mobility characteristics, and is suitable for transistors that operate at high speed.

[0315] OS transistors have a large energy gap in the semiconductor layer, and therefore exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm of channel width). OS transistors also have characteristics different from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short channel effects, and can form highly reliable circuits with high voltage resistance. OS transistors are also less susceptible to variations in electrical characteristics caused by non-uniformity in crystallinity, which is a problem with Si transistors.

[0316] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn oxide containing indium, zinc, and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn oxide can be typically formed by a sputtering method. Alternatively, it may be formed by an ALD (atomic layer deposition) method.

[0317] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide by the sputtering method preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratio of the semiconductor layer to be formed includes a variation of ±40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0318] The semiconductor layer is made of an oxide semiconductor with a low carrier density. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3Less than 1×10, more preferably 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Less than 1×10, more preferably 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above oxide semiconductors can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and has stable characteristics.

[0319] Note that the composition is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the required semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0320] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase and the semiconductor layer becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0321] When an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, it may generate carriers, which may increase the off-state current of a transistor. For this reason, the concentration of an alkali metal or an alkaline earth metal in a semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0322] When nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons that act as carriers are generated, increasing the carrier density and making the semiconductor more likely to be n-type. As a result, a transistor using an oxide semiconductor that contains nitrogen is likely to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0323] When hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it reacts with oxygen bonded to a metal atom to form water, which may form oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in a channel formation region in an oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen has entered the oxygen vacancies may function as donors and generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a large amount of hydrogen is likely to have normally-on characteristics.

[0324] A defect in which hydrogen has entered an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Thus, an oxide semiconductor may be evaluated by its carrier concentration instead of its donor concentration. Thus, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0325] Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0326] The semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0327] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not include a crystalline component, or an oxide film having an amorphous structure has, for example, a completely amorphous structure and does not include a crystalline portion.

[0328] The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a multilayer structure including two or more of the above-mentioned regions.

[0329] The following describes the structure of a cloud-aligned composite (CAC)-OS, which is one type of non-single crystal semiconductor layer.

[0330] CAC-OS is, for example, a material in which elements constituting an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts. Note that, hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or thereabouts, is also referred to as a mosaic or patch shape.

[0331] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0332] For example, the CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS may be specifically referred to as CAC-IGZO) is an indium oxide (hereinafter, InO X1 (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter, In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (GaO X3 (X3 is a real number greater than 0). ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic shape, and the mosaic shape of InO X1 , or In X2 Zinc Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter, also referred to as a cloud-like structure).

[0333] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the first region is said to have a higher In concentration than the second region.

[0334] IGZO is a common name and may refer to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number).

[0335] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure, where multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the ab plane.

[0336] On the other hand, CAC-OS is a material composition of oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly distributed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0337] Note that the CAC-OS does not include a laminated structure of two or more films with different compositions, such as a two-layer structure consisting of a film mainly containing In and a film mainly containing Ga.

[0338] In addition, GaO X3The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 In some cases, it may be difficult to observe a clear boundary between the region in which the main component is the

[0339] In addition, when one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are contained instead of gallium, the CAC-OS has a configuration in which some regions observed to be in the form of nanoparticles mainly composed of the metal element and some regions observed to be in the form of nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0340] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as a deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is, for example, 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0341] CAC-OS has the characteristic that no clear peaks are observed when it is measured using the θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, the X-ray diffraction measurement shows that there is no orientation in the ab plane direction or the c axis direction in the measurement area.

[0342] In the electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called nano-beam electron beam) with a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) and multiple bright spots are observed in the ring region. Therefore, the electron beam diffraction pattern shows that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar direction and cross-sectional direction.

[0343] For example, in the case of the CAC-OS of In-Ga-Zn oxide, the EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) showed that GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 It can be seen that the region in which the main component is the crystalline silicon is unevenly distributed and mixed.

[0344] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. X3 The main components are In X2 Zinc Y2 O Z2 , or InO X1 The structure is such that the regions having each element as the main component are separated from each other in a mosaic pattern.

[0345] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y2 O Z2 , or InO X1 When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is expressed. X2Zinc Y2 O Z2 , or InO X1 When the region mainly composed of is distributed in a cloud shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0346] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X1 This region has higher insulating properties than the region where GaO is the main component. X3 When a region containing these as main components is distributed in an oxide semiconductor, leakage current can be suppressed and favorable switching operation can be achieved.

[0347] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the MOSFET and the MOSFET's resistance to the MOSFET's resistance work in a complementary manner, resulting in a high on-state current (I on ), and high field-effect mobility (μ).

[0348] Semiconductor elements using CAC-OS have high reliability, making CAC-OS suitable as a constituent material for various semiconductor devices.

[0349] <Laminated structure 1> Next, the laminated structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Alternatively, some of the elements shown below may be omitted. Also, the laminated structure shown below can be formed using a bonding process, a polishing process, etc., as necessary.

[0350] FIG. 19 is an example of a cross-sectional view of a laminate having layers 560, 561, and a layer 563, with a bonding surface between layers 563a and 563b that constitute layer 563.

[0351] <layer 563b> The layer 563b can have a functional circuit provided in the silicon substrate 611. Here, the transistor 105 and the transistor 108 included in the circuit 130 are shown as part of the functional circuit.

[0352] The layer 563b includes a silicon substrate 611, an insulating layer 612, an insulating layer 613, an insulating layer 614, an insulating layer 616, an insulating layer 617, an insulating layer 618, and a conductive layer 619. The insulating layer 612 functions as a protective film. The insulating layer 613, the insulating layer 614, the insulating layer 616, and the insulating layer 617 function as an interlayer insulating film and a planarizing film. The insulating layer 618 and the conductive layer 619 function as bonding layers. The conductive layer 619 is electrically connected to the gate of the transistor 105.

[0353] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarizing film, for example, an inorganic insulating film such as a silicon oxide film, and an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. The lamination layer will be described later.

[0354] The conductor that can be used as wiring, electrodes, and plugs for electrical connection between devices may be a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as components, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may be multiple layers composed of different materials.

[0355] <Layer 563a> The layer 563a includes elements of the pixel 100. The layer 563a may also include elements of a functional circuit. Here, the transistors 102 and 103 included in the circuit 130 are shown as elements of the functional circuit.

[0356] The layer 563a is provided with a silicon substrate 632, an insulating layer 631, an insulating layer 633, an insulating layer 634, an insulating layer 635, an insulating layer 637, and an insulating layer 638. In addition, a conductive layer 636 and a conductive layer 639 are provided.

[0357] The insulating layer 631 and the conductive layer 639 function as bonding layers. The insulating layers 634, 635, and 637 function as an interlayer insulating film and a planarizing film. The insulating layer 633 functions as a protective film. The insulating layer 638 functions to insulate the silicon substrate 632 and the conductive layer 639. The insulating layer 638 can be formed of the same material as the other insulating layers. The insulating layer 638 may be formed of the same material as the insulating layer 631.

[0358] The conductive layer 639 is electrically connected to the other of the source or the drain of the transistor 102 and one of the source or the drain of the transistor 103. The conductive layer 639 is also electrically connected to the gate of the transistor 105 and the conductive layer 619. The conductive layer 636 is also electrically connected to the wiring 114 (see FIG. 4).

[0359] Fig. 19 shows a fin-type Si transistor having a channel formation region in a silicon substrate (silicon substrate 611, silicon substrate 632). A cross section in the channel width direction (a cross section of A1-A2 shown in layer 563a in Fig. 19) is shown in Fig. 20A. The Si transistor may be a planar type as shown in Fig. 20B.

[0360] 20C, it may be a transistor having a silicon thin-film semiconductor layer 545. The semiconductor layer 545 may be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on a silicon substrate 632.

[0361] <layer 561> The layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on the layer 563a. Fig. 19 shows a configuration in which the organic photoconductive film shown in Fig. 18C is used for the photoelectric conversion layer as the photoelectric conversion device 101. Here, the layer 567a is a cathode, and the layer 567e is an anode.

[0362] Layer 561 is provided with insulating layer 651, insulating layer 652, insulating layer 653, insulating layer 654, and conductive layer 655.

[0363] The insulating layers 651, 653, and 654 function as an interlayer insulating film and a planarizing film. The insulating layer 654 is provided to cover the end of the photoelectric conversion device 101, and also functions to prevent a short circuit between the layer 567e and the layer 567a. The insulating layer 652 functions as an element isolation layer. It is preferable to use an organic insulating film or the like as the element isolation layer.

[0364] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102 included in the layer 563a. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 included in the layer 563a through the conductive layer 655.

[0365] <layer 560> The layer 560 is formed on the layer 561. The layer 560 includes a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0366] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 671. In addition, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated.

[0367] When the photoelectric conversion device 101 has sensitivity to visible light, a color filter can be used for the optical conversion layer 672. A color image can be obtained by assigning colors such as (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to the color filters for each pixel. For example, as shown in the perspective view (including the cross section) of FIG. 26A, a color filter 672R (red), a color filter 672G (green), and a color filter 672B (blue) can be assigned to different pixels.

[0368] In an appropriate combination of the photoelectric conversion device 101 and the optical conversion layer 672, if a wavelength cut filter is used in the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be obtained.

[0369] For example, an infrared imaging device can be formed by using an infrared filter that blocks light with wavelengths equal to or shorter than visible light in the optical conversion layer 672. A far-infrared imaging device can be formed by using a filter that blocks light with wavelengths equal to or shorter than near-infrared light in the optical conversion layer 672. An ultraviolet imaging device can be formed by using an ultraviolet filter that blocks light with wavelengths equal to or longer than visible light in the optical conversion layer 672.

[0370] In addition, a plurality of different optical conversion layers may be arranged in one imaging device. For example, as shown in FIG. 26B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0371] 26C, color filter 672R (red), color filter 672G (green), color filter 672B (blue), and ultraviolet filter 672UV can be assigned to different pixels. In this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0372] If a scintillator is used for the optical conversion layer 672, an imaging device can be provided that obtains an image that visualizes the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting the light with the photoelectric conversion device 101. An imaging device having this configuration may also be used as a radiation detector or the like.

[0373] The scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with the radiation. For example, Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc., dispersed in resin or ceramics can be used.

[0374] By imaging with infrared or ultraviolet light, it is possible to provide the imaging device with an inspection function, a security function, a sensor function, etc. For example, by imaging with infrared light, it is possible to perform non-destructive inspection of produce, sorting of agricultural products (such as measuring sugar content), vein authentication, medical testing, etc. Furthermore, by imaging with ultraviolet light, it is possible to detect ultraviolet light emitted from a light source or a flame, and it is possible to manage light sources, heat sources, production equipment, etc.

[0375] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below, and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, concentrated light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of a resin or glass that is highly translucent to light of the target wavelength.

[0376] <Lamination> Next, the bonding of the layer 563b and the layer 563a will be described.

[0377] The layer 563b is provided with an insulating layer 618 and a conductive layer 619. The conductive layer 619 has a region buried in the insulating layer 618. The surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that they are at the same height.

[0378] The layer 563a is provided with an insulating layer 631 and a conductive layer 639. The conductive layer 639 has a region buried in the insulating layer 631. The surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that they are at the same height.

[0379] Here, the conductive layer 619 and the conductive layer 639 preferably contain the same metal element as a main component. The insulating layer 618 and the insulating layer 631 preferably contain the same component.

[0380] For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the conductive layer 619 and the conductive layer 639. In view of ease of bonding, Cu, Al, W, or Au is preferably used. Furthermore, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layer 618 and the insulating layer 631.

[0381] That is, the same metal material as described above is preferably used for the conductive layer 619 and the conductive layer 639. The same insulating material as described above is preferably used for the insulating layer 618 and the insulating layer 631. With this structure, the layer 563b and the layer 563a can be bonded to each other at a boundary between them.

[0382] The conductive layers 619 and 639 may have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 618 and 631 may also have a multi-layer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0383] This bonding makes it possible to obtain electrical connection between the conductive layer 619 and the conductive layer 639. Also, it makes it possible to obtain a connection between the insulating layer 618 and the insulating layer 631 that has sufficient mechanical strength.

[0384] To bond metal layers together, a surface activation bonding method can be used, in which oxide films and adsorbed layers of impurities on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact with each other to bond them. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded together using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0385] To bond insulating layers together, a hydrophilic bonding method can be used, in which surfaces that have been treated with hydrophilicity using oxygen plasma or the like are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating the surfaces using a heat treatment. Hydrophilic bonding also produces bonds at the atomic level, resulting in mechanically excellent bonds.

[0386] When bonding the layer 563b and the layer 563a, an insulating layer and a metal layer are mixed on each bonding surface, so that, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0387] For example, a method of cleaning the surface after polishing, subjecting the surface of the metal layer to an anti-oxidation treatment, and then subjecting it to a hydrophilic treatment and bonding can be used. The surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than the above-mentioned methods may also be used.

[0388] By the above-mentioned bonding, the elements of the layer 563b and the elements of the pixel 100 of the layer 563a can be electrically connected to each other.

[0389] <Modification of Laminate Structure 1> FIG. 21 shows a modified example of the stacked structure shown in FIG. 19, in which the configuration of the photoelectric conversion device 101 in the layer 561 and a portion of the configuration of the layer 563a are different, and a bonding surface is also provided between the layer 561 and the layer 563a.

[0390] The layer 561 includes the photoelectric conversion device 101 , an insulating layer 661 , an insulating layer 662 , an insulating layer 664 , an insulating layer 665 , and a conductive layer 685 and a conductive layer 686 .

[0391] The photoelectric conversion device 101 is a pn junction type photodiode, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Here, an example is shown in which a pn junction type photodiode is formed on a silicon substrate. The photoelectric conversion device 101 is a buried type photodiode, and a thin p-type region (part of layer 565b) provided on the surface side (current extraction side) of layer 565a can suppress dark current and reduce noise.

[0392] The insulating layer 661, the conductive layer 685, and the conductive layer 686 function as bonding layers. The insulating layer 662 functions as an interlayer insulating film and a planarizing film. The insulating layer 664 functions as an element isolation layer.

[0393] The silicon substrate is provided with grooves for separating pixels, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the grooves. By providing the insulating layer 665, it is possible to prevent carriers generated in the photoelectric conversion device 101 from flowing out to adjacent pixels. The insulating layer 665 also has a function of preventing the intrusion of stray light. Therefore, the insulating layer 665 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0394] The insulating layer 664 can be formed by using a LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed by using a STI (Shallow Trench Isolation) method or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide resin or acrylic resin can be used as the insulating layer 665. The insulating layer 665 may have a multi-layer structure. A space may be provided in a part of the insulating layer 665. The space may contain air or a gas such as an inert gas. The space may be in a reduced pressure state.

[0395] A layer 565a (n-type region, corresponding to a cathode) of the photoelectric conversion device 101 is electrically connected to a conductive layer 685. A layer 565b (p-type region, corresponding to an anode) is electrically connected to a conductive layer 686. The conductive layers 685 and 686 have regions embedded in an insulating layer 661. The surfaces of the insulating layer 661, the conductive layers 685 and 686 are flattened so that they are at the same height.

[0396] In the layer 563a, an insulating layer 638 is formed over the insulating layer 637. In addition, a conductive layer 683 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0397] The insulating layer 638, the conductive layer 683, and the conductive layer 684 function as bonding layers. The conductive layer 683 and the conductive layer 684 have a region buried in the insulating layer 638. The surfaces of the insulating layer 638, the conductive layer 683, and the conductive layer 684 are flattened so that they are all at the same height.

[0398] Here, the conductive layer 683, the conductive layer 684, the conductive layer 685, and the conductive layer 686 are the same bonding layers as the above-mentioned conductive layer 619 and the conductive layer 639. The insulating layer 638 and the insulating layer 661 are the same bonding layers as the above-mentioned insulating layer 618 and the insulating layer 631.

[0399] Therefore, by bonding the conductive layer 683 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 684 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 to the wiring 114 (see FIG. 4). Also, by bonding the insulating layer 638 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 563a.

[0400] 22 shows a modified example different from the above, in which the transistor 102 is provided in the layer 561. In this configuration, one of the source and the drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source and the drain acts as a node FD. In this configuration, the charge accumulated in the photoelectric conversion device 101 can be completely transferred, and an imaging device with low noise can be obtained. The insulating layer 663 functions as a protective film for the transistor 102.

[0401] Here, the other of the source and the drain of the transistor 102 in the layer 561 is electrically connected to the conductive layer 692. One of the source and the drain of the transistor 103 in the layer 563a is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are the same bonding layers as the conductive layers 619 and 639 described above.

[0402] <Laminated structure 2> 23 is an example of a cross-sectional view of a stack including layers 560, 561, 562, and 563 and no bonding surface. A Si transistor is provided in layer 563. An OS transistor is provided in layer 562. Note that the configurations of layers 563, 561, and 560 are the same as those shown in FIG. 19, and therefore description thereof will be omitted here.

[0403] <layer 562> The layer 562 is formed over the layer 563. The layer 562 includes OS transistors. Here, the transistors 102 and 103 are shown. In the cross-sectional view shown in FIG. 23, electrical connection between the two is not shown.

[0404] The layer 562 includes an insulating layer 621, an insulating layer 622, an insulating layer 623, an insulating layer 624, an insulating layer 625, an insulating layer 626, and an insulating layer 628. In addition, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 114 (see FIG. 4).

[0405] The insulating layer 621 functions as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 function as an interlayer insulating film and a planarizing film. The insulating layer 624 functions as a protective film.

[0406] It is preferable to use a film having a function of preventing hydrogen diffusion as the blocking layer. In a Si device, hydrogen is required to terminate dangling bonds, but hydrogen near an OS transistor is one of the factors that generate carriers in an oxide semiconductor layer and reduces reliability. Therefore, it is preferable to provide a hydrogen blocking film between a layer in which a Si device is formed and a layer in which an OS transistor is formed.

[0407] For example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like can be used as the blocking film.

[0408] The other of the source and the drain of the transistor 103 is electrically connected to the gate of the transistor 105 through a plug. In addition, the conductive layer 627 is electrically connected to the wiring 114 (see FIG. 4).

[0409] One of the source and the drain of the transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in the layer 561. The conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in the layer 561.

[0410] Fig. 24A shows details of an OS transistor. The OS transistor shown in Fig. 24A has a self-aligned structure in which an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer, and a source electrode 705 and a drain electrode 706 are formed by providing openings that reach the oxide semiconductor layer.

[0411] The OS transistor can have a structure including a channel formation region 708, a source region 703, and a drain region 704 formed in the oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0412] As shown in FIG. 24B, the OS transistor may have a self-aligned structure in which a source region 703 and a drain region 704 are formed in a semiconductor layer using a gate electrode 701 as a mask.

[0413] Alternatively, as shown in FIG. 24C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0414] Although the OS transistor has a back gate 735, it may have a structure without a back gate. The back gate 735 may be electrically connected to the front gate of the transistor provided opposite to the back gate, as shown in the cross-sectional view of the transistor in the channel width direction in Fig. 24D. Note that Fig. 24D shows the cross section of the transistor taken along line B1-B2 in Fig. 24A as an example, but the same applies to transistors of other structures. In addition, a fixed potential different from that of the front gate may be supplied to the back gate 735.

[0415] <Modification of Laminate Structure 2> FIG. 25 shows a modified example of the stacked structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 included in the layer 561 and a portion of the configuration of the layer 562 are different, and a bonding surface is provided between the layers 561 and 562.

[0416] The photoelectric conversion device 101 included in the layer 561 is a pn junction type photodiode, and has the same configuration as that shown in FIG.

[0417] In the layer 562, an insulating layer 648 is formed over the insulating layer 628. In addition, a conductive layer 688 electrically connected to one of the source and the drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0418] The insulating layer 648, the conductive layer 688, and the conductive layer 689 function as bonding layers. The conductive layers 688 and 689 have a region buried in the insulating layer 648. The surfaces of the insulating layer 648 and the conductive layers 683 and 684 are flattened so that they are at the same height.

[0419] Here, the conductive layers 688 and 689 are the same lamination layers as the previously described conductive layers 619 and 639. The insulating layer 648 is the same lamination layer as the previously described insulating layers 618 and 631.

[0420] Therefore, by bonding the conductive layer 688 and the conductive layer 685 together, it is possible to electrically connect the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device to one of the source or drain of the transistor 102. Also, by bonding the conductive layer 689 and the conductive layer 686 together, it is possible to electrically connect the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device to the wiring 114 (see FIG. 4). Also, by bonding the insulating layer 648 and the insulating layer 661 together, it is possible to electrically and mechanically bond the layer 561 to the layer 562a.

[0421] When stacking multiple Si devices, polishing and bonding processes are required multiple times. This poses issues such as a large number of steps, the need for dedicated equipment, low yields, and high manufacturing costs. OS transistors can be formed by stacking on a semiconductor substrate on which devices are already formed, eliminating the need for bonding processes.

[0422] In this structure, a transistor 102 may be provided in the layer 561 as shown in FIG.

[0423] <Package, module> Fig. 27A1 is a perspective view showing the appearance of the upper surface of a package containing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450 (see Fig. 27A3), a cover glass 420, and an adhesive 430 for bonding the two together.

[0424] 27A2 is a perspective view of the exterior of the bottom surface of the package. The bottom surface of the package has a BGA (Ball grid array) with solder balls as bumps 440. Note that the package is not limited to a BGA, and may have an LGA (Land grid array) or a PGA (Pin Grid Array), etc.

[0425] 27A3 is a perspective view of the package with a portion of the cover glass 420 and the adhesive 430 omitted. Electrode pads 460 are formed on the package substrate 410, and the electrode pads 460 and the bumps 440 are electrically connected via through holes. The electrode pads 460 are electrically connected to the image sensor chip 450 by wires 470.

[0426] Fig. 27B1 is an external perspective view of the upper surface side of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module has a package substrate 411 for fixing an image sensor chip 451 (see Fig. 27B3), a lens cover 421, a lens 435, and the like. In addition, an IC chip 490 (see Fig. 27B3) having functions such as a drive circuit and a signal conversion circuit of an imaging device is also provided between the package substrate 411 and the image sensor chip 451, and the camera module has a configuration as a SiP (System in Package).

[0427] 27B2 is a perspective view of the appearance of the bottom surface side of the camera module. The bottom surface and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) configuration with lands 441 for mounting. Note that this configuration is one example, and a QFP (Quad flat package) or the above-mentioned BGA may also be provided.

[0428] 27B3 is a perspective view of the module in which a portion of lens cover 421 and lens 435 is omitted. Land 441 is electrically connected to electrode pad 461, and electrode pad 461 is electrically connected to image sensor chip 451 or IC chip 490 by wire 471.

[0429] By housing the image sensor chip in a package of the above-mentioned type, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0430] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes.

[0431] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in Figures 28A to 28F.

[0432] 28A shows an example of a portable information terminal, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The portable information terminal includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger, a stylus, or the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable information terminal.

[0433] The camera 987 has an imaging device according to one embodiment of the present invention, and can acquire distance information of a subject from an image acquired by the camera 987. A part of the image acquired by the camera 987 can be processed based on the distance information. For example, image processing can be performed to blur the front and rear of the main subject.

[0434] 28B shows an information terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919, and the characters can be output as voice through the speaker 913. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to the portable data terminal.

[0435] 28C shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and the like, and can capture images of the entire surroundings by installing it on a ceiling. The imaging device and its operating method according to one embodiment of the present invention can be applied to the elements for acquiring images in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the use. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0436] 28D shows a video camera, which has a first housing 971, a second housing 972, a display unit 973, operation keys 974, a lens 975, a connection unit 976, a speaker 977, a microphone 978, and the like. The operation keys 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. An imaging device and an operation method thereof according to one embodiment of the present invention can be applied to the video camera.

[0437] 28E shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this digital camera.

[0438] 28F shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera 939, and the like. The display unit 932 includes a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and have excellent wearability on the body. The imaging device and the operating method thereof according to one embodiment of the present invention can be applied to this information terminal.

[0439] FIG. 29A illustrates an external view of an automobile as an example of a moving object. The automobile 890 has a plurality of cameras 891 and the like, and can acquire information on the front, rear, left, right, and above the automobile 890. The imaging device and the operation method thereof according to one embodiment of the present invention can be applied to the camera 891. The automobile 890 also includes various sensors (not shown) such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 890 can analyze images acquired by the camera 891 in a plurality of imaging directions 892, determine surrounding traffic conditions such as the presence or absence of guardrails and pedestrians, and perform automatic driving. The automobile 890 can also be used in a system that performs road guidance, hazard prediction, and the like.

[0440] In the imaging device of one embodiment of the present invention, the obtained image data can be subjected to arithmetic processing such as a neural network, thereby enabling processes such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reducing reflected glare.

[0441] In the above, an automobile is described as an example of a moving body, but the automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen automobile, and the like. In addition, the moving body is not limited to an automobile. For example, the moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), and the like. A computer according to one embodiment of the present invention may be applied to these moving bodies to provide a system using artificial intelligence.

[0442] This embodiment mode can be appropriately combined with the descriptions of other embodiment modes. [Explanation of symbols]

[0443] FL11: first filter, FL12: third filter, FL13: fifth filter, FL21: second filter, FL22: fourth filter, FL23: sixth filter, 100: pixel, 101: photoelectric conversion device, 102: transistor, 102a: transistor, 102b: transistor, 103: transistor, 103a: transistor, 103b: transistor, 104: capacitor, 104a: capacitor, 104b: capacitor, 105: transistor, 105a: transistor, 105b: transistor, 106: transistor, 10 6a: transistor, 106b: transistor, 108: transistor, 111a: wiring, 111a_1: wiring, 111a_2: wiring, 111a_3: wiring, 111b: wiring, 111b_1: wiring, 111b_2: wiring, 111b_3: wiring, 112a: wiring, 112a_1: wiring, 112a_2: wiring, 112a_3: wiring, 112b: wiring, 112b_1: wiring, 112b_2: wiring, 112b_3: wiring, 113: wiring, 114: wiring, 115a: wiring, 115b: wiring, 116a: wiring, 116b: wiring, 117a: wiring, 117b: wiring, 11 8a: wiring, 118b: wiring, 119a: wiring, 119b: wiring, 122: wiring, 122_1: wiring, 122_2: wiring, 122_3: wiring, 130a: circuit, 130b: circuit, 161: transistor, 162: transistor, 163: capacitor, 200: pixel block, 201: circuit, 202: capacitor, 203: transistor, 204: transistor, 205: transistor, 206: transistor, 207: transistor, 212: wiring, 213: wiring, 213A: wiring, 213B: wiring, 215: wiring, 216: wiring, 217: wiring, 218 : Wiring, 219: Wiring, 300: Pixel array, 301: Circuit, 302: Circuit, 303: Circuit, 304: Circuit, 305: Circuit, 311: Wiring, 320: Memory cell, 325: Reference memory cell, 330: Circuit, 350: Circuit, 360: Circuit, 370: Circuit, 410: Package substrate, 411: Package substrate, 420: Cover glass, 421: Lens cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image sensor chip, 451: Image sensor chip, 460: Electrode pad, 461: Electrode pad, 470: Wire,471: wire, 490: IC chip, 545: semiconductor layer, 546: insulating layer, 560: layer, 561: layer, 562: layer, 562a: layer, 562b: layer, 563: layer, 563a: layer, 563b: layer, 563c: layer, 565a: layer, 565b: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 611: silicon substrate, 612: insulating layer, 613: insulating layer, 614: insulating layer, 616: insulating layer, 617: insulating layer, 618: insulating layer, 619: conductive layer, 621: insulating layer, 622 : insulating layer, 623: insulating layer, 624: insulating layer, 625: insulating layer, 626: insulating layer, 627: conductive layer, 628: insulating layer, 631: insulating layer, 632: silicon substrate, 633: insulating layer, 634: insulating layer, 635: insulating layer, 636: conductive layer, 637: insulating layer, 638: insulating layer, 639: conductive layer, 648: insulating layer, 651: insulating layer, 652: insulating layer, 653: insulating layer, 654: insulating layer, 655: conductive layer, 661: insulating layer, 662: insulating layer, 663: insulating layer, 664: insulating layer, 665: insulating layer, 671: light shielding layer, 672: optical conversion layer, 672B: color filter, 672 G: color filter, 672IR: infrared filter, 672R: color filter, 672UV: ultraviolet filter, 673: microlens array, 683: conductive layer, 684: conductive layer, 685: conductive layer, 686: conductive layer, 688: conductive layer, 689: conductive layer, 691: conductive layer, 692: conductive layer, 701: gate electrode, 702: gate insulating film, 703: source region, 704: drain region, 705: source electrode, 706: drain electrode, 707: oxide semiconductor layer, 708: channel formation region, 735: back gate, 890: automobile, 891: camera, 892: camera Image direction, 911: housing, 912: display unit, 913: speaker, 919: camera, 932: display unit, 933: housing / wristband, 939: camera, 951: support stand, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation keys, 975: lens, 976: connection unit, 977: speaker, 978: microphone, 981: housing, 982: display unit, 983: operation button, 984: external connection port, 985: speaker,986: Microphone, 987: Camera,

Claims

[Claim 1] A plurality of pixels are included. the pixel has a function of applying a first weight to image data acquired in an n-th frame (n is an integer equal to or greater than 2) to generate first data for the n-th frame; the pixel has a function of applying a second weight to image data acquired in an (n-1)th frame to generate first data in the (n-1)th frame; The pixel has a function of generating second data by adding the first data of the (n-1)th frame and the first data of the nth frame.

Images