Signal transmission device, electronic device, and vehicle

Abstract

To reduce noise in signals transmitted between the primary and secondary circuit systems.SOLUTION: A signal generating circuit (411x) includes a switch output stage (412) and current limiting circuits (418a, 418b). The switch output stage (412) is configured to generate a pulse signal (PS) that is pulse-driven between a first voltage and a second voltage through a switching operation. The current limiting circuits (418a, 418b) are connected between an application terminal of the first voltage and the switch output stage (412) and configured to limit a current (I2) flowing through the switch output stage (412).SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a signal transmission device, an electronic device, and a vehicle. [Background technology]

[0002] Conventionally, there is a signal transmission device that transmits a signal between a primary circuit system and a secondary circuit system while electrically insulating the primary circuit system from the secondary circuit system. Such a signal transmission device is used in various applications (such as a power supply device or a motor drive device).

[0003] As an example of the related art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944

[0005] [overview] The semiconductor device corresponding to the primary circuit system of the signal transmission device disclosed in Patent Document 1 leaves room for further consideration regarding noise in the signal transmitted between the primary circuit system and the secondary circuit system.

[0006] The signal generating circuit disclosed herein includes a switch output stage and a current limiting circuit. The switch output stage is configured to generate a pulse signal that is pulse-driven between a first voltage and a second voltage through a switching operation. The current limiting circuit is connected between an application terminal of the first voltage and the switch output stage and configured to limit a current flowing through the switch output stage.

[0007] The electronic device disclosed in this specification includes a signal transmission device having the above-described configuration.

[0008] The vehicle disclosed in this specification is equipped with an electronic device having the above-described configuration. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a basic configuration of a signal transmission device. [Diagram 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Diagram 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel type transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Diagram 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of the region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a block diagram showing a configuration of a signal transmission device 400Y of the comparative example. [Figure 11] FIG. 11 is a block diagram showing a configuration of a signal transmission device 400X according to the first embodiment of the present disclosure. [Figure 12] FIG. 12 is a block diagram showing a configuration of a signal transmission device 400X according to the second embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram showing the external appearance of the vehicle.

[0010] [Detailed Description] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while isolating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0011] The controller chip 210 is a semiconductor chip that operates by receiving a supply of a power supply voltage VCC1 (for example, a maximum of 7 V with respect to GND1). In the controller chip 210, for example, a pulse transmission circuit 211 and buffers 212 and 213 are integrated.

[0012] The pulse transmitting circuit 211 is a pulse generator that generates the transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputs a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either one of the transmission pulse signals S11 and S21 in response to the logical level of the input pulse signal IN.

[0013] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0014] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0015] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (for example, a maximum of 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0016] The buffer 221 shapes the waveform of the reception pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse reception circuit 223.

[0017] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0018] The pulse receiving circuit 223 generates an output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so as to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. That is, the pulse receiving circuit 223 switches the logical level of the output pulse signal OUT in response to the logical level of the input pulse signal IN. Note that, for example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0019] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0020] The transformer chip 230 uses transformers 231 and 232 to provide DC insulation between the controller chip 210 and the driver chip 220, and outputs the transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 to the pulse reception circuit 223 as reception pulse signals S12 and S22, respectively. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0021] More specifically, the transformer 231 outputs a receiving pulse signal S12 from the secondary coil 231s in response to a transmitting pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a receiving pulse signal S22 from the secondary coil 232s in response to a transmitting pulse signal S21 input to the primary coil 232p.

[0022] As described above, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to a rise signal and a fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0023] Incidentally, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0024] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), making it possible to reduce manufacturing costs.

[0025] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or xEVs such as FCEVs / FCVs (fuel cell electric vehicle / fuel cell vehicle)).

[0026] <Trans chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of the transformer chip 230. In the transformer chip 230 of this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that face each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that face each other in the vertical direction.

[0027] Both the primary coils 231p and 232p are formed in a first wiring layer (lower layer) 230a of the transformer chip 230. Both the secondary coils 231s and 232s are formed in a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0028] The primary coil 231p is laid in a spiral shape starting from a first end connected to the internal terminal X21 so as to surround the periphery of the internal terminal X21 in a clockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral shape starting from a first end connected to the internal terminal X23 so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and a second end corresponding to the end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0029] The internal terminal X21 is connected to the external terminal T21 of the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 of the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 of the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged in a straight line and are used for wire bonding with the controller chip 210.

[0030] The secondary coil 231s is laid in a spiral shape so as to surround the external terminal T24 in a counterclockwise direction, starting from a first end connected to the external terminal T24, and a second end corresponding to the end point is connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral shape so as to surround the external terminal T26 in a clockwise direction, starting from a first end connected to the external terminal T26, and a second end corresponding to the end point is connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the illustrated order, and are used for wire bonding with the driver chip 220.

[0031] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0032] <Trans chip (2 channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low potential coil 22 (corresponding to a primary coil of a transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high potential coil 23 (corresponding to a secondary coil of a transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0033] 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide band gap semiconductor, and a compound semiconductor.

[0034] The wide band gap semiconductor is made of a semiconductor whose band gap exceeds that of silicon (about 1.12 eV). The band gap of the wide band gap semiconductor is preferably 2.0 eV or more. The wide band gap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride) and GaAs (gallium arsenide).

[0035] In this embodiment, the semiconductor chip 41 includes a semiconductor substrate made of silicon. The semiconductor chip 41 may be an epitaxial substrate having a layered structure including a semiconductor substrate made of silicon and an epitaxial layer made of silicon. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0036] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0037] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0038] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface in a plan view. The insulating main surface 52 extends parallel to the first main surface .

[0039] The insulating side walls 53A-53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A-44D. Specifically, the insulating side walls 53A-53D are formed flush with the chip side walls 44A-44D. The insulating side walls 53A-53D form ground surfaces flush with the chip side walls 44A-44D.

[0040] The insulating layer 51 has a multi-layer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 layers in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0041] Each of the interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the lowermost insulating layer 55 side and a second insulating layer 59 on the uppermost insulating layer 56 side. The first insulating layer 58 may include silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0042] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0043] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of layers of the interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be realized. In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0044] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformer). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0045] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side to the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. In the following, the structure of the first transformer 21A will be described as an example. The structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D are omitted because the description of the structure of the first transformer 21A applies mutatis mutandis.

[0046] 5 to 7, the first transformer 21A includes a low potential coil 22 and a high potential coil 23. The low potential coil 22 is formed in an insulating layer 51. The high potential coil 23 is formed in the insulating layer 51 so as to face the low potential coil 22 in the normal direction Z. In this embodiment, the low potential coil 22 and the high potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0047] The low potential coil 22 is formed on the lowermost insulating layer 55 (semiconductor chip 41) side within the insulating layer 51, and the high potential coil 23 is formed on the uppermost insulating layer 56 (insulating main surface 52) side of the low potential coil 22 within the insulating layer 51. In other words, the high potential coil 23 faces the semiconductor chip 41 with the low potential coil 22 in between. The low potential coil 22 and the high potential coil 23 may be disposed in any position. Furthermore, it is sufficient that the high potential coil 23 faces the low potential coil 22 with one or more interlayer insulating layers 57 in between.

[0048] The distance between the low potential coil 22 and the high potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is appropriately adjusted according to the dielectric strength and electric field strength between the low potential coil 22 and the high potential coil 23. In this embodiment, the low potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0049] The low potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. A portion forming the innermost periphery of the first spiral portion 26 defines a first inner region 66 having an elliptical shape in a plan view.

[0050] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0051] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0052] The low potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low potential coil 22 may have a laminated structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0053] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape extending in an elliptical shape (oval shape) in a plan view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 having an elliptical shape in a plan view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0054] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical portion 29 exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26, or may be equal to the number of turns of the first helical portion 26.

[0055] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0056] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0057] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or in a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0058] The high potential coil 23 is preferably formed of the same conductive material as the low potential coil 22. That is, like the low potential coil 22, the high potential coil 23 preferably includes a barrier layer and a body layer.

[0059] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0060] The low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the low potential terminals 11 are formed in a region on the insulating sidewall 53B side at intervals in the second direction Y from the transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0061] The low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E and a sixth low potential terminal 11F. In this embodiment, two of each of the low potential terminals 11A to 11F are formed. The number of the low potential terminals 11A to 11F is arbitrary.

[0062] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in a plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in a plan view.

[0063] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0064] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0065] The multiple high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the multiple low potential terminals 11. Specifically, the multiple high potential terminals 12 are formed in a region on the insulating sidewall 53A side at intervals from the multiple low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0066] The multiple high potential terminals 12 are formed in areas close to the corresponding transformers 21A to 21D in a plan view. The closeness of the high potential terminals 12 to the transformers 21A to 21D means that the distance between the high potential terminals 12 and the transformers 21 in a plan view is less than the distance between the low potential terminals 11 and the high potential terminals 12.

[0067] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A-21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A-21D in the first direction X in a plan view.

[0068] The multiple high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the multiple high potential terminals 12A to 12F are formed. The number of the multiple high potential terminals 12A to 12F is arbitrary.

[0069] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in a region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in a region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0070] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0071] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0072] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0073] The first low potential wiring 31 and the second low potential wiring 32 fix the low potential coil 22 of the first transformer 21A and the low potential coil 22 of the second transformer 21B to the same potential. The first low potential wiring 31 and the second low potential wiring 32 also fix the low potential coil 22 of the third transformer 21C and the low potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low potential wiring 31 and the second low potential wiring 32 fix all the low potential coils 22 of the transformers 21A to 21D to the same potential.

[0074] The first high potential wiring 33 and the second high potential wiring 34 fix the high potential coil 23 of the first transformer 21A and the high potential coil 23 of the second transformer 21B to the same potential. The first high potential wiring 33 and the second high potential wiring 34 also fix the high potential coil 23 of the third transformer 21C and the high potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high potential wiring 33 and the second high potential wiring 34 fix all the high potential coils 23 of the transformers 21A to 21D to the same potential.

[0075] The multiple first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The multiple first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The structure of the other first low potential wirings 31 will be omitted, as the description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis.

[0076] The first low potential wiring 31 includes a through wiring 71, a low potential connection wiring 72, a pull-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0077] The through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low potential coil 22, etc. In other words, the through wiring 71, the low potential connection wiring 72, the lead-out wiring 73, the first connection plug electrode 74, the second connection plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0078] The through wiring 71 penetrates the interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape extending along the normal direction Z. In this embodiment, the through wiring 71 is formed in a region between the lowermost insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low potential coil 22.

[0079] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 are each formed of the same conductive material as the low potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrode 80 each include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0080] The first electrode layer 78 forms an upper end of the through wiring 71. The second electrode layer 79 forms a lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0081] The multiple wiring plug electrodes 80 are embedded in the multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be electrically connected to each other, and electrically connect the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 each have a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0082] The number of layers of the multiple wiring plug electrodes 80 coincides with the number of layers of the multiple interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 penetrating the multiple interlayer insulating layers 57 may be formed.

[0083] The low potential connecting wire 72 is formed in the first inner region 66 of the first transformer 21A (low potential coil 22) in the same interlayer insulating layer 57 as the low potential coil 22. The low potential connecting wire 72 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. It is preferable that the low potential connecting wire 72 has a planar area larger than the planar area of ​​the wiring plug electrode 80. The low potential connecting wire 72 is electrically connected to the first inner end 24 of the low potential coil 22.

[0084] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the lowermost insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in a region between the semiconductor chip 41 and the low potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0085] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0086] The multiple pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The multiple substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0087] 6 and 7, the first high potential wirings 33 are electrically connected to the corresponding high potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high potential coils 23). The first high potential wirings 33 each have a similar structure. In the following, the structure of the first high potential wiring 33 connected to the first high potential terminal 12A and the first transformer 21A will be described as an example. The structure of the other first high potential wirings 33 will be omitted, since the description of the structure of the first high potential wiring 33 connected to the first transformer 21A applies mutatis mutandis.

[0088] The first high potential wiring 33 includes a high potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high potential connection wiring 81 and the pad plug electrode 82 are preferably formed of the same conductive material as the low potential coil 22, etc. In other words, the high potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0089] The high potential connection wiring 81 is formed in the second inner region 67 of the high potential coil 23 in the same interlayer insulating layer 57 as the high potential coil 23. The high potential connection wiring 81 is formed in an island shape and faces the high potential terminal 12 (first high potential terminal 12A) in the normal direction Z. The high potential connection wiring 81 is electrically connected to the second inner end 27 of the high potential coil 23. The high potential connection wiring 81 is formed at a distance from the low potential connection wiring 72 in a plan view and does not face the low potential connection wiring 72 in the normal direction Z. This increases the insulation distance between the low potential connection wiring 72 and the high potential connection wiring 81, and increases the dielectric strength voltage of the insulating layer 51.

[0090] The multiple pad plug electrodes 82 are formed in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81 in the uppermost insulating layer 56, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. Each of the multiple pad plug electrodes 82 has a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0091] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0092] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0093] The dummy pattern 85 is formed in a pattern different from that of the high-potential coil 23 and the low-potential coil 22 (a discontinuous pattern) and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high-potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high-potential coil 23.

[0094] The depth position of the dummy pattern 85 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high potential coil 23 than the low potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low potential coil 22.

[0095] In this case, electric field concentration on the high potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high potential coil 23 in the normal direction Z, the more the electric field concentration on the high potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high potential coil 23. In this case, electric field concentration on the high potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes a plurality of dummy patterns having different electrical states. The dummy pattern 85 may include a high potential dummy pattern.

[0096] The depth position of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0097] Dummy pattern 85 includes a floating dummy pattern formed in an electrically floating state within insulating layer 51 so as to be located around transformers 21A to 21D.

[0098] In this embodiment, the floating dummy pattern is laid out in a dense line shape so as to partially cover and partially expose the area around the high potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0099] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0100] The number of floating lines is arbitrary and is adjusted according to the electric field to be relaxed. The floating dummy pattern may be composed of a plurality of floating lines.

[0101] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed by utilizing a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is shown in a simplified manner by a dashed line drawn on the surface layer portion of the first main surface 42.

[0102] The second functional device 60 is electrically connected to the low potential terminal 11 via a low potential wiring, and is electrically connected to the high potential terminal 12 via a high potential wiring. The low potential wiring has a similar structure to the first low potential wiring 31 (second low potential wiring 32) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high potential wiring has a similar structure to the first high potential wiring 33 (second high potential wiring 34) except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A specific description of the low potential wiring and high potential wiring related to the second functional device 60 will be omitted.

[0103] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more of the passive devices, the semiconductor rectifier device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0104] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifier device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0105] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape spaced apart from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0106] The device region 62 is a region including the first functional device 45 (multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. The outer region 63 is a region outside the device region 62.

[0107] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (the multiple transformers 21), the second functional device 60, the multiple low potential terminals 11, the multiple high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path connected to the device region 62.

[0108] The seal conductor 61 is formed in a band shape along the insulating side walls 53 to 53D in a plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in a plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in a plan view.

[0109] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending between the upper end and the lower end in a wall shape. In this embodiment, the upper end of the seal conductor 61 is formed on the semiconductor chip 41 side with a gap therebetween from the insulating principal surface 52, and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed on the upper end side with a gap therebetween from the semiconductor chip 41.

[0110] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the multiple low potential terminals 11 and the multiple high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (multiple transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0111] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or a plurality (a plurality in this embodiment) of seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed of the same conductive material as the low potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low potential coil 22, etc.

[0112] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 toward the uppermost insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 matches the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0113] As long as one annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless shape (annular shape).

[0114] The multiple seal via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the seal plug conductor 64. The multiple seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or greater than the planar area of ​​the seal plug conductor 64.

[0115] The width of the sealing conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the sealing conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction perpendicular to the direction in which the sealing conductor 61 extends.

[0116] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0117] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0118] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a band shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion in which the lower end portion (seal via conductor 65) of the seal conductor 61 is embedded toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0119] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body portion 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0120] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 with a gap therebetween from the chip sidewalls 44A to 44D.

[0121] The main body portion 130C has a flat surface extending approximately parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body portion 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 may take various forms in addition to the field insulating film 131.

[0122] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0123] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may include silicon oxide. The first inorganic insulating layer 141 preferably includes USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may include silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high potential coil 23 can be increased.

[0124] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of the USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0125] The first inorganic insulating layer 141 may contain at least one of BPSG (boron doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0126] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral portion of the low potential terminal 11. The inorganic insulating layer 140 may have an overlapping portion that rides up onto the peripheral portion of the high potential terminal 12.

[0127] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0128] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low potential coil 22 and the high potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. According to these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high potential coil 23.

[0129] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0130] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high potential terminal openings 149 that expose the plurality of high potential terminals 12 (high potential pad openings 144). The second portion 147 may have an overlap portion that rises onto the periphery (overlap portion) of the high potential pad opening 144.

[0131] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the multiple high potential coils 23, the multiple high potential terminals 12, the first high potential dummy pattern 87, the second high potential dummy pattern 88, and the floating dummy pattern 121.

[0132] The embodiment of the present invention can be embodied in further other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form having only the second functional device 60 without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0133] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the sealing conductor 61. Also, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the sealing conductor 61.

[0134] In the above embodiment, an example has been described in which the second functional device 60 is formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0135] In the above embodiment, an example has been described in which the dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required, and may be removed.

[0136] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type device including a plurality of transformers 21. However, a first functional device 45 of a single-channel type device including a single transformer 21 may be adopted.

[0137] <Transformer arrangement> 9 is a plan view (top view) showing a schematic example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the above-mentioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0138] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s forming a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s forming a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0139] Moreover, pads a3 and b3 are connected to one end of a secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0140] Note that the primary coil forming the first transformer 301, the primary coil forming the second transformer 302, the primary coil forming the third transformer 303, and the primary coil forming the fourth transformer 304 are not shown in the figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s, respectively.

[0141] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0142] Moreover, pads a7 and b7 are connected to one end of a primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Moreover, pads a8 and b8 are connected to one end of a primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0143] However, the above-mentioned pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0144] Among the above-mentioned pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0145] Therefore, the transformer chip 300 of this configuration example can accurately measure the series resistance component of each coil during the defective product inspection. Therefore, it is possible to not only reject defective products in which each coil has a break in wiring, but also to appropriately reject defective products in which each coil has an abnormal resistance value (for example, a short circuit between coils), and ultimately to prevent defective products from being released onto the market.

[0146] For the transformer chip 300 that has passed the defective product inspection, the above-mentioned multiple pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0147] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0148] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0149] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner of being coupled for each signal transmission direction, as shown in Fig. 9. In accordance with this figure, for example, the first transformer 301 and the second transformer 302 which transmit signals from the primary side chip to the secondary side chip are made into a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 which transmit signals from the secondary side chip to the primary side chip are made into a second pair by a second guard ring 306.

[0150] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil forming each of the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0151] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0152] In the transformer chip 300, the pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. The pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. The pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. The pads c4 and d4 are shared between the corresponding primary coils. With this configuration, the number of pads can be reduced, and the transformer chip 300 can be made smaller.

[0153] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are desirably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. With this configuration, the area of ​​the overlapping portion between the primary coil and the secondary coil becomes larger, and the transmission efficiency of the transformer can be improved.

[0154] Of course, the transformer arrangement in this figure is merely one example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. In addition, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general in which coils are integrated on a semiconductor chip.

[0155] Incidentally, the above-mentioned primary circuit system (corresponding to the above-mentioned controller chip 210) operates on a power supply voltage (corresponding to the above-mentioned power supply voltage VCC1). That is, the primary circuit system generates a pulse signal based on the power supply voltage.

[0156] The configuration of such a signal transmission device will be described in detail below. First, the signal transmission device 400Y will be described as a comparative example of the signal transmission device 400X of the present disclosure. Next, problems of the comparative example will be described, and then the signal transmission device 400X of the present disclosure will be described.

[0157] <Regarding the signal transmission device 400Y of the comparative example> 10 is a block diagram showing a configuration of a signal transmission device 400Y of a comparative example. The signal transmission device 400Y may be mounted in an electronic device Ay together with a microcomputer, a load, and the like. The signal transmission device 400Y includes a first chip 410y, a second chip 420, and a third chip 430. The first chip 410y, the second chip 420, and the third chip 430 may be sealed in a single package.

[0158] Like the signal transmission device 200 (FIG. 1) described above, the signal transmission device 400Y may be a semiconductor integrated circuit device (a so-called insulated gate driver IC) that generates a pulse signal according to an input pulse signal while isolating input from output, to drive a switch element.

[0159] In this case, the first chip 410y corresponds to the previously mentioned controller chip 210. The second chip 420 corresponds to the previously mentioned driver chip 220. The third chip 430 corresponds to the previously mentioned transformer chip 230.

[0160] The first chip 410y includes an input terminal ts, a power terminal tv, a ground terminal tg, and a transmission circuit 411y. The input terminal ts, the power terminal tv, and the ground terminal tg are means for establishing an electrical connection between the signal transmission device 400Y and the outside of the device. The input terminal ts receives an input signal IN as an external input. The power terminal tv receives a power supply voltage VCC (corresponding to the above-mentioned VCC1). The ground terminal tg receives a ground voltage GND.

[0161] The transmission circuit 411y is integrated on a first chip 410y. The transmission circuit 411y includes a switch output stage 412, a driver circuit 416, and a driver control circuit 417.

[0162] The switch output stage 412 includes a high-side transistor 413, a low-side transistor 414, and a capacitor C1. The high-side transistor 413 is a P-channel type MOSFET [P-channel type Metal Oxide Semiconductor Field Effect Transistor]. The low-side transistor 414 is an N-channel type MOSFET [N-channel type Metal Oxide Semiconductor Field Effect Transistor].

[0163] The switch output stage 412 generates a rectangular wave pulse signal PS that is pulse-driven between a power supply voltage VCC (first voltage) and a ground voltage GND (second voltage) by complementarily turning on / off the high-side transistor 413 and the low-side transistor 414.

[0164] In this specification, the term "complementary" is used to mean not only the case where the on / off states of the high-side transistor 413 and the low-side transistor 414 are completely reversed, but also the case where a delay is provided in the timing of each on / off transition (i.e., a simultaneous off period is provided).

[0165] A source terminal of the high-side transistor 413 is connected to a power supply terminal tv. A gate terminal of the high-side transistor 413 is connected to an application terminal of the driver circuit 416 (more specifically, an output terminal of a high-side driver HD described later). A drain terminal of the high-side transistor 413 is connected to a drain terminal of the low-side transistor 414.

[0166] A gate signal G1 is input to the gate of the high-side transistor 413. The high-side transistor 413 is turned on when the gate signal G1 is at a low level (ground voltage GND level) and is turned off when the gate signal G1 is at a high level (power supply voltage level VCC).

[0167] A source terminal of the low-side transistor 414 is connected to a ground terminal tg. A gate terminal of the low-side transistor 414 is connected to an application terminal of the driver circuit 416 (more specifically, an output terminal of a low-side driver LD described later).

[0168] A gate signal G2 is input to the gate of the low-side transistor 414. The low-side transistor 414 is turned on when the gate signal G2 is at a high level (power supply voltage VCC level) and is turned off when the gate signal G2 is at a low level (ground voltage GND level).

[0169] When the high-side transistor 413 is on, a current I1 flows from the power supply terminal tv to the high-side transistor 413. At this time, a current I2 flows from a connection node n1 between the drain terminal of the high-side transistor 413 and the drain terminal of the low-side transistor 414 toward the insulating element 431. The current value of the current I2 is approximately equal to the power supply voltage VCC divided by the on-resistance of the high-side transistor 413.

[0170] A first terminal of the capacitor C1 is connected to the power supply terminal tv together with the source of the high-side transistor 413. A second terminal of the capacitor C1 is connected to the source terminal of the low-side transistor 414 together with the ground terminal tg.

[0171] The driver circuit 416 includes a high-side driver HD and a low-side driver LD.

[0172] The high-side driver HD generates a gate signal G1 according to a driver control signal S1, which will be described later, and inputs it to the gate of the high-side transistor 413. When the driver control signal S1 is at a high level, the high-side driver HD outputs a gate signal G1 at a high level (power supply voltage VCC level). When the driver control signal S1 is at a low level, the high-side driver HD outputs a gate signal G1 at a low level (ground voltage GND level).

[0173] The low-side driver LD generates a gate signal G2 according to a driver control signal S2, which will be described later, and inputs it to the gate terminal of the low-side transistor 414. When the driver control signal S2 is at a high level, the low-side driver LD outputs a gate signal G2 at a high level (power supply voltage VCC level). When the driver control signal S2 is at a low level, the low-side driver LD outputs a gate signal G2 at a low level (ground voltage GND level).

[0174] The driver control circuit 417 controls the high-side driver HD and the low-side driver LD. Specifically, the driver control circuit 417 generates driver control signals S1 and S2 according to the input signal IN. The driver control circuit 417 inputs the driver control signal S1 to the high-side driver HD. The driver control circuit 417 inputs the driver control signal S2 to the low-side driver LD.

[0175] The receiving circuit 421 is integrated in the second chip 420. The receiving circuit 421 performs a predetermined internal control in response to the pulse signal PS transmitted from the transmitting circuit 411y via the insulating element 431. As an example of the predetermined internal control, the receiving circuit 421 sets an operating parameter of the second chip 420.

[0176] The isolation element 431 is integrated in the third chip 430. The isolation element 431 transmits a pulse signal PS between the transmission circuit 411y and the reception circuit 421 while isolating them from each other. The isolation element 431 may be a transformer or a capacitor.

[0177] <Considerations about noise> In the above-described signal transmission device 400Y, the power supply voltage VCC is directly connected to the switch output stage 412. That is, the resistance between the application end of the power supply voltage VCC (power supply terminal tv in FIG. 10) and the output end of the switch output stage 412 (connection node n1 in FIG. 10) is relatively low. For this reason, the peak current of the current I2 during the switching operation of the switch output stage 412 becomes relatively large. This may cause noise to occur in the pulse signal PS.

[0178] In response to such problems, the signal transmission device 400X of the present disclosure is capable of suppressing the generation of noise. The signal transmission device 400X according to each embodiment of the present disclosure will be described in detail below. Note that the signal transmission device 400X according to each embodiment of the present disclosure includes a configuration common to the signal transmission device 400Y described above. For this reason, the common configuration is denoted by the same reference numerals and description thereof will be omitted.

[0179] <Regarding the signal transmission device 400X according to the first embodiment of the present disclosure> 11 is a block diagram showing a configuration of a signal transmission device 400X according to a first embodiment of the present disclosure. The signal transmission device 400X according to the first embodiment may be mounted in an electronic device Ax together with a microcomputer, a load, and the like. The signal transmission device 400X includes a first chip 410x, a second chip 420, and a third chip 430. The first chip 410x, the second chip 420, and the third chip 430 may be sealed in a single package.

[0180] The signal transmission device 400X may be a semiconductor integrated circuit device (so-called insulated gate driver IC) that generates an output pulse signal according to an input pulse signal while insulating input and output, and drives a switch element, like the signal transmission device 200 (FIG. 1). In this case, the first chip 410x corresponds to the controller chip 210.

[0181] The first chip 410x includes an input terminal ts, a power supply terminal tv, a ground terminal tg, and a transmission circuit 411x (signal generation circuit). The input terminal ts, the power supply terminal tv, and the ground terminal tg serve as means for establishing electrical connection with the outside of the signal transmission device 400X.

[0182] The transmission circuit 411x is integrated into the first chip 410x. The transmission circuit 411x includes a switch output stage 412, a driver circuit 416, a driver control circuit 417, and a current limiting circuit 418a.

[0183] The current limiting circuit 418a is disposed between the power supply terminal tv and the switch output stage 412 (more specifically, the source terminal of the high-side transistor 413). The current limiting circuit 418a limits the current I2 so that it does not exceed a predetermined value. Specifically, it is as follows.

[0184] The current limiting circuit 418a includes a resistor R1. The resistor R1 has a predetermined resistance value. The first end of the resistor R1 is connected to the power supply terminal tv. The second end of the resistor R1 is connected to the source terminal of the high-side transistor 413. The current value of the current I2 is approximately equal to the value obtained by dividing the power supply voltage VCC by the sum of the resistance value of the resistor R1 and the on-resistance value of the high-side transistor 413.

[0185] As described above, in the signal transmission device 400X according to this embodiment, the resistor R1 is disposed between the high-side transistor 413 and the power supply terminal tv. As a result, the current I2 becomes relatively small according to the resistance value of the resistor R1. Then, the peak current of the current I2 becomes relatively small, and the generation of noise in the pulse signal PS can be suppressed.

[0186] Also, by adopting a configuration in which the peak current of the current I2 is made relatively small by the resistor R1 as described above, the generation of noise in the pulse signal PS can be suppressed with a relatively simple configuration.

[0187] <Regarding the signal transmission device 400X according to the second embodiment> Next, a second embodiment of the signal transmission device 400X will be described. In the following, differences from the first embodiment will be described, and configurations similar to those in the first embodiment will be denoted by the same reference numerals and description thereof will be omitted.

[0188] 12 is a block diagram showing a configuration of a signal transmission device 400X according to a second embodiment of the present disclosure. A transmission circuit 411x in the signal transmission device 400X according to the second embodiment includes a current limiting circuit 418b.

[0189] The current limiting circuit 418b is disposed between the power supply terminal tv and the switch output stage 412 (more specifically, the source terminal of the high-side transistor 413). The current limiting circuit 418b limits the current I2 so that it does not exceed a predetermined value. Specifically, it is as follows.

[0190] The current limiting circuit 418b includes a current limiting transistor 419. The current limiting transistor 419 is a P-channel MOSFET. A source terminal of the current limiting transistor 419 is connected to the power supply terminal tv. A drain terminal of the current limiting transistor 419 is connected to the switch output stage 412 (more specifically, the source terminal of the high-side transistor 413). A ground voltage GND is input to a gate terminal of the current limiting transistor 419.

[0191] When the power supply voltage VCC is applied to the source terminal of the current limiting transistor 419, the current limiting transistor 419 is turned on. The current limiting transistor 419 has a predetermined on-resistance. The current value of the current I2 is approximately equal to the power supply voltage VCC divided by the sum of the on-resistance of the current limiting transistor 419 and the on-resistance of the high-side transistor 413.

[0192] As described above, in the signal transmission device 400X according to the present embodiment, the current limiting transistor 419 is disposed between the high-side transistor 413 and the power supply terminal tv. This makes the current I2 relatively small according to the on-resistance value of the current limiting transistor 419. This makes the peak current of the current I2 relatively small, making it possible to suppress the generation of noise in the pulse signal PS.

[0193] <Application to vehicles> Fig. 13 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices (including electronic device Ax) that operate by receiving power supply from a battery (see Fig. 12).

[0194] Vehicle B includes not only engine vehicles but also electric vehicles (BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicle / plug-in hybrid vehicle), or xEVs such as FCEVs / FCVs (fuel cell electric vehicle / fuel cell vehicle)).

[0195] The signal transmission device 200 or 400X described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0196] <Modification> The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure. For example, the current limiting circuit 418a of the first embodiment can be configured to include another resistor in addition to the resistor R1. The current limiting circuit 418a can be configured to include a MOSFET similar to the current limiting transistor 419 in addition to the resistor R1. In this case, the current I2 is limited by the MOSFET and the resistor R1. The current limiting circuit 418b of the second embodiment can also be configured to include a resistor in addition to the current limiting transistor 419.

[0197] <Additional Notes> The signal generating circuit (411x) disclosed in the specification is configured to include a switch output stage (412) configured to generate a pulse signal (PS) that is pulse-driven between a first voltage and a second voltage through a switching operation, and a current limiting circuit (418a, 418b) connected between the application terminal of the first voltage and the switch output stage (412) and configured to limit a current (I2) flowing through the switch output stage (412) (first configuration).

[0198] In addition, in the signal generating circuit (411x) according to the first configuration, the current limiting circuit (418a) may be configured to include a resistor (R1) connected between the application terminal of the first voltage and the switch output stage (412) (second configuration).

[0199] In addition, in the signal generating circuit (411x) relating to the first or second configuration, the current limiting circuit (418b) includes a switch element (419) having a first terminal connected to an application terminal of a first voltage, a second terminal connected to the switch output stage (412), and a third terminal connected to an application terminal of a reference voltage, and which is turned on / off depending on the potential difference between the first terminal and the third terminal, and the reference voltage is preferably configured to be less than the first voltage (third configuration).

[0200] In addition, in the signal generating circuit (411x) according to the third configuration, the switch element (419) may be configured as a MOSFET having a first terminal as a source terminal, a second terminal as a drain terminal, and a third terminal as a gate terminal (fourth configuration).

[0201] In addition, in the signal generating circuit (411x) according to any one of the first to fourth configurations, the second voltage may be a ground voltage (GND) (fifth configuration).

[0202] The signal transmission device (400X) disclosed in the specification includes a transmitting circuit (410x), a receiving circuit (421), and an insulating element (431) configured to transmit a pulse signal (PS) between the transmitting circuit (410x) and the receiving circuit (421) while isolating them, and the transmitting circuit (410x) may be configured to include a signal generating circuit (411x) relating to any one of the first to fifth configurations (sixth configuration).

[0203] In addition, the signal transmission device (400X) of the sixth configuration further includes a first chip (410x) in which a transmitting circuit (410x) is integrated, a second chip (420) in which a receiving circuit (421) is integrated, and a third chip (430) in which an insulating element (431) is integrated, and the first chip (410x), the second chip (420), and the third chip (430) are preferably configured to be sealed in a single package (seventh configuration).

[0204] The electronic device (AX) disclosed in the specification is configured to include a signal transmission device (400X) according to the sixth or seventh configuration (eighth configuration).

[0205] The vehicle (B) disclosed in the specification is configured to include an electronic device (AX) according to the eighth configuration (ninth configuration).

[0206] The signal generating circuit (411x) according to the first configuration can prevent the current (I2) flowing through the switch output stage (412) from becoming a large current, thereby preventing noise from being generated in the pulse signal (PS).

[0207] According to the signal generating circuit (411x) of the second configuration, the current limiting circuit (418a) can be configured with a relatively simple structure, which makes it possible to suppress the occurrence of noise in the pulse signal (PS) and to suppress an increase in manufacturing costs.

[0208] The signal transmission device (400X) of the third configuration can more effectively prevent the current (I2) flowing through the switch output stage (412) from becoming a large current.

[0209] According to the signal transmission device (400X) according to the fourth configuration, it is possible to more preferably suppress the current (I2) flowing through the switch output stage (412) from becoming a large current.

[0210] According to the signal transmission device (400X) according to the fifth configuration, the switch output stage (412) can be configured to pulse-drive the pulse signal (PS) between the ground voltage (GND) and a predetermined first voltage.

[0211] According to the signal transmission device (400X) according to the sixth configuration, it is possible to provide a signal transmission device (400X) that can suppress the generation of noise in the pulse signal (PS).

[0212] According to the signal transmission device (400X) according to the seventh configuration, it is possible to provide a signal transmission device (400X) that can suppress the generation of noise in the pulse signal (PS) while miniaturizing the package.

[0213] According to the electronic device (AX) according to the eighth configuration, it is possible to provide an electronic device that can suppress the generation of noise in the pulse signal (PS).

[0214] According to the electronic device (AX) according to the ninth configuration, it is possible to provide a vehicle (B) that can suppress the generation of noise in the pulse signal.

Explanation of Reference Numerals

[0215] 5 Semiconductor device 11, 11A to 11F Low potential terminals 12, 12A to 12F High potential terminals 21, 21A to 21D Transformers 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 First inner end 25 First outer end 26 First spiral part 27 Second inner end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor Chip 42 First main surface 43 Second main surface 44A~44D Chip side wall 45 First Functional Device 51 Insulating layer 52 Insulating surface 53A~53D Insulated sidewall 55 Bottom insulation layer 56 Top insulation layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through Wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 Board plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 2nd Pattern 95 3rd Pattern 96 First Outer Line 97 2nd Outer Line 98 1st Intermediate Line 99 First connecting line 100 Slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic Insulating Layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 Buffer 220 Driver Chip (2nd Chip) 221, 222 Buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Trans Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 Transformers 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd Transformer 303 3rd Transformer 304 4th Transformer 305 1st Guard Ring 306 2nd Guard Ring a1 to a8 pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 Pads (corresponding to the second current supply pads) d1~d4 Pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil T21, T22, T23, T24, T25, T26 External terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias 400X Signal Transmitter 400Y Signal Transmission Device 410x 1st chip 410y 1st chip 411x Transmitter Circuit 411y Transmitting circuit 412 Switch output stage 413 High-side transistor 414 Low-side transistor 416 Driver Circuit 417 Driver control circuit 418a Current limiting circuit 418b Current limiting circuit 419 Current limiting transistor 420 2nd Chip 421 Receiver Circuit 430 3rd Chip 431 Isolation element Ax electronics Ay electronic equipment B Vehicle C1 Capacitor G1 Gate signal G2 Gate signal GND Ground voltage HD High Side Driver IN Input signal I1 current I2 current LD Low Side Driver OUT Output pulse signal PS Pulse Signal R1 resistor S1, S2 driver control signals VCC Power supply voltage n1 Connection node tg ground terminal ts input terminal tv power terminal

Claims

1. a switch output stage configured to generate a pulsed signal that is pulsed between a first voltage and a second voltage through a switching action; a current limiting circuit connected between the application terminal of the first voltage and the switch output stage and configured to limit a current flowing through the switch output stage; A signal generating circuit comprising:

2. 2. The signal generating circuit according to claim 1, wherein the current limiting circuit includes a resistor connected between the application terminal of the first voltage and the switch output stage.

3. the current limiting circuit includes a switch element having a first terminal connected to an application terminal of the first voltage, a second terminal connected to the switch output stage, and a third terminal connected to an application terminal of a reference voltage, and turned on / off in response to a potential difference between the first terminal and the third terminal; 3. The signal generating circuit according to claim 1, wherein the reference voltage is less than the first voltage.

4. 4. The signal generating circuit according to claim 3, wherein the switch element is a MOSFET having the first end as a source terminal, the second end as a drain terminal, and the third end as a gate terminal.

5. 3. The signal generating circuit according to claim 1, wherein the second voltage is a ground voltage.

6. A transmission circuit; A receiving circuit; an isolation element configured to transmit the pulse signal between the transmitting circuit and the receiving circuit while insulating them from each other; Equipped with A signal transmission device, wherein the transmission circuit includes the signal generating circuit according to claim 1 .

7. a first chip in which the transmission circuit is integrated; a second chip in which the receiving circuit is integrated; a third chip in which the isolation element is integrated; Further equipped with The signal transmission device according to claim 6 , wherein the first chip, the second chip, and the third chip are sealed in a single package.

8. An electronic device comprising the signal transmission device according to claim 6 or 7.

9. A vehicle comprising the electronic device according to claim 8.

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