Program, information processing system and information processing method
The system addresses the challenge of reflecting verification results in the design model by identifying logical elements and generating presentation information, ensuring consistency between design and implementation and facilitating high-quality development deliverables.
Patent Information
- Application Number
- JP2024196334
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-04-08
- Filing Date
- 2024-11-08
- Publication Date
- 2025-05-23
- Estimated Expiration
- 2044-11-08
AI Technical Summary
Existing systems struggle to reflect verification results of implemented code in the designed model, leading to inconsistencies between design and implementation.
A program and information processing system that identifies logical elements and verification items from implemented code, acquires verification results, and generates presentation information to reflect these results in the designed model, ensuring consistency between design and implementation.
The system effectively reflects verification results in the design model, maintaining consistency between design and implementation, and enabling the continuous production of high-quality development deliverables.
Smart Images

Figure 2025080232000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to a program, an information processing system, and an information processing method. [Background technology]
[0002] When constructing a system, the processes are carried out in the order of designing a model, implementing the designed model using code, and verifying the implemented code, and the code is modified depending on the verification results. Note that, for example, the technique described in Patent Document 1 has been proposed as a technique for verifying a software program.
[0003] Patent Document 1 discloses a method and system for verifying a software program in an integrated development environment, the method for verifying a software program in an integrated development environment includes generating source code of the software program, including logging statements, based on a specification of the software program. The method further includes executing the source code having the logging statements and generating one or more log files during the execution of the source code based on the logging statements. The method further includes generating a representation of the source code in a modeling language using the one or more log files. The method includes verifying that the source code complies with the specification by comparing the representation of the source code in the modeling language with the specification in the modeling language. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] Special Publication No. 2020-505710 Summary of the Invention [Problem to be solved by the invention]
[0005] However, implemented code is often modified multiple times, and during this process, implementation and verification are repeated, so that the modifications may not be reflected in the design.
[0006] In view of the above circumstances, the present invention provides a program, an information processing system, and an information processing method that are capable of reflecting the verification results of implemented code in a designed model. [Means for solving the problem]
[0007] According to one aspect of the present invention, there is provided a program that causes at least one computer to execute the following steps: in an identification step, a logical element to be verified and a verification item for the logical element are identified from code implemented based on a model; in an acquisition step, verification results for the logical element are acquired; and in a generation step, the verification results are associated with the logical elements to generate presentation information that represents the model in a diagram.
[0008] According to one aspect of the present invention, the verification results of the implemented code can be reflected in the designed model. [Brief description of the drawings]
[0009] [Figure 1] 1 is a diagram showing a configuration of an information processing device 1. FIG. [Diagram 2] 1 is a block diagram showing a functional configuration of an information processing device 1. FIG. [Diagram 3] 13 is a block diagram showing the functional configuration of a reflection unit 140. FIG. [Figure 4] 2 is a flowchart showing an overview of processing executed by the information processing device 1. [Diagram 5] 13 is a flowchart showing the flow of operations of the reflection unit 140. [Figure 6] 11 is a diagram for explaining the operation of a reflection unit 140. FIG. [Figure 7] FIG. 11 is a diagram showing an example of presentation information. [Figure 8]FIG. 11 is a diagram showing an example of presentation information in which a verification result is reflected. [Figure 9] 13 is a diagram showing an example of presentation information of a logic element including progress information and the like. FIG. [Figure 10] 13 is a diagram showing an example of presentation information of a logic element including progress information and the like. FIG. [Figure 11] FIG. 13 is a diagram showing an example of extension of presentation information. [Figure 12] This is a diagram showing the flow of integrating design and implementation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Various features shown in the following embodiments can be combined with each other.
[0011] Incidentally, a program for realizing the software appearing in one embodiment may be provided as a non-transitory computer-readable recording medium, or may be provided so as to be downloadable from an external server, or may be provided so that the program is launched on an external computer and its functions are realized on a client terminal (so-called cloud computing).
[0012] In addition, in various information processing according to an embodiment, an input and an output according to the input can be realized. Here, as long as an output is obtained as a result of the input, the form of information referenced in such information processing (hereinafter referred to as reference information) is not limited. The reference information may be, for example, rule-based information such as a database, a lookup table, or a predetermined function (including a judgment formula such as a regression formula constructed by a statistical method), or may be a trained model that has previously trained the correlation between the input and the output, or may be a large-scale language model that can output a desired result by inputting a prompt.
[0013] In one embodiment, the term "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In one embodiment, various information is handled, and this information is represented by, for example, physical values of signal values representing voltage and current, high and low signal values as a binary bit collection consisting of 0 or 1, or quantum superposition (so-called quantum bits), and communication and calculation can be performed on the circuit in the broad sense.
[0014] Furthermore, a circuit in the broad sense is a circuit realized by at least appropriately combining a circuit, circuitry, a processor, and a memory. The processor may be a general-purpose processor or a dedicated circuit. In other words, it includes an application specific integrated circuit (ASIC), a programmable logic device (e.g., a simple programmable logic device (SPLD), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA)), etc.
[0015] 1. Configuration of information processing device 1 is a diagram showing the configuration of an information processing device 1. As shown in the figure, the information processing device 1 has a processor 11, a storage unit 12, a temporary storage unit 13, an external device connection unit 14, and a communication unit 15, and these components are electrically connected inside the information processing device 1 via a communication bus 16.
[0016] The processor 11 is realized by, for example, a central processing unit (CPU), and operates according to a predetermined program stored in the storage unit 12 to realize various functions. That is, information processing by software stored in the storage unit 12 can be specifically realized by the processor 11, which is an example of hardware, and executed as each functional unit included in the processor 11. These will be described in more detail in the next section. The processor 11 is not limited to being single, and may be implemented with multiple processors 11 for each function. Also, a combination of these may be used.
[0017] The storage unit 12 is a non-volatile storage medium that stores various information. This is realized by a storage device such as a hard disk drive (HDD) or a solid state drive (SSD). The storage unit 12 can also be arranged in another device that can communicate with the information processing device 1.
[0018] The temporary storage unit 13 is a volatile storage medium. This is realized by a memory such as a random access memory (RAM), and stores information (arguments, arrays, etc.) that is temporarily required when the processor 11 operates.
[0019] The external device connection unit 14 is a connection unit that conforms to standards such as Universal Serial Bus (USB) and High-Definition Multimedia Interface (HDMI (registered trademark)), and allows the connection of input devices such as a keyboard and display devices such as a monitor.
[0020] The communication unit 15 is, for example, a communication means conforming to a local area network (LAN) standard, and realizes communication between the information processing device 1 and the local area network or a network such as the Internet via the local area network.
[0021] It should be noted that the information processing device 1 may be a general-purpose server computer or a personal computer, and the information processing device 1 may be configured using a plurality of computers.
[0022] 2. Functions of the information processing device 1 Next, an information processing system will be described. The information processing system is an information processing system consisting of at least one device, and has at least one processor capable of executing each step of a program described later. Here, the information processing system is composed of one or more devices or components. Therefore, even an information processing device 1 alone is included in the information processing system. In other words, the device constituting the information processing system is, for example, the information processing device 1, and the information processing system is realized by one or more information processing devices 1. Note that, in the following, an example will be described in which an information processing system is constituted by one information processing device 1.
[0023] The functions of the information processing device 1 will be described. The information processing device 1 operates according to a program to realize each of the functional units described later. This program causes at least one computer to execute each of the steps described later. Specifically, the processor 11, which is hardware, operates based on a program stored in the storage unit 12, i.e., software, to realize each of the functional units described later. At this time, the processor 11 operates the storage unit 12, the temporary storage unit 13, the external device connection unit 14, and the communication unit 15 as necessary.
[0024] 2 is a block diagram showing a functional configuration of the information processing device 1. As shown in the figure, the information processing device 1 includes a design unit 110, an implementation unit 120, a verification unit 130, and a reflection unit 140. That is, information processing by software stored in the storage unit 12 is specifically realized by a processor 11, which is an example of hardware, and can be executed as each functional unit included in the processor 11.
[0025] Specifically, the design unit 110 is a functional unit that designs a model, the implementation unit 120 is a functional unit that implements the model designed by the design unit 110 with code, the verification unit 130 is a functional unit that verifies the code implemented by the implementation unit 120, and the reflection unit 140 is a functional unit that reflects the verification results by the verification unit 130 in the model designed by the design unit 110. Note that the design unit 110, the implementation unit 120, and the verification unit 130 can each be realized by general-purpose software, and in that case, depending on the specifications of each software, it is also permitted that information is passed from the design unit 110 to the reflection unit 140 or from the implementation unit 120 to the reflection unit 140, as shown by the dashed arrow in FIG. 2.
[0026] Next, the function of the reflection unit 140 will be described. FIG. 3 is a block diagram showing the functional configuration of the reflection unit 140. As shown in FIG. 3, the reflection unit 140 includes a specification unit 141, an acquisition unit 142, and a generation unit 143. The specification unit 141 executes a specification step, in which a logical element to be verified and a verification item of the logical element are specified from the code implemented based on the model. The acquisition unit 142 executes an acquisition step, in which a verification result of the logical element is acquired. The generation unit 143 executes a generation step, in which the verification result is associated with the logical element and presentation information in which the model is represented by a diagram is generated. The model represented by the diagram, that is, the model designed by the design unit 110, is, for example, described in a modeling language or described as a model on a modeling tool. According to this embodiment, various verification functions of the present program described later can be realized for a model described in a modeling language or a model described as a model on a modeling tool. 3. Information processing method This section describes an information processing method executed by an information processing system (here, the information processing device 1). Note that the order of processes included in the information processing method can be changed as appropriate, multiple processes can be executed simultaneously, and some processes can be omitted.
[0027] 3.1 Overview As described above, the information processing device 1 includes at least one processor 11, and the processor 11 functions as each of the following units by reading a program. In other words, the information processing method includes steps corresponding to each unit of the information processing system. From another perspective, the program causes a computer to execute steps corresponding to each unit of the information processing system. FIG. 4 is a flowchart showing an outline of the processing executed by the information processing device 1. Each step shown in FIG. 4 will be described below.
[0028] First, in the process shown in FIG. 4, in the identification step, a logic element 2 to be verified and a verification item 3 of the logic element 2 are identified from the code implemented based on the model (step S001). In the acquisition step, a verification result 4 of the logic element 2 is acquired (step S002). In the generation step, the verification result 4 is associated with the logic element 2, and presentation information is generated that shows the model in a diagram (step S003). According to this embodiment, the verification result of the implemented code can be reflected in the designed model, and the consistency between the design and the implementation can be verified. Providing this means for verifying the consistency between the design and the implementation leads to a development system that maintains the consistency between the design and the implementation over a long period of time, and as a result, an environment in which high-quality development deliverables can be continuously produced can be realized. In addition, a huge number of verification results can be reflected in the design model at once, making it possible to prevent deviation between the design model and the implemented code.
[0029] 3.2 Specific examples A specific example may be included within the scope defined in the above-mentioned overview. Fig. 5 is a flowchart showing the flow of the operation of the reflection unit 140. Fig. 6 is a diagram for explaining the operation of the reflection unit 140. In the specific example, it is assumed that a user who has implemented source code and test code in an implementation environment included in this program tests the source code. Specifically, a button for executing a test, which is included in the user interface of the implementation environment, is pressed by the user (for example, a click operation, a tap operation, etc.), and a test is executed.
[0030] When an initial pressing operation is performed, first, the identification unit 141 identifies the logical element 2 from the source code and test code implemented by the implementation unit 120 (step S101), and identifies the verification item 3 from the identified logical element 2 (step S102). In other words, as the identification step, the identification unit 141 identifies the logical element 2 to be verified and the verification item 3 of the logical element 2 from the code implemented based on the model. Since the source code and the test code are written according to predetermined rules, the logical element 2 and the verification item 3 can be identified according to the rules and specifications of the corresponding programming language.
[0031] Next, the reflection unit 140 causes the verification unit 130 to execute verification, and waits for the verification to end (step S103). Note that step S103 in Fig. 3 is not an operation of the reflection unit 140, but is described for the purpose of explanation.
[0032] When the verification by the verification unit 130 is completed, the acquisition unit 142 of the reflection unit 140 acquires the verification result 4 and records it in association with the corresponding test item (step S104). In other words, the acquisition unit 142 acquires the verification result 4 of the logic element 2 as an acquisition step.
[0033] Next, in response to an operation by the user, a transition is made from the screen of the implementation environment to the screen of the model design environment (step S105).
[0034] Next, in response to a user operation, the identifying unit 141 analyzes the contents of the implemented test code and extracts a list of verification items 3, which conventionally had to be done manually, on the user interface of the model design environment (step S106).
[0035] Then, the generating unit 143 generates presentation information in a manner that allows the listing of the verification items 3 to be understood (step S107). The generated presentation information may be displayed on a display (not shown) connected via the external device connecting unit 14. This allows the user to understand the verification items 3 that are automatically listed as described above and the corresponding verification results 4 in the model design environment via the generated presentation information. Details will be explained further in the next section. In other words, the generating unit 143 generates presentation information in which the model is represented by a diagram by associating the verification results 4 with the logical elements 2 as a generation step.
[0036] The above is the process flow according to the specific example. Note that the above assumptions and process flow are merely examples and are not limited to these. For example, step S107 may be executed before steps S105 and S106. In any case, the user can grasp the verification items 3 automatically listed as described above and the corresponding verification results 4 in the model design environment through the generated presentation information. Conventionally, it was not possible to visually confirm the consistency between the design and the implementation, but according to the above-mentioned aspect, it is possible to prevent the divergence between the design model and the implemented code caused by the conventional independent work.
[0037] 4. Presentation information Next, the presentation information generated by the generating unit 143 will be described. FIG. 7 is a diagram showing an example of the presentation information. The presentation information shown in the figure is a diagram showing the model designed by the design unit 110, and is composed of a logic element 201, a logic element 202, a logic element 203, a logic element 204, a logic element 205, and a logic element 206. It is also shown that the logic element 201 is composed of a logic element 202, a logic element 203, a logic element 204, a logic element 205, and a logic element 206. Each logic element 2 has a corresponding verification item 3, and the verification items 3 are automatically listed in the user interface of the model design environment. For example, when the logic element 202 is referred to, the verification items 3 such as fff(), ggg(), and hhh() are automatically listed. For example, when there are 1000 verification items 3, it may be time-consuming to input 1000 verification items 3 in the model design environment, but this program eliminates such time-consuming work. In particular, because the relationships between multiple logical elements 2 can be visually grasped, for example, if there are consecutive logical elements 2, if the verification of the preceding logical element 2 fails, the subsequent logical element 2 will also fail, making it possible to visually and intuitively grasp this. Furthermore, not only does it ensure the consistency of design and implementation, but it also makes it possible to judge the validity of verification on the design model. In other words, it realizes an environment in which logical consistency can be grasped in a single go through the series of processes of design, implementation, and verification.
[0038] Furthermore, when the verification is performed by the verification unit 130, the presentation information generated by the generation unit 143 reflects the verification result. FIG. 8 is a diagram showing an example of the presentation information reflecting the verification result. The presentation information is presented in a manner in which the colors representing the logical elements are different depending on whether the verification result is successful, that is, the verification is passed, or the verification result is unsuccessful, that is, the verification is unsuccessful. In the example shown in FIG. 8, the logical elements 202 and 204 are successfully verified and are represented in a color indicating successful verification, for example, green. On the other hand, the logical elements 201, 203, and 205 are represented in a color indicating unsuccessful verification, for example, red. According to this manner, it is possible to recognize whether the verification result of the implemented code is successful or unsuccessful through easy-to-understand visual information such as the difference in color.
[0039] In addition, the presented information is displayed in a color different from the color of the logical elements corresponding to the verification result, which is different from the color of the logical elements not corresponding to the verification result. In the example shown in FIG. 8, since the logical element 206 does not correspond to the verification result, it is displayed in a color different from the logical elements 201 and 202, for example, in white. According to this aspect, the verification result of the implemented code can be recognized through easy-to-understand visual information such as a difference in color. Note that the verification by the verification unit 130 may be performed repeatedly, and in this case, the presented information may be displayed in a manner that the color of the logical elements not corresponding to the verification result is maintained the same as the previous color. According to this aspect, the color of the logical elements not corresponding to the verification result among the implemented code is not changed, so that the user can recognize it more clearly.
[0040] Meanwhile, the verification by the verification unit 130 is performed for each verification item, but a logical element may include multiple verification items. In this case, the color of the logical element indicated by the presentation information may not only be a color for a successful verification and a color for a failed verification, but may also be a color indicating that more than half of the verification items have been successful, such as yellow, and the presentation information may further be a color indicating the logical element according to the proportion of the verification results that have been successful. According to this aspect, multiple verification items can be recognized from the verification results of the implemented code through easy-to-understand visual information such as different colors.
[0041] In addition, when a logic element includes a plurality of verification items, the presented information may be displayed in such a manner that progress information indicating the percentage of verification results that have been successful is associated with the logic element corresponding to the progress information, or a character string indicating the verification result is associated with the logic element corresponding to the verification result among the logic elements. According to such an embodiment, the progress of a plurality of verification items can be easily grasped, and the user can recognize the verification result more clearly. FIG. 9 and FIG. 10 are diagrams showing examples of presented information of a logic element including progress information and the like. As shown in the diagram, a logic element 210 includes a name 211, summary information 212, progress status information 213, and verification result information 214. This logic element 210 is used as a substitute for the logic elements 201, 202, and the like shown in FIG. 8.
[0042] The name 211 is the name of the logic element 210, and the summary information 212 is information indicating the summary of the definition information, functions, etc. included in the logic element 210. The progress status information 213 indicates the ratio of verification items that have been successfully verified by the verification unit 130 as the progress status (indicated as a test success rate in the figure). For example, if the number of verification items is 10 and the number of verifications that have been successfully verified is 50%, the progress status is 50%. The verification result information 214 is character string information indicating the verification result. Note that, by setting the color of the bar 213B indicating the progress status included in the progress status information 213 to a color (e.g., green) when the progress information of the logic element 210 becomes 100%, that is, when the verification of all the verification items is successful, the color of the logic element 210 is unified as shown in FIG. 10, and the visibility of the diagram including the logic element 210 is improved.
[0043] 5. Expansion of displayed information Here, an example of extension of the presentation information will be described. FIG. 11 is a diagram showing an example of extension of the presentation information. As shown in the figure, when progress status information is included in a logical element included in a diagram of the presentation information, the progress information can be graphed and displayed as the presentation information. This graph is generated for each logical element, and graphs showing the progress information of each of the logical elements can also be displayed side by side. According to this aspect, the progress of multiple actual verification items can be easily grasped through easy-to-understand visual information such as a graph. In this example, the number of successes is 110, while the number of failures is 7. In particular, when there are a huge number of verification items, such as more than 100, the user can instantly grasp the success rate through visual information such as a graph.
[0044] 6. Integrating Design and Implementation As described above, by using the information processing device 1, it is possible to integrate a designed model and implementation based on the model. Fig. 12 is a diagram showing a flow of integrating design and implementation. If design and implementation are not integrated, there are problems such as design information not being updated even though the design and implementation are completely different, the comprehensiveness of verification for the entire system not being understood, and no end in sight to repeated ad hoc verification. One of the reasons for these problems is the gradual loss of opportunities to access design information in the process of designing, implementing, and verifying.
[0045] In contrast, if you integrate design and implementation, - Reflecting a huge amount of unit test results in the design model (UML, SysML) all at once - Unit test date and time, and the location and cause of failure when a test fails can also be reflected. -Successful elements are green and failed elements are red, allowing you to instantly distinguish between them -Supports large-scale development · Contribute to updating design information in organizations working on design, implementation, and verification -Ideal for building a system that ensures consistency between design, implementation, and verification - Implementation can be visually confirmed on the design information, making it efficient to grasp the implementation status - Visual judgment helps maintain motivation at the development site This makes it possible to:
[0046] 5.Other The information processing system according to the above embodiment may adopt the following aspects.
[0047] At least one of the devices (e.g., the information processing device 1) included in the information processing system may be installed outside Japan. For example, the information processing device 1 may be installed outside Japan, and a user terminal connected to the information processing device 1 via a network may be installed inside Japan. Similarly, a user may access the information processing device 1 installed inside Japan using his / her own user terminal from outside Japan. This form may be, for example, a type of SaaS using a website provided by the information processing device 1. In such a service, it is preferable that a user accesses the website and uploads predetermined information such as a test code, thereby obtaining presentation information in which the verification result 4 is reflected in a model. That is, according to such an embodiment, a more convenient experience can be provided to the user through various management forms.
[0048] In one embodiment, various functional units are described as functional units realized by the processor 11 of the information processing device 1, but at least some of them may be implemented as functional units realized by a server other than the information processing device 1. Alternatively, they may be implemented as functional units realized by a processor of a user terminal. Furthermore, various information described in the above example may be stored not only in the storage unit 12 of the information processing device 1 but also in other external devices in a distributed manner using block chain technology or the like.
[0049] Furthermore, it may be provided in the following aspects:
[0050] (1) A program that causes at least one computer to execute the following steps: in an identification step, identifying logical elements to be verified from code implemented based on a model and verification items for the logical elements; in an acquisition step, acquiring verification results for the logical elements; and in a generation step, associating the verification results with the logical elements and generating presentation information that represents the model in a diagram.
[0051] According to this aspect, the verification results of the implemented code can be reflected in the designed model, making it possible to verify the consistency between the design and the implementation. Providing this means for verifying the consistency between design and implementation leads to a development system that maintains the consistency between design and implementation over the long term, and as a result, it is possible to realize an environment in which high-quality development deliverables can be continuously produced. In addition, a huge amount of verification results can be reflected in the design model all at once, making it possible to prevent deviation between the design model and the implemented code.
[0052] (2) A program in which the presentation information represents a logical element among the logical elements that corresponds to the verification result in a color different from a color representing a logical element that does not correspond to the verification result.
[0053] According to this embodiment, the verification result of the implemented code can be recognized through easy-to-understand visual information such as the difference in color.
[0054] (3) The program according to (2) above, wherein the presentation information is presented in such a manner that the color representing the logical element is different when the verification result is a success and when the verification result is a failure.
[0055] According to this aspect, the verification result of the implemented code can be recognized as a success or failure through easy-to-understand visual information such as a difference in color.
[0056] (4) A program according to (2) or (3) above, wherein the logical element includes a plurality of the verification items, and the presented information is a program in which the color representing the logical element is expressed in a color corresponding to the percentage of the verification results that are successful.
[0057] According to this aspect, among the verification results of the implemented code, a plurality of verification items can be recognized through easy-to-understand visual information such as differences in color.
[0058] (5) A program according to any one of (2) to (4) above, wherein the logical element includes a plurality of the verification items, and the presented information is progress information indicating the percentage of the verification results that were successful, and the progress information is displayed in association with the logical element corresponding to the progress information.
[0059] According to this embodiment, the progress of multiple verification items can be easily grasped.
[0060] (6) In the program described above in (5), the presented information is a program in which the progress information is displayed in the form of a graph.
[0061] According to this embodiment, the progress of multiple verification items can be easily grasped through easy-to-understand visual information in the form of a graph.
[0062] (7) A program according to any one of (2) to (6) above, wherein the presentation information is displayed in a manner that maintains the color of logical elements that do not correspond to the verification result from among the logical elements the same as their previous color.
[0063] According to this aspect, by not changing the color of the logical elements that do not correspond to the verification results of the implemented code, the user can more clearly recognize the results.
[0064] (8) A program according to any one of (2) to (7) above, wherein the presentation information is displayed in a manner in which a string indicating the verification result is associated with a logical element among the logical elements that corresponds to the verification result.
[0065] According to this embodiment, the user can recognize the verification result in a more understandable manner.
[0066] (9) A program according to any one of (1) to (8) above, wherein the model is written in a modeling language or as a model on a modeling tool.
[0067] According to this embodiment, various verification functions of the present program can be realized for a model described in a modeling language or a model described as a model on a modeling tool.
[0068] (10) An information processing system consisting of at least one device, the system having at least one processor capable of executing each step of the program described in any one of (1) to (9) above.
[0069] According to this aspect, the verification results of the implemented code can be reflected in the designed model, making it possible to verify the consistency between the design and the implementation. Providing this means for verifying the consistency between design and implementation leads to a development system that maintains the consistency between design and implementation over the long term, and as a result, it is possible to realize an environment in which high-quality development deliverables can be continuously produced. In addition, a huge number of verification results can be reflected in the design model all at once, making it possible to prevent deviation between the design model and the implemented code.
[0070] (11) An information processing method comprising the steps of the program according to any one of (1) to (9) above.
[0071] According to this aspect, the verification results of the implemented code can be reflected in the designed model, making it possible to verify the consistency between the design and the implementation. Providing this means for verifying the consistency between design and implementation leads to a development system that maintains the consistency between design and implementation over the long term, and as a result, it is possible to realize an environment in which high-quality development deliverables can be continuously produced. In addition, a huge number of verification results can be reflected in the design model all at once, making it possible to prevent deviation between the design model and the implemented code. Of course, this is not the case.
[0072] Finally, although various embodiments of the present invention have been described, these are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. The embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]
[0073] 1: Information processing equipment 2: Logical elements 3: Verification items 4: Verification results 11: Processing section 12: Storage section 13:Temporary storage 14: External device connection 15: Communications Department 16: Communication bus 110:Design Department 120: Mounting section 130: Verification Department 140: Reflection section 141: Specific part 142: Acquisition Department 143 :Generation part 201: Logical elements 202: Logical elements 203: Logical elements 204: Logical elements 205 :Logical elements 206: Logical elements 210: Logical elements 211 :Name 212: Overview 213 :Progress information 213B: Bar 214: Verification result information
Claims
1. A program, Having at least one computer perform the steps of: In the identification step, a logic element to be verified and verification items of the logic element are identified from the code implemented based on the model; In the obtaining step, a verification result of the logic element is obtained; In the generating step, the verification results are associated with the logical elements to generate presentation information that represents the model in a diagram. program.
2. The program according to claim 1, The presentation information is such that a color representing a logic element corresponding to the verification result among the logic elements is different from a color representing a logic element not corresponding to the verification result. program.
3. The program according to claim 2, The presentation information is displayed in such a manner that the color representing the logic element is different depending on whether the verification result is a success or a failure. program.
4. The program according to claim 2, The logic element includes a plurality of the verification items, The presented information is represented by a color representing the logic element according to a ratio of the verification results that are successful. program.
5. The program according to claim 2, The logic element includes a plurality of the verification items, The presented information is displayed in such a manner that progress information indicating the percentage of the verification results that have been successful is associated with the logic element that corresponds to the progress information. program.
6. The program according to claim 5, The presented information is a graph of the progress information. program.
7. The program according to claim 2, The presented information is displayed in such a manner that the color representing the logical elements that do not correspond to the verification result is maintained the same as the previous color. program.
8. The program according to claim 2, The presented information is displayed in such a manner that a character string indicating the verification result is associated with a logical element corresponding to the verification result among the logical elements. program.
9. The program according to claim 1, The model is described in a modeling language or as a model on a modeling tool. program.
10. An information processing system comprising at least one device, The present invention comprises at least one processor capable of executing the steps of the program according to any one of claims 1 to 9. system.
11. 1. An information processing method, comprising: The program includes steps according to any one of claims 1 to 9. method.
Citation Information
Patent Citations
Project test processing method and device, equipment and storage medium
CN114610615A
Low-code platform flow configuration method based on data flow
CN114895872A
Software test support device
JP2005316710A
Control software development program
JP2017016416A
Program, method, and apparatus for assisting creation of business model chart
WO2006033159A1