Display with light-emitting diodes

Abstract

To solve the problem in which, when designing a device with light-emitting diodes, high transistor leakage currents, slow transistor switching speeds, routing complexity, voltage drops due to ohmic losses, and other issues may adversely affect display performance.SOLUTION: A display is provided with a plurality of pixels, and the pixel in the plurality of pixels comprises: a first transistor; a second transistor; a third transistor; a light-emitting diode, where the first transistor, second transistor, third transistor, and light-emitting diode are connected in series between a first power source terminal and a second power source terminal; a fourth transistor coupled to a source of the second transistor; and a fifth transistor coupled to an anode of the light-emitting diode. In the display, a gate of the fifth transistor and a gate of the fourth transistor receive a common control signal.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This application generally relates to electronic devices, and more specifically to electronic devices having a display. This application claims priority to U.S. Patent Application No. 15 / 263,803, filed on September 13, 2016, and U.S. Provisional Patent Application No. 62 / 263,074, filed on December 4, 2015, the entireties of which are incorporated herein by reference.

Background Art

[0002] Electronic devices often include a display. Displays, such as organic light-emitting diode displays, have pixels with light-emitting diodes.

[0003] Designing a display with a light-emitting diode display can be challenging. Without consideration, high leakage current of transistors, low switching speed of transistors, routing complexity, voltage drop due to ohmic loss, and other problems may negatively affect the performance of the display.

Summary of the Invention

[0004] An electronic device may have a display. The display may have an array of pixels aligned in rows and columns. Each of the pixels may have a light-emitting diode, such as an organic light-emitting diode, that emits light in response to the application of a drive current. A drive transistor within each pixel may supply a drive current to the light-emitting diode of that pixel in response to a gate-source voltage between the gate and source of the drive transistor.

[0005] The source of each drive transistor may be coupled to a positive power supply. The light-emitting transistor may be coupled in series between the positive power supply and the ground power supply to the drive transistor and the light-emitting diode of each pixel. The pixel may include first and second switching transistors. The data storage capacitor may be coupled between the gate and the source of the drive transistor in each pixel. The control signal may be supplied from the display driver circuit to each gate of the switching transistor and the light-emitting transistor.

[0006] Signal lines may be provided within the column of pixels to send signals such as a data signal, a sensed drive current from the drive transistor, and a predetermined voltage such as a reference voltage between the display driver circuit and the pixel. The switching transistor, the light-emitting transistor, and the drive transistor may include a semiconductor oxide transistor and a silicon transistor, and may be an n-channel transistor or a p-channel transistor.

[0007] Further features will become more apparent from the accompanying drawings and the following detailed description.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] Displays such as display 14 in FIG. 1 may be used in devices such as tablet computers, laptop computers, desktop computers, displays, mobile phones, media players, wristwatch devices or other wearable electronic devices, or other suitable electronic devices.

[0010] Display 14 may be an organic light emitting diode display, or a display based on other types of display technologies (e.g., a display having light emitting diodes formed from discrete crystal semiconductors, a display having quantum dot light emitting diodes, etc.). A configuration in which display 14 is an organic light emitting diode display may be described herein as an example. However, this is merely illustrative. Any suitable type of display may be used if desired.

[0011] Display 14 may have a rectangular shape (i.e., display 14 may have a rectangular footprint and a rectangular peripheral edge extending around the rectangular footprint), or may have other suitable shapes. Display 14 may be flat or may have a curved contour.

[0012] As shown in FIG. 1, display 14 may have an array of pixels 22 formed on substrate 24. Substrate 24 may be formed from glass, metal, plastic, ceramic, or other substrate materials. Pixels 22 may receive data signals and other signals on paths such as vertical path 16. Each vertical path 16 may be associated with each column of pixels 22 and may include one or more signal lines. Pixels 22 may receive horizontal control signals (sometimes referred to as emission enable control signals or emission signals, scan signals, or gate signals) via paths such as horizontal path 18. Each horizontal path 18 may include one or more horizontal signal lines.

[0013] The display 14 may have a suitable number of (e.g., dozens or more, hundreds or more, or thousands or more) rows and columns of pixels 22. Each pixel 22 may have a light-emitting diode that emits light under the control of a pixel circuit formed from a thin-film transistor circuit (e.g., a thin-film transistor, a thin-film capacitor, etc.). The thin-film transistor circuit of the pixel 22 may include a silicon thin-film transistor such as a polysilicon thin-film transistor, a semiconductor oxide thin-film transistor such as an indium gallium zinc oxide transistor, or a thin-film transistor formed from other semiconductors. The pixel 22 may include light-emitting diodes of various colors (e.g., red, green, and blue diodes for red, green, and blue pixels) to provide the display 14 with the ability to display a color image.

[0014] The pixels 22 may be arranged in a rectangular array or an array of other shapes. The array of pixels 22 forms an active area for the display 14 and is used when displaying an image for the user. The non-active portion of the display 14 may extend along one or more of the edges of the active area AA. The non-active area forms a boundary for the display 14 and may not include the pixels 22.

[0015] The operation of the pixels 22 may be controlled using a display driver circuit 20. The display driver circuit 20 may be formed from an integrated circuit, a thin-film transistor circuit, or other suitable circuits and may be located within the non-active area of the display 14. The display driver circuit 20 may include a communication circuit for communicating with a system control circuit such as a microprocessor, a storage device, and other storage and processing circuits. During operation, the system control circuit may supply information regarding the image to be displayed on the display 14 to the circuit 20.

[0016] To display an image on pixel 22, a display driver circuit such as circuit 20A may supply image data to vertical line 16 while issuing a clock signal and other control signals to an auxiliary display driver circuit (e.g., a gate drive circuit) such as display driver circuit 20B via path 26. Optionally, circuit 20 may also supply a clock signal and other control signals to gate drive circuit 20B on the opposing edge of display 14.

[0017] Gate drive circuit 20B (which may sometimes be referred to as a horizontal control line control circuit) may be implemented as part of an integrated circuit and / or may be implemented using a thin film transistor circuit. Horizontal control lines 18 within display 14 may transmit gate line signals (e.g., scan line signals, emission enable control signals, and other horizontal control signals) for controlling the pixels of each row. Any suitable number (e.g., one or more, two or more, three or more, four or more, etc.) of horizontal control signals per row of pixels may be present.

[0018] Pixel 22 may each include a drive transistor coupled in series with a light emitting diode. The emission enable transistor (emission transistor) may be coupled in series with the drive transistor and the light emitting diode between a positive power supply terminal and a ground power supply terminal. The storage capacitor within each pixel may be used to store loaded data (e.g., data defining the pixel luminance value of the pixel) between successive image frames. Each pixel may also have one or more switching transistors to support data load operations and other operations.

[0019] The frame rate of display 14 may be 60 Hz or other suitable frame rates. Optionally, display 14 may support variable refresh rate operation. During normal refresh rate operation, the refresh rate of display 14 may be relatively high (e.g., 60 Hz). When static content is being displayed on display 14, the refresh rate of display 14 may be decreased (e.g., to 1 - 5 Hz or other suitable low refresh rate) to conserve power.

[0020] The circuitry of pixel 22 (e.g., transistors such as drive transistors, light emitting diodes, etc.) may be affected by aging effects. Display driver circuitry 20 (e.g., circuitry 20A) may include a current sensing circuit and other compensation circuitry that periodically measures the performance of pixel 22. Based on these periodic measurements (e.g., periodic current sensing measurements for measuring the current generated by the drive transistor of the pixel), display driver circuitry 20 may adjust the data loaded to pixel 22. The adjustment made to the loaded pixel data can compensate for measured variations in pixel performance (e.g., the adjustment can compensate for aging effects, such that display 14 can reliably exhibit desired uniformity and other attributes). Current sensing (e.g., sensing the current of the drive transistor within pixel 22) may be performed using a vertical line within display 14, such as line 16. During normal operation (sometimes referred to as the "emission" mode of display 14), the emission control line may be asserted to turn on the emission enable transistor within pixel 22. The emission enable transistor may be turned off during data load operations and current sensing operations.

[0021] The pixel 22 may use both a semiconductor oxide transistor and a silicon transistor. The semiconductor oxide transistor tends to exhibit a lower leakage current than the silicon transistor. The silicon transistor tends to switch faster than the semiconductor oxide transistor. By appropriately selecting which transistor in each pixel is to be a semiconductor oxide transistor and which transistor in each pixel is to be a silicon transistor, and further by appropriately configuring the horizontal lines, vertical lines, and other pixel circuits, the performance of the display can be optimized. FIGS. 2 to 13 show various pixel circuit arrangements and related signal timing diagrams associated with an exemplary embodiment for the display 14.

[0022] As shown in the exemplary configuration for the pixel 22 of FIG. 2, each pixel 22 may include a light-emitting diode such as a light-emitting diode 30 that emits light 32 in response to the application of a drive current Id. The light-emitting diode 30 may be, for example, an organic light-emitting diode. The transistor and capacitor structure of the pixel 22 may be formed from a thin-film circuit on the substrate 24 (FIG. 1). Generally, each pixel 22 of the display 14 may include a p-channel transistor, an n-channel transistor, a semiconductor oxide transistor, a silicon transistor, one or more storage capacitors, and signal paths (e.g., a part of one or more vertical signal lines and one or more horizontal signal lines).

[0023] In the example of FIG. 2, the light-emitting diode 30 is coupled in series with a light-emission enable transistor (light-emission transistor) TE and a drive transistor TD between a positive power supply Vddel and a ground power supply Vssel. The storage capacitor Cst1 maintains the loaded data value on Node2 connected to the gate of the drive transistor TD. The source S of the drive transistor TD is coupled to the positive power supply Vddel. The value of the gate-source voltage Vgs of the drive transistor TD (i.e., the voltage difference between Node2 and the power supply terminal Vddel of the source S of the transistor TD) determines the drive current Id flowing through the light-emitting diode 30. Light emission is enabled or disabled using a light-emission enable control signal EM applied to the gate of the light-emission transistor TE. The switching transistors T1 and T2 are used for data load operations and current sensing operations. The transistors T1, T2, TD, and TE may all be (by way of example) p-channel silicon transistors.

[0024] Each column of pixels 22, such as pixel 22 in FIG. 2, may be associated with a pair of vertical signal lines 16. The vertical signal lines may include a data line (Data) and a reference voltage line (Vref). The data line may be used to load data onto the data storage capacitor Cst1. The reference voltage line, which may sometimes be called a sense line, may be used to measure the current of the drive transistor TD during a current sensing operation (e.g., to evaluate aging). The reference voltage line may also be used when loading a predetermined voltage onto the node between the light-emission transistor TE and the light-emitting diode 30 (i.e., Node3).

[0025] Each row of pixels 22, such as pixel 22 in FIG. 2, may be associated with three horizontal signal lines 18. The horizontal signal lines 18 may include a first switching transistor control signal (scan signal) Scan1 applied to the gate of the switching transistor T1, a second switching transistor control signal (scan signal) Scan2 applied to the gate of the switching transistor T2, and a light-emission enable signal (light-emission signal) EM applied to the gate of the light-emission transistor TE.

[0026] A signal timing diagram showing a signal associated with the loading of data from the data line Data onto the storage capacitor Cst1 of Node2 of pixel 22 in FIG. 2 is shown in FIG. 3. During normal operation (light emission operation), since EM is held low by the display driver circuit 20B, the transistor TE is turned on. When TE is turned on, the data value on Node2 sets a desired Vgs value between the gate G and the source S of the drive transistor TD (the source S is connected to Vddel), thereby setting the magnitude of the drive current Id of the light emitting diode 30. During the data load operation, EM is set high by the circuit 20B to turn off the transistor TE and cut off the current Id. While EM is high, the circuit 20B sets signals Scan1 and Scan2 low to turn on transistors T1 and T2. When T2 is turned on, a known reference voltage can be supplied from line Vref to Node3. When T1 is turned on, the current data signal on the data line (Data) can be loaded onto the capacitor Cst1 of Node2. Next, the light emission operation may be resumed by setting EM low and Scan1 and Scan2 high. During light emission, the data value loaded onto the capacitor Cst1 of Node2 determines the output level of the light 32 from the light emitting diode 30.

[0027] A signal timing diagram showing a signal associated with the current sensing operation (this operation can be periodically executed once an hour, once a week, etc. by interrupting the normal light emission operation) is shown in FIG. 4.

[0028] During preloading, EM is set high while keeping Scan1 and Scan2 low to prevent current from flowing through the light emitting diode 30. While Scan2 is low, the transistor T2 is turned on and a known reference voltage is loaded from line Vref onto Node3. While Scan1 is low, known reference data ("sensing data") is loaded from the data line Data onto Node2 through the on transistor T1. Thereby, known conditions (for example, a predetermined Vgs value and a predetermined voltage on Node3) for operating the drive transistor TD are determined.

[0029] After loading the sensing data into the pixel 22, a current sensing operation is performed. During the sensing operation, while Scan1 is set high, EM is set low, and Scan2 is held low. Thereby, the current flowing through the driving transistor TD is sent to the line Vref, and this line then functions as a sensing line. The current sensing circuit within the compensation circuit of the display driver circuit 20B can measure the amount of current flowing through the transistor TD, thereby evaluating the performance of the transistor TD. The compensation circuit of the display driver circuit 20B can use such a current measurement value to compensate the pixel 22 for the aging effect (e.g., aging that affects the amount of drive current Id generated by the transistor TD for a given Vgs value).

[0030] After the current sensing operation is completed, data may be loaded from the data line Data onto Node2 by setting EM high, setting Scan1 low to turn on the transistor T1, and holding Scan2 low. The pixel 22 may be put into the light emitting mode after loading the data by setting EM low to turn on the transistor TE, and setting Scan1 and Scan2 high to turn off the transistors T1 and T2.

[0031] The configuration for the pixel 22 in FIG. 2 uses three gate control signals on three horizontal control lines within each row of the pixel 22, and sends data, a reference voltage signal, and a current measurement value through two vertical lines within each column of the pixel 22. The vertical lines of each column operate independently of the vertical lines of other columns (i.e., a display having N columns of pixels 22 has N independent lines Data and N independent lines Vref).

[0032] (For example, when the display 14 is configured to support variable refresh rate operation), a semiconductor oxide switching transistor may be provided in the pixel 22 in order to reduce the leakage current of the transistor and thereby operate the display 14 efficiently at a low refresh rate. For example, the data load transistor T1 of the pixel 22 in FIG. 5 may be an n-channel semiconductor oxide transistor. The transistors TE, TD, and T2 may be p-channel silicon transistors.

[0033] FIG. 6 shows a signal timing diagram showing a signal associated with the loading of data from the data line Data onto the storage capacitor Cst1 of Node2 in the pixel 22 of FIG. 5.

[0034] During the normal operation (light emission operation) of the pixel 22 in FIG. 5, since EM is held low by the display driver circuit 20B, the transistor TE is turned on. The source S of the drive transistor TD is at Vddel. When TE is turned on, the data value on Node2 determines a desired gate-source voltage Vgs value between the gate G and the source S of the drive transistor TD, thereby setting the magnitude of the drive current Id for the light emitting diode 30.

[0035] During the data load operation, EM is set high by the circuit 20B to turn off the transistor TE and cut off the current Id. While EM is high, the circuit 20B turns on the transistors T1 and T2 by setting the signal Scan1 high and Scan2 low. Since the transistor T1 is a semiconductor oxide transistor, it may be desirable to extend the time that Scan1 is high (compared to the scenario where T1 is a silicon transistor) to ensure sufficient time for the transistor T1 to stabilize. When T2 is turned on for data loading, a known reference voltage may be supplied from the line Vref to Node3. When T1 is turned on, the data signal present on the data line (Data) may be loaded onto the capacitor Cst1 of Node2. Next, the light emission operation may be resumed by setting EM and Scan1 low and Scan2 high.

[0036] A signal timing diagram showing a signal associated with the periodic current sensing operation for pixel 22 in FIG. 5 is shown in FIG. 7.

[0037] During the preload of pixel 22 in FIG. 5, while Scan1 is set high and Scan2 is set low, EM is set high to prevent current from flowing through light emitting diode 30. When Scan2 goes low, transistor T2 turns on and a known reference voltage is loaded onto Node3 from line Vref. When Scan1 goes high, known reference data (“sensing data”) is loaded onto Node2 from line Data through the on transistor T1. This determines known conditions (e.g., a predetermined Vgs value and a predetermined voltage on Node3) for operating drive transistor TD.

[0038] During the sensing operation for pixel 22 in FIG. 5, EM and Scan1 go low and Scan2 is held low. As a result, the current flowing through drive transistor TD is sent to line Vref, and this line functions as a sensing line. The current sensing circuit in the compensation circuit of display driver circuit 20B can measure the amount of current flowing through transistor TD, thereby evaluating the performance of transistor TD. Similar to the scenario in FIG. 2, the compensation circuit of display driver circuit 20B can use such current measurement values to compensate pixel 22 in FIG. 5 for aging effects (e.g., aging that affects the amount of drive current Id generated by transistor TD for a given Vgs value).

[0039] After the sensing operation is completed, data can be loaded onto Node2 from data line Data by setting EM and Scan1 high while holding Scan2 low. Pixel 22 may be put into the light emitting mode after the data is loaded by setting EM and Scan1 low and Scan2 high, thereby turning on transistor TE and turning on transistors T1 and T2.

[0040] Since the EM signal and the Scan1 signal are identical, the functions of these signals can be implemented using a single combined signal transmitted on a single signal line (i.e., a single signal EM / Scan1 can replace the separately adjusted EM signal and Scan1 signal of pixel 22 in FIG. 2). Therefore, the configuration for pixel 22 in FIG. 5 saves routing resources by using only two gate control signals on two horizontal control lines. Two vertical lines (Data and Vref) can be used to transmit data, a reference voltage signal, and current measurements within each column of pixel 22. The vertical lines of each column of the display with pixels 22 of the type shown in FIG. 5 operate independently of the vertical lines of other columns (i.e., a display with N columns of pixels 22 has N independent lines Data and N independent lines Vref).

[0041] Optionally, the number of horizontal control signals associated with each row of pixel 22 can be further reduced using a circuit of the type shown for pixel 22 in FIG. 8. In the configuration of FIG. 8, both transistor T1 and transistor T2 are n-channel semiconductor oxide transistors, while both transistor TE and transistor TD are p-channel silicon transistors. Using semiconductor oxide transistors in pixel 22 (e.g., for transistor T1) reduces leakage current, thereby helping to operate display 14 efficiently at a low refresh rate (e.g., when display 14 is configured to support variable refresh rate operation).

[0042] FIG. 9 shows a signal timing diagram of the signal associated with the loading of data from the data line Data onto the storage capacitor Cst1 of Node2 in pixel 22 of FIG. 8.

[0043] During the normal operation (light emission operation) of pixel 22 in FIG. 8, since EM is held low by display driver circuit 20B, transistor TE is turned on. When TE is turned on, the data value on node Node2 determines a desired Vgs value between the gate G and source S of drive transistor TD, thereby setting the magnitude of drive current Id for light emitting diode 30. Signals Scan1 and Scan2 may be held low during light emission to turn off transistors T1 and T2 during light emission.

[0044] During the data load operation, EM is set high by circuit 20B to turn off transistor TE and cut off current Id. While EM is high, circuit 20B sets signals Scan1 and Scan2 high to turn on transistors T1 and T2. Since transistor T1 is a semiconductor oxide transistor, it may be desirable to extend the time that Scan1 is high (compared to the scenario where T1 is a silicon transistor) to ensure sufficient time for transistor T1 to stabilize. When T2 is turned on for data loading, a known reference voltage may be supplied from line Vref to Node3 between transistor TE and light emitting diode 30. When T1 is turned on, the data signal present on the data line (Data) may be loaded onto capacitor Cst1 of Node2. Next, the light emission operation may be resumed by setting EM, Scan1, and Scan2 low.

[0045] FIG. 10 shows a signal timing diagram showing signals associated with the periodic current sensing operation for pixel 22 in FIG. 8.

[0046] During the preloading of pixel 22 in FIG. 8, while Scan1 and Scan2 are set high, EM is set high to prevent current from flowing through light-emitting diode 30. When Scan2 goes high, transistor T2 turns on, and a known reference voltage is loaded onto Node3 from line Vref. When Scan1 goes high, known reference data (“sensing data”) is loaded onto Node2 from line Data through transistor T1 which is on. This determines the known conditions (e.g., a predetermined Vgs value and a predetermined voltage on Node3) for operating drive transistor TD.

[0047] During the sensing operation for pixel 22 in FIG. 8, EM and Scan1 go low, and Scan2 is held high. Thereby, the current flowing through drive transistor TD is sent to sensing line Vref. The current sensing circuit within the compensation circuit of display driver circuit 20B measures the amount of current flowing through transistor TD, and thereby can evaluate the performance of transistor TD. Similar to the scenario in FIG. 2, the compensation circuit of display driver circuit 20B can use such current measurement values to compensate pixel 22 in FIG. 8 for the aging effect (e.g., aging that affects the amount of drive current Id generated by transistor TD for a given Vgs value).

[0048] After the sensing operation is completed, data can be loaded onto Node2 from data line Data by setting EM and Scan1 high while holding Scan2 high. Pixel 22 may be put into the light-emitting mode after the data is loaded by setting EM, Scan1, and Scan2 low, thereby turning on transistor TE and turning off transistors T1 and T2.

[0049] Since the EM signal, Scan1 signal, and Scan2 signal are identical (i.e., because transistor T2 is an n-channel transistor like transistor T1), the functions of these signals can be implemented using a single combined signal transmitted on a single signal line (i.e., a single signal EM / Scan1 / Scan2 can replace the separately adjusted EM signal, Scan1 signal, and Scan2 signal of pixel 22 in FIG. 2). Therefore, the configuration for pixel 22 in FIG. 5 helps minimize routing resources by using only a single gate control signal on a single associated horizontal control line within each row of pixel 22. Two vertical lines (Data and Vref) can be used to transmit data, reference voltage signals, and current measurements within each column of pixel 22. The vertical lines of each column of the display with pixels 22 of the type shown in FIG. 8 operate independently of the vertical lines of other columns (i.e., within a display with N columns of pixels 22, there are N independent lines Data and N independent lines Vref).

[0050] Pixels having the type of configuration shown in FIGS. 2, 5, and 8 may be susceptible to variations in Vddel due to IR drop (ohmic losses) because Vddel is distributed throughout display 14. This is because the source voltage of the source S of drive transistor TD is coupled to Vddel and can vary as Vddel changes depending on the position of each pixel 22 within display 14.

[0051] Optionally, a pixel circuit of the type shown in FIG. 11 may be used for pixel 22 to help reduce performance variations due to variations in Vddel. In the exemplary configuration of FIG. 11, T1 is coupled between line Vref and Node2, while transistor T2 is coupled between data line Data and Node1. Therefore, transistor T2 can function as a data load transistor. Node2 is coupled to the gate of drive transistor TD.

[0052] During the light emission operation, the voltage on the capacitor Cst1 (i.e., the voltage on Node2) is preferably maintained at a constant level to ensure a steady output level for the light 32. During operations such as variable refresh rate operations, the refresh rate of the display 14 may be relatively low (e.g., 1 to 5 Hz). To prevent the leakage current of the transistor that may adversely affect the stability of the data voltage of Node2, the transistor T1 may be implemented using a semiconductor oxide transistor (e.g., an n-channel semiconductor oxide transistor). The transistors TE, TD, and T2 may be p-channel silicon transistors. Since the transistor T2 is a silicon transistor, data can be quickly loaded from the data line Data to Node1.

[0053] Unlike the arrangements in FIGS. 2, 5, and 8, the source S of the driving transistor TD in FIG. 11 is connected to Node1 instead of Vddel. The level of the voltage Vddel can vary due to IR loss because Vddel is distributed throughout the display 14, but the voltage Vs on the source S does not vary throughout the display 14 (i.e., Vs is independent of the position of the pixel 22 within the display 14). This is because the voltage Vs is determined by loading a predetermined reference voltage onto Node1 from the data line Data via the transistor T2.

[0054] FIG. 12 shows a signal timing diagram showing the signal associated with the loading of data from the data line Data onto the storage capacitor Cst1 of Node1 of the pixel 22 in FIG. 11.

[0055] During normal operation (light emission operation), since EM is held low by the display driver circuit 20B, the transistor TE is turned on. Scan1 is low to keep the transistor T1 off. Scan2 is high to keep the transistor T2 off. When TE is turned on, the data value on node Node1 (and the voltage on Node2) determines a desired Vgs value between the gate G and the source S of the driving transistor TD, thereby setting the magnitude of the drive current Id for the light emitting diode 30.

[0056] During the data load operation, EM is set high by the circuit 20B to turn off the transistor TE and cut off the current Id. While EM is high, the circuit 20B sets the signal Scan1 high to turn on the transistor T1. When the transistor T1 is turned on, Node2 is pre-charged to a predetermined voltage, thereby determining a known gate voltage Vg at Node2 of the transistor TD. Scan2 is initially high, thereby keeping T2 off. When Scan2 goes low (which can occur at a time for one line before light emission start, two lines before light emission start, or any other suitable time), the transistor T2 is turned on and a desired data value is loaded from the data line Data to Node1 via the transistor T2. The light emission operation may then be resumed by setting EM low, Scan1 low, and Scan2 high.

[0057] FIG. 13 shows a signal timing diagram showing signals associated with the periodic current sensing operation for the pixel 22 of FIG. 11.

[0058] During preloading, while setting Scan1 high and Scan2 low, set EM high to prevent current from flowing through the light emitting diode 30. When Scan2 goes low, the transistor T2 turns on and known reference data ("sensing data") is loaded from the line Data onto Node1. When Scan1 goes high, the transistor T1 turns on and a predetermined voltage (e.g., -5.5V or other suitable value) is provided from the reference voltage line Vref to Node2. Thereby, known conditions (e.g., a predetermined Vgs value) for operating the driving transistor TD are determined.

[0059] During the sensing operation, EM is held high, Scan1 goes low, and Scan2 is held low. Thereby, TE is held off, T1 turns off, and T2 is held on, whereby the current flowing through the driving transistor TD is sent through the line Data. Thus, this line functions as a sensing line. The current sensing circuit in the compensation circuit of the display driver circuit 20B can measure the amount of current flowing through the transistor TD via the line Data, thereby evaluating the performance of the transistor TD. The current sensing can be performed over a period of 100 microseconds or other suitable time. The compensation circuit of the display driver circuit 20B can use such current measurement values to compensate the pixel 22 for the aging effect (e.g., aging that affects the amount of drive current Id generated by the transistor TD for a given Vgs value).

[0060] After the current sensing operation is completed, hold EM high to turn off transistor TE, set Scan1 high to turn on transistor T1, thereby transmitting a predetermined voltage from Vref to Node2, and further hold Scan2 low to keep transistor T2 on, allowing the desired data signal to pass from data line Data to Node1, so that data can be loaded into pixel 22. Pixel 22 may be set to the light emitting mode after the data is loaded by setting EM low to turn on transistor TE, setting Scan1 low to turn off transistor T1, and setting Scan2 high to turn off transistor T2.

[0061] The voltage range of signal EM may be -10V to 8V, -8V to 8V, or any other suitable voltage range. The voltage of Vddel may be 5 to 8V or other suitable positive power supply voltage levels. The voltage of Vssel may be -2V or other suitable ground power supply voltage levels. The voltage range of the signal on line Data may be -4.5V to -0.3V or other suitable voltage ranges. The voltage range of Scan2 may be -10V to -8V, -12V to -4V, or other suitable voltage ranges. The voltage range of Scan1 may be -10V to -8V, -8V to 8V, or other suitable voltage ranges.

[0062] The configuration for pixel 22 in FIG. 2 uses three gate control signals (EM, Scan1, and Scan2) on three horizontal control lines within each row of pixel 22, and two vertical lines, namely Vref and Data, within each column of pixel 22 to send data, a reference voltage signal, and current measurement values. One of the vertical lines (line Data) is a shared line used for both current sensing operations and data loading operations. Preferably, there is an individual Data line for each column of pixel 22 within display 14. The other of the vertical lines (line Vref) associated with pixel 22 is part of a global path that can be used to distribute a common voltage in parallel to all of pixel 22 within display 14. Since Vref is a global signal path, it is only necessary to provide a single Vref signal to pixel 22 by display driver circuit 20A (i.e., the amount of signal routing resources between display driver circuit 20B and pixel 22 is reduced compared to a scenario where individual Vref signal lines are used for each column). Instead of providing two separate vertical signal lines of the type shown in FIGS. 2, 5, and 8, it is only necessary to provide a single separate vertical signal line Data for each column. Thus, the arrangement in FIG. 11 indicates that the fanout of the display driver circuit is small.

[0063] By using a semiconductor oxide transistor with low leakage current for transistor T1, the refresh rate of display 14 may be reduced to a low rate (e.g., 1 - 5 Hz) during variable refresh rate operation. By implementing transistor T2 using a silicon transistor, the charging time (i.e., the time associated with charging Node1 to a desired value during a data loading operation) may be minimized. The pixel arrangement in FIG. 11 is less affected by variations in Vddel (e.g., variations due to IR drop) because both Node1 and Node2 are actively loaded by a desired voltage during data loading, thereby defining a desired gate - source voltage across driving transistor TD without using Vddel.

[0064] FIG. 14 is a diagram of an exemplary pixel circuit including five transistors and one capacitor. Driving transistor TD is coupled in series between a positive power supply terminal 40 and a ground power supply terminal 42, with light-emitting enable transistors TE1 and TE2, and further with a light-emitting diode 44 (e.g., an organic light-emitting diode). Transistors TE1 and TE2 may be respectively controlled using horizontal control signals (gate signals) such as light-emitting enable control signals EM1 and EM2. Switching transistors TS1 and TS2 may be respectively controlled using horizontal control signals (gate signals) such as operation control signals SCAN1 and SCAN2. Transistor TS1 may be, for example, a semiconductor oxide transistor, and transistors TS2, TE1, TE2, and TD may be (as an example) silicon transistors. Capacitor Cst1 may be coupled between Node2 (of the gate of driving transistor TD) and Node1 (of the source of transistor TD). A reference voltage may be supplied to the column of pixel 22 using line Vref. Data signal (D) may be supplied to pixel 22 using data line Data.

[0065] FIG. 15 is a timing diagram showing signals related to operating a display including pixels of the type shown in FIG. 14. As shown in FIG. 15, on-bias stress may be applied during the operation of on-bias stress period 200, data writing may be executed during data writing period 202, and light-emitting operation may be executed during light-emitting period 204.

[0066] FIG. 16 is a diagram of the pixel circuit of FIG. 14 during on-bias stress period 200. During this period, transistor TE2 is turned off to prevent a driving current from flowing through diode 44, and transistor TS1 is turned on to supply on-bias stress to the gate of driving transistor TD to pre-adjust transistor TD. The voltage Vgs of transistor TD is high. This is because TE1 is on and Node1 is Vddel, and TS1 is on and Node2 is Vref.

[0067] FIG. 17 is a diagram of the pixel circuit of FIG. 14 during the data writing operation (period 202 in FIG. 15). During data writing, first, transistor TS1 is turned on to load a known reference voltage Vref onto Node2, and transistor TS2 is turned on to load a data signal (which may be referred to as Vdata, Data, or signal D) onto Node1. Transistor TE1 is turned off to isolate Node1 from Vddel. As a result, a voltage Vdata - Vref is generated across both ends of capacitor Cst1. Next, as shown in FIG. 18, transistors TS1 and TS2 are turned off, and transistor TE1 is turned on. When TE1 is turned on, the voltage of Node1 becomes Vddel. Since the voltage across both ends of capacitor Cst1 does not change instantaneously, when Node1 becomes Vddel, Node2 becomes Vddel - (Vdata - Vref). Since current flows through diode 44, therefore, during the light emission period 204, light emission 46 is proportional to Vdata.

[0068] FIGS. 19, 20A, 20B, 21, and 22 show how the display driver circuit 20 can compensate the display 14 for variations in the threshold voltage Vt of drive transistors such as transistor TD within the pixel 22 of the display 14.

[0069] FIG. 19 is a diagram of the pixel circuit of FIG. 14 when collecting threshold voltage information according to a type of arrangement that may sometimes be referred to as a "current sensing" arrangement. FIG. 20A is a timing diagram showing signals related to the operation of collecting threshold voltage information. As shown in FIG. 20A, during the on-bias stress period 200, on-bias stress may be applied to the transistor TD. During the period 202', predetermined data used during the threshold voltage compensation operation may be loaded into the pixel 22 (i.e., a known voltage may be applied across the capacitor Cst1 as described in connection with loading Vdata onto Node1 in relation to FIG. 17). Image data may be loaded into the pixel 22 during the data write period 202, and the amount of light emitted by the diode 44 during the emission period 204 may be controlled using the loaded image data. Between the period 202' and the period 202, the display driver circuit 20 may measure the threshold voltage Vt of the driving transistor TD during the sensing period 206. To determine the threshold voltage Vt of the transistor TD, a known reference data value Vref is written during the period 202'. Next, the flow of current on the data line Data is measured by the current sensor, and the threshold voltage Vt is calculated from the measured current. Next, during the period 202, externally compensated data for any variations in Vt can be written into the pixel 22. By adjusting the value of the image data supplied by the display driver circuit 20 to the pixel 22 during the period 202, each of the pixels 22 in the display 14, such as the pixel 22 of FIG. 14, can be compensated for any measured variations in the threshold voltage Vt (i.e., the display driver circuit 20 can implement an external threshold voltage compensation method).

[0070] FIG. 19 shows the operation of pixel 22 during sensing period 206 (sometimes referred to as threshold voltage sensing or current sensing). As shown in FIG. 19, during period 206, transistor TE1 is turned off to isolate Node1 from Vddel. Transistor TS1 is turned off to float Node2. During period 206, the gate-source voltage Vgs of transistor TD is determined by the known data loaded into capacitor Cst1 during period 202'. Since transistor TS2 is on, the known data on transistor TD (and the threshold voltage Vt of transistor TD) determines the current flowing on the Data line. The display driver circuit 20 measures this current during period 206 to confirm the value of the threshold voltage Vt. Next, an appropriate threshold voltage compensation operation can be performed by adjusting the value of the image data loaded into pixel 22 during data write operation 202 (FIG. 20A).

[0071] FIG. 21 is a diagram of the pixel circuit of FIG. 14 when collecting threshold voltage information according to another exemplary external threshold voltage compensation method (i.e., a type of method sometimes referred to as the "voltage sensing" method). FIG. 22 is a timing diagram showing the signals involved when operating a display including pixels as shown in FIG. 21.

[0072] As shown in FIG. 22, an on-bias stress may be applied to transistor TD during on-bias stress period 200. Image data may be loaded into pixel 202 during data write period 22, and the amount of light emitted by diode 44 during emission period 204 may be controlled using the loaded image data. Between periods 200 and 202, display driver circuit 20 may measure the threshold voltage Vt of drive transistor TD during sense period 208. First, transistor TS1 may be turned on to set Node2 to Vref. Thereby, a known current is determined on data line Data. Since transistors TD and TE2 are on, current flows through light-emitting diode 44. Since the voltage drops across transistors TE2, TD, and TS2 are small, the generated voltage Voled on data line Data can be measured. Next, the threshold voltage Vt can be obtained from the known values of the flowing current and voltage Voled. By adjusting the value of the image data supplied by display driver circuit 20 to pixel 22 during period 202, pixel 22 can be compensated for any variation in the threshold voltage Vt measured during sense period 208 (i.e., display driver circuit 20 can implement an external threshold voltage compensation method).

[0073] Figure 21 shows the operation of pixel 22 during sensing period 208 (sometimes referred to as voltage sensing or Voled sensing). As shown in Figure 21, during period 208, transistor TE1 is turned off to isolate Node1 from Vddel. Transistor TS1 is turned on to supply the reference voltage Vref to Node2 at the gate G of driving transistor TD. The known data voltage Vdata is supplied to Node1 at the source S of driving transistor TD through the Data line and further through transistor TS2 which is on. Thereby, a known gate-source voltage Vgs is determined across driving transistor TD. The known Vgs value and threshold voltage Vt of transistor TD determine the amount of current flowing from the Data line to diode 44. The display driver circuit 20 measures this current during period 208 to confirm the value of the threshold voltage Vt. Next, an appropriate threshold voltage compensation operation can be performed by adjusting the value of the image data loaded into pixel 22 during data write operation 202 (Figure 22).

[0074] Optionally, as shown in Figure 20B, a settling time may be inserted into the process of Figure 20A. With this settling time, the voltage on data line Data can be set to a high voltage near Vddel, and the light-emitting diode 44 can reproduce a normal light-emitting operation during current sensing. By sensing the settling operation, the analog / digital converter circuit within circuit 20 coupled to data line Data can sample the voltage on line Data for a sufficient time.

[0075] FIG. 23 shows an exemplary 6T1C configuration for pixel 22. Transistor TS3 and transistor TS2 may be controlled by scan signal Scan2 as shown in FIG. 23, or the gate of transistor TS3 may be controlled using a pre-scan line signal (e.g., Scan2(n-1) from the previous row). Transistor TS3 in FIG. 23 may be used to reset Node4 at the anode of light emitting diode 44. The parasitic capacitance of light emitting diode 44 can quickly discharge Node4 (e.g., from about 2.5 volts to -6 volts) during data writing to quickly turn off light emitting diode 44. This helps to reduce Node4 below the threshold voltage of light emitting diode 44 and helps to prevent light emitting diode 44 from lighting up due to leakage from drive transistor TD while a black image is being displayed on display 14. FIG. 24 shows exemplary control signals that may be used to operate pixel 22 of FIG. 23 during on-bias stress, data writing, and light emitting periods.

[0076] In an exemplary configuration for pixel 22 of FIG. 25, TS3 is replaced by a bypass transistor TS4 (controlled by Scan3) that helps to prevent current from passing through transistor TD and an undesirably lit diode 44 while performing a current sensing operation on transistor TD. Optionally, transistor TS4 may be placed at an alternative location TS4'. The example of FIG. 25 is merely illustrative. FIG. 26 shows control signals that may be used when operating pixel 22 of FIG. 25. FIG. 27 shows pixel 25 of FIG. 22 during an on-bias stress operation. FIG. 28 shows pixel 22 of FIG. 25 during data writing. FIG. 29 shows pixel 22 of FIG. 25 during a light emitting operation. FIG. 30 shows pixel 22 of FIG. 25 during a current sensing operation for measuring the Vt of TD (in this case, light emitting diode 44 is not lit by a current bypass path defined by transistor TS4. In the example of FIG. 31, transistor TS4 is used in a voltage sensing manner. In the voltage sensing manner of FIG. 31, the sensing accuracy is improved by preventing a voltage drop across transistors TS2, TD, and TE2 using transistor TS3.

[0077] FIG. 32 is a diagram of the type shown in FIG. 26 showing how a type of current sensing operation described in connection with FIG. 30 can be performed.

[0078] As these examples show, additional transistors may be incorporated into pixel 22 to create a current bypass path during threshold voltage measurement for drive transistor TD. The additional transistors are used to create a bypass path that bypasses light emitting diode 44, and thus the additional transistors may sometimes be referred to as bypass transistors. The bypass transistors may be, for example, silicon transistors (i.e., transistors having a silicon active region).

[0079] According to one embodiment, a display is provided that includes a display driver circuit, an array of pixels, and signal lines that communicate signals between the display driver circuit and the pixels. Each pixel includes a light emitting transistor, a drive transistor, a light emitting diode, a first switching transistor coupled between a first path and the gate of the drive transistor, a second switching transistor coupled between a second path and the source of the drive transistor, and a capacitor coupled between the gate and the source of the drive transistor, all of which are coupled in series between a positive power supply and a ground power supply.

[0080] According to another embodiment, the drive transistor is coupled between the light emitting transistor and the light emitting diode, and the first switching transistor includes a semiconductor oxide transistor.

[0081] According to another embodiment, the second switching transistor includes a silicon transistor.

[0082] According to another embodiment, the drive transistor and the light emitting transistor are silicon transistors.

[0083] According to another embodiment, the first switching transistor is an n-channel transistor, and the second switching transistor, the light-emitting transistor, and the driving transistor are p-channel transistors.

[0084] According to another embodiment, the second path is a common path that transmits the current sensed during the current sensing operation from the driving transistor to the display driver circuit and transmits the data signal to the capacitor during the data loading operation.

[0085] According to another embodiment, the array of pixels includes pixel columns and pixel rows, and the signal lines include individual signal lines that function as the second path for each pixel in the respective columns.

[0086] According to another embodiment, the first path includes a global signal path that supplies a common voltage from the display driver circuit to each of the pixels in the pixel rows and columns.

[0087] According to another embodiment, the first switching transistor includes an n-channel transistor, a light-emitting transistor, and a driving transistor, and the second switching transistor includes a p-channel transistor.

[0088] According to another embodiment, the first switching transistor includes a semiconductor oxide transistor.

[0089] According to another embodiment, the light-emitting transistor, the driving transistor, and the second switching transistor include silicon transistors.

[0090] According to one embodiment, a display is provided that includes a display driver circuit, an array of pixels, and signal lines that convey signals between the display driver circuit and the pixels. Each pixel includes a driving transistor having a source coupled to a positive power supply, which is serially coupled between the positive power supply and a ground power supply, a light-emitting transistor, a light-emitting diode, a first switching transistor coupled between a first path and the gate of the driving transistor, a second switching transistor coupled between a second path and a node between the light-emitting transistor and the light-emitting diode, and a capacitor coupled between the gate and the source of the driving transistor.

[0091] According to another embodiment, the first switching transistor, the second switching transistor, the driving transistor, and the light-emitting transistor include p-channel transistors.

[0092] According to another embodiment, the first switching transistor, the second switching transistor, the driving transistor, and the light-emitting transistor include silicon transistors. The pixels are arranged in rows and columns. Each column of pixels has a data line that forms the respective first path of the pixels within the column and a reference voltage line that forms the respective second path of the pixels within the column.

[0093] According to one embodiment, a display is provided that includes a display driver circuit, a data line coupled to the display driver circuit, a gate line coupled to the display driver circuit, and an array of pixels. The pixels receive data from the display driver circuit via the data line and are controlled by a control signal received from the display driver circuit via the gate line. Each pixel in the array of pixels has a light-emitting diode, a driving transistor, and first and second light-emitting enable transistors coupled in series between a first power terminal and a second power terminal. Each pixel has a capacitor coupled between the source terminal of the driving transistor and the gate terminal of the driving transistor. Each pixel has a first switching transistor coupled between a reference voltage line and the gate of the driving transistor and a second switching transistor coupled between one of the data lines and the source terminal of the driving transistor. The gate line supplies a control signal to the first and second light-emitting transistors and the first and second switching transistors. The first switching transistor has a semiconductor oxide active region, and the second switching transistor, the first and second enable transistors, and the driving transistor have silicon active regions.

[0094] According to another embodiment, the display driver circuit is configured to operate the array of pixels by supplying a control signal and data during an on-bias stress period in which an on-bias stress is applied to the driving transistor to pre-adjust the driving transistor.

[0095] According to another embodiment, the display driver circuit is configured to perform a threshold voltage measurement on the driving transistor by measuring a current flowing through the data line during a sensing period.

[0096] According to another embodiment, the display driver circuit is configured to supply a control signal via a gate line during a sensing period to turn off the first switching transistor, turn on the second switching transistor, turn off the first light-emitting transistor, and turn on the second light-emitting transistor.

[0097] According to another embodiment, the display driver circuit is configured to supply a control signal via a gate line during a sensing period to turn on the first switching transistor, turn on the second switching transistor, turn off the first light-emitting transistor, and turn on the second light-emitting transistor.

[0098] According to one embodiment, a display is provided that includes a display driver circuit, a data line coupled to the display driver circuit, a gate line coupled to the display driver circuit, and an array of pixels. The pixels receive data from the display driver circuit via the data line and are controlled by a control signal received from the display driver circuit via the gate line. Each pixel in the array of pixels includes a light-emitting diode having an anode and a cathode coupled in series between a first power terminal and a second power terminal, a driving transistor, and first and second light-emitting enable transistors. Each pixel includes a capacitor coupled between the source terminal of the driving transistor and the gate terminal of the driving transistor. Each pixel includes a first switching transistor coupled between a reference voltage line and the gate of the driving transistor and a second switching transistor coupled between one of the data lines and the source terminal of the driving transistor. Each pixel includes a bypass transistor having a terminal coupled to the anode of the light-emitting diode. The gate line supplies a control signal to the first and second light-emitting transistors and the first and second switching transistors. The first switching transistor has a semiconductor oxide active region, and the second switching transistor, the first and second enable transistors, the driving transistor, and the bypass transistor have silicon active regions.

[0099] The above are merely examples, and various modifications can be made to the described embodiments. The above embodiments can be implemented individually or in any combination.

Claims

1. A display, A display driver circuit; an array of pixels; signal lines for transmitting signals between the display driver circuit and the pixels; each pixel comprises: a light emitting transistor, a drive transistor, and a light emitting diode coupled in series between a positive power supply and a ground power supply; a first switching transistor coupled between a first path and a gate of the drive transistor, a second switching transistor coupled between a second path and a source of the drive transistor, and a capacitor coupled between the gate and the source of the drive transistor; Including the display.

2. 2. The display of claim 1, wherein the drive transistor is coupled between the light emitting transistor and the light emitting diode, and the first switching transistor comprises a semiconductor oxide transistor.

3. 3. The display of claim 2, wherein the second switching transistor comprises a silicon transistor.

4. 4. The display of claim 3, wherein the drive transistors and the light emitting transistors are silicon transistors.

5. 5. The display of claim 4, wherein the first switching transistor is an n-channel transistor and the second switching transistor, the light emitting transistor and the drive transistor are p-channel transistors.

6. 6. The display of claim 5, wherein the second path is a shared path that conveys a sensed current from the drive transistor to the display driver circuit during a current sensing operation and conveys a data signal to the capacitor during a data loading operation.

7. 7. A display as claimed in claim 6, wherein the array of pixels comprises columns of pixels and rows of pixels, and the signal lines comprise a respective signal line in each of the columns that serves as the second path for each of the pixels in the column.

8. 8. A display as claimed in claim 7, wherein the first path comprises a global signal path which provides a common voltage from the display driver circuit to each of the pixels in the row and column of pixels.

9. 2. The display of claim 1, wherein the first switching transistor comprises an n-channel transistor, and the light emitting transistor, the drive transistor and the second switching transistor comprise p-channel transistors.

10. 10. The display of claim 9, wherein the first switching transistor comprises a semiconductor oxide transistor.

11. 11. The display of claim 10, wherein the light emitting transistor, the drive transistor and the second switching transistor comprise silicon transistors.

12. A display, A display driver circuit; an array of pixels; signal lines for transmitting signals between the display driver circuit and the pixels; each pixel comprises: a drive transistor having a source coupled to a positive power supply, a light emitting transistor, and a light emitting diode coupled in series between a positive power supply and a ground power supply; a first switching transistor coupled between a first path and a gate of the drive transistor, a second switching transistor coupled between a second path and a node between the light emitting transistor and the light emitting diode, and a capacitor coupled between the gate and the source of the drive transistor; Including the display.

13. 13. The display of claim 12, wherein the first switching transistor, the second switching transistor, the drive transistor and the light emitting transistor comprise p-channel transistors.

14. 14. The display of claim 13, wherein the first switching transistor, the second switching transistor, the drive transistor and the light emitting transistor comprise silicon transistors, the pixels are arranged in rows and columns, each column of pixels having a data line forming the first path of each of the pixels in the column and a reference voltage line forming the second path of each of the pixels in the column.

15. A display, A display driver circuit; data lines coupled to the display driver circuit; a gate line coupled to the display driver circuit; an array of pixels, the pixels receiving data from the display driver circuit via the data lines and controlled by control signals received from the display driver circuit via the gate lines, each pixel in the array of pixels having a light emitting diode, a drive transistor, and first and second light emission enable transistors coupled in series between a first power supply terminal and a second power supply terminal, each pixel having a capacitor coupled between a source terminal of the drive transistor and a gate terminal of the drive transistor, each pixel having a first switching transistor coupled between a reference voltage line and the gate of the drive transistor and a second switching transistor coupled between one of the data lines and the source terminal of the drive transistor, the gate line providing the control signals to the first and second light emission enable transistors and the first and second switching transistors, the first switching transistor having a semiconductor oxide active area, and the second switching transistor, the first and second light emission enable transistors, and the drive transistor having silicon active areas; A display comprising:

16. 16. The display of claim 15, wherein the display driver circuitry is configured to provide the control signals and data to operate the array of pixels during an on-bias stress period to apply an on-bias stress to the drive transistors to precondition the drive transistors.

17. 16. A display as claimed in claim 15, wherein the display driver circuitry is configured to perform threshold voltage measurements on the drive transistors by measuring current through the data lines during a sensing period.

18. 18. The display of claim 17, wherein the display driver circuit is configured to provide the control signals via the gate lines during the sensing period to turn off the first switching transistor, turn on the second switching transistor, turn off the first light emitting transistor, and turn on the second light emitting transistor.

19. 18. The display of claim 17, wherein the display driver circuit is configured to provide the control signals via the gate lines during the sensing period to turn on the first switching transistor, turn on the second switching transistor, turn off the first light emitting transistor, and turn on the second light emitting transistor.

20. A display, A display driver circuit; data lines coupled to the display driver circuit; a gate line coupled to the display driver circuit; an array of pixels, the pixels receiving data from the display driver circuit via the data lines and controlled by control signals received from the display driver circuit via the gate lines, each pixel in the array of pixels having a light emitting diode having an anode and a cathode coupled in series between a first power supply terminal and a second power supply terminal, a drive transistor, and first and second light emission enable transistors, each pixel having a capacitor coupled between a source terminal of the drive transistor and a gate terminal of the drive transistor, each pixel having a first switching transistor coupled between a reference voltage line and the gate of the drive transistor; an array of pixels, each pixel having a first data line and a second switching transistor coupled between one of the data lines and the source terminal of the drive transistor, each pixel having a bypass transistor having a terminal coupled to the anode of the light emitting diode, the gate line providing the control signal to the first and second light emission enable transistors and the first and second switching transistors, the first switching transistor having a semiconductor oxide active area, and the second switching transistor, the first and second light emission enable transistors, the drive transistor and the bypass transistor having silicon active areas; A display comprising:

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