Display device

Abstract

To provide a structure that alleviates electric field concentration that may occur between a source electrode and a drain electrode and suppresses deterioration in switching characteristics in a bottom gate type thin film transistor and a method for manufacturing the same.SOLUTION: A bottom gate type thin film transistor has an oxide semiconductor layer on a source electrode and a drain electrode. By making an angle θ1 of a side surface of the source electrode in contact with the oxide semiconductor layer and an angle θ2 of a side surface of the drain electrode 20° or more and less than 90°, a distance from an electrode upper end to an electrode lower end at a side surface of the source electrode and the drain electrode is increased.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display device using an oxide semiconductor and a method for manufacturing the same.

Background Art

[0002] Thin film transistors formed on a flat plate such as a glass substrate, typified by liquid crystal display devices, are made of amorphous silicon or polycrystalline silicon. Although thin film transistors using amorphous silicon have a low field-effect mobility, they can respond to the enlargement of the area of the glass substrate. On the other hand, thin film transistors using crystalline silicon have a high field-effect mobility, but require a crystallization process such as laser annealing and do not necessarily suit the enlargement of the area of the glass substrate. On the contrary, a technique of manufacturing a thin film transistor using an oxide semiconductor and applying it to electronic devices and optical devices

[0003] has attracted attention. For example, a technique of manufacturing a thin film transistor using zinc oxide or an In-Ga-Zn-O-based oxide semiconductor as an oxide semiconductor film and using it for a switching element of an image display device is disclosed in Patent Document 1 and Patent Document 2. is disclosed in Patent Document 1 and Patent Document 2.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a bottom-gate type thin film transistor, there is a risk of electric field concentration occurring between the source electrode and the drain electrode, and a structure for alleviating the same and a manufacturing method thereof are provided as one of the problems.

[0006] Also, providing a structure for improving the coverage of the oxide semiconductor layer and a manufacturing method thereof is also a problem.

Means for Solving the Problem

[0007] A bottom-gate type thin film transistor having an oxide semiconductor layer on the source electrode and the drain electrode, and the angle θ1 of the side surface of the source electrode in contact with the oxide semiconductor layer and the side surface of the drain electrode are set to be 20° or more and less than 90°, so that the distance from the upper end of the electrode to the lower end of the electrode on the side surfaces of the source electrode and the drain electrode is increased.

[0008] One configuration of the invention disclosed in this specification is a gate electrode on a substrate having an insulating surface, an insulating layer on the gate electrode, a source electrode and a drain electrode on the insulating layer, a side surface of the source electrode, and an oxide semiconductor layer overlapping via the gate electrode and the insulating layer between the side surface of the source electrode and the side surface of the drain electrode facing the side surface, and the angle formed by the substrate surface of the substrate and the side surface of the source electrode and the angle formed by the substrate surface of the substrate and the side surface of the drain electrode are 20° or more and less than 90°, and a semiconductor device characterized by this is provided.

[0009] The above configuration solves at least one of the above problems.

[0010] Although it depends on the metal material used for the source electrode and the drain electrode, a natural oxide film is formed on at least the side surfaces of the source electrode and the drain electrode. This natural oxide film is formed in the air after etching ​​​​​It is formed when it comes into contact with an oxygen-containing atmosphere such as this. Also, when the oxide semiconductor layer is formed in a film-forming atmosphere containing oxygen after etching, a natural oxide film is formed on the side surface of the electrode. When the film-forming atmosphere for forming the oxide semiconductor layer contains oxygen, a natural oxide film is formed on the side surface of the electrode. It occurs.

[0011] Also, in order to prevent the formation of a natural oxide film on the upper surface of the electrode, a buffer layer (also called an n-layer) is continuously formed in contact with the metal film obtained by the sputtering method without coming into contact with the atmosphere. It is preferable. This buffer layer is an oxide semiconductor layer with a lower resistance than the oxide semiconductor layer and functions as a source region or a drain region. + It is formed without coming into contact with the atmosphere. In the above configuration, the buffer layer is provided on the upper surfaces of the source electrode and the drain electrode, and the oxide semiconductor layer is provided on the buffer layer. The buffer layer (also called an n-layer) is continuously formed without coming into contact with the atmosphere. By doing so, the formation of a natural oxide film on the upper surfaces of the source electrode and the drain electrode is prevented.

[0012] In the bottom gate type thin film transistor, when a voltage much larger than the threshold voltage is applied to the gate electrode to turn it on, the path of the drain current (the current path in the channel length direction) is first from the drain electrode through the oxide semiconductor layer near the interface of the gate insulating film to the source electrode. It reaches the source electrode. + In the bottom gate type thin film transistor having an oxide semiconductor layer on the source electrode and the drain electrode, the channel length corresponds to the shortest distance between the source electrode and the drain electrode and is the distance of the oxide semiconductor layer near the interface with the gate insulating film sandwiched between the source electrode and the drain electrode. It is. It is to prevent this.

[0013] Also, in the bottom gate type thin film transistor, when a voltage much larger than the threshold voltage is applied to the gate electrode to turn it on, the path of the drain current (the current path in the channel length direction) is first from the drain electrode through the oxide semiconductor layer near the interface of the gate insulating film to the source electrode. It reaches the source electrode. The path is first from the drain electrode through the oxide semiconductor layer near the interface of the gate insulating film to the source electrode. It reaches the source electrode.

[0014] Note that the channel length of the bottom gate type thin film transistor having an oxide semiconductor layer on the source electrode and the drain electrode corresponds to the shortest distance between the source electrode and the drain electrode and is the distance of the oxide semiconductor layer near the interface with the gate insulating film sandwiched between the source electrode and the drain electrode. It is. The distance of the oxide semiconductor layer near the interface with the gate insulating film sandwiched between the source electrode and the drain electrode. It is.

[0015] n + When forming a layer in contact with the upper surfaces of the drain electrode and the source electrode, if the conductivity of the natural oxide film formed on the side surfaces of the electrodes is low, the main path of the drain current is from the drain electrode through the n layer, through the oxide semiconductor layer near the interface on the side surface of the drain electrode, through the oxide semiconductor layer near the interface of the gate insulating film, through the oxide semiconductor layer near the interface on the side surface of the source electrode, and through the n + layer to reach the source electrode. The oxide semiconductor layer obtained by the sputtering method tends to have the film quality near the interface with the film formation surface affected by the material of the film formation surface. The oxide semiconductor layer has interfaces with the n + layer, the side surface of the source electrode (and the side surface of the drain electrode), and the interface with the gate insulating film, and has at least three interfaces with different materials. Therefore, in the oxide semiconductor layer, since the interface state with the natural oxide film on the side surface of the drain electrode is different from the interface state with the gate insulating film, the oxide semiconductor layer near the interface on the side surface of the drain electrode functions as a first electric field concentration relaxation region region. Also, since the interface state with the natural oxide film on the side surface of the source electrode is different from the interface state with the gate insulating film, the oxide semiconductor layer near the interface on the side surface of the source electrode functions as a second electric field concentration + relaxation region. film, and has at least three interfaces with different materials. Therefore, in the oxide semiconductor layer, since the interface state with the natural oxide film on the side surface of the drain electrode is different from the interface state with the gate insulating film, the oxide semiconductor layer near the interface on the side surface of the drain electrode functions as a first electric field concentration relaxation region region. Also, since the interface state with the natural oxide film on the side surface of the source electrode is different from the interface state with the gate insulating film, the oxide semiconductor layer near the interface on the side surface of the source electrode functions as a second electric field concentration relaxation region. relaxation region. As described above, the regions overlapping with the side surfaces of the source electrode and the drain electrode in the oxide semiconductor layer function as electric field concentration relaxation regions.

[0016] As described above, the regions overlapping with the side surfaces of the source electrode and the drain electrode in the oxide semiconductor layer function as electric field concentration relaxation regions. As described above, the regions overlapping with the side surfaces of the source electrode and the drain electrode in the oxide semiconductor layer function as electric field concentration relaxation regions.

[0017] The oxide semiconductor used in this specification forms a thin film represented by InMO 3 (ZnO) m (m > 0), and a thin film transistor using the thin film as a semiconductor layer is manufactured. Note that M is formed, and a thin film transistor using the thin film as a semiconductor layer is manufactured. Note that M is , indicating one or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co . For example, in addition to the case where M is Ga, there may be cases where other metal elements such as Ga and Ni or Ga and Fe are included. Further, in the above oxide semiconductor, in addition to the metal element contained as M, there are some that contain Fe, Ni, other transition metal elements, or oxides of the transition metals as impurity elements. In this specification, this thin film is also referred to as an In-Ga-Zn-O-based non-crystalline film.

[0018] The crystal structure of the In-Ga-Zn-O-based non-crystalline film is observed to be an amorphous structure by XRD analysis. The analyzed In-Ga-Zn-O-based non-crystalline film is heat-treated at 200 °C to 500 °C, typically 300 to 400 °C for 10 minutes to 100 minutes after film formation by sputtering.

[0019] The angles θ1 of the side surfaces of the source electrode in contact with the oxide semiconductor layer and θ2 of the side surfaces of the drain electrode are set to be 20° or more and less than 90°, and by increasing the distance from the upper end to the lower end of the electrode on the side surfaces of the source electrode and the drain electrode, the lengths of the first electric field concentration relaxation region and the second electric field concentration relaxation region are increased to relax the electric field concentration. Further, by increasing the film thicknesses of the source electrode and the drain electrode, the distance from the upper end to the lower end of the electrode on the side surfaces of the electrodes can also be increased.

[0020] Further, when the oxide semiconductor layer is formed by sputtering, the film thickness formed on the side surface of the electrode perpendicular to the substrate surface may be thinner than the film thickness formed on the upper surface of the electrode. The angles θ1 of the side surfaces of the source electrode in contact with the oxide semiconductor layer and θ2 of the side surfaces of the drain electrode are 20° or more and less than 90°. By satisfying the above condition, the uniformity of the film thickness can be improved even on the side surfaces, and the electric field concentration can be alleviated. It is also possible.

[0021] As shown in Figure 1, the line connecting the lower end of the side of the source electrode and the upper end of the side of the source electrode is If the line approximately coincides with the inclination of the side surface of the source electrode, the source electrode has a tapered shape. However, the angle θ1 between the substrate surface and the side surface of the source electrode can be called the first taper angle. In addition, a straight line that starts from the lower end of the drain electrode side and connects the upper end of the drain electrode side is If the slope of the drain electrode side surface is almost the same as the slope of the drain electrode side surface, the drain electrode is said to have a tapered shape. The angle θ2 between the substrate surface and the side surface of the drain electrode can also be called a second taper angle.

[0022] In addition, the shape of the electrode side surface is not limited to one angle, and at least the side of the source electrode The angle θ1 of the side surface of the end portion and the angle θ2 of the side surface of the lower end portion of the drain electrode are 20° to 90°. If it is less than this, the electrode side surface may have a step.

[0023] In addition, the configuration of another invention is a gate electrode on a substrate having an insulating surface, and an insulating film on the gate electrode. a source electrode and a drain electrode on the insulating layer; a side surface of the source electrode; The gate electrode and the oxide semiconductor layer are overlapped between the side surfaces of the drain electrode and the insulating layer. The angle between the substrate surface of the substrate and the side surface of the lower end of the source electrode and the angle between the substrate surface of the substrate and the drain electrode A semiconductor device characterized in that the angle between the bottom end and the side surface is 20° or more and less than 90°. be.

[0024] In the above-mentioned structure, the angle between the substrate surface of the substrate and the side surface of the lower end of the source electrode is Make it different from the angle formed by the upper end side of the source electrode. Also, in the above configuration, the base angle formed by the substrate surface and the side surface of the lower end of the drain electrode is different from the angle formed by the substrate surface of the substrate and the side surface of the upper end of the drain electrode. Note that since the cross-sectional shapes of the source electrode side surface and the drain electrode side surface facing each other across the oxide semiconductor layer go through the same etching process, they are substantially the same.

[0025] For example, make the angle of the side surface of the lower end of the source electrode (and drain electrode) different from the angle of the side surface of the upper end of the source electrode (and drain electrode), and the angle of the side surface of the upper end of the source electrode (and drain electrode) may be 90°. By making the angle of the side surface of the upper end of the source electrode (and drain electrode) larger than the angle of the side surface of the lower end of the source electrode (and drain electrode), the interval between the masks for forming the source electrode and the drain electrode can be designed to be narrow, and as a result the channel length can be designed to be short, for example, the channel length can be designed to be 1 μm to 10 μm.

[0026] Also, the side surface shape of the source electrode and the drain electrode may have a curved surface at least in part, for example, in the cross-sectional shape of the source electrode and the drain electrode, the lower end of the electrode may also have one curved surface determined by the center of the radius of curvature located outside the electrode. Also, the side surface shape of the source electrode and the drain electrode may have a cross-sectional shape that flares out from the upper surface of the electrode toward the substrate.

[0027] The formation of the electrodes having the various cross-sectional shapes described above is performed by dry etching or wet etching. As the etching apparatus used for dry etching, reactive ion etching, etc. can be used. As the etching apparatus used for dry etching, reactive ion ​​​​​An etching apparatus using a reactive ion etching (RIE) method, or a dry etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductively Coupled Plasma) can be used. yclotron Resonance) or ICP (Inductively Coup led Plasma). In addition, as a dry etching apparatus that can easily obtain a uniform discharge over a wide area compared to an ICP etching apparatus, there is an etching apparatus in an ECCP (Enhanced Capacitively Coupled Plasma) mode in which the upper electrode is grounded, a high-frequency power source of 13.56 MHz is connected to the lower electrode, and a low-frequency power source of 3.2 MHz is further connected to the lower electrode. With this ECCP mode etching apparatus, for example, it is possible to handle even when using a substrate with a size exceeding 3 m of the 10th generation as the substrate. Furthermore, the source electrode and the drain electrode may be a single layer, or may be a multilayer of two or more layers made of at least two different materials. Hz high-frequency power source, and a low-frequency power source of 3.2 MHz is further connected to the lower electrode. CP (Enhanced Capacitively Coupled Plasma) mode etching apparatus. With this ECCP mode etching apparatus, for example, even when using a substrate with a size exceeding 3 m of the 10th generation as the substrate, it is possible to handle it.

[0028] Also, one configuration of the invention regarding the manufacturing method for realizing the above structure is a manufacturing method of a semiconductor device in which a gate electrode is formed on a substrate having an insulating surface, a gate insulating layer covering the gate electrode is formed, a conductive layer and a buffer layer are laminated on the gate insulating layer without exposure to the atmosphere, the buffer layer and the conductive layer are selectively etched to form a source electrode and a drain electrode having a side surface with an angle of 20° or more and less than 90° with respect to the substrate surface of the substrate, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode, and the drain electrode.

[0029] Also, one configuration of the invention regarding the manufacturing method for realizing the above structure is a manufacturing method of a semiconductor device in which a gate electrode is formed on a substrate having an insulating surface, a gate insulating layer covering the gate electrode is formed, a conductive layer and a buffer layer are laminated on the gate insulating layer without exposure to the atmosphere, the buffer layer and the conductive layer are selectively etched to form a source electrode and a drain electrode having a side surface with an angle of 20° or more and less than 90° with respect to the substrate surface of the substrate, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode, and the drain electrode. A gate electrode is formed on a substrate having an insulating surface, a gate insulating layer covering the gate electrode is formed, a conductive layer and a buffer layer are laminated on the gate insulating layer without exposure to the atmosphere, the buffer layer and the conductive layer are selectively etched to form a source electrode and a drain electrode having a side surface with an angle of 20° or more and less than 90° with respect to the substrate surface of the substrate, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode, and the drain electrode. A gate electrode is formed on a substrate having an insulating surface, a gate insulating layer covering the gate electrode is formed, a conductive layer and a buffer layer are laminated on the gate insulating layer without exposure to the atmosphere, the buffer layer and the conductive layer are selectively etched to form a source electrode and a drain electrode having a side surface with an angle of 20° or more and less than 90° with respect to the substrate surface of the substrate, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode, and the drain electrode. A gate electrode is formed on a substrate having an insulating surface, a gate insulating layer covering the gate electrode is formed, a conductive layer and a buffer layer are laminated on the gate insulating layer without exposure to the atmosphere, the buffer layer and the conductive layer are selectively etched to form a source electrode and a drain electrode having a side surface with an angle of 20° or more and less than 90° with respect to the substrate surface of the substrate, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode, and the drain electrode. A gate electrode is formed on a substrate having an insulating surface, a gate insulating layer covering the gate electrode is formed, a conductive layer and a buffer layer are laminated on the gate insulating layer without exposure to the atmosphere, the buffer layer and the conductive layer are selectively etched to form a source electrode and a drain electrode having a side surface with an angle of 20° or more and less than 90° with respect to the substrate surface of the substrate, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode, and the drain electrode. A gate electrode is formed on a substrate having an insulating surface, a gate insulating layer covering the gate electrode is formed, a conductive layer and a buffer layer are laminated on the gate insulating layer without exposure to the atmosphere, the buffer layer and the conductive layer are selectively etched to form a source electrode and a drain electrode having a side surface with an angle of 20° or more and less than 90° with respect to the substrate surface of the substrate, and an oxide semiconductor layer is formed on the gate insulating layer, the source electrode, and the drain electrode.

[0030] ​​In the configuration related to the above manufacturing method, the buffer layer contains indium, gallium, and zinc and the same target as the oxide semiconductor layer formed on the buffer layer can be used. By changing the film formation atmosphere, the buffer layer and the oxide semiconductor layer can be differentiated and the manufacturing cost can be reduced by using a common target.

[0031] In the configuration related to the above manufacturing method, the conductive layer and the buffer layer are laminated on the gate insulating layer without being exposed to the air and one of the features is to perform continuous film formation.

[0032] In the configuration related to the above manufacturing method, the conductive layer for forming the source electrode and the drain electrode is formed using a metal material such as aluminum, tungsten, chromium, tantalum, titanium, molybdenum or an alloy material thereof. Further, the conductive layer may be a laminate of two or more layers, for example, a laminate having an aluminum film as the lower layer and a titanium film as the upper layer, a laminate having a tungsten film as the lower layer and a molybdenum film as the upper layer, a laminate having an aluminum film as the lower layer and a molybdenum film as the upper layer, etc. can be used.

[0033] In this specification, continuous film formation means that during a series of processes from the first film formation step performed by sputtering to the second film formation step performed by sputtering, the atmosphere in which the substrate to be processed is placed does not come into contact with a contaminated atmosphere such as air and is always controlled in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere). By performing continuous film formation, film formation can be performed while avoiding reattachment of moisture and the like to the cleaned substrate to be processed. Performing a series of processes from the first film formation step to the second film formation step in the same chamber

[0034] ​ is assumed to be within the scope of continuous film formation in this specification.

[0035] Also, when performing a series of processes from the first film formation step to the second film formation step in different chambers, after completing the first film formation step, the substrate is transported between the chambers without being exposed to the atmosphere, and performing the second film formation is also assumed to be within the scope of continuous film formation in this specification.

[0036] Note that between the first film formation step and the second film formation step, there may be a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc., and it is assumed to be within the scope of continuous film formation in this specification.

[0037] However, when a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as defined in this specification. shall not apply.

[0038] In this specification, words indicating directions such as up, down, side, horizontal, vertical, etc. refer to the directions based on the substrate surface when a device is placed on the substrate surface. shall be used as a reference.

[0039] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate specific names for identifying the invention in this specification. shall not apply.

Advantages of the Invention

[0040] By adjusting the angle formed between the substrate surface of the substrate and the side surface of the source electrode, and the angle formed between the substrate surface of the substrate and the side surface of the drain electrode, the coverage of the oxide semiconductor layer provided on the source electrode and the drain electrode is improved. shall be improved.

[0041] By providing an electric field concentration relaxation region, the possible electric field concentration generated between the source electrode and the drain electrode is relaxed, and deterioration of the switching characteristics of the thin film transistor is suppressed.

Brief Description of the Drawings

[0042]

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Mode for Carrying Out the Invention

[0043] This embodiment will be described below.

[0044] (Embodiment 1) FIG. 1 shows an example of providing a thin film transistor 170 on a substrate. Note that FIG. 1 is an example of a cross-sectional view of a thin film transistor is shown.

[0045] The gate electrode 101 provided on the substrate 100 having an insulating surface is covered with a gate insulating layer 102, and a first wiring or a second wiring is provided on the gate insulating layer 102 overlapping the gate electrode 101. A buffer layer is provided on each of the first wiring or the second wiring that functions as the source electrode layer 105a or the drain electrode layer 105b. A first buffer layer 104a is provided on the source electrode layer 105a, and a second buffer layer is provided on the drain electrode layer 105b. And an oxide semiconductor layer 103 is provided on the first buffer layer 104a and the second buffer layer 104b. On the source electrode layer 105a, a first buffer layer 104a is provided, and on the drain electrode layer 105b, a second buffer layer 104b is provided. And on the first buffer layer 104a and the second buffer layer 104b, there is an oxide semiconductor layer 103.

[0046] In FIG. 1, for the substrate 100 having translucency, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning's 7059 glass or 173 7 glass can be used.

[0047] The gate electrode 101 is made of a single layer or a laminate made of different metal materials. Also, the material of the gate electrode 101 is a metal material (aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neo dymium), etc.). ​An element selected from Y (yttrium), Sc (scandium), or an alloy containing the above-described elements as components ) is used, and the angle of the side surface of the gate electrode 101 is set to be 20° or more and less than 90°. At least at the end portion is etched so that a tapered shape is formed to form the gate electrode 101.

[0048] Also, the gate insulating layer 102 may be formed as a single layer or a laminated structure made of these materials using an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, or a tantalum oxide film obtained by a sputtering method or a plasma CVD method. Note that when etching the source electrode layer 105a and the drain electrode layer 105b formed on the gate insulating layer 102 it is preferable to select a material with a sufficient selectivity ratio. Also, when etching the source electrode layer 105a and the drain electrode layer 105b, the surface of the gate insulating layer 102 may be etched to about 20 nm, and it is preferable to remove a little surface layer to eliminate etching residues of the metal material.

[0049] The source electrode layer 105a and the drain electrode layer 105b are formed as a single layer or a laminate made of different metal materials. The materials of the source electrode layer 105a and the drain electrode layer 105b are metal materials ( aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), Sc (scandium )), an element selected from the above, or an alloy containing the above-described elements as components) are used.

[0050] As shown in FIG. 1, the cross-sectional shape of the source electrode layer 105a is such that the angle θ1 formed by the substrate surface of the substrate and the side surface of the source electrode layer 105a is 20° or more and less than 90°. Also, the drain electrode layer 1 05a ​​​​​As shown in FIG. 1, the cross-sectional shape of 05b is such that the angle θ2 formed by the substrate surface of the substrate and the side surface of the drain electrode layer 105b is 20° or more and less than 90°. Since they are formed by the same etching process (dry etching or wet etching), the angle θ1 and the angle θ2 are substantially the same. By setting the angle θ1 of the side surface of the source electrode layer 105a in contact with the oxide semiconductor layer and the angle θ2 of the side surface of the drain electrode layer 105b to 20° or more and less than 90°, the distance from the upper end to the lower end of the electrode on the side surfaces of the source electrode layer 105a and the drain electrode layer 105b is increased. Since they are formed by the same etching process (dry etching or wet etching), the angle θ1 and the angle θ2 are substantially the same. As shown in FIG. 1, the cross-sectional shape of 05b is such that the angle θ2 formed by the substrate surface of the substrate and the side surface of the drain electrode layer 105b is 20° or more and less than 90°. By setting the angle θ1 of the side surface of the source electrode layer 105a in contact with the oxide semiconductor layer and the angle θ2 of the side surface of the drain electrode layer 105b to 20° or more and less than 90°, the distance from the upper end to the lower end of the electrode on the side surfaces of the source electrode layer 105a and the drain electrode layer 105b is increased. By setting the angle θ1 of the side surface of the source electrode layer 105a in contact with the oxide semiconductor layer and the angle θ2 of the side surface of the drain electrode layer 105b to 20° or more and less than 90°, the distance from the upper end to the lower end of the electrode on the side surfaces of the source electrode layer 105a and the drain electrode layer 105b is increased.

[0051] In FIG. 1, the back plane of the substrate is used as the substrate surface to represent the angles θ1 and θ2. However, it is not particularly limited. Since the front plane and the back plane of the substrate are parallel, it goes without saying that they have the same angle when the front plane of the substrate is used as the substrate surface. In FIG. 1, the back plane of the substrate is used as the substrate surface to represent the angles θ1 and θ2. However, it is not particularly limited. Since the front plane and the back plane of the substrate are parallel, it goes without saying that they have the same angle when the front plane of the substrate is used as the substrate surface. In FIG. 1, the back plane of the substrate is used as the substrate surface to represent the angles θ1 and θ2. However, it is not particularly limited. Since the front plane and the back plane of the substrate are parallel, it goes without saying that they have the same angle when the front plane of the substrate is used as the substrate surface.

[0052] The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is a film formed using a target of an oxide semiconductor containing In, Ga, and Zn (InO:GaO:ZnO = 1:1:1) with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon atmosphere containing oxygen. After that, a resist mask is formed and selectively etched to remove unnecessary portions. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is a film formed using a target of an oxide semiconductor containing In, Ga, and Zn (InO:GaO:ZnO = 1:1:1) with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon atmosphere containing oxygen. After that, a resist mask is formed and selectively etched to remove unnecessary portions. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is a film formed using a target of an oxide semiconductor containing In, Ga, and Zn (InO:GaO:ZnO = 1:1:1) with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon atmosphere containing oxygen. After that, a resist mask is formed and selectively etched to remove unnecessary portions. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1) is used, and the film is formed in an argon atmosphere containing oxygen with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW. After that, a resist mask is formed and selectively etched to remove unnecessary portions. The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is a film formed using a target of an oxide semiconductor containing In, Ga, and Zn (InO:GaO:ZnO = 1:1:1) with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon atmosphere containing oxygen. After that, a resist mask is formed and selectively etched to remove unnecessary portions. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is a film formed using a target of an oxide semiconductor containing In, Ga, and Zn (InO:GaO:ZnO = 1:1:1) with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon atmosphere containing oxygen. After that, a resist mask is formed and selectively etched to remove unnecessary portions. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is a film formed using a target of an oxide semiconductor containing In, Ga, and Zn (InO:GaO:ZnO = 1:1:1) with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon atmosphere containing oxygen. After that, a resist mask is formed and selectively etched to remove unnecessary portions. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. The oxide semiconductor layer 103 is formed on the source electrode layer 105a and the drain electrode layer 105b having such shapes. The oxide semiconductor layer 103 is a film formed using a target of an oxide semiconductor containing In, Ga, and Zn (InO:GaO:ZnO = 1:1:1) with a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon atmosphere containing oxygen. After that, a resist mask is formed and selectively etched to remove unnecessary portions. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. The film thickness of the oxide semiconductor film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the oxide semiconductor film is 100 nm. ​

[0053] Note that a first buffer layer 104a is preferably provided between the source electrode layer 105a and the oxide semiconductor layer 103. Also, a second buffer layer 104b is preferably provided between the drain electrode layer 105b and the oxide semiconductor layer 103. Note that a first buffer layer 104a is preferably provided between the source electrode layer 105a and the oxide semiconductor layer 103. Also, a second buffer layer 104b is preferably provided between the drain electrode layer 105b and the oxide semiconductor layer 103. Note that a first buffer layer 104a is preferably provided between the source electrode layer 105a and the oxide semiconductor layer 103. Also, a second buffer layer 104b is preferably provided between the drain electrode layer 105b and the oxide semiconductor layer 103.

[0054] The first buffer layer 104a and the second buffer layer 104b are oxide semiconductor layers (n-type layers) having a lower resistance than the oxide semiconductor layer 103 and function as source regions or drain regions. The first buffer layer 104a and the second buffer layer 104b are oxide semiconductor layers (n-type layers) having a lower resistance than the oxide semiconductor layer 103 and function as source regions or drain regions. + The first buffer layer 104a and the second buffer layer 104b are oxide semiconductor layers (n-type layers) having a lower resistance than the oxide semiconductor layer 103 and function as source regions or drain regions. The first buffer layer 104a and the second buffer layer 104b are oxide semiconductor layers (n-type layers) having a lower resistance than the oxide semiconductor layer 103 and function as source regions or drain regions.

[0055] n + The n-type layer uses a target with InO:GaO:ZnO = 1:1:1, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced to perform sputtering film formation. Despite intentionally using a target with InO:GaO:ZnO = 1:1:1, an In-Ga-Zn-O based polycrystalline film containing crystal grains with a size of 1 nm to 10 nm may be formed immediately after film formation. 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced to perform sputtering film formation. Despite intentionally using a target with InO:GaO:ZnO = 1:1:1, an In-Ga-Zn-O based polycrystalline film containing crystal grains with a size of 1 nm to 10 nm may be formed immediately after film formation. :ZnO = 1:1:1, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced to perform sputtering film formation. Despite intentionally using a target with InO:GaO:ZnO = 1:1:1, an In-Ga-Zn-O based polycrystalline film containing crystal grains with a size of 1 nm to 10 nm may be formed immediately after film formation. :ZnO = 1:1:1, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced to perform sputtering film formation. Despite intentionally using a target with InO:GaO:ZnO = 1:1:1, an In-Ga-Zn-O based polycrystalline film containing crystal grains with a size of 1 nm to 10 nm may be formed immediately after film formation. 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced to perform sputtering film formation. Despite intentionally using a target with InO:GaO:ZnO = 1:1:1, an In-Ga-Zn-O based polycrystalline film containing crystal grains with a size of 1 nm to 10 nm may be formed immediately after film formation. 1:1:1, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced to perform sputtering film formation. Despite intentionally using a target with InO:GaO:ZnO = 1:1:1, an In-Ga-Zn-O based polycrystalline film containing crystal grains with a size of 1 nm to 10 nm may be formed immediately after film formation. 1:1:1, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm introduced to perform sputtering film formation. Despite intentionally using a target with InO:GaO:ZnO = 1:1:1, an In-Ga-Zn-O based polycrystalline film containing crystal grains with a size of 1 nm to 10 nm may be formed immediately after film formation. 3000 W:8-inch φ), temperature (room temperature to 100 °C), reactive sputtering film formation conditions, etc., can be adjusted as appropriate, and it can be said that the presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted in the range of 1 nm to 10 nm. The film thickness of the second In-Ga-Zn-O based polycrystalline film is 5 nm to 20 nm. Of course, when crystal grains are contained in the film, the size of the contained crystal grains 3000 W:8-inch φ), temperature (room temperature to 100 °C), reactive sputtering film formation conditions, etc., can be adjusted as appropriate, and it can be said that the presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted in the range of 1 nm to 10 nm. The film thickness of the second In-Ga-Zn-O based polycrystalline film is 5 nm to 20 nm. Of course, when crystal grains are contained in the film, the size of the contained crystal grains 3000 W:8-inch φ), temperature (room temperature to 100 °C), reactive sputtering film formation conditions, etc., can be adjusted as appropriate, and it can be said that the presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted in the range of 1 nm to 10 nm. The film thickness of the second In-Ga-Zn-O based polycrystalline film is 5 nm to 20 nm. Of course, when crystal grains are contained in the film, the size of the contained crystal grains 3000 W:8-inch φ), temperature (room temperature to 100 °C), reactive sputtering film formation conditions, etc., can be adjusted as appropriate, and it can be said that the presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted in the range of 1 nm to 10 nm. The film thickness of the second In-Ga-Zn-O based polycrystalline film is 5 nm to 20 nm. Of course, when crystal grains are contained in the film, the size of the contained crystal grains In this embodiment, the second In-Ga-Zn-O system non-single crystal The thickness of the crystal film is 5 nm.

[0056] In addition, a conductive film to be the source electrode layer 105a or the drain electrode layer 105b and + Layered Acid The source is then removed during the manufacturing process by depositing the semiconductor film by sputtering without exposing it to the atmosphere. This can prevent the electrode layer or the drain electrode layer from being exposed and causing dust to adhere thereto.

[0057] The oxide semiconductor layer 103 obtained by a sputtering method has a film quality near the interface with a surface on which the film is to be formed. The oxide semiconductor layer is affected by the material of the n + layer, the interface with the source electrode layer The gate insulating film is made of a different material. Therefore, in the oxide semiconductor layer 103, the drain electrode The interface state between the native oxide film on the side of the gate electrode and the gate insulating film is different. The oxide semiconductor layer near the interface of the electrode layer side functions as a first electric field concentration alleviation region 106a. In addition, the interface state between the source electrode and the native oxide film on the side surface is different from the interface state between the source electrode and the gate insulating film. Therefore, the oxide semiconductor layer near the interface on the side of the source electrode becomes the second electric field concentration relaxation region 106. Functions as b. Angle θ1 of the side surface of the source electrode in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode is set to 20° or more and less than 90°, and the angle from the upper end of the electrode on the side surface of the source electrode and the drain electrode is By increasing the distance to the lower end of the electrode, the length L of the first electric field concentration alleviation region 106a is The length L2 of the first and second electric field concentration relief regions 106b is increased to relieve the electric field concentration. By increasing the film thickness of the source electrode and the drain electrode, the distance from the upper end to the lower end of the electrode on the side surface of the electrode can also be increased. The distance from the upper end of the electrode to the lower end of the electrode can be increased.

[0058] Further, when the oxide semiconductor layer 103 is formed by sputtering, the film thickness formed on the side surface of the electrode perpendicular to the substrate surface may be thinner than the film thickness formed on the upper surface of the electrode. The angles θ1 of the side surface of the source electrode in contact with the oxide semiconductor layer and θ2 of the side surface of the drain electrode are set to 20° or more and less than 90°. By doing so, the film thickness uniformity can be improved even on the side surface, the region where the oxide semiconductor layer 103 becomes locally thin can be reduced, and the electric field concentration can also be alleviated. The angles θ1 of the side surface of the source electrode in contact with the oxide semiconductor layer and θ2 of the side surface of the drain electrode are set to 20° or more and less than 90°. By doing so, the film thickness uniformity can be improved even on the side surface, the region where the oxide semiconductor layer 103 becomes locally thin can be reduced, and the electric field concentration can also be alleviated. 103. The region where the oxide semiconductor layer 103 becomes locally thin can be reduced, and the electric field concentration can also be alleviated.

[0059] (Embodiment 2) In FIG. 1, an example is shown in which a straight line connecting the lower end of the side surface of the source electrode layer (drain electrode layer) as a starting point and the upper end of the side surface of the source electrode layer (drain electrode layer) substantially coincides with the inclination of the side surface of the source electrode layer (drain electrode layer). However, in the present embodiment, an example having a step on the side surface of the source electrode layer (drain electrode layer) will be described with reference to FIG. 2. If at least the angle θ1 of the side surface of the lower end portion of the source electrode layer and the angle θ2 of the side surface of the lower end portion of the drain electrode layer are 20° or more and less than 90°, the electrode may have a step on the side surface. In FIG. 2, the same reference numerals are used for the portions common to FIG. 1. The gate electrode 101 provided on the substrate 100 having an insulating surface is covered with the gate insulating layer 102, and a first wiring or a second wiring is provided on the gate insulating layer 102 overlapping the gate electrode 101. On the first wiring or the second wiring functioning as the source electrode layer 405a or the drain electrode layer 405b, buffer layers are respectively provided. On the source electrode layer 405a .

[0060] The gate electrode 101 provided on the substrate 100 having an insulating surface is covered with the gate insulating layer 102, and a first wiring or a second wiring is provided on the gate insulating layer 102 overlapping the gate electrode 101. A buffer layer is provided on each of the first wiring or the second wiring functioning as the source electrode layer 405a or the drain electrode layer 405b. On the source electrode layer 405a covered by the gate insulating layer 102, a first wiring or a second wiring is provided on the gate insulating layer 102 overlapping the gate electrode 101. A buffer layer is provided on each of the first wiring or the second wiring functioning as the source electrode layer 405a or the drain electrode layer 405b. On the source electrode layer 405a covered by the gate insulating layer 102, a first wiring or a second wiring is provided on the gate insulating layer 102 overlapping the gate electrode 101. A buffer layer is provided on each of the first wiring or the second wiring functioning as the source electrode layer 405a or the drain electrode layer 405b. On the source electrode layer 405a covered by the gate insulating layer 102, a first wiring or a second wiring is provided on the gate insulating layer 102 overlapping the gate electrode 101. A buffer layer is provided on each of the first wiring or the second wiring functioning as the source electrode layer 405a or the drain electrode layer 405b. On the source electrode layer 405a On the top, a first buffer layer 404a is provided, and on the drain electrode layer 405b, a second buffer layer 404b is provided. Then, an oxide semiconductor layer 403 is provided on the first buffer layer 404a and the second buffer layer 404b.

[0061] Regarding the substrate 100 having an insulating surface, the gate electrode 101, and the gate insulating layer 102, since they are the same as those in Embodiment 1, detailed description thereof is omitted here.

[0062] In addition, the source electrode layer 405a and the drain electrode layer 405b are a single layer or a laminate made of different metal materials. The materials of the source electrode layer 405a and the drain electrode layer 405b are metal materials (elements selected from aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), Sc (scandium), or alloys containing the above-described elements as components).

[0063] Here, a single layer of a tungsten film with a thickness of 100 nm is used as the source electrode layer 405a and the drain electrode layer 405b, and an ICP etching apparatus using a coil-shaped antenna is used to form the side surface shapes of the source electrode layer 405a and the drain electrode layer 405b shown in FIG. 2. An example will be described.

[0064] In this embodiment, the gas flow rate of CF 4 is 25 (sccm), the gas flow rate of Cl 3 is 25 (s ccm), the gas flow rate of O 2 is 10 (sccm), and RF (13.56 MHz) power of 500 W is applied to a coil-type electrode at a pressure of 1.5 Pa to generate plasma for etching. Perform. Apply 10 W of RF (13.56 MHz) power to the substrate side (sample stage) as well, and apply a substantially negative self-bias voltage. When at least the gate insulating film 102 is exposed to a certain extent, stop this etching midway, thereby forming a stepped electrode side surface.

[0065] Under the above etching conditions, the cross-sectional shape of the source electrode layer 405a can be such that the angle θ1 formed by the substrate surface of the substrate and the lower end side surface of the source electrode layer 405a is 20° or more and less than 90°. As shown in FIG. 2, θ1 is about 40°. Also, the angle formed by the substrate surface of the substrate and the upper end side surface of the source electrode layer 405 a is about 90°. Note that the cross-sectional shapes of the source electrode layer 405a side surface and the drain electrode layer 405b side surface facing each other across the oxide semiconductor layer 403 are substantially the same because they go through the same etching process.

[0066] In this way, by making the angle of the side surface of the upper end of the source electrode layer 405a (and the drain electrode layer 405b) larger than the angle of the side surface of the lower end of the source electrode layer 405a (and the drain electrode layer 405b), the interval of the photomask (or resist mask) for forming the source electrode layer 405a and the drain electrode layer 405b can be designed to be narrow. As a result, the channel length can be designed to be short. For example, the channel length can be designed to be 1 μm to 10 μm.

[0067] Also, not limited to the above method, stack materials with different etching rates of the etching gas used for the source electrode layer 405a and the drain electrode layer 405b, make the lower layer a material layer with a low etching rate and the upper layer a material layer with a high etching rate, and when etching, a step can be formed on the electrode side surface. ​​​​​​

[0068] By providing steps on two opposing electrode side surfaces sandwiching the oxide semiconductor layer 403, the distance from the upper end to the lower end of the electrodes on the side surfaces of the source electrode layer and the drain electrode layer is increased to lengthen the length L3 of the first electric field concentration relaxation region 406a and the length L4 of the second electric field concentration relaxation region 406b, thereby relaxing the electric field concentration.

[0069] Furthermore, in order to increase the distance from the upper end to the lower end of the electrodes on the side surfaces of the source electrode layer and the drain electrode layer, after the above-described dry etching, wet etching may be further performed to provide a curved surface on a part of the two opposing electrode side surfaces sandwiching the oxide semiconductor layer 403.

[0070] Alternatively, instead of the above-described dry etching, wet etching may be performed for forming the source electrode layer and the drain electrode layer, such that at least the angle θ1 of the side surface of the lower end portion of the source electrode layer and the angle θ2 of the side surface of the lower end portion of the drain electrode layer are 20° or more and less than 90°, and the cross-sectional shape may be flaring from the upper surface of the electrode toward the substrate.

[0071] Also, this embodiment can be freely combined with Embodiment 1.

[0072] (Embodiment 3) In this embodiment, the thin film transistor and its manufacturing process will be described with reference to FIGS. 3 to 9.

[0073]

[0073] In FIG. 3(A), a glass substrate such as barium borosilicate glass or aluminosilicate glass can be used as the substrate 100 having translucency.

[0074] Next, after forming a conductive layer over the entire surface of the substrate 100, a first photolithography process is performed, a resist mask is formed, and unnecessary portions are removed by etching to form wiring and electrodes (gate wiring including the gate electrode 101, capacitor wiring 108, and the first terminal 121). At this time, etching is performed such that a tapered shape is formed at least at the ends of the gate electrode 101. The top view at this stage is shown in FIG. 3(A). Note that the top view at this stage corresponds to FIG. 5.

[0075] The gate wiring including the gate electrode 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion are made of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium ( Cr), neodymium (Nd), aluminum (Al), copper (Cu), an element selected therefrom, or an alloy containing the above-described elements as components, an alloy film combining the above-described elements, or a nitride containing the above-described elements as components. Among these, it is desirable to form them using a low-resistance conductive material such as aluminum (Al) or copper (Cu). However, since pure Al has poor heat resistance and is prone to corrosion, etc., they are formed of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), an element selected therefrom, or an alloy film combining the above-described elements, or a nitride containing the above-described elements as components.

[0076] Next, a gate insulating layer 102 is formed over the entire surface on the gate electrode 101. The gate insulating layer 10 2 is formed by a sputtering method or the like, and the film thickness is set to 50 to 250 nm.

[0077] For example, a silicon oxide film is used as the gate insulating layer 102 by a sputtering method, and 100 nm ​It is formed with such thickness. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film but other insulating films such as silicon oxynitride film, silicon nitride film, aluminum oxide, tantalum oxide film may be used and formed as a single layer or a laminated structure made of these materials too.

[0078] Next, a conductive film made of a metal material is formed on the gate insulating layer 102 by sputtering or vacuum evaporation method. As the material of the conductive film, elements selected from Al, Cr, Ta, Ti, Mo, W, or an alloy containing the above-mentioned elements as components, or an alloy film combining the above-mentioned elements, etc. can be mentioned Here, an aluminum (Al) film is used as the conductive film, and a Ti film is laminated on the aluminum (Al) film Also, the conductive film may have a three-layer structure, and a titanium film may be laminated on a tungsten film Also, the conductive film may have a single-layer structure of an aluminum film containing silicon or a single-layer structure of a tungsten film too.

[0079] Next, a first oxide semiconductor film (in this embodiment, a first In-Ga-Zn-O system non-single crystal film) is formed on the conductive film by sputtering. Here, In 2 O 3 :Ga 2 O 3 :ZnO= 1:1:1 target is used, and the film formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and an argon gas flow rate of 40 sccm are introduced for sputtering film formation to be performed. Despite intentionally using a target with In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1, immediately after film formation, it contains In-Ga-Zn crystal grains with a size of 1 nm to 10 nm even though it is intended. An -O-based polycrystalline film may be formed. Note that the component ratio of the target, the film formation pressure (0. 1 Pa to 2.0 Pa), the power (250 W to 3000 W: 8-inch φ), the temperature (room temperature to 10 0 °C), the film formation conditions of reactive sputtering, etc. can be appropriately adjusted to control the presence or absence of crystal grains, the density, and the diameter size of the crystal grains, which can be said to be adjustable in the range of 1 nm to 10 nm. The thickness of the first In- Ga-Zn-O-based polycrystalline film is set to 5 nm to 20 nm. Of course, when crystal grains are included in the film, the size of the included crystal grains does not exceed the film thickness. In this embodiment the thickness of the first In-Ga-Zn-O-based polycrystalline film is set to 5 nm.

[0080] Next, a second photolithography process is performed to form a resist mask, and the first In- Ga-Zn-O-based polycrystalline film is etched. Here, wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) is used to remove unnecessary portions in the pixel portion to form the first In -Ga-Zn-O-based polycrystalline films 111a and 111b. Note that the etching here is not limited to wet etching, and dry etching may also be used.

[0081] Next, using the same resist mask as the etching of the first In-Ga-Zn-O-based polycrystalline film, unnecessary portions are removed by etching to form the source electrode layer 105a and the drain electrode layer 105b. As the etching method at this time, wet etching or dry etching is used. Here, a conductive film formed by laminating an Al film and a Ti film is etched by dry etching using a mixed gas of SiCl and Cl 4 and BCl 2 as the reaction gas 3 to form the source electrode ​​Form the top layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in FIG. 3(B) as shown. Note that the top view at this stage corresponds to FIG. 6.

[0082] By the etching here, the angle θ1 of the side surface of the source electrode layer 105a in contact with the oxide semiconductor layer to be formed later and the angle θ2 of the side surface of the drain electrode layer 105b are made 20° or more and less than 90° so as to be. By making the two electrode side surfaces facing each other across the oxide semiconductor layer into a tapered shape, the acid The region overlapping the side surface of the source electrode layer and the side surface of the drain electrode layer in the oxide semiconductor layer can function as a critical concentration relaxation region.

[0083] Also, in this second photolithography process, the second terminal 122 made of the same material as the source electrode layer 105a and the drain electrode layer 105b is left at the terminal portion. Note that the second terminal 122 is electrically connected to the source wiring (source wiring including the source electrode layer 105a). Also, in the terminal portion, the first In-Ga-Zn-O-based non-single crystal film 123 that exists above the second terminal 122 and overlaps the second terminal 122 remains.

[0084] Also, in the capacitor portion, a capacitor electrode layer 124 made of the same material as the source electrode layer 105a and the drain electrode layer 105b is left. Also, in the capacitor portion, the first In-Ga-Zn-O-based non-single crystal film 111c that exists above the capacitor electrode layer 124 and overlaps the capacitor electrode layer 124 remains.

[0085] Next, after removing the resist mask, without exposing to the atmosphere, a second oxide semiconductor film (in the form of the second In-Ga-Zn-O-based non-single crystal film in this embodiment) is formed. After plasma treatment, large ​​​Forming the second In-Ga-Zn-O based non-single crystal film without exposure is useful in that it does not attach dust or the like to the interface between the gate insulating layer and the semiconductor film. Here, an oxide semiconductor target (InO:GaO:ZnO = 1:1:1) containing In, Ga, and Zn with a diameter of 8 inches is used, and the film is formed at a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon or oxygen atmosphere. Note that using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the second In-Ga-Zn-O based non-single crystal film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the second In-Ga-Zn-O based non-single crystal film is set to 100 nm. It is useful in that it does not attach dust or the like to the interface between the gate insulating layer and the semiconductor film. Here, an oxide semiconductor target (InO:GaO:ZnO = 1:1:1) containing In, Ga, and Zn with a diameter of 8 inches is used, and the film is formed at a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon or oxygen atmosphere. oxide semiconductor target (In 2 O 3 :Ga 2 O 3 :Z nO=1:1:1) is used, and the film is formed at a distance of 170 mm between the substrate and the target, a pressure of 0.4 Pa, a DC power supply of 0.5 kW, and in an argon or oxygen atmosphere. Pa, a DC power supply of 0.5 kW, and in an argon or oxygen atmosphere. Note that using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. Using a pulsed DC power supply is preferable because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the second In-Ga-Zn-O based non-single crystal film is set to 5 nm to 200 nm. In this embodiment, the film thickness of the second In-Ga-Zn-O based non-single crystal film is set to 100 nm. The film thickness of the second In-Ga-Zn-O based non-single crystal film is set to 100 nm.

[0086] By making the forming conditions of the second In-Ga-Zn-O based non-single crystal film different from those of the first In-Ga-Zn-O based non-single crystal film, a film with higher electrical resistance than the first In-Ga-Zn-O based non-single crystal film is obtained. For example, the ratio of the oxygen gas flow rate to the argon gas flow rate in the forming conditions of the second In-Ga-Zn-O based non-single crystal film is made higher than the ratio in the forming conditions of the first In-Ga-Zn-O based non-single crystal film. Specifically, the forming conditions of the first In-Ga-Zn-O based non-single crystal film are in a rare gas (argon, helium, etc.) atmosphere (or oxygen gas 10% or less, argon gas 90% or more), and the forming conditions of the second In-Ga-Zn-O based non-single crystal film are in an oxygen atmosphere (or the ratio of the oxygen gas flow rate to the argon gas flow rate is 1:1 or more). By making the forming conditions of the second In-Ga-Zn-O based non-single crystal film different from those of the first In-Ga-Zn-O based non-single crystal film, a film with higher electrical resistance than the first In-Ga-Zn-O based non-single crystal film is obtained. For example, the ratio of the oxygen gas flow rate to the argon gas flow rate in the forming conditions of the second In-Ga-Zn-O based non-single crystal film is made higher than the ratio in the forming conditions of the first In-Ga-Zn-O based non-single crystal film. The forming conditions of the second In-Ga-Zn-O based non-single crystal film are such that the ratio of the oxygen gas flow rate to the argon gas flow rate is higher than the ratio in the forming conditions of the first In-Ga-Zn-O based non-single crystal film. Specifically, the forming conditions of the first In-Ga-Zn-O based non-single crystal film are in a rare gas (argon, helium, etc.) atmosphere (or oxygen gas 10% or less, argon gas 90% or more), and the forming conditions of the second In-Ga-Zn-O based non-single crystal film are in an oxygen atmosphere (or the ratio of the oxygen gas flow rate to the argon gas flow rate is 1:1 or more). The forming conditions of the first In-Ga-Zn-O based non-single crystal film are in a rare gas (argon, helium, etc.) atmosphere (or oxygen gas 10% or less, argon gas 90% or more), and the forming conditions of the second In-Ga-Zn-O based non-single crystal film are in an oxygen atmosphere (or the ratio of the oxygen gas flow rate to the argon gas flow rate is 1:1 or more). atmosphere (or oxygen gas 10% or less, argon gas 90% or more), and the forming conditions of the second In-G a-Zn-O based non-single crystal film are in an oxygen atmosphere (or the ratio of the oxygen gas flow rate to the argon gas flow rate is 1:1 or more). The forming conditions of the second In-Ga-Zn-O based non-single crystal film are in an oxygen atmosphere (or the ratio of the oxygen gas flow rate to the argon gas flow rate is 1:1 or more).

[0087] Next, heat treatment is preferably performed at 200°C to 600°C, typically 300°C to 500°C. Here, it is placed in a furnace and heat-treated at 350°C for 1 hour under a nitrogen atmosphere or an air atmosphere. By this heat treatment, atomic-level rearrangement of the In-Ga-Zn-O-based amorphous film is carried out. Since the strain that inhibits the movement of carriers is released by this heat treatment, the heat treatment here (including photo annealing) is important. Note that the timing of the heat treatment is not particularly limited as long as it is after the formation of the second In-Ga-Zn-O-based amorphous film. For example, it may be performed after the formation of the pixel electrode.

[0088] Next, a third photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the semiconductor layer 103. Here, the second In-Ga-Zn-O-based amorphous film is removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) to form the semiconductor layer 103. When removing by wet etching, the oxide semiconductor can be regenerated from the etching waste liquid and reused for the production of the target.

[0089] Indium and gallium contained in the oxide semiconductor are known to be rare and valuable metals. By reusing them, resource conservation can be achieved and the cost of products formed using the oxide semiconductor can be reduced.

[0090] Note that since the same etchant is used for the first In-Ga-Zn-O-based amorphous film and the second In-Ga-Zn-O-based amorphous film, the first In-Ga-Zn-O-based amorphous film is removed by the etching here. Therefore, the first In-Ga-Zn-O-based amorphous film is removed by the second In-Ga-Zn-O-based amorphous film. The side surfaces of the covered first In-Ga-Zn-O-based non-single crystal film are protected, but as shown in Fig. 4(A), the exposed first In-Ga-Zn-O-based non-single crystal films 111a and 111b are etched to form the first buffer layer 104a and the second buffer layer 104b. Note that the etching of the semiconductor layer 103 is not limited to wet etching, and dry etching may also be used. In the above process, a thin-film transistor 170 with the semiconductor layer 103 as the channel formation region can be fabricated. The cross-sectional view at this stage is shown in Fig. 4(A). Note that the top view at this stage corresponds to Fig. 7. The cross-sectional view at this stage is shown in Fig. 4(A). Note that the top view at this stage corresponds to Fig. 7.

[0091] Next, the resist mask is removed, and a protective insulating film 107 covering the semiconductor layer is formed. The protective insulating film 107 can be a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a tantalum oxide film, etc. obtained by using a sputtering method or the like. The protective insulating film 107 can be a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a tantalum oxide film, etc. obtained by using a sputtering method or the like. The protective insulating film 107 can be a silicon nitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a tantalum oxide film, etc. obtained by using a sputtering method or the like. can be used.

[0092] Next, a fourth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b, contact holes 127 reaching the second terminal 122, and contact holes 109 reaching the capacitive electrode layer 124 are formed by etching the protective insulating film 107. In order to reduce the number of masks, it is preferable to form the contact hole 126 reaching the gate electrode by etching the gate insulating layer with the same resist mask. The cross-sectional view at this stage is shown in Fig. 4(B). Next, a fourth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b, contact holes 127 reaching the second terminal 122, and contact holes 109 reaching the capacitive electrode layer 124 are formed by etching the protective insulating film 107. In order to reduce the number of masks, it is preferable to form the contact hole 126 reaching the gate electrode by etching the gate insulating layer with the same resist mask. The cross-sectional view at this stage is shown in Fig. 4(B). Next, a fourth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b, contact holes 127 reaching the second terminal 122, and contact holes 109 reaching the capacitive electrode layer 124 are formed by etching the protective insulating film 107. In order to reduce the number of masks, it is preferable to form the contact hole 126 reaching the gate electrode by etching the gate insulating layer with the same resist mask. The cross-sectional view at this stage is shown in Fig. 4(B). Next, a fourth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b, contact holes 127 reaching the second terminal 122, and contact holes 109 reaching the capacitive electrode layer 124 are formed by etching the protective insulating film 107. In order to reduce the number of masks, it is preferable to form the contact hole 126 reaching the gate electrode by etching the gate insulating layer with the same resist mask. The cross-sectional view at this stage is shown in Fig. 4(B). Next, a fourth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b, contact holes 127 reaching the second terminal 122, and contact holes 109 reaching the capacitive electrode layer 124 are formed by etching the protective insulating film 107. In order to reduce the number of masks, it is preferable to form the contact hole 126 reaching the gate electrode by etching the gate insulating layer with the same resist mask. The cross-sectional view at this stage is shown in Fig. 4(B). Next, a fourth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b, contact holes 127 reaching the second terminal 122, and contact holes 109 reaching the capacitive electrode layer 124 are formed by etching the protective insulating film 107. In order to reduce the number of masks, it is preferable to form the contact hole 126 reaching the gate electrode by etching the gate insulating layer with the same resist mask. The cross-sectional view at this stage is shown in Fig. 4(B). Next, a fourth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b, contact holes 127 reaching the second terminal 122, and contact holes 109 reaching the capacitive electrode layer 124 are formed by etching the protective insulating film 107. In order to reduce the number of masks, it is preferable to form the contact hole 126 reaching the gate electrode by etching the gate insulating layer with the same resist mask. The cross-sectional view at this stage is shown in Fig. 4(B).

[0093] Next, after removing the resist mask, a transparent conductive film is formed. As the material for the transparent conductive film there is indium oxide (In 2 O 3 ), indium tin oxide alloy (In 2 O 3 —SnO 2 , abbreviated as ITO), etc., which are formed using a sputtering method, a vacuum evaporation method, or the like. The etching treatment of such materials is performed using a hydrochloric acid-based solution. However, especially for the etching of ITO residue is likely to occur, so in order to improve the etching processability, indium zinc oxide alloy (In 2 O 3 —ZnO) may be used.

[0094] Next, a fifth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode 110.

[0095] Also, in this fifth photolithography process, using the gate insulating layer 10 2 in the capacitor portion as a dielectric, a holding capacitor is formed between the capacitor electrode layer 124 and the pixel electrode 110. The capacitor wiring 108 is electrically connected to the capacitor electrode layer 124 via the contact hole 109.

[0096] Also, in this fifth photolithography process, the first terminal and the second terminal are covered with a resist mask to leave the transparent conductive films 128 and 129 formed in the terminal portion. The transparent conductive films 12 8 and 129 serve as electrodes or wirings used for connection to the FPC. The transparent conductive film 12 9 formed on the second terminal 122 serves as a terminal electrode for connection that functions as an input terminal of the source wiring .

[0097] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in Fig. 4(C). Note that the top view at this stage corresponds to Fig. 8.

[0098] Also, Figs. 9(A1) and 9(A2) respectively show the top view and cross-sectional view of the gate wiring terminal portion at this stage. Fig. 9(A1) corresponds to the cross-sectional view along the line C1 - C2 in Fig. 9(A2). In Fig. 9(A1), the transparent conductive film 15 5 formed on the protective insulating film 154 is a terminal electrode for connection that functions as an input terminal. Also, in Fig. 9(A1), in the terminal portion, a first terminal 151 formed of the same material as the gate wiring and a connection electrode 153 formed of the same material as the source wiring overlap via a gate insulating layer 152 and are electrically connected by the transparent conductive film 1 55. Note that the portion where the transparent conductive film 128 shown in Fig. 4(C) contacts the first terminal 12 1 corresponds to the portion where the transparent conductive film 155 in Fig. 9(A1) contacts the first terminal 151 and is in contact.

[0099] Also, Figs. 9(B1) and 9(B2) respectively show the top view and cross-sectional view of a source wiring terminal portion different from the source wiring terminal portion shown in Fig. 4(C). Also, Fig. 9(B1) is corresponding to the cross-sectional view along the line D1 - D2 in Fig. 9(B2). In Fig. 9(B1), the transparent conductive film 155 formed on the protective insulating film 154 is a terminal electrode for connection that functions as an input terminal. Also, in Fig. 9(B1), in the terminal portion, an electrode 156 formed of the same material as the gate wiring overlaps below the second terminal 150 electrically connected to the source wiring via a gate insulating layer 102. The electrode 156 is not electrically connected to the second terminal 150 and the electrode 156 is at a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc. is formed and overlaps via a gate insulating layer 102 below the second terminal 150 electrically connected to the source wiring. The electrode 156 is not electrically connected to the second terminal 150 and the electrode 156 is at a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc. and the electrode 156 is at a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc. What setting should be made to form a capacitance for noise countermeasures or a capacitance for electrostatic countermeasures? Also, the second terminal 150 is electrically connected to the transparent conductive film 155 via the protective insulating film 154.

[0100] A plurality of gate wirings, source wirings, and capacitance wirings are provided according to the pixel density. Also, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitance wiring, etc. are arranged side by side. The number of each terminal may be set to an arbitrary number, and the implementer may appropriately determine it.

[0101] In this way, through five photolithography processes, using five photomasks, a pixel having a thin-film transistor 170 which is a bottom-gate type n-channel thin-film transistor can be completed. And by arranging these in a matrix corresponding to individual pixels to form a pixel portion, it can be used as one substrate for manufacturing an active matrix type display device. In this specification, for convenience, such a substrate is referred to as an active matrix substrate. When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. Note that a common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. This fourth terminal sets the common electrode to a fixed potential, for example, GND, 0V, etc.

[0102] When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. ​​​​​​​​​​is a terminal for

[0103] Also, this embodiment is not limited to the pixel configuration of FIG. 8, and an example of a top view different from FIG. 8 is shown in FIG. 1 0. In FIG. 10, a capacitance wiring is not provided, and a holding capacitance is formed by a capacitance electrode layer that overlaps via a gate wiring and a gate insulating layer of pixels adjacent to the pixel electrode with the gate insulating layer as a dielectric This is an example, and in this case, the capacitance wiring and the third terminal connected to the capacitance wiring can be omitted Note that in FIG. 10, the same parts as those in FIG. 8 are described using the same reference numerals

[0104] In an active matrix type liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix Specifically, a voltage is applied between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, whereby the optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by an observer as a display pattern

[0105] In the video display of a liquid crystal display device, since the response of the liquid crystal molecules themselves is slow, there are problems such as afterimages and blurring of the video. To improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion in which full-screen black display is performed every other frame

[0106] Also, there is a driving technique called so-called double-speed driving in which the response speed is improved by making the normal vertical period 1.5 times or 2 times or more, and at the same time the gradation to be written is selected for each of a plurality of divided fields within each frame

[0107] Also, to improve the video characteristics of the liquid crystal display device, a plurality of LEDs (light emitting ​​​​A surface light source is configured using a diode light source or a plurality of EL light sources, etc., and the surface light source is configured There is also a driving technique in which each light source that exists is independently driven to blink within one frame period. As the surface light source Three or more types of LEDs may be used, or white light-emitting LEDs may be used. Since a plurality of LEDs can be independently controlled, the light emission timing of the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. This driving technique can partially turn off the LEDs Therefore, especially in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved.

[0108] By combining these driving techniques, display characteristics such as the video characteristics of the liquid crystal display device can be improved more than before.

[0109] The n-channel type transistor obtained in this embodiment uses a semiconductor layer of an In-Ga-Zn-O based non-single crystal film in the channel formation region and has good dynamic characteristics, so these driving techniques can be combined.

[0110] Also, when manufacturing a light-emitting display device, one electrode (also called the cathode) of the organic light-emitting element is set to a low power supply potential, for example, GND, 0V, etc., so a fourth terminal for setting the cathode to a low power supply potential, for example, GND, 0V, etc., is provided at the terminal portion. Also, when manufacturing a light-emitting display device, a power supply line is provided in addition to the source wiring and the gate wiring. Therefore, a fifth terminal electrically connected to the power supply line is provided at the terminal portion.

[0111] In this embodiment, the gate electrode layer, the gate insulating layer, the source electrode layer and the drain electrode layer, the so - A source region or a drain region (an oxide semiconductor layer containing In, Ga, and Zn), a semiconductor layer ( An oxide semiconductor layer containing In, Ga, and Zn) having a stacked structure of a thin film transistor By modifying the surface of the gate insulating layer by plasma treatment, the film thickness of the semiconductor layer can be made thin While remaining so, the parasitic capacitance can be suppressed. Even if it is a thin film, since the ratio with respect to the gate insulating layer Is sufficient, the parasitic capacitance is sufficiently suppressed.

[0112] According to this embodiment, a thin film transistor with a high on-off ratio can be obtained, and a thin film transistor with good dynamic Characteristics can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided.

[0113] (Embodiment 4) In this embodiment, an example of an electronic paper is shown as a semiconductor device.

[0114] Fig. 11 shows an active matrix type electronic Paper as an example of a semiconductor device different from a liquid crystal display device. As the thin film transistor 581 used in the pixel portion of the semiconductor device, it can be manufactured in the same manner as the thin film transistor in the pixel portion shown in Embodiment 3, and is a thin film transistor including an In-Ga-Zn-O based Non-single crystal film as a semiconductor layer. Also, as shown in Embodiment 1, by making the side surfaces of two electrodes facing each other with a tapered shape across the oxide semiconductor layer, it is possible to realize an electronic paper equipped with a highly reliable thin film transistor provided with an electric Field relaxation region It is possible.

[0115] The electronic paper in Fig. 11 is an example of a display device using a twist ball display method. The twist The ball display method is an electrode layer that uses spherical particles painted white and black as display elements​​​ It is arranged between the first electrode layer and the second electrode layer, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles, thereby performing display. This is a method of performing display.

[0116] The thin film transistor 581 is a thin film transistor with a bottom gate structure, and the source electrode layer or the drain electrode layer is in contact with and electrically connected to the first electrode layer 587 through an opening formed in the insulating layer 585. There is a black region 5 90a and a white region 590b between the first electrode layer 587 and the second electrode layer 588, and a cavity 594 filled with liquid around it contains spherical particles 589. The periphery of the spherical particles 589 is filled with a filler 595 such as resin (see Fig. 11).

[0117] Also, instead of the twist ball, it is also possible to use an electrophoresis element. A transparent liquid and microcapsules with a diameter of about 10 μm to 20 0 μm, which encapsulate positively charged white fine particles and negatively charged black fine particles, are used. When an electric field is applied to the microcapsules provided between the first electrode layer and the second electrode layer by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. A display element applying this principle is an electrophoresis display element, which is also called electronic paper. Since the electrophoresis display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required, and moreover, the power consumption is small, and the display part can be recognized even in a dim place. Also, even when no power is supplied to the display part, the image once displayed can be retained. Therefore, from a radio wave transmission source to a semiconductor device with a display function (simply a display device or a semiconductor device equipped with a display device) ​​​​Even when the body device (also referred to as such) is moved away, it is possible to save the displayed image. It becomes so.

[0118] By the above steps, it is possible to fabricate electronic paper with reduced manufacturing costs as a semiconductor device. It can be done.

[0119] This embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3. It is possible.

[0120] (Embodiment 5) In this embodiment, in a display device which is an example of a semiconductor device, an example of fabricating at least a part of a drive circuit and a thin film transistor disposed in a pixel portion on the same substrate will be described below. It will be described below. It will be done.

[0121] The thin film transistor disposed in the pixel portion is formed according to Embodiment 1 or Embodiment 2. Also, since the thin film transistor shown in Embodiment 1 or Embodiment 2 is an n-channel type TFT, a part of the drive circuit that can be configured by n-channel type TFTs in the drive circuit is formed on the same substrate as the thin film transistor in the pixel portion. Since it is, It is formed on the same substrate as the thin film transistor in the pixel portion.

[0122] An example of a block diagram of an active matrix type liquid crystal display device which is an example of a semiconductor device is shown in FIG. 12(A). The display device shown in FIG. 12(A) has a pixel portion 5301 having a plurality of pixels provided with display elements on a substrate 5300, a scanning line drive circuit 5302 for selecting each pixel, and a signal line drive circuit 5303 for controlling the input of a video signal to the selected pixel. It has. It has.

[0123] The pixel portion 5301 has a plurality of signal lines extending in the column direction from the signal line drive circuit 5303 and arranged. Connected to the signal line driving circuit 5303 by lines S1 to Sm (not shown), and extended in the row direction from the scanning line driving circuit A plurality of scanning lines G1 to Gn (not shown) arranged are connected to the scanning line driving circuit 5302 Connected to the scanning line driving circuit 5302, and having a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is connected to A signal line Sj (any one of the signal lines S1 to Sm), and a scanning line Gi (any one of the scanning lines G1 to Gn). One of the signal lines S1 to Sm), and a scanning line Gi (any one of the scanning lines G1 to Gn). Connected to one of the scanning lines G1 to Gn).

[0124] Also, the thin film transistor shown in Embodiment 1 or Embodiment 2 is an n-channel type TFT, and the signal line driving circuit composed of n-channel type TFTs will be described with reference to FIG. 13. Connected to one of the scanning lines G1 to Gn).

[0125] The signal line driving circuit shown in FIG. 13 includes a driver IC 5601, a switch group 5602_1 to 56 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 56 21_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film Transistor 5603c.

[0126] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613 And the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 561 3 and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to the first Of the wirings 5621_1 to 5621_M is connected to the first The thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are connected to three signal lines. For example, the wiring 5621_J in the J-th column (any one of the wirings 5621_1 to 5621_M) is connected to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c that the switch group 5602_J has. The wiring 5621_J in the J-th column (any one of the wirings 5621_1 to 5621_M) is connected to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c that the switch group 5602_J has. _J (any one of the wirings 5621_1 to 5621_M) is connected to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c that the switch group 5602_J has. _J (any one of the wirings 5621_1 to 5621_M) is connected to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c that the switch group 5602_J has. _J (any one of the wirings 5621_1 to 5621_M) is connected to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c that the switch group 5602_J has. _J (any one of the wirings 5621_1 to 5621_M) is connected to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c that the switch group 5602_J has.

[0127] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively. Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0128] Note that it is desirable that the driver IC 5601 be formed on a single crystal semiconductor substrate. Furthermore, it is desirable that the switch groups 5602_1 to 5602_M be formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M may be connected via an FPC or the like. Furthermore, it is desirable that the switch groups 5602_1 to 5602_M be formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M may be connected via an FPC or the like. Furthermore, it is desirable that the switch groups 5602_1 to 5602_M be formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M may be connected via an FPC or the like.

[0129] Next, the operation of the signal line driving circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. 14. Note that the timing chart of FIG. 14 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 13 operates in the same manner as in FIG. 14 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. 14. Note that the timing chart of FIG. 14 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 13 operates in the same manner as in FIG. 14 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. 14. Note that the timing chart of FIG. 14 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 13 operates in the same manner as in FIG. 14 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. 14. Note that the timing chart of FIG. 14 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 13 operates in the same manner as in FIG. 14 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. 14. Note that the timing chart of FIG. 14 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 13 operates in the same manner as in FIG. 14 even when scanning lines of other rows are selected. Next, the operation of the signal line driving circuit shown in FIG. 13 will be described with reference to the timing chart of FIG. 14. Note that the timing chart of FIG. 14 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 13 operates in the same manner as in FIG. 14 even when scanning lines of other rows are selected.

[0130] Note that the timing chart of FIG. 14 shows the case where the wiring 5621_J in the J-th column is the first thin film transistor When the fifth thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are connected to the signal line Sj-1, the signal line Sj, and the signal line Sj+1, respectively, it is shown as follows. When the fifth thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are connected to the signal line Sj-1, the signal line Sj, and the signal line Sj+1, respectively, it is shown as follows. Shown.

[0131] Note that the timing chart in FIG. 14 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that the timing chart in FIG. 14 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. When the fifth thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are connected to the signal line Sj-1, the signal line Sj, and the signal line Sj+1, respectively, it is shown as follows. Note that the timing chart in FIG. 14 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Shown.

[0132] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Further, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively. Let them be Data_j-1, Data_j, and Data_j+1, respectively.

[0133] As shown in FIG. 14, during the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. is turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2 , the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin film transistor 5603b . In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0134] From the above, the signal line driving circuit in FIG. 13 divides one gate selection period into three, so that a video signal can be input from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driving circuit in FIG. 13 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1 / 3 compared to the number of signal lines. By reducing the number of connections to about 1 / 3, the signal line driving circuit in FIG. 13 can improve reliability, yield, etc. Note that as shown in FIG. 13, if one gate selection period is divided into a plurality of sub-selection periods, and a video signal can be input from one wiring to each of a plurality of signal lines in each of the plurality of sub-selection periods, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0135]

[0136] ​​​For example, when inputting video signals from one wiring to three or more signal lines respectively in each of three or more sub-selection periods, thin film transistors and wiring for controlling the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. As another example, as shown in the timing chart of FIG. 15, one selection period may be divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Further, the timing chart of FIG. 15 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 15, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film film transistor 5603c are turned off. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off.

[0137] In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. As shown in FIG. 15, the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column are shown. As shown in FIG. 15, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. In the third selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. The thin-film transistor 5603c turns off. At this time, Dat input to the wiring 5621_J a_j-1 is input to the signal line Sj-1 via the first thin-film transistor 5603a . In the second sub-selection period T2, the second thin-film transistor 5603b turns on, and the first thin film transistor 5603a and the third thin-film transistor 5603c turn off. At this time , Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin-film transistor 5603b . In the third sub-selection period T3, the third thin-film transistor 5603c turns on, and the first thin-film transistor 5603a and the second thin-film transistor 5 603b turn off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin-film transistor 5603c.

[0138] From the above, the signal line driving circuit of FIG. 13 to which the timing chart of FIG. 15 is applied provides a precharge selection period before the sub-selection period, so that the signal line can be precharged , and the video signal can be written to the pixel at high speed. In FIG. 15 , those similar to FIG. 14 are denoted by common reference numerals, and detailed descriptions of the same parts or parts having similar functions are omitted.

[0139] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit includes a shift register and a buffer. In some cases, it may also include a level shifter. In the scanning line driving circuit, a selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP ) to the shift register. The generated selection signal is sent to the buffer is buffer-amplified and supplied to the corresponding scanning line. The scanning line is connected to the gate electrodes of the transistors for one line of pixels. And since the transistors for one line of pixels must be turned on all at once, a buffer that can pass a large current is used. A form of a shift register used as part of a scanning line driving circuit will be described with reference to FIGS. 16 and 17. Since the transistors for one line of pixels must be turned on all at once, a buffer that can pass a large current is used. is used.

[0140] A form of a shift register used as part of a scanning line driving circuit will be described with reference to FIGS. 16 and 17. is used.

[0141] FIG. 16 shows the circuit configuration of the shift register. The shift register shown in FIG. 16 is composed of a plurality of flip-flops 5701_i (any one of flip-flops 5701_1 to 5701_n). Also, it operates with the input of the first clock signal, the second clock signal, the start pulse signal, and the reset signal. A form of a shift register used as part of a scanning line driving circuit will be described with reference to FIGS. 16 and 17. Since the transistors for one line of pixels must be turned on all at once, a buffer that can pass a large current is used. is used.

[0142] The connection relationship of the shift register in FIG. 16 will be described. In the shift register of FIG. 16, the i-th stage flip-flop 5701_i (any one of flip-flops 5701_1 to 5701_n) has the first wiring 5501 shown in FIG. 17 connected to the seventh wiring 5717_i - 1, the second wiring 5502 shown in FIG. 17 connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in FIG. 17 connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 17 connected to the fifth wiring 5715. A form of a shift register used as part of a scanning line driving circuit will be described with reference to FIGS. 16 and 17. In the shift register of FIG. 16, the i-th stage flip-flop 5701_i (any one of flip-flops 5701_1 to 5701_n) has the first wiring 5501 shown in FIG. 17 connected to the seventh wiring 5717_i - 1, the second wiring 5502 shown in FIG. 17 connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in FIG. 17 connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 17 connected to the fifth wiring 5715. is connected, the second wiring 5502 shown in FIG. 17 is connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in FIG. 17 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 17 is connected to the fifth wiring 5715. The third wiring 5503 shown in FIG. 17 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 17 is connected to the fifth wiring 5715. is connected, and the sixth wiring 5506 shown in FIG. 17 is connected to the fifth wiring 5715.

[0143] Also, the fourth wiring 5504 shown in FIG. 17 is connected to the second wiring 5712 in the flip-flops of the odd-numbered stages and to the third wiring 5713 in the flip-flops of the even-numbered stages, and the fifth wiring 5505 shown in FIG. 17 is connected to the fourth wiring 5714. In the shift register of FIG. 16, the i-th stage flip-flop 5701_i (any one of flip-flops 5701_1 to 5701_n) has the first wiring 5501 shown in FIG. 17 connected to the seventh wiring 5717_i - 1, the second wiring 5502 shown in FIG. 17 connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in FIG. 17 connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 17 connected to the fifth wiring 5715. is connected, and the fifth wiring 5505 shown in FIG. 17 is connected to the fourth wiring 5714.

[0144] However, the first wiring 5501 shown in FIG. 17 of the first-stage flip-flop 5701_1 is connected to the first wiring 5711, and the second wiring 5502 shown in FIG. 17 of the nth-stage flip-flop 5701_n is connected to the sixth wiring 5716.

[0145] Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power supply line and the second power supply line, respectively.

[0146] Next, the details of the flip-flop shown in FIG. 16 are shown in FIG. 17. The flip flop shown in FIG. 17 includes a first thin-film transistor 5571, a second thin-film transistor 5572, a third thin-film transistor 5573, a fourth thin-film transistor 5574, a fifth thin-film trans istor 5575, a sixth thin-film transistor 5576, a seventh thin-film transistor 5577, and an eighth thin-film transistor 5578. Note that the first thin-film transistor 5571, the second thin-film transistor 5572, the third thin-film transistor 5573, the fourth thin-film trans istor 5574, the fifth thin-film transistor 5575, the sixth thin-film transistor 5576, the seventh thin-film transistor 5577, and the eighth thin-film transistor 5578 are n-channel type transistors, and are assumed to be in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

[0147] Next, the connection configuration of the flip-flop shown in FIG. 16 is shown below. ​​

[0148] The first electrode (one of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504, and the second electrode (the other of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

[0149] The first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and the second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

[0150] The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and the second electrode of the third thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505 .

[0151] The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, and the second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571.

[0152] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 .

[0153] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the second The second electrode of the thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0154] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 . The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506 and the second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550 1.

[0155] Note that the connection points of the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574 , the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 are defined as node 5543. Further, the connection points of the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574 , the gate electrode of the sixth thin film transistor 5576 and the second electrode of the eighth thin film transistor 5578 are defined as node 5544.

[0156] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5 504 may be respectively referred to as the first signal line, the second signal, the third signal line and the fourth signal line.​​​ Okay. Further, the fifth wiring 5505 may be referred to as the first power line, and the sixth wiring 5506 may be referred to as the second power line. This can also be said.

[0157] In addition, the signal line driving circuit and the scanning line driving circuit can also be fabricated only with the n-channel type TFTs shown in Embodiment 1 or Embodiment 2. Since the mobility of the transistor using the oxide semiconductor layer is high, it becomes possible to increase the driving frequency of the driving circuit. Further, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, and thus has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion. Moreover, since the mobility of the transistor using the oxide semiconductor layer is large, it is possible to increase the driving frequency of the driving circuit. Also, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, so that it has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion. Moreover, since the mobility of the transistor using the oxide semiconductor layer is large, it is possible to increase the driving frequency of the driving circuit. Also, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, so that it has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion. Moreover, since the mobility of the transistor using the oxide semiconductor layer is large, it is possible to increase the driving frequency of the driving circuit. Also, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, so that it has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion. Moreover, since the mobility of the transistor using the oxide semiconductor layer is large, it is possible to increase the driving frequency of the driving circuit. Also, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, so that it has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion. Moreover, since the mobility of the transistor using the oxide semiconductor layer is large, it is possible to increase the driving frequency of the driving circuit. Also, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, so that it has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion. Moreover, since the mobility of the transistor using the oxide semiconductor layer is large, it is possible to increase the driving frequency of the driving circuit. Also, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, so that it has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion. Moreover, since the mobility of the transistor using the oxide semiconductor layer is large, it is possible to increase the driving frequency of the driving circuit. Also, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a reduced parasitic capacitance due to the source region or the drain region, so that it has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can operate at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion.

[0158] Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the even-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the opposite side, thereby realizing an increase in the frame frequency. Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the even-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the opposite side, thereby realizing an increase in the frame frequency. Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the even-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the opposite side, thereby realizing an increase in the frame frequency. Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the even-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the opposite side, thereby realizing an increase in the frame frequency. Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the even-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the opposite side, thereby realizing an increase in the frame frequency.

[0159] In addition, when manufacturing an active matrix type light emitting display device, which is an example of a semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of the block diagram of the active matrix type light emitting display device is shown in FIG. 12(B). In addition, when manufacturing an active matrix type light emitting display device, which is an example of a semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of the block diagram of the active matrix type light emitting display device is shown in FIG. 12(B). In addition, when manufacturing an active matrix type light emitting display device, which is an example of a semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of the block diagram of the active matrix type light emitting display device is shown in FIG. 12(B). In addition, when manufacturing an active matrix type light emitting display device, which is an example of a semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of the block diagram of the active matrix type light emitting display device is shown in FIG. 12(B).

[0160] The light-emitting display device shown in FIG. 12B has a plurality of pixels each having a display element over a substrate 5400. A pixel portion 5401 for selecting each pixel, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. A driver circuit 5404 and a signal line driver circuit 5405 for controlling the input of a video signal to a selected pixel 403.

[0161] In the case where a video signal input to a pixel of the light-emitting display device shown in FIG. 12(B) is in a digital format, When a pixel is turned on, the transistor is switched on and off to make it either emitting light or not. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by changing the time when the pixel emits light. This is a driving method that displays gradations by controlling the period during which the liquid crystal display is turned on.

[0162] Light-emitting elements have a higher response speed than liquid crystal elements, so they are more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, the light emitting element of the pixel is divided into sub-frame periods according to the video signal. By dividing the period into multiple subframes, The total length of time that pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0163] In the light-emitting display device shown in FIG. 12B, a switching TFT and a When two TFTs are arranged, the first TFT, which is the gate wiring of the switching TFT, The signal input to the scanning line is generated by the first scanning line driver circuit 5402, and the current control TFT A signal input to the second scanning line, which is the gate wiring of the second pixel, is generated by a second scanning line driver circuit 5404. The example shows a configuration in which a signal input to the first scanning line and a signal input to the second scanning line are The signals to be output may be generated by a single scanning line driving circuit. The operation of the switching element is controlled by the number of transistors that the switching element has. A plurality of first scan lines may be provided for each pixel. Alternatively, all of the signals input to the first scanning lines may be generated by a single scanning line driver circuit. Alternatively, the signals may be generated by a plurality of scanning line driving circuits.

[0164] In addition, in the light-emitting display device, the driver circuit may be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those shown in Embodiment 1 or 2. It is also possible to fabricate the device using only channel TFTs.

[0165] Through the above steps, a display device with high reliability as a semiconductor device can be manufactured.

[0166] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0167] (Embodiment 6) In this embodiment mode, a light-emitting display device is shown as an example of a semiconductor device. Here, a light-emitting element that uses electroluminescence is used as the element. Light-emitting devices that utilize electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL device, and the latter is called an inorganic EL device. When a voltage is applied to an organic EL device, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state and emits light when returning from the excited state to the ground state. Based on such a mechanism, such a light-emitting device is called a current-excited type light-emitting device.

[0168]

[0169] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices according to their device structures. The dispersed inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type luminescence that utilizes donor levels and acceptor levels. The thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized luminescence that utilizes inner shell electron transitions of metal ions. Here, an organic EL device is used for explanation as the light-emitting device.

[0170] Figure 18 is a diagram showing an example of a pixel configuration to which digital time-division driving can be applied as an example of a semiconductor device.

[0171] The configuration and operation of a pixel to which digital time-division driving can be applied will be described. Here, an n-type oxide semiconductor layer (In-Ga-Zn-O based non-single crystal film) is used in the channel formation region. ​​​​​​​​​​​​​​An example of using two channel-type transistors in one pixel is shown.

[0172] Pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The switching transistor 64 01 has its gate connected to the scanning line 6406, and one of its first electrodes (either the source electrode or the drain electrode) is connected to the signal line 6405, and the other of its second electrodes (either the source electrode or the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, its first electrode connected to the power supply line 640 7, and its second electrode connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408.

[0173] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential lower than the high power supply potential set for the power supply line 6407, and examples of the low power supply potential include GND, 0V, etc. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light-emitting element 6404. Each potential is set accordingly.

[0174] Note that the capacitive element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, the channel region A capacitance may be formed between the [element] and the gate electrode.

[0175] Here, in the case of the voltage input voltage drive method, to the gate of the driving transistor 6402, a video signal is input such that the driving transistor 6402 has two states of being fully on or off. That is, the driving transistor 6402 operates in the linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that to the signal line 6405, a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied. (Power supply line voltage + Vth of the driving transistor 6402) or higher voltage is applied.

[0176] Also, when performing analog gradation driving instead of digital time gradation driving, by changing the signal input, the same pixel configuration as in FIG. 18 can be used.

[0177] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 64 04 refers to the voltage for a desired luminance, and includes at least the forward threshold voltage. Note that by inputting a video signal such that the driving transistor 6402 operates in the saturation region, current can flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed. 04 refers to the voltage for a desired luminance, and includes at least the forward threshold voltage. Note that by inputting a video signal such that the driving transistor 6402 operates in the saturation region, current can flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed. 04 refers to the voltage for a desired luminance, and includes at least the forward threshold voltage. Note that by inputting a video signal such that the driving transistor 6402 operates in the saturation region, current can flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed. By inputting a video signal such that the driving transistor 6402 operates in the saturation region, current can flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed. Since the driving transistor 6402 operates in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed. Since the driving transistor 6402 operates in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed. By making the video signal analog, current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed.

[0178] Note that the pixel configuration shown in FIG. 18 is not limited thereto. For example, a switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added to the pixel shown in FIG. 18.

[0179] Next, the configuration of the light-emitting element will be described with reference to FIGS. 19(A), 19(B), and 19(C). Here, the case where the driving TFT is the thin-film transistor 170 shown in FIG. 1(B) will be taken as an example to describe the cross-sectional structure of the pixel. The driving TFTs TFT7001, 7011, and 7021 used in the semiconductor devices of FIGS. 19(A), 19(B), and 19(C) can be manufactured in the same manner as the thin-film transistor 170 shown in Embodiment 1, and are thin-film transistors having high electrical characteristics including an In-Ga-Zn-O-based non-single crystal film as a semiconductor layer.

[0180] For the light-emitting element, at least one of the anode and the cathode may be transparent in order to extract light. Thus, there are a top emission type in which a thin-film transistor and a light-emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, a bottom emission type in which light is extracted from the surface on the substrate side, and a double-sided emission structure type in which light is extracted from both the substrate side and the surface opposite to the substrate. The pixel configuration shown in FIG. 18 can be applied to any of the light-emitting elements having these emission structures.

[0181] The top emission type light-emitting element will be described with reference to FIG. 19(A).

[0182] FIG. 19(A) shows a cross-sectional view of a pixel in the case where the driving TFT TFT7001 is the thin-film transistor 170 shown in FIG. 1(B) and the light emitted from the light-emitting element 7002 escapes to the anode 7005 side. In FIG. 19(A), the cathode 7003 of the light-emitting element 7002 and the driving TFT ​​​​​​​​​​​​TFT 7001, which is denoted as T, is electrically connected, and a light-emitting layer 7004 is laminated on a cathode 7003 in this order. An anode 7005 is laminated thereon in this order. The cathode 7003 has a low work function and can be made of various materials as long as it is a conductive film that reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. The light-emitting layer 7004 may be composed of a single layer or a plurality of laminated layers. When it is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated on the cathode 7003 in this order. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or other light-transmitting conductive films. The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 19(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow. Next, a light-emitting element with a bottom emission structure will be described with reference to Fig. 19(B). The driving TFT 7 011 is the thin-film transistor 170 shown in Fig. 1(A), and a cross-sectional view of the pixel is shown when the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side. In Fig. 19(B), the driving

[0183]

[0184] 011 is the thin-film transistor 170 shown in Fig. 1(A), and a cross-sectional view of the pixel is shown when the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side. In Fig. 19(B), the driving ​​​​​​​​​On a conductive film 7017 having translucency that is electrically connected to the driving TFT 7011, a light-emitting element 7012's cathode 7013 is formed, and a light-emitting layer 7014 and an anode 70 15 are sequentially laminated thereon. When the anode 7015 has translucency, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode . The cathode 70 13 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of FIG. 19(A). However, the film thickness should be such that light can pass through (preferably about 5 nm to 3 0 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013 . And the light-emitting layer 7014 can be either composed of a single layer or configured such that a plurality of layers are laminated, similar to FIG. 19(A). The anode 7015 does not necessarily need to transmit light, but can be formed using a translucent conductive material, similar to FIG. 19(A). And the shielding film 7016 can be made of, for example, a metal that reflects light, etc , but is not limited to a metal film. For example, a resin with a black pigment added, etc. can also be used . The region where the cathode 7013 and the anode 7015 sandwich the light-emitting layer 7014 corresponds to the light-emitting element 7012 . In the case of the pixel shown in FIG. 19(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow .

[0185] Next, a light-emitting element with a double-sided emission structure will be described with reference to FIG. 19(C). In FIG. 19(C) , on a conductive film 7027 having translucency that is electrically connected to the driving TFT 7021, the cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023

[0186] . ​​​ The anodes 7025 are stacked in sequence. The cathode 7023 can be made of various materials as long as they are conductive materials with a small work function. However, the film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, either way is acceptable, similar to the case of Fig. 19(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to the case of Fig. 19(A). As long as it is a conductive material with a small work function, various materials can be used. However, the film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, either way is acceptable, similar to the case of Fig. 19(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to the case of Fig. 19(A). As long as it is a conductive material with a small work function, various materials can be used. However, the film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, either way is acceptable, similar to the case of Fig. 19(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to the case of Fig. 19(A). As long as it is a conductive material with a small work function, various materials can be used. However, the film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, either way is acceptable, similar to the case of Fig. 19(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to the case of Fig. 19(A). As long as it is a conductive material with a small work function, various materials can be used. However, the film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, either way is acceptable, similar to the case of Fig. 19(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to the case of Fig. 19(A). As long as it is a conductive material with a small work function, various materials can be used. However, the film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, either way is acceptable, similar to the case of Fig. 19(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to the case of Fig. 19(A). As long as it is a conductive material with a small work function, various materials can be used. However, the film thickness should be such that it allows light to pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or multiple stacked layers, either way is acceptable, similar to the case of Fig. 19(A). The anode 7025 can be formed using a conductive material with light-transmitting properties, similar to the case of Fig. 19(A).

[0187] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 19(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 19(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 19(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0188] Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element. Here, although the light-emitting element is described as an organic EL element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0189] In this embodiment, an example where a thin-film transistor (driving TFT) for controlling the driving of the light-emitting element and the light-emitting element are electrically connected is shown. However, a configuration where a current control TFT is connected between the driving TFT and the light-emitting element may also be acceptable. In this embodiment, an example where a thin-film transistor (driving TFT) for controlling the driving of the light-emitting element and the light-emitting element are electrically connected is shown. However, a configuration where a current control TFT is connected between the driving TFT and the light-emitting element may also be acceptable. In this embodiment, an example where a thin-film transistor (driving TFT) for controlling the driving of the light-emitting element and the light-emitting element are electrically connected is shown. However, a configuration where a current control TFT is connected between the driving TFT and the light-emitting element may also be acceptable.

[0190] The semiconductor device shown in this embodiment is not limited to the configurations shown in Fig. 19(A), Fig. 19(B), and Fig. 19(C), and various modifications based on the disclosed technical idea are possible. The semiconductor device shown in this embodiment is not limited to the configurations shown in Fig. 19(A), Fig. 19(B), and Fig. 19(C), and various modifications based on the disclosed technical idea are possible. The semiconductor device shown in this embodiment is not limited to the configurations shown in Fig. 19(A), Fig. 19(B), and Fig. 19(C), and various modifications based on the disclosed technical idea are possible.

[0191] Next, the upper surface and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIGS. 22(A) and 22(B). FIG. 22(A) is a top view of the panel in which thin film transistors and light-emitting elements formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 22(B) corresponds to a cross-sectional view taken along H-I in FIG. 22(A).

[0192] A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on a first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Thus, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) or a cover material so as not to be exposed to the outside air.

[0193] Further, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 include a plurality of thin film transistors. In FIG. 22(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are illustrated as examples.

[0194] ​​​​​​​​​​​​​The thin film transistors 4509 and 4510 can apply the thin film transistor shown in the highly reliable Embodiment 1 including an In-Ga-Zn-O-based non-single crystal film as a semiconductor layer.

[0195] Also, 4511 corresponds to a light emitting element, and the first electrode layer 4517 which is a pixel electrode of the light emitting element 4511 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The structure of the light emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but it is not limited to the structure shown in this embodiment. The structure of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511 and the like.

[0196] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and form it so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0197] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be stacked.

[0198] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0199] Also, the signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b ​​​​​​​​Or, the various signals and potentials supplied to the pixel section 4502 are supplied from the FPCs 4518a and 4518 b.

[0200] In this embodiment, the connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4 517 of the light emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4509 and 4 510.

[0201] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive film 4519 electrically.

[0202] The second substrate located in the light extraction direction of the light from the light emitting element 4511 must be translucent In that case, a translucent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

[0203] In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. A (ethylene vinyl acetate) can be used.

[0204] Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection reflection. reflection.

[0205] The signal line drive circuits 4503a and 4503b, and the scanning line drive circuits 4504a and 4504b may be mounted on a drive circuit formed of a single crystal semiconductor substrate prepared separately, or a single crystal semiconductor film or a polycrystalline semiconductor film on an insulating substrate. Also, only the signal line drive circuit, or a part thereof, or only the scanning line drive circuit, or only a part thereof may be separately formed and mounted, and the present embodiment is not limited to the configurations of FIGS. 22(A) and 22(B).

[0206] By the above steps, a light-emitting display device (display panel) with reduced manufacturing cost can be fabricated.

[0207] The present embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3.

[0208] (Embodiment 7) In this embodiment, the top surface and cross section of a liquid crystal display panel corresponding to one form of a semiconductor device will be described with reference to FIGS. 20(A1), 20(A2), and 20(B). FIG. 20(A1) and FIG. 20(A2) are top views of the panel in which the thin film transistors 4010, 4011, including the In-Ga-Zn-O based non-single crystal film shown in Embodiment 1 formed on the first substrate 4001 as a semiconductor layer, and the liquid crystal element 4013 are sealed with a sealing material 4005 between the second substrate 4006. FIG. 20(B) corresponds to a cross-sectional view taken along M-N in FIGS. 20(A1) and 20(A2). The sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. Also, between the pixel portion 4002 and the scanning line drive circuit

[0209] and the like, the sealing material 4005 is provided. ​​​ A second substrate 4006 is provided on the path 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006 and. Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0210] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 20(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 20(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0211] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 20(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. Insulating layers 4020 and 402 1 are provided on the thin film transistors 4010 and 4011.

[0212] The thin film transistors 4010 and 4011 can be applied to the thin film transistors shown in Embodiment 1 including an In-Ga-Zn-O-based non-single crystal film as a semiconductor layer . The thin film transistor 4011 corresponds to the thin film transistor 170 shown in FIG. 1 of Embodiment 1.

[0213] Also, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 that function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031, respectively, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0214] As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0215] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between the pair of substrates using a common connection portion. Note that the conductive particles are contained in the sealing material 4005. ​

[0216] Alternatively, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range and used. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 10 μs to 100 μs, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence

[0217] Note that this embodiment is an example of a transmissive liquid crystal display device, but it can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device

[0218] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and an example is shown in which a coloring layer and an electrode layer used for the display element are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate Also, the laminated structure of the polarizing plate and the coloring layer is not limited to this embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the coloring layer. Further, a light-shielding film that functions as a black matrix may be provided

[0219] In this embodiment, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor obtained in Embodiment 1 is covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as a protective film or a planarizing insulating film The protective film prevents contamination impurities such as organic substances, metal substances, and water vapor floating in the air ​​​​​​​​It is for preventing the intrusion of and a dense film is preferred. The protective film can be formed by sputtering a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, a aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film. In this embodiment, an example of forming the protective film by sputtering is shown, but it is not particularly limited and may be formed by various methods such as the PCVD method.

[0220] Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed by sputtering as the first layer of the insulating layer 402 0. When a silicon oxide film is used as the protective film, it is effective in preventing hillocks of the aluminum film used as the source electrode layer and the drain electrode layer.

[0221] Also, an insulating layer is formed as the second layer of the protective film. Here, a silicon nitride film is formed by sputtering as the second layer of the insulating layer 4020. When a silicon nitride film is used as the protective film, it is possible to suppress ions such as sodium from entering the semiconductor region and changing the electrical characteristics of the TFT.

[0222] Also, after forming the protective film, annealing (300 ° C to 400 ° C) of the semiconductor layer may be performed.

[0223] Also, an insulating layer 4021 is formed as the planarization insulating film. As the insulating layer 4021, heat-resistant organic materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. It is possible. By laminating a plurality of insulating films formed of these materials, the insulating layer 4021 may be formed.

[0224] Note that the siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. As substituents, the siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group. Further, the organic group may have a fluoro group as well.

[0225] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method , spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 4021 using a material liquid, annealing (300°C to 400°C) of the semiconductor layer may be performed simultaneously in the baking process. By combining the baking process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device .

[0226] The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc. .

[0227] Further, as the pixel electrode layer 4030 and the counter electrode layer 4031, a conductive polymer (conductive polymer ​It can be formed using a conductive composition (also referred to as). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less. The pixel electrode formed has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned. Also, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018.

[0228] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0229] Also, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018. In this embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and drain electrode layer of the thin film transistors 4010, 4011.

[0230] In this embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and drain electrode layer of the thin film transistors 4010, 4011. In this embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and drain electrode layer of the thin film transistors 4010, 4011. In this embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and drain electrode layer of the thin film transistors 4010, 4011.

[0231] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

[0232] Also, in FIGS. 20(A1) and 20(A2), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but this embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or only a part of the scanning line driving circuit may be separately formed and mounted. Also, in FIGS. 20(A1) and 20(A2), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but this embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or only a part of the scanning line driving circuit may be separately formed and mounted. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or only a part of the scanning line driving circuit may be separately formed and mounted. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or only a part of the scanning line driving circuit may be separately formed and mounted.

[0233] FIG. 21 shows the configuration of a liquid crystal display module as a semiconductor device using a TFT substrate 2600. This shows an example.

[0234] FIG. 21 is an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed by an adhesive material 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, a coloring layer 2605, and a polarizing plate 2606 are provided therebetween to form a display region. The coloring layer 2605 is necessary when performing color display. In the case of the RGB method, coloring layers corresponding to each of the red, green, and blue colors are provided corresponding to each pixel. On the outside of the TFT substrate 2600 and the counter substrate 2601, polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, it may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer. The liquid crystal display module includes a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment), an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bire fringence) mode, etc. On the outside of the TFT substrate 2600 and the counter substrate 2601, polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, between the polarizing plate and the liquid crystal layer, it may be laminated in a state having a retardation plate. The liquid crystal display module may be laminated in a state having a retardation plate between the polarizing plate and the liquid crystal layer.

[0235] The liquid crystal display module includes TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, etc. n-Plane-Switching) mode, FFS (Fringe Field S witching) mode, MVA (Multi-domain Vertical A lignment) mode, PVA (Patterned Vertical Alig nment), ASM (Axially Symmetric aligned Mic ro-cell) mode, OCB (Optical Compensated Bire fringence) mode, FLC (Ferroelectric Liquid C rystal) mode, AFLC (AntiFerroelectric Liquid Crystal), etc. can be used.

[0236] Through the above steps, a liquid crystal display panel with reduced manufacturing cost as a semiconductor device can be fabricated. That is possible.

[0237] This embodiment can be implemented in appropriate combination with the configurations described in Embodiment 1, Embodiment 2, or Embodiment 3. That is possible.

[0238] (Embodiment 8) An electronic paper can be used in electronic devices in any field as long as it can display information. For example, it can be applied to displays in electronic books (e-books), posters, in-vehicle advertisements in trains or other vehicles, various cards such as credit cards, etc. using an electronic paper. An example of an electronic device is shown in FIGS. 23 and 24. That is possible. An example of an electronic device is shown in FIGS. 23 and 24.

[0239] FIG. 23(A) shows a poster 2631 made of an electronic paper. When the advertising medium is a paper print, the advertisement is exchanged manually, but when using the electronic paper to which this Embodiment 3 is applied, the advertisement display can be changed in a short time. Also, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information. When the advertising medium is a paper print, the advertisement is exchanged manually, but when using the electronic paper to which this Embodiment 3 is applied, the advertisement display can be changed in a short time. Also, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information. When the advertising medium is a paper print, the advertisement is exchanged manually, but when using the electronic paper to which this Embodiment 3 is applied, the advertisement display can be changed in a short time. Also, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information. When the advertising medium is a paper print, the advertisement is exchanged manually, but when using the electronic paper to which this Embodiment 3 is applied, the advertisement display can be changed in a short time. Also, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information. That is possible.

[0240] Also, FIG. 23(B) shows an in-vehicle advertisement 2632 in a vehicle such as a train. When the advertising medium is a paper print, the advertisement is exchanged manually, but when using the electronic paper to which this Embodiment 3 is applied, the advertisement display can be changed in a short time. When the advertising medium is a paper print, the advertisement is exchanged manually, but when using the electronic paper to which this Embodiment 3 is applied, the advertisement display can be changed in a short time. By using the electronic paper employed, it is possible to change the display of advertisements in a short time without much manual effort. Moreover, a stable image can be obtained without the display being distorted. Incidentally, the in-vehicle advertisement may be configured to be able to transmit and receive information wirelessly.

[0241] Also, FIG. 24 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed about the shaft portion 2711 as an axis. With such a configuration, it is possible to perform operations similar to those of a paper book.

[0242] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen, or may be configured to display different screens. With a configuration of displaying different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 24), and an image can be displayed on the left display unit (display unit 2707 in FIG. 24).

[0243] Also, in FIG. 24, an example in which the housing 2701 is provided with an operation unit and the like is shown. For example, in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, and the like are provided. By operating the operation keys 2723, pages can be turned. Incidentally, a configuration in which a key board, a pointing device, or the like is provided on the same surface as the display unit of the housing may also be adopted. Also, external connection terminals (earphone terminals, USB terminals, or an AC adapter and USB A configuration including terminals connectable to various cables such as cables, a recording medium insertion part, etc. It may be configured as such. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary. It may be.

[0244] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, It is possible to purchase and download desired book data, etc. from an electronic book server. It is also possible.

[0245] (Embodiment 9) The semiconductor device can be applied to various electronic devices (including gaming machines). Electronic devices include, for example, television devices (also called TVs or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, large gaming machines such as pachinko machines, etc.

[0246] Figure 25(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9703 can display images. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0247] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control unit 9610. The operation keys 9609 provided on the remote control unit 9610 can be used to operate channels and volume, and are displayed on the display unit 9603 The video can be operated. Also, the remote control operation device 9610 may be configured to include a display unit 9607 for displaying information output from the remote control operation device 9610.

[0248] Note that the television device 9600 is configured to include a receiver, a modem, and the like. The receiver can receive more general television broadcasts, and can be connected to a communication network by wire or wirelessly via a modem, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0249] FIG. 25(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and can function in the same way as a normal photo stand by displaying image data taken with, for example, a digital camera.

[0250] Note that the digital photo frame 9700 is configured to include an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables, etc.), a recording medium insertion unit, and the like. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface to improve the design. For example, an image memory storing image data taken with a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to capture image data and display the captured image data on the display unit 9703.

[0251] Also, the digital photo frame 9700 may be configured to be able to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired image data is wirelessly captured and displayed.

[0252] FIG. 26(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891, and is connected in an openable and closable manner by a connecting portion 9893. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. Further, the portable gaming machine shown in FIG. 26(A) also includes, among other things, a speaker portion 9884, a recording medium insertion portion 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least a semiconductor device having a thin film transistor shown in Embodiment 1 or Embodiment 2, and other accessory equipment may be appropriately provided. The portable gaming machine shown in FIG. 26(A) has a function of reading a program or data recorded on a recording medium and displaying it on the display portion, and a function of performing wireless communication with another portable gaming machine to share information. In addition, the functions of the portable gaming machine shown in FIG. 26(A) are not limited to this, and it can have various functions. It is composed of two housings, a housing 9881 and a housing 9891, and is connected in an openable and closable manner by a connecting portion 9893. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. Further, the portable gaming machine shown in FIG. 26(A) also includes, among other things, a speaker portion 9884, a recording medium insertion portion 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be a configuration including at least a semiconductor device having a thin film transistor shown in Embodiment 1 or Embodiment 2, and other accessory equipment may be appropriately provided. The portable gaming machine shown in FIG. 26(A) has a function of reading a program or data recorded on a recording medium and displaying it on the display portion, and a function of performing wireless communication with another portable gaming machine to share information. In addition, the functions of the portable gaming machine shown in FIG. 26(A) are not limited to this, and it can have various functions. It is also possible to adopt a configuration in which desired image data is wirelessly captured and displayed. FIG. 26(B) shows an example of a slot machine 9900 which is a large gaming machine. The slot machine 9900 has a display portion 9903 incorporated in a housing 9901. Further, the slot machine 9900 also includes, among other things, a speaker portion 9904, a recording medium insertion portion 9906, an LED lamp 9910, input means (operation keys 9905, connection terminals 9907, a sensor 9908 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9909), etc. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration including at least a semiconductor device having a thin film transistor shown in Embodiment 1 or Embodiment 2, and other accessory equipment may be appropriately provided. The slot machine 9900 has a function of reading a program or data recorded on a recording medium and displaying it on the display portion, and a function of performing wireless communication with another slot machine to share information. In addition, the functions of the slot machine 9900 are not limited to this, and it can have various functions. It is also possible to adopt a configuration in which desired image data is wirelessly captured and displayed. The portable gaming machine shown in FIG. 26(A) has a function of reading a program or data recorded on a recording medium and displaying it on the display portion, and a function of performing wireless communication with another portable gaming machine to share information. In addition, the functions of the portable gaming machine shown in FIG. 26(A) are not limited to this, and it can have various functions. FIG. 26(B) shows an example of a slot machine 9900 which is a large gaming machine. The slot machine 9900 has a display portion 9903 incorporated in a housing 9901. Further, the slot machine 9900 also includes, among other things, a speaker portion 9904, a recording medium insertion portion 9906, an LED lamp 9910, input means (operation keys 9905, connection terminals 9907, a sensor 9908 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9909), etc.

[0253] Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration including at least a semiconductor device having a thin film transistor shown in Embodiment 1 or Embodiment 2, and other accessory equipment may be appropriately provided. The slot machine 9900 has a function of reading a program or data recorded on a recording medium and displaying it on the display portion, and a function of performing wireless communication with another slot machine to share information. In addition, the functions of the slot machine 9900 are not limited to this, and it can have various functions. Machine 9900 also includes operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above, and it may be a configuration having at least a semiconductor device having a thin film transistor shown in Embodiment 1 or Embodiment 2, and other accessory equipment may be provided as appropriate. That's okay.

[0254] FIG. 27 shows an example of a mobile phone 1000. The mobile phone 1000 includes, in addition to a display unit 1002 incorporated in a housing 100 1, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc.

[0255] The mobile phone 1000 shown in FIG. 27 can input information by touching the display unit 1002 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 100 2 with a finger or the like.

[0256] The screen of the display unit 1002 mainly has three modes. The first is a display mode mainly for displaying images, the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the two modes of the display mode and the input mode are mixed.

[0257] For example, when making a call or creating an email, the display unit 1002 can be set to a character input mode mainly for inputting characters, and an input operation of the characters displayed on the screen can be performed. In this case , it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002.

[0258] ​​In addition, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (portrait or landscape) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched.

[0259] Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. It can also be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0260] Also, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and when there is no input by the touch operation of the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0261] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 1002, palm prints, fingerprints, etc. can be imaged to perform personal authentication. Also, if a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light is used for the display unit, finger veins, palm veins, etc. can also be imaged.

[0262] (Embodiment 10) In Embodiment 1 or Embodiment 2, an example of providing a buffer layer was shown, but in this embodiment, an example of not providing a buffer layer is shown. Also, an example of configuring an inverter circuit using two n-channel thin film transistors will be described below.

[0263] ​​​​​​​​​​​​ The drive circuit for driving the pixel portion is configured using an inverter circuit, a capacitor, a resistor, etc. . When forming an inverter circuit by combining two n-channel type TFTs, when formed by combining an enhancement type transistor and a depletion type transistor ( hereinafter referred to as an EDMOS circuit), and when formed by enhancement type TFTs (hereinafter referred to as an EEMOS circuit). When the threshold voltage of the n-channel type TFT is positive , it is defined as an enhancement type transistor, and when the threshold voltage of the n-channel type TFT is negative , it is defined as a depletion type transistor, and this definition is followed throughout this specification .

[0264] The pixel portion and the drive circuit are formed on the same substrate. In the pixel portion, the on / off switching of voltage application to the pixel electrode is switched using enhancement type transistors arranged in a matrix . The enhancement type transistors arranged in this pixel portion use an oxide semiconductor . Its electrical characteristics have an on / off ratio of 10 at a gate voltage of ±20V . Since it is 9 or more, the leakage current is small, and low power consumption driving can be realized.

[0265] The cross-sectional structure of the inverter circuit of the drive circuit is shown in Fig. 32(A). In Fig. 32(A), a first gate electrode 1401 and a second gate electrode 1402 are provided on a substrate 1400 . The materials of the first gate electrode 1401 and the second gate electrode 1402 can be formed using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material mainly composed of these, either in a single layer or laminated . . or laminated.

[0266] For example, a two-layer stacked structure of the first gate electrode 1401 and the second gate electrode 1402 may be a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, or a two-layer structure in which a molybdenum layer is stacked on a copper layer, or a two-layer structure in which a titanium nitride layer or tantalum nitride is stacked on a copper layer, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked. It is preferable to use. As a three-layer stacked structure, it is preferable to stack a tungsten layer or tungsten nitride, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer . In addition, on the gate insulating layer 1403 covering the first gate electrode 1401 and the second gate electrode 1402, a first wiring 1409, a second wiring 1410, and a third wiring 1411 are provided. The second wiring 1410 is directly connected to the second gate electrode 1402 through a contact hole 1404 formed in the gate insulating layer 1403 .

[0267] Also, a first oxide semiconductor layer 1405 in contact with the first wiring 1409 and the second wiring 1410 at a position overlapping the first gate electrode 1401, and a second oxide semiconductor layer 1407 in contact with the second wiring 1410 and the third wiring 1411 at a position overlapping the second gate electrode 1402 are provided .

[0268] The first thin film transistor 1430 has the first gate electrode 1401 and the first oxide semiconductor layer 1405 overlapping the first gate electrode 1401 through the gate insulating layer 1403 . The first wiring 1409 is a power line (ground power line) at a ground potential . This power line at a ground potential is

[0269] ​​​​​​​It may also be a power supply line (negative power supply line) to which a negative voltage VDL is applied.

[0270] Further, the second thin film transistor 1431 has a second gate electrode 1402 and a second oxide semiconductor layer 1407 that overlaps the second gate electrode 1402 via a gate insulating layer The third wiring 1411 is a power supply line (positive power supply line) to which a positive voltage VDD is applied.

[0271] By making the side surfaces of the first wiring 1409 and the second wiring 14 10 facing each other across the first oxide semiconductor layer 1405 have a tapered shape, the regions overlapping the side surfaces of the source electrode layer and the drain electrode layer in the oxide semiconductor layer function as electric field concentration relaxation regions.

[0272] Also, by making the side surfaces of the second wiring 1410 and the third wiring 14 11 facing each other across the second oxide semiconductor layer 1407 have a tapered shape, the regions overlapping the side surfaces of the source electrode layer and the drain electrode layer in the oxide semiconductor layer function as electric field concentration relaxation regions.

[0273] As shown in FIG. 32(A), the second wiring 1410 electrically connected to both the first oxide semiconductor layer 1405 and the second oxide semiconductor layer 14 07 is directly connected to the second gate electrode 1402 of the second thin film transistor 1431 through a contact hole 1404 formed in the gate insulating layer 1403. By directly connecting the second wiring 1410 and the second gate electrode 1402, a good contact can be obtained and the contact resistance can be reduced. Compared with the case where the second gate electrode 1402 and the second wiring 1410 are connected through another conductive film, for example, a transparent conductive film, the number of contact holes can be reduced, and compared with the case where the number of contact holes is reduced, The occupied area can be reduced by subtraction.

[0274] Further, a top view of the inverter circuit of the drive circuit is shown in Fig. 32(C). In Fig. 32(C), the cross section cut along the dashed line Z1-Z2 corresponds to Fig. 32(A).

[0275] Further, an equivalent circuit of the EDMOS circuit is shown in Fig. 32(B). The circuit connection shown in Figs. 32(A) and 32(C) corresponds to Fig. 32(B), and an example is given in which the first thin film transistor 1430 is an enhancement type n-channel transistor, and the second thin film transistor 1431 is a depletion type n-channel transistor.

[0276] Further, although an example of the EDMOS circuit has been shown in this embodiment, in either case, a drive circuit may be configured using an EEMOS circuit in which both are enhancement type n-channel transistors.

[0277] Further, in this embodiment, an example in which no buffer layer is provided has been shown, but it is not particularly limited, and similar to Embodiment 1, a buffer layer may be provided on the top surface of the first wiring 1409, the top surface of the second wiring 1410, and the top surface of the third wiring 1411.

[0278] Further, this embodiment can be combined with any one of Embodiments 1 to 9.

[0279] (Embodiment 11) In this embodiment, stress is applied to the thin film transistor having the model structure shown in Fig. 33 to obtain the degree of deterioration of the electrical characteristics by calculation.

[0280] The structure shown in Fig. 33(A) is such that a gate electrode layer 302, a gate insulating layer 3 They are stacked in the order of 03, and a source electrode layer 304 and a drain electrode layer 305 are formed thereon. An oxide layer 307 is provided on the side surface of the source electrode layer 304, and an oxide layer 308 is provided on the side surface of the drain electrode layer 305. Here, the oxide layers 307 and 308 are natural oxide films of the source electrode layer 304 and the drain electrode layer 305. Further, an oxide semiconductor layer 306 is formed to cover the source electrode layer 304, the drain electrode layer 305, and the oxide layers 307 and 308.

[0281] The gate electrode layer 302 is made of molybdenum, and the source electrode layer 304 and the drain electrode layer 305 are also set to use the same material. The gate insulating layer 303 is a silicon oxide film with a film thickness of 100 nm and a relative dielectric constant εr of 4.1. The film thickness of the oxide semiconductor layer 306 is 50 nm, and an In-Ga-Zn-O based non-single crystal film is used as the material. The channel length L of the thin film transistor is 10 μm, and the channel width W is 10 μm.

[0282] The stress applied to the thin film transistor is such that the gate voltage Vgs = 2V, the voltage Vds between the source electrode and the drain electrode is 20V, the time for applying this stress is 1000 seconds, and the electrical characteristics are compared before and after the stress application.

[0283] In this calculation, it was calculated using the simulation software "Atlas" manufactured by Silvaco.

[0284] Also, the taper angle θ1 of the source electrode layer 304 was calculated as 27 degrees, 45 degrees, or 63 degrees. The taper angle θ1 of the source electrode layer 304 is set to the same angle as the taper angle θ of the drain electrode layer 305.

[0285] The calculation results when the taper angle θ1 of the source electrode layer 304 is 27 degrees are shown in FIG. 34.

[0286] Also, the calculation results when the taper angle θ1 of the source electrode layer 304 is 45 degrees are shown in FIG. 35 as shown.

[0287] Also, the calculation results when the taper angle θ1 of the source electrode layer 304 is 63 degrees are shown in FIG. 36 as shown.

[0288] From the results of FIGS. 34, 35, and 36, it can be obtained that the smaller the taper angle θ1 of the source electrode layer 304, the less likely it is to deteriorate. The result is obtained that it is less likely to deteriorate.

[0289] Also, for comparison, the results of performing the same calculation on the structure shown in FIG. 33(B) with 90 degrees are shown in FIG. 37(A). The structure shown in FIG. 33(B) is the same as FIG. 33(A) except for the different angles. It is the same.

[0290] Also, for comparison, the results of performing the same calculation on the structure shown in FIG. 33(C) with 27 degrees and having an oxide layer on the side surface of the source electrode layer 304 and no oxide layer on the side surface of the drain electrode layer 305 are shown in FIG. 37(B). When there is no oxide layer on the side surface, the same result is obtained regardless of the taper angle θ1. When there is no oxide layer on the side surface, since the interface between the gate insulating layer 303 and the oxide semiconductor layer 306 becomes the current path, the taper angle on the side surface of the source electrode layer 304 has no effect on the current path no matter what degree it is. Since the interface between the gate insulating layer 303 and the oxide semiconductor layer 306 becomes the current path, no matter what degree the taper angle on the side surface of the source electrode layer 304 is, it has no influence on the current path.

[0291] From these results, it can be said that by providing an oxide layer 307 on the side surface of the source electrode layer 304 and an oxide layer 308 on the side surface of the drain electrode layer 30 5, and further making the taper angle θ1 smaller than 90 degrees, the deterioration of the electrical characteristics of the thin film transistor can be suppressed.

[0292] Regarding the embodiment having the above configuration, a more detailed description will be given with the following examples. This will be done.

Example

[0293] In this example, the characteristics of a thin film transistor fabricated using an oxide semiconductor layer will be shown. .

[0294] Hereinafter, the manufacturing method of the transistor used in this example will be described.

[0295] First, after forming a first conductive film on the substrate, the first conductive film was patterned using photolithography to form a gate electrode 502. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere. using electrode 502 Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere. using Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502. Subsequently, a second conductive film and a buffer layer were formed on the gate insulating layer 503. Note that the second conductive film and the buffer layer were continuously formed without exposing the substrate to the atmosphere. Subsequently, the second conductive film and the buffer layer were patterned using photolithography to form a source electrode layer 506a and a drain electrode layer 506b, a part of which overlaps with the gate electrode. Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 510 that functions as a channel formation region. Subsequently, heat treatment was performed at 350°C for 1 hour in a nitrogen atmosphere.

[0296] As the substrate, a glass substrate (product name AN100) manufactured by Asahi Glass Co., Ltd. was used.

[0297] As the first conductive film serving as the gate electrode 502, a tungsten film with a thickness of 100 nm was formed using a sputtering method.

[0298] As the gate insulating layer 503, a silicon oxynitride film with a thickness of 100 nm was formed using a plasma CVD method.

[0299] As the second conductive film serving as the source electrode layer 506a and the drain electrode layer 506b, a tungsten film with a thickness of 100 nm was formed using a sputtering method.

[0300] The buffer layer was formed by sputtering an In-Ga-Zn-O-based polycrystalline film with a thickness of 5 to 10 nm. The film formation conditions were as follows: only argon gas was used, and the target was an In O 2 3 :Ga 2 O 3 :ZnO = 1:1:1 target.

[0301] The oxide semiconductor layer was formed by sputtering an In-Ga-Zn-O-based polycrystalline film with a thickness of 150 nm. The film formation conditions were as follows: the pressure was 0.4 Pa, the power was 500 W, the film formation temperature was 25 °C, the argon gas flow rate was 10 sccm, the oxygen flow rate was 5 sccm, the distance between the glass substrate and the target was 170 mm, and it was performed in direct current (DC). The target was an In O :Ga 2 O 3 :ZnO = 1:1:1 target (In:Ga:Zn = 1:1:0.5). After plasma treatment, the oxide semiconductor layer was continuously formed without exposing the substrate 500 to the atmosphere. The composition of the oxide semiconductor layer obtained under these film formation conditions was analyzed by inductively coupled plasma mass spectrometry (Inductive 2 O 3 :ZnO = 1:1:1 target (In:Ga:Zn = 1:1:0.5). After plasma treatment, the oxide semiconductor layer was continuously formed without exposing the substrate 500 to the atmosphere. The composition of the oxide semiconductor layer obtained under these film formation conditions was analyzed by inductively coupled plasma mass spectrometry (Inductive substrate 500 to the atmosphere. The composition of the oxide semiconductor layer obtained under these film formation conditions was analyzed by inductively coupled plasma mass spectrometry (Inductive Coupled Plasma Mass Spectrometry). ly Coupled Plasma Mass Spectrometry: ICP- The results measured by MS analysis) were InGa 0.94 Zn 0.40 O 3.31 It was 。

[0302] Fig. 28 shows the Vg-Id curve of the thin-film transistor. In this example, the measurement of the transistor was performed with the drain voltage (the voltage of the drain with respect to the voltage of the source) set to 1V 。

[0303] Also, in this example, the structure of the transistor was formed as shown in Fig. 29. Specifically, the channel length L of the transistor was 100 μm, the channel width W was 100 μm, the length Ls where the source electrode layer 5 06a overlaps with the gate electrode 502 was 5 μm, the length Ld where the drain electrode layer 506b overlaps with the gate electrode 502 was 5 μm, and the length A of the region where the oxide semiconductor layer 510 does not overlap with the source electrode layer 506a and the drain electrode layer 506b in the direction parallel to the channel width direction was 5 μm. 。

[0304] As described above, by continuously forming the second conductive film and the buffer layer without exposing the substrate to the atmosphere it was found that the on-off ratio of the transistor can be increased and the field-effect mobility can be increased 。

Example

[0305] Also, in this example, an example of the electrode shape after etching is shown. First, the process of manufacturing the sample will be described with reference to Fig. 30. Note that Example 1 differs only in that the cross-sectional shapes of the source electrode layer and the drain electrode layer are different and the buffer layer is not formed Therefore, the same reference numerals are used to describe the same parts.

[0306] First, after forming a first conductive film on a substrate, the first conductive film was patterned using photolithography to form a gate electrode 502. Subsequently, a gate insulating layer 503 was formed on the gate electrode 502 (see Fig. 30(A)). Subsequently, a second conductive film was formed on the gate insulating layer 503. Subsequently, the second conductive film was patterned using photolithography to form a source electrode layer 606a and a drain electrode layer 606b, a part of which overlaps with the gate electrode (see Fig. 30(B)). Subsequently, after forming an oxide semiconductor layer on the gate insulating layer, the source electrode layer, and the drain electrode layer, the oxide semiconductor layer was patterned using photolithography to form an island-shaped oxide semiconductor layer 610 that functions as a channel formation region (see Fig. 30(C)). As the substrate, a glass substrate (product name: AN100) manufactured by Asahi Glass Co., Ltd. was used. As the first conductive film that becomes the gate electrode 502, a tungsten film with a thickness of 100 nm was formed using sputtering. As the gate insulating layer 503, a silicon oxynitride film with a thickness of 100 nm was formed using plasma CVD. As the second conductive film that becomes the source electrode layer 606a and the drain electrode layer 606b, a tungsten film with a thickness of 100 nm was formed using sputtering. The oxide semiconductor layer is a 150-nm In-Ga-Zn-O-based non-single crystal film formed by sputtering.

[0307]

[0308]

[0309]

[0310]

[0311] ​ was formed. The film formation conditions are the same as those in Example 1.

[0312] Etching of the source electrode layer 606a and the drain electrode layer 606b was performed using an ICP etching apparatus using a coiled antenna. The gas flow rate of CF 4 was 25 (sccm), and the gas flow rate of C l 2 was 25 (sccm), and the gas flow rate of O 2 was 10 (sccm). RF (13.56 MHz) power of 500 W was applied to the coil-type electrode at a pressure of 1.5 Pa to generate plasma and perform etching. RF (13.56 MHz) power of 10 W was also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. At the stage where at least the gate insulating film 503 was exposed to some extent, this etching was stopped halfway, thereby forming electrode side surfaces having a step . By the above etching conditions, the cross-sectional shape of the source electrode layer 606a can be such that the angle θ1 formed by the substrate surface of the substrate and the lower end side surface of the source electrode layer 606a is 20° or more and less than 90°. A cross-sectional photograph of the portion surrounded by the dotted line shown in FIG. 30(C) is shown in FIG. 31(A). Note that FIG. 31(B) is a schematic diagram of FIG. 31(A). As shown in FIG. 31(A), θ1 is about 40

[0313] °. Also, as shown in FIG. 31(A), the angle formed by the substrate surface of the substrate and the upper end side surface of the source electrode layer 606a is about 90°. Note that the cross-sectional shapes of the side surfaces of the source electrode layer 606a and the drain electrode layer 606b facing each other with the oxide semiconductor layer 610 interposed therebetween are substantially the same because they undergo the same etching process.

[0314] According to this example, the cross-sectional shapes of the source electrode layer and the drain electrode layer shown in Embodiment 2 were fabricated. It can be said that it was able to suggest doing.

Explanation of Signs

[0315] 100: Substrate 101: Gate electrode 102: Gate insulating layer 103: Oxide semiconductor layer 104a: First buffer layer 104b: Second buffer layer 105a: Source electrode layer 105b: Drain electrode layer

Claims

1. a pixel portion including a first pixel having a first transistor and a second pixel having a second transistor; the first pixel and the second pixel are disposed adjacent to each other in a first direction, a first conductive layer having a function as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; a second conductive layer having a region in contact with a top surface of the first insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive layer having a region in contact with a top surface of the first insulating layer and functioning as the other of the source electrode and drain electrode of the first transistor; a first oxide semiconductor layer including a region in contact with the second conductive layer and a region in contact with the third conductive layer and including a channel formation region of the first transistor; a fourth conductive layer having a region in contact with the third conductive layer and functioning as a pixel electrode of the first pixel; a fifth conductive layer having the same material as the first conductive layer and having a function as a gate electrode of the second transistor and a function as one electrode of a capacitor element; a sixth conductive layer having a region in contact with an upper surface of the first insulating layer and a region overlapping with the fifth conductive layer and having a function as the other electrode of the capacitance element; the second conductive layer is electrically connected to a second oxide semiconductor layer including a channel formation region of the second transistor; and the first insulating layer has a region in contact with an upper surface of the fifth conductive layer; the fourth conductive layer has a region overlapping with the fifth conductive layer via the sixth conductive layer, the sixth conductive layer has the same material as the second conductive layer and the third conductive layer; A display device, wherein, when viewed cross-sectionally in the first direction, the fifth conductive layer has a region that extends beyond an end of the sixth conductive layer.

2. a pixel portion including a first pixel having a first transistor and a second pixel having a second transistor; the first pixel and the second pixel are disposed adjacent to each other in a first direction, a first conductive layer having a function as a gate electrode of the first transistor; a first insulating layer having a region in contact with an upper surface of the first conductive layer; a second conductive layer having a region in contact with a top surface of the first insulating layer and functioning as one of a source electrode and a drain electrode of the first transistor; a third conductive layer having a region in contact with a top surface of the first insulating layer and functioning as the other of the source electrode and drain electrode of the first transistor; a first oxide semiconductor layer including a region in contact with the second conductive layer and a region in contact with the third conductive layer and including a channel formation region of the first transistor; a fourth conductive layer having a region in contact with the third conductive layer and functioning as a pixel electrode of the first pixel; a fifth conductive layer having the same material as the first conductive layer and having a function as a gate electrode of the second transistor and a function as one electrode of a capacitor element; a sixth conductive layer having a region in contact with an upper surface of the first insulating layer and a region overlapping with the fifth conductive layer and having a function as the other electrode of the capacitance element; the second conductive layer is electrically connected to a second oxide semiconductor layer including a channel formation region of the second transistor; and the first insulating layer has a region in contact with an upper surface of the fifth conductive layer; the fourth conductive layer has a region overlapping with the fifth conductive layer via the sixth conductive layer, the sixth conductive layer has the same material as the second conductive layer and the third conductive layer; When viewed in a cross-sectional view in the first direction, the fifth conductive layer has a region that extends beyond an end of the sixth conductive layer, A display device, wherein, in a plan view, the fourth conductive layer has a region that extends beyond an end of the fifth conductive layer toward the second pixel side.

3. In claim 1 or 2, The display device, wherein the first insulating layer has a laminated structure.

Images