Display device

Abstract

SOLUTION: A display device includes: a substrate including a plurality of subpixels; a first assembly line and a second assembly line which are disposed in the plurality of subpixels on the substrate and are spaced; a first upper planarization layer which is disposed on the first assembly line and the second assembly line and has an opening overlapping the first assembly line and the second assembly line; a light-emitting element which is disposed in the opening and includes a first electrode, a first semiconductor layer, a light emission layer, a second semiconductor layer and a second electrode; a contact electrode which electrically connects the first assembly line and the second assembly line with the first electrode; and an organic insulating layer which is disposed above the first upper planarization layer and covers a part of the side surface and a part of the top surface of the light-emitting element.EFFECT: Thus, the fixing force of the light-emitting element can be improved.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present specification relates to a display device, and more particularly to a display device using LEDs (Light Emitting Diodes). [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide variety of applications, including not only computer monitors and TVs but also personal portable devices. Research is currently underway into display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials rather than organic materials, so they are highly reliable and have a longer lifespan than LCDs and OLEDs. LEDs not only light up quickly, but also have excellent luminous efficiency, strong impact resistance, excellent stability, and can display high brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device capable of improving the fixing force of light-emitting elements.

[0006] Another problem to be solved by the present specification is to provide a display device with improved efficiency in the manufacturing process.

[0007] The subject of the present specification is not limited to the subject mentioned above, and other subjects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to an embodiment of the present specification includes a substrate including a plurality of sub-pixels, a first assembly wiring and a second assembly wiring disposed in the plurality of sub-pixels on the substrate and spaced apart from each other, a first upper planarization layer disposed on the first assembly wiring and the second assembly wiring and having an opening overlapping the first assembly wiring and the second assembly wiring, a light emitting element disposed in the opening and including a first electrode, a first semiconductor layer, a light emitting layer, a second semiconductor layer, and a second electrode, a contact electrode electrically connecting the first assembly wiring and the second assembly wiring to the first electrode, and an organic insulating layer disposed on the first upper planarization layer and covering a part of a side surface and a part of a top surface of the light emitting element, thereby improving the fixing force of the light emitting element.

[0009] Further details of the embodiments are included in the detailed description and the drawings.

[0010] The present invention can minimize the movement of the light emitting device after self-assembly and improve the fixing strength of the light emitting device.

[0011] The present disclosure can improve the efficiency of the bonding process of the light emitting device.

[0012] The effects of the present specification are not limited to the above-mentioned examples, and various other effects are included in the present specification. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic diagram illustrating a configuration of a display device according to an embodiment of the present specification. [Diagram 2] FIG. 1 is an enlarged plan view of a display device according to an embodiment of the present specification. [Diagram 3] FIG. 3 is an enlarged plan view of a region X in FIG. [Figure 4a] 3 is a cross-sectional view taken along line AA' in FIG. 2 and line BB' in FIG. [Figure 4b] FIG. 4 is a cross-sectional view taken along the line CC' in FIG. [Figure 4c] FIG. 4 is a cross-sectional view taken along the line DD' in FIG. [Figure 5a] 1A to 1C are process diagrams illustrating a process for forming a display device according to an embodiment of the present specification. [Figure 5b] 1A to 1C are process diagrams illustrating a process for forming a display device according to an embodiment of the present specification. [Figure 5c] 1A to 1C are process diagrams illustrating a process for forming a display device according to an embodiment of the present specification. [Figure 5d] 1A to 1C are process diagrams illustrating a process for forming a display device according to an embodiment of the present specification. [Figure 5e] 1A to 1C are process diagrams illustrating a process for forming a display device according to an embodiment of the present specification. [Figure 5f] 1A to 1C are process diagrams illustrating a process for forming a display device according to an embodiment of the present specification. [Figure 6] FIG. 13 is an enlarged plan view of a display device according to another embodiment of the present specification. [Figure 7] FIG. 13 is an enlarged plan view of a display device according to still another embodiment of the present specification. [Figure 8] FIG. 13 is an enlarged plan view of a display device according to still another embodiment of the present specification. [Figure 9a] FIG. 13 is an enlarged plan view of a display device according to still another embodiment of the present specification. [Figure 9b] 9b is a cross-sectional view taken along line EE' of FIG. 9a. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The advantages and features of the present invention, and the methods for achieving the same, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely for the purpose of making the disclosure of the present invention complete and fully conveying the scope of the invention to those skilled in the art to which the present invention pertains.

[0015] The shapes, dimensions (e.g., length, width, height, thickness, radius, diameter, area), ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present specification are illustrative, and the present specification is not limited to the matters illustrated. The dimensions, including the size and thickness, of each component shown in the drawings are shown for convenience of explanation, and the present invention is not limited to the size and thickness of the components shown, and the relative size, position, and thickness of the components illustrated in the drawings are part of the present disclosure. The same reference numerals refer to the same components throughout the specification. In addition, in describing this specification, if it is determined that a specific description of related known technology may unnecessarily obscure the gist of this specification, the detailed description will be omitted. When the terms "include", "have", "be made", etc. mentioned in this specification are used, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the plural unless otherwise expressly stated.

[0016] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0017] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., one or more other parts may be located between the two parts, so long as "immediately" or "directly" is not used.

[0018] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0019] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of this specification.

[0020] Like reference numbers refer to like elements throughout the specification.

[0021] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0022] The features of the various embodiments of this specification may be partially or fully combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0023] Various embodiments of the present specification will now be described in detail with reference to the accompanying drawings.

[0024] FIG. 1 is a schematic plan view of a display device according to an embodiment of the present specification.

[0025] For ease of explanation, FIG. 1 shows only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC among various components of the display device 100.

[0026] Referring to FIG. 1, a display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD for supplying various signals to the display panel PN, and a timing controller TC for controlling the gate driver GD and the data driver DD.

[0027] The display panel PN is a component for displaying an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL cross each other in the display panel PN, and each of the sub-pixels SP is connected to the scan lines SL and the data lines DL. In addition, each of the sub-pixels SP may be connected to a high potential power supply line VDD, a low potential power supply line, a reference line RL, etc.

[0028] The sub-pixels SP are the minimum units constituting a screen, and each of the sub-pixels SP includes a light-emitting element and a pixel circuit for driving the light-emitting element. The light-emitting elements may be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0029] The gate driver GD supplies a plurality of scan signals SCAN to a plurality of scan lines SL in response to a plurality of gate control signals GCS provided from a timing controller TC. Although one gate driver GD is shown to be disposed at a distance from one side of the display panel PN in FIG. 1, the number and arrangement of the gate driver GD are not limited thereto.

[0030] The data driver DD converts image data RGB input from the timing controller TC into data voltages Vdata using a reference gamma voltage in response to a plurality of data control signals DCS provided from the timing controller TC. The data driver DD can supply the converted data voltages Vdata to a plurality of data lines DL.

[0031] The timing controller TC aligns externally input image data RGB and supplies it to the data driver DD. The timing controller TC can generate gate control signals GCS and data control signals DCS using externally input synchronous signals, for example, a dot clock signal, a data enable signal, and a horizontal / vertical synchronous signal. The timing controller TC can then supply the generated gate control signals GCS and data control signals DCS to the gate driver GD and data driver DD, respectively, to control the gate driver GD and data driver DD.

[0032] In the following, reference will be made jointly to FIGS. 2 to 4 for a more detailed description of the display panel PN of the display device 100. FIG.

[0033] FIG. 2 is an enlarged plan view of a display device according to an embodiment of the present specification. FIG. 3 is an enlarged plan view of an X region of FIG. 2. FIG. 4a is a cross-sectional view taken along A-A' in FIG. 2 and B-B' in FIG. 3. FIG. 4b is a cross-sectional view taken along C-C' in FIG. 3. FIG. 4c is a cross-sectional view taken along D-D' in FIG. 3. Referring to FIG. 2, each of the sub-pixels SP includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor Cst, and one or more light-emitting elements LED. In FIG. 2, for the sake of simplicity, the hatching of the assembly wiring 120 and the light-emitting element LED is omitted, the contact electrode CE is omitted, and the organic insulating layer OL is omitted. In FIG. 3, the pixel electrode PE is omitted.

[0034] Referring to FIG. 2, the display device 100 includes a plurality of sub-pixels SP, which are repeated in the row direction, including a first sub-pixel SP1 arranged in a first column, a second sub-pixel SP2 arranged in a second column, and a third sub-pixel SP3 arranged in a third column.

[0035] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a light-emitting element LED and a pixel circuit and independently emit light. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel, but is not limited thereto. In addition, the pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0036] The display panel PN includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a first passivation layer 114, a lower planarization layer 115, a second passivation layer 116, a third passivation layer 117, a first upper planarization layer 118, an organic insulating layer OL, and a second upper planarization layer 119.

[0037] The substrate 110 is a component for supporting various components included in the display panel PN and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. The substrate 110 may also be made of a material including a polymer or plastic and having flexibility.

[0038] On a substrate 110, a high potential power supply line VDD, a plurality of data lines DL, a reference line RL, an assembly line 120, a light shielding layer LS, and a first capacitor electrode SC1 are arranged.

[0039] The high potential power supply wiring VDD is a wiring that transmits a high potential power supply voltage to each of the sub-pixels SP. The multiple high potential power supply wirings VDD can transmit the high potential power supply voltage to the second transistor T2 of each of the sub-pixels SP. The high potential power supply wiring VDD can extend along the column direction between the multiple sub-pixels SP. For example, the high potential power supply wiring VDD can be disposed along the column direction between the first sub-pixel SP1 and the third sub-pixel SP3. The high potential power supply wiring VDD can transmit the high potential power supply voltage to each of the multiple sub-pixels SP arranged in the row direction through an auxiliary high potential power supply wiring VDDA described later. In this case, the high potential power supply wiring VDD can be referred to as a first power supply wiring. The column direction can be referred to as a first direction, and the row direction can be referred to as a second direction.

[0040] The data lines DL are lines that transmit data voltages Vdata to the subpixels SP, respectively. The data lines DL may be connected to the first transistors T1 of the subpixels SP, respectively. The data lines DL may extend in the column direction between the subpixels SP. For example, the data line DL extending in the column direction between the first subpixel SP1 and the high potential power line VDD may transmit the data voltage Vdata to the first subpixel SP1, the data line DL disposed between the first subpixel SP1 and the second subpixel SP2 may transmit the data voltage Vdata to the second subpixel SP2, and the data line DL disposed between the third subpixel SP3 and the high potential power line VDD may transmit the data voltage Vdata to the third subpixel SP3.

[0041] The reference line RL is a line that transmits a reference voltage to each of the subpixels SP. The reference line RL may be connected to the third transistor T3 of each of the subpixels SP. The reference line RL may extend in the column direction between the subpixels SP. For example, the reference line RL may extend in the column direction between the second subpixel SP2 and the third subpixel SP3. The third drain electrodes DE3 of the third transistors T3 of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 adjacent to the reference line RL may extend in the row direction and be electrically connected to the reference line RL. In this case, the reference line RL may be referred to as a third power supply line.

[0042] In each of the sub-pixels SP, a light blocking layer LS is disposed on the substrate 110. The light blocking layer LS may block light incident on a transistor below the substrate 110 to minimize leakage current. For example, the light blocking layer LS may block light incident on a second active layer ACT2 of a second transistor T2, which is a driving transistor.

[0043] In each of the sub-pixels SP, a first capacitor electrode SC1 is disposed on the substrate 110. The first capacitor electrode SC1 may form a storage capacitor Cst together with other capacitor electrodes. The first capacitor electrode SC1 may be formed integrally with the light blocking layer LS.

[0044] A buffer layer 111 is disposed on the high potential power supply line VDD, the plurality of data lines DL, the reference line RL, the light shielding layer LS, and the first capacitor electrode SC1. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be, for example, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, and is not limited to this.

[0045] First, a first transistor T1 is disposed on the buffer layer 111 in each of the sub-pixels SP. The first transistor T1 is a transistor that transmits a data voltage Vdata to a second gate electrode GE2 of the second transistor T2. The first transistor T1 may be turned on by a scan signal from a scan line SL, and the data voltage Vdata may be transmitted from a data line DL to the second gate electrode GE2 of the second transistor T2 through the turned-on first transistor T1. Therefore, the first transistor T1 may be referred to as a switching transistor.

[0046] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0047] A first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0048] A gate insulating layer 112 is disposed on the first active layer ACT1. The gate insulating layer 112 is an insulating layer for insulating the first active layer ACT1 and the first gate electrode GE1, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0049] A first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 may be electrically connected to the scan line SL. The first gate electrode GE1 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0050] An interlayer insulating layer 113 is disposed on the first gate electrode GE1. Contact holes are formed in the interlayer insulating layer 113 for connecting the first source electrode SE1 and the first drain electrode DE1 to the first active layer ACT1. The interlayer insulating layer 113 is an insulating layer for protecting the components below the interlayer insulating layer 113, and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0051] A first source electrode SE1 and a first drain electrode DE1 electrically connected to the first active layer ACT1 are disposed on the interlayer insulating layer 113. The first drain electrode DE1 may be connected to the data line DL and the first active layer ACT1, and the first source electrode SE1 may be connected to the first active layer ACT1 and the second gate electrode GE2 of the second transistor T2. The first source electrode SE1 and the first drain electrode DE1 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0052] A second transistor T2 is disposed on the buffer layer 111 in each of the sub-pixels SP. The second transistor T2 is a transistor that supplies a driving current to the light-emitting element LED. The second transistor T2 can be turned on to control the driving current flowing through the light-emitting element LED. Therefore, the second transistor T2 that controls the driving current can be referred to as a driving transistor.

[0053] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0054] A second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0055] A gate insulating layer 112 is disposed on the second active layer ACT2, and a second gate electrode GE2 is disposed on the gate insulating layer 112. The second gate electrode GE2 may be electrically connected to the first source electrode SE1 of the first transistor T1. The second gate electrode GE2 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0056] An interlayer insulating layer 113 is disposed on the second gate electrode GE2, and a second source electrode SE2 and a second drain electrode DE2 electrically connected to the second active layer ACT2 are disposed on the interlayer insulating layer 113. The second drain electrode DE2 may be electrically connected to the second active layer ACT2 and a high potential power wiring VDD, and the second source electrode SE2 may be electrically connected to the second active layer ACT2 and the light emitting element LED. The second source electrode SE2 and the second drain electrode DE2 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0057] A third transistor T3 is disposed on the buffer layer 111 in each of the sub-pixels SP. The third transistor T3 is a transistor for compensating for a threshold voltage of the second transistor T2. The third transistor T3 is connected between the second source electrode SE2 of the second transistor T2 and a reference line RL. The third transistor T3 is turned on to transmit a reference voltage to the second source electrode SE2 of the second transistor T2 to sense the threshold voltage of the second transistor T2. Thus, the third transistor T3 sensing the characteristic of the second transistor T2 may be referred to as a sensing transistor.

[0058] The third transistor T3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3 and a third drain electrode DE3.

[0059] A third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0060] A gate insulating layer 112 is disposed on the third active layer ACT3, and a third gate electrode GE3 is disposed on the gate insulating layer 112. The third gate electrode GE3 may be electrically connected to a scan line SL. The third gate electrode GE3 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0061] An interlayer insulating layer 113 is disposed on the third gate electrode GE3, and a third source electrode SE3 and a third drain electrode DE3 electrically connected to the third active layer ACT3 are disposed on the interlayer insulating layer 113. The third drain electrode DE3 may be electrically connected to the third active layer ACT3 and a reference line RL, and the third source electrode SE3 may be electrically connected to the third active layer ACT3 and a second source electrode SE2 of the second transistor T2. The third source electrode SE3 and the third drain electrode DE3 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0062] The first transistor T1 and the third transistor T3 shown in FIG. 2 are both transistors connected to the scan line SL and controlled, but are not limited thereto, and the pixel circuit may include a transistor connected to the light emitting line EL.

[0063] A second capacitor electrode SC2 is disposed on the gate insulating layer 112. The second capacitor electrode SC2 is one of electrodes forming the storage capacitor Cst and may be disposed to overlap the first capacitor electrode SC1. The second capacitor electrode SC2 may be integrally formed with the second gate electrode GE2 of the second transistor T2 and may be electrically connected to the second gate electrode GE2. The first capacitor electrode SC1 and the second capacitor electrode SC2 may be disposed spaced apart from each other with the buffer layer 111 and the gate insulating layer 112 interposed therebetween.

[0064] On the interlayer insulating layer 113, a plurality of scan lines SL, an auxiliary high potential power supply line VDDA, and a third capacitor electrode SC3 are arranged.

[0065] First, the scan line SL is a line that transmits a scan signal SCAN to each of the sub-pixels SP. The scan line SL may extend in a row direction across the sub-pixels SP. The scan line SL may be electrically connected to the first gate electrode GE1 of the first transistor T1 and the third gate electrode GE3 of the third transistor T3 of each of the sub-pixels SP.

[0066] An auxiliary high potential power supply wiring VDDA is disposed on the interlayer insulating layer 113. The auxiliary high potential power supply wiring VDDA may be disposed extending in the row direction across the sub-pixels SP. The auxiliary high potential power supply wiring VDDA may be electrically connected to the high potential power supply wiring VDD extending in the column direction and the second drain electrodes DE2 of the second transistors T2 of the sub-pixels SP disposed along the row direction.

[0067] A third capacitor electrode SC3 is disposed on the interlayer insulating layer 113. The third capacitor electrode SC3 is an electrode forming the storage capacitor Cst, and may be disposed to overlap the first capacitor electrode SC1 and the second capacitor electrode SC2. The third capacitor electrode SC3 may be integrally formed with the second source electrode SE2 of the second transistor T2 and may be electrically connected to the second source electrode SE2. The second source electrode SE2 may also be electrically connected to the first capacitor electrode SC1 through a contact hole formed in the interlayer insulating layer 113 and the buffer layer 111. Thus, the first capacitor electrode SC1 and the third capacitor electrode SC3 may be electrically connected to the second source electrode SE2 of the second transistor T2.

[0068] The storage capacitor Cst stores a potential difference between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2 while the light emitting element LED emits light, thereby allowing a constant current to be supplied to the light emitting element LED. The storage capacitor Cst includes a first capacitor electrode SC1 formed on the substrate 110 and connected to the second source electrode SE2, a second capacitor electrode SC2 formed on the buffer layer 111 and the gate insulating layer 112 and connected to the second gate electrode GE2, and a third capacitor electrode SC3 formed on the interlayer insulating layer 113 and connected to the second source electrode SE2, and can store a voltage between the second gate electrode GE2 and the second source electrode SE2 of the second transistor T2.

[0069] A first passivation layer 114 is disposed on the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst. The first passivation layer 114 is an insulating layer for protecting the components below the first passivation layer 114, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0070] The lower planarization layer 115 is disposed on the first passivation layer 114. The lower planarization layer 115 may planarize the upper portion of the substrate 110 on which the plurality of transistors T1, T2, T3 and the storage capacitor Cst are disposed. The lower planarization layer 115 may be configured as a single layer or multiple layers and may be made of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0071] A second passivation layer 116 is disposed on the lower planarization layer 115. The second passivation layer 116 is an insulating layer for protecting the structure below the second passivation layer 116, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0072] A connecting electrode 150 and a plurality of assembly wirings 120 are disposed on the second passivation layer 116 .

[0073] The connecting electrode 150 is an electrode that electrically connects the second transistor T2 and the pixel electrode PE. The connecting electrode 150 is the second source electrode SE2 and may be electrically connected to the third capacitor electrode SC3 through contact holes formed in the second passivation layer 116, the lower planarization layer 115, and the first passivation layer 114.

[0074] The connecting electrode 150 may have a multi-layer structure including a first connecting layer 150a and a second connecting layer 150b. The first connecting layer 150a is disposed on the second passivation layer 116, and the second connecting layer 150b is disposed to cover the first connecting layer 150a. The second connecting layer 150b may be disposed to surround all of the top and side surfaces of the first connecting layer 150a.

[0075] The second connecting layer 150b is made of a material that is more resistant to corrosion than the first connecting layer 150a, and can minimize short circuit defects caused by migration between the first connecting layer 150a and adjacent wiring during the manufacture of the display device 100. For example, the first connecting layer 150a can be made of a conductive material such as copper (Cu) or chromium (Cr), and the second connecting layer 150b can be made of molybdenum (Mo), molybdenum titanium (MoTi), etc., but is not limited thereto.

[0076] A plurality of interconnect fabrication lines 120 are disposed on the second passivation layer 116 .

[0077] The plurality of assembly wirings 120 include a plurality of first assembly wirings 121 and a plurality of second assembly wirings 122 .

[0078] The first assembly wirings 121 and the second assembly wirings 122 may extend in the column direction in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively, and may be spaced apart from each other at regular intervals.

[0079] The assembly wirings 120 may be arranged in an area overlapping with the low potential power supply wiring and electrically connected to the low potential power supply wiring. The low potential power supply wiring is a wiring that transmits a low potential power supply voltage to the light emitting element LED. The low potential power supply wiring may extend in the column direction in each of the sub-pixels SP. For example, the low potential power supply wiring may be arranged in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0080] Each of the multiple assembly wirings 120 includes a conductive layer 121a, 122a disposed on the second passivation layer 116, and a cladding layer 121b, 122b disposed on the conductive layers 121a, 122a and covering all the upper and side surfaces of the conductive layers 121a, 122a.

[0081] The first assembly wiring 121 includes a first conductive layer 121a and a first cladding layer 121b, and the second assembly wiring 122 includes a second conductive layer 122a and a second cladding layer 122b.

[0082] The first conductive layer 121a and the second conductive layer 122a may not overlap the light-emitting element LED, that is, the ends of the first conductive layer 121a and the second conductive layer 122a may be disposed outside the ends of the light-emitting element LED.

[0083] The first cladding layer 121b of the first assembly wiring 121 may be disposed so as to cover the upper surface and side surfaces of the first conductive layer 121a, and the second cladding layer 122b of the second assembly wiring 122 may be disposed so as to cover the upper surface and side surfaces of the second conductive layer 122a. In this case, the first cladding layer 121b and the second cladding layer 122b may extend from the ends of the first conductive layer 121a and the second conductive layer 122a toward the center of the light-emitting element LED and overlap with the light-emitting element LED. For example, the first cladding layer 121b and the second cladding layer 122b may be disposed so as to overlap an area corresponding to less than half of the area of ​​the lower surface of the light-emitting element LED.

[0084] The first conductive layer 121a and the second conductive layer 122a may be made of the same material and through the same process as the first connecting layer 150a of the connecting electrode 150. For example, the first conductive layer 121a and the second conductive layer 122a may be made of a conductive material such as copper (Cu) and chromium (Cr). The first clad layer 121b and the second clad layer 122b may be made of the same material and through the same process as the second connecting layer 150b of the connecting electrode 150. For example, the first clad layer 121b and the second clad layer 122b may be made of a material that is more resistant to corrosion than the first conductive layer 121a and the second conductive layer 122a, such as, but not limited to, molybdenum (Mo) or molybdenum titanium (MoTi).

[0085] A third passivation layer 117 is disposed on the connecting electrodes 150 and the assembly wiring 120. The third passivation layer 117 is an insulating layer for protecting the components below the third passivation layer 117, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0086] The third passivation layer 117 may have some open areas adjacent to the light emitting elements LED. For example, the third passivation layer 117 may expose some upper surfaces of the first assembly wiring 121 and the second assembly wiring 122 in areas adjacent to one side of the light emitting elements LED.

[0087] The first upper planarization layer 118 is disposed on the third passivation layer 117. The first upper planarization layer 118 can planarize an upper portion of the third passivation layer 117. The first upper planarization layer 118 can cover a portion of the first cladding layer 121b of the first assembly wiring 121 and a portion of the first cladding layer 122b of the second assembly wiring 122.

[0088] The first upper planarization layer 118 may be configured as a single layer or multiple layers, and may be made of, for example, an acrylic organic material, but is not limited thereto.

[0089] Meanwhile, the first upper planarization layer 118 includes a plurality of openings 118a arranged at positions corresponding to the plurality of sub-pixels SP. The plurality of openings 118a are portions into which the plurality of light-emitting elements LED are inserted, and may also be referred to as pockets.

[0090] One opening 118a may be arranged to overlap a portion of the first assembly wiring 121 and the second assembly wiring 122 arranged adjacent to each other in one subpixel SP. That is, a portion of the first cladding layer 121b of the first assembly wiring 121 and a portion of the first cladding layer 122b of the second assembly wiring 122 may be arranged inside the opening 118a where the first upper planarization layer 118 is not arranged.

[0091] The third passivation layer 117 may be opened at some regions through the plurality of openings 118a. For example, the third passivation layer 117 may expose some of the top surfaces of the first assembly wiring 121 and the second assembly wiring 122 through the plurality of openings 118a in regions other than the regions where the organic insulating layer OL is disposed, as shown in Figures 4a to 4c.

[0092] A plurality of light emitting elements LED are disposed on the third passivation layer 117 through the plurality of openings 118a. One or more light emitting elements LED are disposed in one sub-pixel SP. As shown in FIG. 2, two light emitting elements LED may be disposed in one sub-pixel SP. The light emitting element LED is an element that emits light by current. The light emitting element LED may include light emitting elements LED that emit red light, green light, blue light, etc., and various colors including white light may be realized by combining these light emitting elements LED. In addition, various colors of light may be realized by using a light emitting element LED that emits light of a specific color and a light conversion member that converts light from the light emitting element LED into light of another color.

[0093] The light emitting element LED can emit light by receiving a driving current from the second transistor T2. The light emitting element LED can include a red light emitting element, a green light emitting element, and a blue light emitting element. For example, the light emitting element LED arranged in the first sub-pixel SP1 can be a red light emitting element, the light emitting element LED arranged in the second sub-pixel SP2 can be a green light emitting element, and the light emitting element LED arranged in the third sub-pixel SP3 can be a blue light emitting element, but is not limited thereto.

[0094] In this case, the light emitting elements LED arranged in one sub-pixel SP may be connected in parallel, that is, one electrode of each of the light emitting elements LED may be connected to the source electrode SE2 of the same second transistor T2, and the other electrodes of each of the light emitting elements LED may be connected to the same assembly wiring 120.

[0095] The light emitting element LED may include a first light emitting element 130 and a second light emitting element 140. The light emitting element LED arranged in each of the plurality of sub-pixels SP may be arranged in a column direction. For example, as shown in FIG. 2 and FIG. 3, the second light emitting element 140 may be arranged above the first light emitting element 130.

[0096] The first light emitting element 130 can emit the same color as the second light emitting element 140. In this case, since the first light emitting element 130 and the second light emitting element 140 are the same type of light emitting element LED, the size of the first light emitting element 130 can be the same as the size of the second light emitting element 140. Here, the size of the light emitting element LED can refer to the area of ​​the bottom surface of the light emitting element LED, the width on the cross section, the volume, the height, etc., but is not limited thereto.

[0097] In Figures 2 and 4, for convenience of explanation, two light-emitting elements LED are arranged in each of the multiple sub-pixels SP, but the number of light-emitting elements LED arranged in each of the multiple sub-pixels SP is not limited to this.

[0098] 3 to 4c, the light emitting element 130 includes a first semiconductor layer 131, a light emitting layer 132, a second semiconductor layer 133, a first electrode 134, a second electrode 135, and an encapsulation layer 136.

[0099] A first semiconductor layer 131 is disposed on the third passivation layer 117, and a second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. with p-type or n-type impurities. The p-type impurities may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium (Ge), tin (Sn), etc., but are not limited thereto.

[0100] A portion of the first semiconductor layer 131 may be disposed to protrude outward from the second semiconductor layer 133. The top surface of the first semiconductor layer 131 may include a portion overlapping the bottom surface of the second semiconductor layer 133 and a portion disposed outside the bottom surface of the second semiconductor layer 133. However, the sizes and shapes of the first semiconductor layer 131 and the second semiconductor layer 133 may be modified in various ways and are not limited thereto.

[0101] The light emitting layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The light emitting layer 132 can have a single layer or a multi-quantum well (MQW) structure and can be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0102] A first electrode 134 is disposed surrounding the bottom and side surfaces of the first semiconductor layer 131. The first electrode 134 is an electrode for electrically connecting the first light emitting element 130 to the assembly wiring 120. The first electrode 134 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but is not limited thereto.

[0103] The second electrode 135 is disposed on an upper surface of the second semiconductor layer 133. The second electrode 135 is an electrode that electrically connects a pixel electrode PE (to be described later) and the second semiconductor layer 133. The second electrode 135 may be made of a conductive material, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0104] An encapsulation layer 136 is disposed to surround at least a portion of the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation layer 136 is made of an insulating material and can protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. The encapsulation layer 136 can be disposed to cover the light emitting layer 132, a portion of a side surface of the first semiconductor layer 131 adjacent to the light emitting layer 132, and a portion of a side surface of the second semiconductor layer 133 adjacent to the light emitting layer 132. The first electrode 134 and the second electrode 135 can be exposed from the encapsulation layer 136, and the first electrode 134 and the second electrode 135 can be electrically connected to a contact electrode CE and a pixel electrode PE to be formed later.

[0105] 4a, the second light emitting element 140 is disposed on the third passivation layer 117. The second light emitting element 140 is disposed above the first light emitting element 130, and is disposed in one sub-pixel SP together with the first light emitting element 130 and the pixel circuit.

[0106] The second light emitting element 140 includes a first semiconductor layer 141, a light emitting layer 142, a second semiconductor layer 143, a first electrode 144, a second electrode 145, and a sealing layer 146. The first semiconductor layer 141, the light emitting layer 142, the second semiconductor layer 143, the second electrode 145, and the sealing layer 146 of the second light emitting element 140 may be substantially the same as the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the second electrode 135, and the sealing layer 136 of the first light emitting element 130. Therefore, a duplicated description will be omitted.

[0107] The second light emitting element 140 may be electrically connected to the first light emitting element 130 and the pixel electrode PE extending from the pixel circuit through a contact hole formed in the organic insulating layer OL and the second upper planarization layer 119. Thus, in one sub-pixel SP, the first light emitting element 130 and the second light emitting element 140 may be electrically connected to the second transistor T2.

[0108] A contact electrode CE is disposed inside the opening 118a. The contact electrode CE electrically connects the first assembly wiring 121 and the second assembly wiring 122 disposed inside the opening 118a to the first electrodes 134 and 144 of the light emitting element LED.

[0109] The contact electrode CE may contact a side surface of the light emitting element LED in an area other than an area where the first portion OL1 of the organic insulating layer OL is disposed. For example, the contact electrode CE may be disposed inside the opening 118a and contact at least a portion of the first electrodes 134, 144. In this case, the contact electrode CE may contact the first cladding layer 121b of the first assembly wiring 121 and the second cladding layer 121b of the second assembly wiring 121 in an area where the third passivation layer 117 is opened, and electrically connect the first assembly wiring 121 and the second assembly wiring 122 to the first electrodes 134, 144.

[0110] Meanwhile, the contact electrode CE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0111] An organic insulating layer OL is disposed on the first upper planarizing layer 118. The organic insulating layer OL is also disposed inside the opening 118a, and a portion of the organic insulating layer OL may be in contact with the plurality of light-emitting elements LED. For example, the organic insulating layer OL may cover a portion of the side surface and a portion of the top surface of the plurality of light-emitting elements LED. At this time, the plurality of light-emitting elements LED may be stably fixed inside the opening 118a by the organic insulating layer OL.

[0112] The organic insulating layer OL may be made of an acryl-based organic material, but is not limited thereto.

[0113] The organic insulating layer OL includes a first portion OL1, a second portion OL2, and a third portion OL3.

[0114] The first portion OL1 is a portion of the upper surface, lower surface, and side surface of the plurality of light-emitting element LEDs that contacts the side surface of the light-emitting element LED. Thus, the first portion OL1 may be a portion of the organic insulating layer OL that is disposed in the opening 118a. On the other hand, the first portion OL1 may be disposed in a portion of the side surface of the light-emitting element LED excluding the portion that contacts the contact electrode CE.

[0115] The first portion OL1 may overlap both the first assembly wiring 121 and the second assembly wiring 122 within the opening 118a. In this case, the first portion OL1 may be disposed on the third passivation layer 117 within the opening 118a, and may be disposed so as to overlap the first assembly wiring 121 and the second assembly wiring 122. In this case, referring to FIG 3, the area of ​​the region where the first portion OL1 overlaps with the first assembly wiring 121 may be the same as the area of ​​the region where the first portion OL1 overlaps with the second assembly wiring 122.

[0116] The first portion OL1 of the organic insulating layer OL may extend outside the opening 118a and be disposed on the first upper planarization layer 118.

[0117] The second portion OL2 of the organic insulating layer OL is disposed on the upper surface of the light-emitting element LED among the upper surfaces, lower surfaces, and side surfaces of the light-emitting element LED, and is a portion that covers a part of the upper surface of the light-emitting element LED. Thus, the side surface of the second portion OL2 may be disposed along a part of the periphery of the second electrodes 135, 145.

[0118] The second portion OL2 is disposed on the upper surfaces of the light-emitting elements LED so that the light-emitting elements LED are fixed without falling off. The third portion OL3 is a portion of the upper, lower and side surfaces of the light-emitting elements LED that is disposed under the light-emitting elements LED.

[0119] The third portion OL3 of the organic insulating layer OL may be disposed in a space between the third passivation layer 117 and the light-emitting element LED. Thus, the third portion OL3 may contact the lower surface of the light-emitting element LED. Also, the third portion OL3 may be disposed so as to overlap the third passivation layer 117 disposed on the first assembly wiring 121 and the second assembly wiring 122 below the plurality of light-emitting elements LED. At this time, the third portion OL3 may function as an adhesive layer so as to fix the light-emitting element LED to the third passivation layer 117.

[0120] A second upper planarization layer 119 is disposed on the organic insulating layer OL and the organic insulating layer opening OLa where no organic insulating layer is formed. The second upper planarization layer 119 can planarize the upper portion of the substrate 110 on the organic insulating layer OL.

[0121] The second upper planarization layer 119 may be configured as a single layer or multiple layers. For example, the second upper planarization layer 119 may be made of an acrylic organic material, but is not limited thereto.

[0122] The second upper planarization layer 119 may fill the opening 118a to planarize the upper portion of the substrate 110 on which the plurality of light-emitting elements LED are disposed. For example, the second upper planarization layer 119 may fill the opening 118a in a region other than the region in which the organic insulating layer OL is disposed. Thus, the second upper planarization layer 119 may be disposed on the contact electrode CE inside the opening 118a. The planar shape of the second upper planarization layer 119 disposed in the opening 118a may be rectangular as shown in FIG. 3.

[0123] Meanwhile, the second upper planarization layer 119 may contact parts of the side surfaces and parts of the top surfaces of the light emitting elements LED through the openings 118a. Referring to Figures 4a to 4c, the second upper planarization layer 119 includes contact holes exposing parts of the top surfaces of the light emitting elements LED. The pixel electrode PE may be disposed in the contact hole of the second upper planarization layer 119 and electrically connected to the second electrodes 135 and 145 of the light emitting elements LED.

[0124] The pixel electrode PE is disposed on the second upper planarization layer 119 .

[0125] The pixel electrode PE is an electrode for electrically connecting the plurality of light emitting elements LED and the connecting electrode 150. The pixel electrode PE is electrically connected to the pixel circuit and is disposed extending to the first light emitting element 130 and the second light emitting element 140. That is, the pixel electrode PE may extend from the first light emitting element 130 and be connected to the second light emitting element 140, and may be electrically connected to the connecting electrode 150 and the second transistor T2 through a contact hole formed in the second upper planarization layer 119.

[0126] 4b, the pixel electrode PE may be disposed on the plurality of light emitting elements LED in an area where the organic insulating layer OL is not disposed. In this case, the pixel electrode PE may contact the second electrodes 135 and 145 in an area on the upper surface of the plurality of light emitting elements LED except for an area where the second portion OL2 is disposed without forming a separate contact hole in the second portion OL2 of the organic insulating layer OL.

[0127] The pixel electrode PE may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0128] A method for manufacturing the display device 100 will be described below with reference to FIGS. 5a to 5f.

[0129] 5a to 5f are process diagrams illustrating a process for forming a display device according to an embodiment of the present disclosure.

[0130] 5a, the light emitting element LED can be self-assembled inside the opening 118a using the first assembly wiring 121 and the second assembly wiring 121. The first upper planarization layer 118 provides a pocket, which is a space in which the light emitting element LED is seated, and the light emitting element LED can be seated on the third passivation layer 117 disposed inside the opening 118a.

[0131] Next, referring to Fig. 5b, an organic insulating layer OL is formed on the front surface of the substrate 110. Specifically, the organic insulating layer OL may be formed on the first upper planarization layer 118 and the light emitting element LED. The organic insulating layer OL may be formed to contact the front surface of the light emitting element LED inside the opening 118a. Also, the organic insulating layer OL may become a third portion OL3 of the organic insulating layer OL that permeates between the third passivation layer 117 and the light emitting element LED while being formed on the front surface of the substrate 110 and serves as an adhesive between the third passivation layer 117 and the light emitting element LED.

[0132] Next, referring to FIG. 5c, the organic insulating layer OL is patterned to remove a portion of the organic insulating layer OL disposed inside the opening 118a. Through the patterning process, a portion of the organic insulating layer OL covering the side of the first upper planarization layer 118, the side of the light emitting element LED, and the upper portion of the light emitting element LED can be removed in the opening 118a. For example, as shown in FIG. 3, a rectangular area in the organic insulating layer OL on a plane can be removed through an ashing process. Thus, a portion of the first portion OL1 of the organic insulating layer OL covering the side of the light emitting element LED and a portion of the second portion OL2 covering the upper surface of the light emitting element LED can remain. Thus, the organic insulating layer OL can fix the light emitting element LED during the subsequent process, and prevent the light emitting element LED from being separated.

[0133] At this time, a portion of the third passivation layer 117 disposed under the organic insulating layer OL may also be removed. For example, the third passivation layer 117 may be removed from a portion of the organic insulating layer OL other than the first portion OL1 and the third portion at the opening 118a. As a result, a portion of the upper surface of the first assembly wiring 121 and a portion of the upper surface of the second assembly wiring 122 may be exposed.

[0134] 5d, a conductive layer CL is formed on the front surface of the substrate 110. Specifically, the conductive layer CL may be formed to cover the first upper planarization layer 118 and the light-emitting element LED. In particular, the conductive layer CL may be formed to contact an upper surface of the first assembly wiring 121 and an upper surface of the second assembly wiring 121 exposed by the third passivation layer 117 inside the opening 118a.

[0135] 5e, a portion of the conductive layer CL disposed on the organic insulating layer OL and the first upper planarization layer 118 is removed through an etching process. For example, only the conductive layer CL disposed on the upper surface of the first assembly wiring 121 exposed through the contact hole of the third passivation layer 117 inside the opening 118a and the upper surface of the second assembly wiring 121 may remain. Thus, a contact electrode CE in contact with a side surface of the first semiconductor layer 131 may be formed.

[0136] 5e, a second upper planarization layer 119 is formed on the front surface of the substrate 110. The second upper planarization layer 119 may fill the area where the first upper planarization layer 118 has been removed. For example, the second upper planarization layer 119 may be disposed in the area inside the opening 118a except for the organic insulating layer OL, and may cover the contact electrode CE and the light-emitting element LED. Thus, the second upper planarization layer 119 may cover the light-emitting element LED together with the organic insulating layer OL inside the opening 118a.

[0137] 5f, a pixel electrode PE is formed on the second upper planarization layer 119. Specifically, a contact hole is formed in a portion of the second upper planarization layer 119 above the light emitting element LED so that the pixel electrode PE can be connected to the light emitting element LED.

[0138] When manufacturing a display device by self-assembling the light emitting devices inside the opening, the light emitting devices are fixed to the substrate by a bonding layer disposed under the light emitting devices. For example, an organic layer is coated on the substrate so that the organic layer can penetrate to the lower part of the light emitting devices after the self-assembly of the light emitting devices. Then, the organic layer is removed from the remaining area except for the organic layer disposed under the light emitting devices, and the light emitting devices are fixed to the substrate by a bonding layer disposed on the organic layer disposed under the light emitting devices. In this case, the bonding layer is disposed only on the lower surface of the light emitting device, so that the fixing force of the light emitting device to the substrate is weakened. Therefore, when the light emitting devices are self-assembled inside the opening and then the contact electrode, the second upper planarization layer, the pixel electrode, etc. are formed on the light emitting devices, the light emitting devices may not be fixed and may move, so that the light emitting devices may be separated from the opening, or the light emitting devices may be moved, so that a contact failure may occur during the process of forming the contact electrode, etc. on the light emitting devices. In addition, a thick organic layer removal process is performed to remove all areas of the organic layer disposed on the substrate except for the organic layer disposed under the light emitting devices, so the efficiency of the process is reduced.

[0139] In the display device 100 according to an embodiment of the present specification, after the light emitting element LED is self-assembled inside the opening 118a on the substrate 110, the organic insulating layer OL for fixing the light emitting element LED may be formed to contact at least the upper surface and the side surface of the light emitting element LED. That is, the organic insulating layer OL may fix the light emitting element LED to the inside of the opening 118a by the upper surface, the side surface, and the lower surface of the light emitting element LED. As a result, the fixing force between the light emitting element LED and the substrate 110 may be improved, and the light emitting element LED may be prevented from being separated. In addition, the occurrence of errors due to the movement of the light emitting element LED may be prevented during the process of forming the contact electrode CE on the self-assembled light emitting element LED.

[0140] In addition, in the display device 100 according to an embodiment of the present specification, the first upper planarization layer 118 and the organic insulating layer OL are also disposed outside the opening 118a. Therefore, the process of removing the first upper planarization layer 118 and the organic insulating layer OL outside the opening 118a is not performed, and the efficiency of the organic layer removal process may be improved.

[0141] In addition, in the display device 100 according to an embodiment of the present specification, the first upper planarization layer 118 and the organic insulating layer OL may extend through the opening 118a to cover the pixel circuit of the sub-pixel SP. Thus, the organic insulating layer OL insulates the pixel circuit from other components without the need for an additional passivation layer, thereby preventing the risk of short circuit.

[0142] Fig. 6 is an enlarged plan view of a display device according to another embodiment of the present specification. The display device 600 of Fig. 6 is substantially the same as the display device 100 of Figs. 1 to 5f except that only the contact electrode CE, the organic insulating layer OL, and the second upper planarization layer are different, and therefore, a duplicated description will be omitted.

[0143] An organic insulating layer OL is disposed on the first upper planarization layer 118. The organic insulating layer OL includes a first portion OL1, a second portion OL2, and a third portion.

[0144] The first portion OL1 may contact a part of the side of the light-emitting element LED at the opening 118a. The first portion OL1 may overlap both the first assembly wiring 121 and the second assembly wiring 122 within the opening 118a. The area of ​​the region where the first portion OL1 overlaps with the first assembly wiring 121 on the first light-emitting element 130 may differ from the area of ​​the region where the first portion OL1 overlaps with the second assembly wiring 122. For example, the first portion OL1 may overlap the entire side of the first light-emitting element 130 arranged on the first assembly wiring 121. Meanwhile, the first portion OL1 may overlap a part of the side of the first light-emitting element 130 arranged on the second assembly wiring 122. As shown in FIG. 6, the first portion OL1 may be arranged to overlap half of the side of the first light-emitting element 130 arranged on the second assembly wiring 122, but is not limited thereto. The first portion OL1 may also overlap a part of the side of the second light-emitting element 140 arranged on the first assembly wiring 121. 6, the first portion OL1 may be disposed so as to overlap half of a side surface of the second light emitting element 140 disposed on the first assembly wiring 121, but is not limited thereto. Meanwhile, the first portion OL1 may overlap the entire side surface of the second light emitting element 140 disposed on the second assembly wiring 122.

[0145] The second portion OL2 is disposed on the plurality of light-emitting elements LED within the opening 118a. The area of ​​the region where the second portion OL2 overlaps with the first assembly wiring 121 on the first light-emitting element 130 may differ from the area of ​​the region where the second portion OL2 overlaps with the second assembly wiring 122. For example, the second portion OL2 may entirely overlap with the upper surface of the first light-emitting element 130 disposed on the first assembly wiring 121. Meanwhile, the second portion OL2 may overlap with a portion of the upper surface of the first light-emitting element 130 disposed on the second assembly wiring 122. As shown in FIG. 6, the second portion OL2 may be disposed so as to overlap with half of the upper surface of the first light-emitting element 130 disposed on the second assembly wiring 122, but is not limited thereto. Also, the second portion OL2 may overlap with a portion of the upper surface of the second light-emitting element 140 disposed on the first assembly wiring 121. 6, the second portion OL2 may be disposed so as to overlap with half of the upper surface of the second light emitting element 140 disposed on the first assembly wiring 121, but is not limited thereto. Meanwhile, the second portion OL2 may overlap with the entire upper surface of the second light emitting element 140 disposed on the second assembly wiring 122.

[0146] Although not shown in FIG. 6, the third portion may be disposed in the space between the third passivation layer 117 and the light-emitting element LED, and may be in contact with the bottom surface of the light-emitting element LED.

[0147] The contact electrode CE is disposed inside the opening 118a. The contact electrode CE is disposed in a region other than the region in which the first portion OL1 of the organic insulating layer OL is disposed. Therefore, the area where the side surface of the light-emitting element LED and the contact electrode CE contact each other may be smaller than the area where the side surface of the light-emitting element LED and the first portion OL1 contact each other.

[0148] Although not shown in FIG. 6, a second upper planarizing layer is disposed on the organic insulating layer OL and in the organic insulating layer openings OLa where no organic insulating layer is formed.

[0149] The second upper planarization layer can fill the opening 118a in the region other than the region where the organic insulating layer OL is disposed in the opening 118a. Thus, the second upper planarization layer can be disposed on the contact electrode CE inside the opening 118a.

[0150] The second upper planarization layer may contact parts of the side surfaces of the plurality of light-emitting element LEDs and parts of the top surfaces of the light-emitting element LEDs at the openings 118a.

[0151] The second upper planarization layer includes a contact hole exposing a portion of an upper surface of the light emitting element LED. A pixel electrode PE is disposed in the contact hole of the second upper planarization layer 119 and may be electrically connected to the second electrodes 135 and 145 of the light emitting element LED.

[0152] In the display device 600 according to another embodiment of the present specification, after the light-emitting element LED is self-assembled inside the opening 118a on the substrate 110, the organic insulating layer OL for fixing the light-emitting element LED may be formed to contact at least the upper surface and the side surface of the light-emitting element LED. As a result, the fixing force between the light-emitting element LED and the substrate 110 may be improved, and the light-emitting element LED may be prevented from coming off.

[0153] In addition, in the display device 600 according to another embodiment of the present specification, the process of removing the first upper planarization layer 118 and the organic insulating layer OL outside the opening 118a is not performed, so that the efficiency of the organic layer removal process may be improved.

[0154] In addition, in the display device 600 according to another embodiment of the present disclosure, the first upper planarization layer 118 and the organic insulating layer OL insulate the pixel circuit from other components without the need for an additional passivation layer, thereby preventing the risk of short circuit.

[0155] In addition, in the display device 600 according to another embodiment of the present specification, the organic insulating layer OL may cover more than half of the area of ​​the top surface of the light-emitting element LED and more than half of the side surface of the light-emitting element LED, thereby improving the fixing force between the light-emitting element LED and the substrate 110 and preventing the light-emitting element LED from coming off.

[0156] 7 is an enlarged plan view of a display device according to another embodiment of the present specification. The display device 700 of FIG. 7 is substantially the same as the display device 100 of FIG. 1 to FIG. 5f except for the contact electrode CE, the organic insulating layer OL, and the second upper planarization layer, and therefore the overlapping description will be omitted.

[0157] An organic insulating layer OL is disposed on the first upper planarization layer 118. The organic insulating layer OL includes a first portion OL1, a second portion OL2, and a third portion.

[0158] The first portion OL1 may contact a part of the side of the light emitting element LED at the opening 118a. The first portion OL1 contacting the first light emitting element 130 may overlap one of the first assembly wiring 121 and the second assembly wiring 122, and the first portion OL1 contacting the second light emitting element 140 may overlap the other one of the first assembly wiring 121 and the second assembly wiring 122. For example, as shown in FIG. 7, the first portion OL1 may be disposed only in a region overlapping the first assembly wiring 121 in the side of the first light emitting element 130. Meanwhile, the first portion OL1 may be disposed only in a region overlapping the second assembly wiring 122 in the side of the second light emitting element 140. Meanwhile, in FIG. 7, the first portion OL1 is disposed only in a region corresponding to 1 / 4 of the side of the first light emitting element 130 and a region corresponding to 1 / 4 of the side of the second light emitting element 140, but the position of the first portion OL1 is not limited thereto.

[0159] The second portion OL2 is disposed on the plurality of light-emitting elements LED within the opening 118a. The second portion OL2 in contact with the first light-emitting element 130 may overlap one of the first assembly wiring 121 and the second assembly wiring 122, and the second light-emitting element 140 and the second portion OL2 may overlap the other one of the first assembly wiring 121 and the second assembly wiring 122. For example, as shown in FIG. 7, the second portion OL2 may be disposed only in a region overlapping with the first assembly wiring 121 in the side of the first light-emitting element 130. Meanwhile, the second portion OL2 may be disposed only in a region overlapping with the second assembly wiring 122 in the side of the second light-emitting element 140. Meanwhile, in FIG. 7, the second portion OL2 is disposed only in a region corresponding to 1 / 4 of the side of the first light-emitting element 130, and the second portion OL2 is disposed only in a region corresponding to 1 / 4 of the side of the second light-emitting element 140, but the position of the second portion OL2 is not limited thereto.

[0160] Although not shown in FIG. 7, the third portion may be disposed in the space between the third passivation layer 117 and the light-emitting element LED, and may be in contact with the bottom surface of the light-emitting element LED.

[0161] The contact electrode CE is disposed inside the opening 118a. The contact electrode CE is disposed in a region other than the region where the first portion OL1 of the organic insulating layer OL is disposed. Thus, the contact electrode CE may be disposed so as to overlap more than half of the side surface of the light-emitting element LED. Thus, the area where the side surface of the light-emitting element LED and the contact electrode CE contact each other may be larger than the area where the side surface of the light-emitting element LED and the first portion OL1 contact each other.

[0162] Although not shown in FIG. 7, a second upper planarizing layer is disposed on the organic insulating layer OL and in the organic insulating layer openings OLa where no organic insulating layer is formed.

[0163] The second upper planarization layer can fill the opening 118a in the region other than the region where the organic insulating layer OL is disposed in the opening 118a. Thus, the second upper planarization layer can be disposed on the contact electrode CE inside the opening 118a.

[0164] The second upper planarization layer may contact parts of the side surfaces of the plurality of light-emitting element LEDs and parts of the top surfaces of the light-emitting element LEDs at the openings 118a.

[0165] The second upper planarization layer includes a contact hole exposing a portion of an upper surface of the light emitting element LED. A pixel electrode PE is disposed in the contact hole of the second upper planarization layer 119 and may be electrically connected to the second electrodes 135 and 145 of the light emitting element LED.

[0166] In the display device 700 according to another embodiment of the present specification, after the light-emitting element LED is self-assembled inside the opening 118a on the substrate 110, the organic insulating layer OL for fixing the light-emitting element LED may be formed to contact at least the upper surface and the side surface of the light-emitting element LED. As a result, the fixing force between the light-emitting element LED and the substrate 110 may be improved, and the light-emitting element LED may be prevented from coming off.

[0167] In addition, in the display device 700 according to another embodiment of the present specification, the process of removing the first upper planarization layer 118 and the organic insulating layer OL outside the opening 118a is not performed, thereby improving the efficiency of the organic layer removal process.

[0168] In addition, in the display device 700 according to another embodiment of the present disclosure, the first upper planarization layer 118 and the organic insulating layer OL insulate the pixel circuit from other components without the need for an additional passivation layer, thereby preventing the risk of short circuit.

[0169] In addition, in the display device 700 according to another embodiment of the present specification, the contact area between the side surface of the light emitting element LED and the contact electrode CE may be larger than the contact area between the side surface of the light emitting element LED and the first portion OL1, thereby increasing the contact area between the light emitting element LED and the contact electrode CE and improving the contact resistance.

[0170] Fig. 8 is an enlarged plan view of a display device according to another embodiment of the present specification. The display device 800 of Fig. 8 is substantially the same as the display device 100 of Figs. 1 to 5f except that only the contact electrode CE, the organic insulating layer OL, and the second upper planarization layer are different, and therefore, a duplicated description will be omitted.

[0171] An organic insulating layer OL is disposed on the first upper planarization layer 118. The organic insulating layer OL includes a first portion OL1, a second portion OL2, and a third portion.

[0172] The first portion OL1 may contact a portion of the side of the light-emitting element LED at the opening 118a. The area of ​​the region where the first portion OL1 overlaps with the first assembly wiring 121 may be different from the area of ​​the region where the first portion OL1 overlaps with the second assembly wiring 122. The first portion OL1 may completely overlap one of the first assembly wiring 121 and the second assembly wiring 122, and partially overlap the other one. For example, as shown in FIG. 8, the first portion OL1 may completely overlap the first assembly wiring 121 and partially overlap the second assembly wiring 122 of the first assembly wiring 121 and the second assembly wiring 122. Thus, the first portion OL1 may overlap more than half of the side of the light-emitting element LED.

[0173] The second portion OL2 is disposed on the plurality of light-emitting elements LED within the opening 118a. The area of ​​the region where the second portion OL2 overlaps with the first assembly wiring 121 may be different from the area of ​​the region where the second portion OL2 overlaps with the second assembly wiring 122. For example, as shown in Fig. 8, the second portion OL2 may completely overlap with the first assembly wiring 121 and partially overlap with the second assembly wiring 122 out of the first assembly wiring 121 and the second assembly wiring 122. Thus, the second portion OL2 may overlap with more than half of the upper surface of the light-emitting element LED.

[0174] Although not shown in FIG. 8, the third portion may be disposed in the space between the third passivation layer 117 and the light-emitting element LED, and may be in contact with the bottom surface of the light-emitting element LED.

[0175] A contact electrode CE is disposed inside the opening 118a.

[0176] The contact electrode CE is disposed in a region excluding the region in which the first portion OL1 of the organic insulating layer OL is disposed. Therefore, the area in which the side surface of the light-emitting element LED and the contact electrode CE contact each other may be narrower than the area in which the side surface of the light-emitting element LED and the first portion OL1 contact each other.

[0177] Although not shown in FIG. 8, a second upper planarizing layer is disposed on the organic insulating layer OL and in the organic insulating layer openings OLa where no organic insulating layer is formed.

[0178] The second upper planarization layer can fill the opening 118a at the organic insulating layer opening OLa in the opening 118a. Then, the second upper planarization layer can be disposed on the contact electrode CE inside the opening 118a.

[0179] The second upper planarization layer may contact parts of the side surfaces of the plurality of light-emitting element LEDs and parts of the top surfaces of the light-emitting element LEDs at the openings 118a.

[0180] The second upper planarization layer includes a contact hole exposing a portion of an upper surface of the light emitting element LED. A pixel electrode PE is disposed in the contact hole of the second upper planarization layer 119 and may be electrically connected to the second electrodes 135 and 145 of the light emitting element LED.

[0181] In the display device 800 according to another embodiment of the present specification, after the light emitting element LED is self-assembled inside the opening 118a on the substrate 110, the organic insulating layer OL for fixing the light emitting element LED may be formed to contact at least the upper surface and the side surface of the light emitting element LED. As a result, the fixing force between the light emitting element LED and the substrate 110 may be improved, and the light emitting element LED may be prevented from coming off.

[0182] In addition, in the display device 800 according to another embodiment of the present specification, the process of removing the first upper planarization layer 118 and the organic insulating layer OL outside the opening 118a is not performed, thereby improving the efficiency of the organic layer removal process.

[0183] In addition, in the display device 800 according to another embodiment of the present disclosure, the first upper planarization layer 118 and the organic insulating layer OL insulate the pixel circuit from other components without the need for an additional passivation layer, thereby preventing the risk of short circuit.

[0184] In addition, in the display device 800 according to another embodiment of the present specification, the organic insulating layer OL may cover more than half of the area of ​​the top surface of the light emitting element LED and more than half of the side surface of the light emitting element LED, thereby improving the fixing force between the light emitting element LED and the substrate 110 and preventing the light emitting element LED from coming off.

[0185] Fig. 9a is an enlarged plan view of a display device according to another embodiment of the present specification. Fig. 9b is a cross-sectional view taken along the line E-E' of Fig. 9a. The display device 900 of Figs. 9a and 9b is substantially the same as the display device 100 of Figs. 1 to 5f except for the second portion OL2 of the organic insulating layer OL, the second upper planarization layer 919, and the pixel electrode PE, and therefore will not be described again.

[0186] An organic insulating layer OL is disposed on the first upper planarization layer 118. The organic insulating layer OL may cover a portion of the side surfaces of the plurality of light-emitting elements LED. The organic insulating layer OL includes a first portion OL1 and a third portion OL3.

[0187] The first portion OL1 is disposed so as to be in contact with the side surfaces of the multiple light-emitting elements LED, and covers a part of the side surfaces of the light-emitting elements LED.

[0188] The third portion OL3 is disposed in the space between the third passivation layer 117 and the light-emitting element LED, and can be in contact with the lower surface of the light-emitting element LED.

[0189] Meanwhile, the organic insulating layer OL may not be disposed on the upper surfaces of the light-emitting elements LED, and thus the organic insulating layer OL may expose the second electrodes 135 and 145 disposed on the upper surfaces of the light-emitting elements LED, as shown in FIG.

[0190] The contact electrode CE is disposed in an area other than the area where the first portion OL1 of the organic insulating layer OL is disposed, and can electrically connect the first electrodes 134 and 144 of the light emitting device LED to the first assembly wiring 121 and the second assembly wiring 122.

[0191] Referring to FIG. 9b, a second upper planarization layer 919 is disposed in the organic insulating layer OL and in the organic insulating layer openings OLa where no organic insulating layer is formed.

[0192] The second upper planarization layer 919 can fill the opening 118a in the region other than the region where the organic insulating layer OL is disposed in the opening 118a. Thus, the second upper planarization layer 919 can be disposed on the contact electrode CE inside the opening 118a.

[0193] The second upper planarization layer 919 includes a contact hole exposing an upper surface of the light emitting element LED. A pixel electrode PE is disposed in the contact hole of the second upper planarization layer 919 and may be electrically connected to the second electrodes 135 and 145 of the light emitting element LED.

[0194] A pixel electrode PE for electrically connecting the plurality of light emitting devices LEDs to the connecting electrode 150 is disposed on the second upper planarization layer 919 .

[0195] In the display device 900 according to another embodiment of the present specification, after the light emitting element LED is self-assembled inside the opening 118a on the substrate 110, the organic insulating layer OL for fixing the light emitting element LED may be formed to contact the side of the light emitting element LED. As a result, the fixing force between the light emitting element LED and the substrate 110 may be improved, and the light emitting element LED may be prevented from coming off.

[0196] In addition, in the display device 900 according to another embodiment of the present specification, the process of removing the first upper planarization layer 118 and the organic insulating layer OL outside the opening 118a is not performed, thereby improving the efficiency of the organic layer removal process.

[0197] In addition, in the display device 900 according to another embodiment of the present disclosure, the first upper planarization layer 118 and the organic insulating layer OL insulate the pixel circuit from other components without the need for an additional passivation layer, thereby preventing the risk of short circuit.

[0198] In addition, in the display device 900 according to another embodiment of the present specification, the organic insulating layer OL is disposed in an area other than the upper surface of the light-emitting element LED. Therefore, the front surfaces of the second electrodes 135 and 145 disposed on the upper surface of the light-emitting element LED can contact the pixel electrode PE. Therefore, the contact resistance between the light-emitting element LED and the pixel electrode PE can be improved.

[0199] The embodiments disclosed in the present specification are for illustrative purposes only and are not intended to limit the technical ideas of the present specification, and the larger the area of ​​the organic insulating layer OL that is left, the stronger the fixing force of the light emitting element LED, and the larger the area of ​​the organic insulating layer OL that is opened, the more stable the contact with the pixel electrode PE. Various formations are possible to ensure appropriate fixing force and contact area depending on the size and design of the light emitting element LED.

[0200] A display device according to various embodiments of the present disclosure can be described as follows.

[0201] A display device according to one embodiment of the present specification includes a substrate including a plurality of subpixels, first and second assembly wirings arranged in the plurality of subpixels on the substrate and spaced apart from each other, a first upper planarization layer arranged on the first and second assembly wirings and having an opening overlapping the first and second assembly wirings, a light-emitting element arranged in the opening and including a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode, a contact electrode electrically connecting the first and second assembly wirings to the first electrode, and an organic insulating layer arranged on the first upper planarization layer and covering a portion of a side surface and a portion of a top surface of the light-emitting element.

[0202] According to another feature of the present specification, the organic insulating layer can include a first portion in contact with the side surface of the light emitting element, except for a portion in contact with the contact electrode.

[0203] According to still another feature of the present specification, the light emitting device may further include a second upper planarization layer disposed on the light emitting element and the organic insulating layer, the second upper planarization layer being disposed to fill the opening.

[0204] According to still another feature herein, the second upper planarization layer can be disposed to fill the opening except for an area in the opening where the organic insulating layer is disposed.

[0205] According to another feature of the present specification, the light-emitting element includes a first light-emitting element and a second light-emitting element arranged in each of a plurality of sub-pixels, and a first portion contacting the first light-emitting element may overlap one of the first assembly wiring and the second assembly wiring, and a first portion contacting the second light-emitting element may overlap the other one of the first assembly wiring and the second assembly wiring.

[0206] According to still another feature of the present specification, the light-emitting element includes a first light-emitting element and a second light-emitting element arranged in each of a plurality of sub-pixels, and a first portion in contact with the first light-emitting element and a first portion in contact with the second light-emitting element may overlap with both the first assembly wiring and the second assembly wiring, respectively.

[0207] According to still another feature of the present specification, the second upper planarizing layer disposed in the opening may have a rectangular planar shape.

[0208] According to still another feature of the present disclosure, an area of ​​a region where the first portion overlaps with the first assembly wiring and an area of ​​a region where the first portion overlaps with the second assembly wiring may be equal to each other.

[0209] According to still another feature of the present disclosure, an area of ​​a region where the first portion overlaps with the first assembly wiring and an area of ​​a region where the first portion overlaps with the second assembly wiring may be different.

[0210] According to still another feature of the present disclosure, the first portion may completely overlap one of the first assembly wiring and the second assembly wiring, and may partially overlap the other one.

[0211] According to another aspect of the present disclosure, an area where a side surface of the light emitting element contacts the contact electrode may be larger than an area where a side surface of the light emitting element contacts the first portion.

[0212] According to another feature of the present specification, an area where a side surface of the light emitting element contacts the contact electrode may be smaller than an area where a side surface of the light emitting element contacts the first portion.

[0213] According to still another feature of the present specification, the organic insulating layer may further include a second portion covering a portion of an upper surface of the light emitting element.

[0214] According to still another feature of the present specification, the light-emitting element may further include a transistor disposed on the substrate and a pixel electrode electrically connecting the transistor and the second electrode, and the pixel electrode may contact the second electrode in an area of ​​the upper surface of the light-emitting element except for an area in which the second portion is disposed.

[0215] According to still other features herein, the side of the second portion may be disposed along a portion of the circumference of the second electrode.

[0216] According to still another feature of the present specification, the organic insulating layer may further include a third portion disposed under the light emitting element.

[0217] Although the embodiments of the present specification have been described in detail above with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments, and may be modified in various ways within the scope of the technical ideas of the present specification. Therefore, the embodiments disclosed in the present specification are for illustration purposes, not for limiting the technical ideas of the present specification, and the scope of the technical ideas of the present specification is not limited by such embodiments. Therefore, the embodiments described above should be understood to be illustrative and not restrictive in all respects. The scope of protection of the present specification should be interpreted based on all the technical ideas discussed, and all technical ideas within the equivalent range should be interpreted as being included in the scope of the present specification.

Claims

1. A substrate including a plurality of sub-pixels; a first assembly wiring and a second assembly wiring disposed on the substrate in a plurality of sub-pixels and spaced apart from each other; a first upper planarization layer disposed over the first assembly wiring and the second assembly wiring; an opening disposed in the first upper planarization layer and overlapping the first assembly wiring and the second assembly wiring; a light emitting element disposed in the opening, the light emitting element including a first electrode and a second electrode disposed on the first electrode, the light emitting element having a top surface and a side surface; a contact electrode electrically connecting the first assembly wiring, the second assembly wiring, and the first electrode; and The display device further comprises an organic insulating layer disposed in a portion of the opening and covering a portion of the side surface of the light-emitting element.

2. a portion of a side surface of the light-emitting element contacts a first portion of the organic insulating layer; The display device according to claim 1 , wherein another part of the side surface of the light-emitting element is in contact with the contact electrode.

3. a second upper planarization layer disposed on the light emitting device and the organic insulating layer; The display device according to claim 2 , wherein the second upper planarization layer is disposed in a portion of the opening.

4. the opening includes an organic insulating layer opening, The display device according to claim 3 , wherein the second upper planarization layer is disposed in the organic insulating layer opening.

5. The light emitting element includes a first light emitting element and a second light emitting element arranged in each of a plurality of sub-pixels, the first portion contacting the first light emitting device overlaps one of the first assembly wiring and the second assembly wiring; The display device of claim 3 , wherein the first portion in contact with the second light emitting element overlaps another one of the first assembly wiring and the second assembly wiring.

6. The light emitting element includes a first light emitting element and a second light emitting element arranged in each of a plurality of sub-pixels, The display device according to claim 3 , wherein the first portion in contact with the first light emitting element and the first portion in contact with the second light emitting element overlap both the first assembly wiring and the second assembly wiring.

7. The display device according to claim 4 , wherein the second upper planarizing layer disposed in the organic insulating layer opening has a rectangular planar shape.

8. The display device according to claim 6 , wherein an area of ​​a region where the first portion overlaps with the first assembly wiring is equal to an area of ​​a region where the first portion overlaps with the second assembly wiring.

9. The display device according to claim 6 , wherein an area of ​​a region where the first portion overlaps with the first assembly wiring is different from an area of ​​a region where the first portion overlaps with the second assembly wiring.

10. The display device of claim 6 , wherein the first portion completely overlaps one of the first assembly wiring and the second assembly wiring and partially overlaps the other one of the first assembly wiring and the second assembly wiring.

11. 3. The display device according to claim 2, wherein an area where the side of the light-emitting element and the contact electrode are in contact with each other is the same as an area where the side of the light-emitting element and the first portion are in contact with each other, or is larger than an area where the side of the light-emitting element and the first portion are in contact with each other.

12. The display device according to claim 2 , wherein an area where the side surface of the light emitting element and the contact electrode are in contact with each other is smaller than an area where the side surface of the light emitting element and the first portion are in contact with each other.

13. The display device according to claim 1 , wherein the organic insulating layer further includes a second portion covering a part of an upper surface of the light emitting element.

14. a transistor disposed on the substrate; and a pixel electrode electrically connecting the transistor and the second electrode, The display device according to claim 13 , wherein the pixel electrode is in contact with the second electrode in an area on the upper surface of the light emitting element excluding an area in which the second portion is disposed.

15. The display device according to claim 13 , wherein the side surface of the second portion is disposed along a portion of the periphery of the second electrode.

16. The display device of claim 1 , wherein the organic insulating layer further comprises a third portion disposed under the light emitting element.

17. the first assembly wiring includes a first conductive layer and a first clad layer covering an upper surface and a side surface of the first conductive layer; the second assembly wiring includes a second conductive layer and a second clad layer covering an upper surface and a side surface of the second conductive layer; the first conductive layer and the second conductive layer do not overlap with the light emitting element, The display device according to claim 1 , wherein the first cladding layer and the second cladding layer overlap the light emitting element.

18. a second upper planarization layer disposed on the light emitting device and the organic insulating layer; The display device according to claim 1 , wherein the second upper planarization layer is disposed on the contact electrode within the opening.

19. The display device according to claim 2 , wherein the first portion extends outside the opening and is disposed on the first upper planarization layer.

20. A display device, comprising: substrate; a plurality of assembly wirings disposed on the substrate at a distance from one another; a first upper planarization layer disposed over the plurality of fabrication interconnects; an opening disposed in the first upper planarization layer; An organic insulating layer; a light emitting element disposed in the opening, the light emitting element including a side surface; and A contact electrode disposed in the opening Equipped with the contact electrode is disposed so as to be in contact with the plurality of assembly wirings and the light emitting element; The organic insulating layer overlaps the plurality of assembly wirings in the opening and contacts a side surface of the light-emitting element.

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