Display panel and manufacturing method of them

Abstract

To provide a display panel that forms a light-emitting device without using a metal mask, in which a display quality is improved, and provide a manufacturing method of them.SOLUTION: A display panel includes: a base layer; a pixel definition film that is arranged onto the base layer, and includes a light emission open part; and a partition wall that is arranged onto the pixel definition film, and includes a partition wall open part that is overlapped with the light emission open part; a plurality of light-emitting devices that includes an anode, a lighting pattern, and a cathode that is contacted to the partition wall, and is arranged into the light emission open part and the partition wall open part; a plurality of lower part sealing inorganic patters covering each of the plurality of light-emitting devices; and a common inorganic film that covers the plurality of lower part sealing inorganic patters, and fills between the partition wall and the plurality of lower part sealing inorganic patters.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a display panel and a method for manufacturing a display panel, and more particularly to a display panel with improved display quality.

Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include a display panel for displaying images. Various display panels such as a liquid crystal display panel, an organic light emitting display panel, an electro Wetting display panel, and an electrophoretic display panel have been developed.

[0003] An organic light emitting display panel can include an anode, a cathode, and a light emitting pattern. The light emitting pattern is separated for each light emitting region, and the cathode can provide a common voltage for each light emitting region.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display panel with improved display quality and a method for manufacturing the same in a display panel for forming a light emitting element without using a metal mask.

Means for Solving the Problems

[0006] A display panel according to an embodiment of the present invention includes a base layer, a pixel definition film disposed on the base layer and having a light-emitting opening, a partition disposed on the pixel definition film and having a partition opening overlapping with the light-emitting opening, an anode, a light-emitting pattern, and a cathode in contact with the partition, respectively, a plurality of light-emitting elements disposed in the light-emitting opening and the partition opening, a plurality of lower sealing inorganic patterns covering each of the plurality of light-emitting elements, and a common inorganic film covering the plurality of lower sealing inorganic patterns and filling a space between the partition and the plurality of lower sealing inorganic patterns.

[0007] The plurality of light-emitting elements each include a first light-emitting element, a second light-emitting element, and a third light-emitting element that emit different colors, and the plurality of lower sealing inorganic patterns can include a first lower sealing inorganic pattern covering the first light-emitting element, a second lower sealing inorganic pattern covering the second light-emitting element, and a third lower sealing inorganic pattern covering the third light-emitting element.

[0008] The common inorganic film can cover the dried first to third lower sealing inorganic patterns.

[0009] The display panel can further include a first additional sealing inorganic pattern covering the dried first lower sealing inorganic pattern, a second additional sealing inorganic pattern covering the dried second lower sealing inorganic pattern, and a third additional sealing inorganic pattern covering the dried third lower sealing inorganic pattern.

[0010] The common inorganic film can cover the first to third additional sealing inorganic patterns.

[0011] An internal region is defined in the common inorganic film, and the internal region can be empty.

[0012] The internal region can have a shape surrounding the light-emitting opening on a plane.

[0013] A part of the inner region can overlap with the plurality of lower sealing inorganic patterns on a plane.

[0014] Each of the plurality of lower sealing inorganic patterns can include an upper surface, a first side surface extending from the upper surface in the thickness direction of the base layer, a lower surface extending from the first side surface toward the center of the anode, and a second side surface extending from the lower surface in the thickness direction of the base layer.

[0015] The common inorganic film can cover the upper surface, the first side surface, the lower surface, and the second side surface of each of the plurality of dried lower sealing inorganic patterns.

[0016] The common inorganic film can contain an inorganic substance.

[0017] The common inorganic film can contain at least one of silicon nitride (SiNx) and silicon oxynitride (SiON).

[0018] The display panel can further include a sealing organic film covering the common inorganic film and an upper sealing inorganic film covering the sealing organic film.

[0019] A method for manufacturing a display panel according to an embodiment of the present invention can include providing a preliminary display panel including a base layer, a pixel definition film disposed on the base layer, and a preliminary partition wall disposed on the pixel definition film; forming a partition wall having a partition wall opening from the preliminary partition wall; etching the pixel definition film to form a light-emitting opening overlapping the partition wall opening; forming a light-emitting element and a lower sealing inorganic pattern covering the light-emitting element in the light-emitting opening and the partition wall opening; and drying the surfaces of the partition wall and the lower sealing inorganic pattern.

[0020] The step of forming the light-emitting element and the lower-sealing inorganic pattern covering the light-emitting element in the light-emitting opening and the partition opening may include a step of forming a first light-emitting element and a first lower-sealing inorganic pattern covering the first light-emitting element, a step of forming a second light-emitting element and a second lower-sealing inorganic pattern covering the second light-emitting element, and a step of forming a third light-emitting element and a third lower-sealing inorganic pattern covering the third light-emitting element.

[0021] The display panel manufacturing method may further include a step of forming a common inorganic film covering the first to third lower-sealing inorganic patterns.

[0022] The display panel manufacturing method may further include a step of forming an additional sealing inorganic pattern covering the lower-sealing inorganic pattern.

[0023] The step of forming the additional sealing inorganic pattern covering the lower-sealing inorganic pattern may include, after the step of forming the first light-emitting element and the first lower-sealing inorganic pattern, a step of drying the surfaces of the partition and the first lower-sealing inorganic pattern, a step of forming a first additional sealing inorganic pattern covering the first lower-sealing inorganic pattern, after the step of forming the second light-emitting element and the second lower-sealing inorganic pattern, a step of drying the surfaces of the partition and the second lower-sealing inorganic pattern, a step of forming a second additional sealing inorganic pattern covering the second lower-sealing inorganic pattern, after the step of forming the third light-emitting element and the third lower-sealing inorganic pattern, a step of drying the surfaces of the partition and the third lower-sealing inorganic pattern, and a step of forming a third additional sealing inorganic pattern covering the third lower-sealing inorganic pattern.

[0024] The display panel manufacturing method may further include a step of forming a common inorganic film covering the first to third additional sealing inorganic patterns.

[0025] A display panel according to an embodiment of the present invention includes a base layer, a pixel definition film disposed on the base layer and having a light-emitting opening, a partition disposed on the pixel definition film and having a partition opening overlapping the light-emitting opening, an anode, a light-emitting pattern, and a cathode in contact with the partition, respectively, a plurality of light-emitting elements disposed in the light-emitting opening and the partition opening, and a plurality of lower sealing inorganic patterns covering each of the plurality of light-emitting elements, and only an inorganic substance can be disposed between the lower sealing inorganic pattern and the upper surface of the partition.

Advantages of the Invention

[0026] According to the above-described configuration, in a display panel that forms light-emitting elements without using a metal mask, it is possible to provide a display panel or the like with improved display quality.

Brief Description of the Drawings

[0027]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7A

Figure 7B

Figure 7C

Figure 7D

Figure 7E

Figure 7F

Figure 7G

Figure 7H

Figure 7I

Figure 8A

Figure 8B

Figure 8C

Figure 8D

Figure 8E

Figure 9

Embodiments for Carrying Out the Invention

[0028] In this specification, when a predetermined component (or region, layer, part, etc.) is described as being "on", "connected to", or "coupled to" another component, it means that it can be directly disposed / connected / coupled on the other component, or a third component can also be disposed between them.

[0029] Identical reference numerals denote identical components. Also, in the drawings, the thickness, ratio, and dimensions of the components are exaggerated for the efficient explanation of the technical content. "And / or" includes all one or more combinations that the associated components can define.

[0030] Terms such as first, second, etc. can be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component can be referred to as the second component, and similarly, the second component can also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0031] Also, terms such as "below", "beneath", "above", "over", etc. are used to explain the association relationship of the components illustrated in the drawings. The terms are relative concepts and are explained based on the directions shown in the drawings.

[0032] Terms such as "comprising" or "having" are intended to specify that there are features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and it should be understood that the presence or addition possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof is not precluded in advance.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Also, terms such as those defined in commonly used dictionaries shall be interpreted to have a meaning consistent with the meaning in the context of the relevant art, and here, unless explicitly defined otherwise, shall not be interpreted in an overly idealized or overly formal sense.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0035] FIG. 1A is a perspective view of a display device DD according to an embodiment of the present invention, and FIG. 1B is an exploded perspective view of the display device DD according to an embodiment of the present invention.

[0036] In one embodiment, the display device DD can be a large electronic device such as a television, a monitor, or an external billboard. Also, the display device DD can be a medium or small electronic device such as a personal computer, a notebook computer, a personal digital terminal, an automotive navigation unit, a game machine, a smartphone, a tablet, and a camera. However, this is exemplary, and can be adopted for other display devices as long as it does not deviate from the concept of the present invention. In FIGS. 1A and 1B, the display device DD is illustrated as a smartphone by way of example.

[0037] Referring to FIGS. 1A and 1B, the display device DD can display an image IM in a third direction DR3 on a display surface FS that is parallel to each of a first direction DR1 and a second direction DR2. The image IM can include not only a dynamic image but also a still image. In FIG. 1A, a clock window and an icon are illustrated as an example of the image IM. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device DD.

[0038] In the present embodiment, the front surface (or the upper surface) and the back surface (or the lower surface) of each member are defined based on the direction in which the image IM is displayed. The front surface and the back surface face each other in the third direction DR3, and the normal direction of each of the front surface and the back surface can be parallel to the third direction DR3. On the other hand, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and can be converted to other directions. In this specification, "on a plane" can mean when viewed in the third direction DR3.

[0039] The display device DD can include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU can be coupled to each other to form the appearance of the display device DD.

[0040] The window WP can include an optically transparent insulating material. For example, the window WP can include glass or plastic. The front surface of the window WP can define the display surface FS of the display device DD. The display surface FS can include a transmissive region TA and a bezel region BZA. The transmissive region TA can be an optically transparent region. For example, the transmissive region TA can be a region having a visible light transmittance of about 90% or more.

[0041] The bezel region BZA can be a region having a relatively low light transmittance compared to the transmissive region TA. The bezel region BZA can define the shape of the transmissive region TA. The bezel region BZA is adjacent to the transmissive region TA and can surround the transmissive region TA. However, this is shown by way of example, and the bezel region BZA of the window WP can be omitted. The window WP can include at least one of a fingerprint prevention layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0042] The display module DM can be disposed below the window WP. The display module DM can be configured to substantially generate the image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is visually recognized by the user outside through the transmissive region TA.

[0043] The display module DM can include a display area DA and a non-display area NDA. The display area DA can be an area activated in response to an electrical signal. The non-display area NDA can be adjacent to the display area DA. The non-display area NDA can surround the display area DA. The non-display area NDA is formed in an area covered by the bezel area BZA and may not be visible from the outside.

[0044] The housing HAU can be coupled to the window WP. The housing HAU can be coupled to the window WP to provide a predetermined internal space. The display module DM can be housed in the internal space.

[0045] The housing HAU can include a relatively strong material. For example, the housing HAU can include glass, plastic, or metal, or can include a plurality of frames and / or plates composed of a combination thereof. The housing HAU can stably protect the configuration of the display device DD housed in the internal space from external impacts.

[0046] FIG. 2 is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0047] Referring to FIG. 2, the display module DM can include a display panel DP and an input sensor INS. Alternatively, a display device DD (see FIG. 1A) according to an embodiment of the present invention can further include a protective member disposed on the lower surface of the display panel DP or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0048] The display panel DP can be a light-emitting display panel. However, this is exemplary and not particularly limited thereto. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel can include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel can include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0049] The display panel DP can include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS can be directly disposed on the thin film encapsulation layer TFE. As used herein, "A configuration is directly disposed on B configuration" means that no adhesive layer is disposed between the A configuration and the B configuration.

[0050] The base layer BL can include at least one plastic film. The base layer BL is a flexible substrate and can include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc. The display area DA and the non-display area NDA described in FIG. 1B can be similarly defined in the base layer BL.

[0051] The circuit element layer DP-CL can include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, driving circuits of pixels, etc.

[0052] The display element layer DP-OLED can include partitions and light-emitting elements. The light-emitting elements can include an anode, an intermediate layer, and a cathode.

[0053] The thin film encapsulation layer TFE can include a plurality of thin films. Some of the thin films can be disposed to improve optical efficiency, and some of the thin films can be disposed to protect the organic light-emitting diodes.

[0054] The input sensor INS acquires coordinate information of an external input. The input sensor INS can have a multilayer structure. The input sensor INS can include a single-layer or multilayer conductive layer. Also, the input sensor INS can include a single-layer or multilayer insulating layer. The input sensor INS can sense an external input by a capacitance method. However, this is exemplary and not limited thereto. For example, in one embodiment, the input sensor INS may sense an external input by an electromagnetic induction method or a pressure sensing method. On the other hand, in another embodiment of the present invention, the input sensor INS can be omitted.

[0055] FIG. 3 is a plan view of a display panel according to an embodiment of the present invention.

[0056] Referring to FIG. 3, a display area DA and a non-display area NDA around the display area DA can be defined in the display panel DP. The display panel DP can include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP can include a driving circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA can be distinguished by the presence or absence of the arrangement of the pixels PX. Pixels PX can be arranged in the display area DA. The driving circuit GDC and the pad portion PLD can be arranged in the non-display area NDA.

[0057] The pixels PX can be arranged along a first direction DR1 and a second direction DR2. The pixels PX can include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0058] The signal line SGL can include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the gate lines GL can be connected to a corresponding pixel among the pixels PX, and each of the data lines DL can be connected to a corresponding pixel among the pixels PX. The power line PL can be electrically connected to the pixel PX. The control signal line CSL can be connected to the driving circuit GDC to provide a control signal to the driving circuit GDC.

[0059] The driving circuit GDC can include a gate driving circuit. The gate driving circuit can generate a gate signal and sequentially output the generated gate signal to the gate line GL. The gate driving circuit can further output other control signals to the pixel driving circuit.

[0060] The pad portion PLD can be a portion to which a flexible circuit board is connected. The pad portion PLD can include pixel pads D-PD, and the pixel pads D-PD can be pads for connecting a flexible circuit board to the display panel DP. Each of the pixel pads D-PD can be connected to a corresponding signal line among the signal lines SGL. The pixel pads D-PD can be connected to corresponding pixels PX through the signal lines SGL. Also, any one of the pixel pads D-PD can be connected to the driving circuit GDC.

[0061] Also, the pad portion PLD can further include input pads. The input pads can be pads for connecting a flexible circuit board to an input sensor INS (see FIG. 2). However, it is not limited thereto, and the input pads can be arranged on the input sensor INS (see FIG. 2) and can be connected to another circuit board different from the pixel pads D-PD. Or, the input sensor INS (see FIG. 2) can be omitted and may not further include input pads.

[0062] FIG. 4 is an enlarged plan view of a part of a display area DA (see FIG. 2) of a display panel DP according to an embodiment of the present invention. FIG. 4 shows a plan view of the display module DM as seen on the display surface IS (see FIG. 1B) of the display module DM, and shows the arrangement of the light emitting regions PXA-R, PXA-G, and PXA-B.

[0063] Referring to FIG. 4, the display area DA can include first to third light emitting regions PXA-R, PXA-G, PXA-B and a peripheral region NPXA surrounding the first to third light emitting regions PXA-R, PXA-G, PXA-B. The first to third light emitting regions PXA-R, PXA-G, PXA-B can respectively correspond to regions where light provided from light emitting elements is emitted. The first to third light emitting regions PXA-R, PXA-G, PXA-B can be classified according to the color of light emitted toward the outside of the display module DM (see FIG. 2).

[0064] The first to third light emitting regions PXA-R, PXA-G, PXA-B can each provide first to third color lights having different colors from each other. For example, the first color light can be red light, the second color light can be green light, and the third color light can be blue light. However, the exemplification of the first to third color lights is not necessarily limited to the above example.

[0065] Each of the first to third light emitting regions PXA-R, PXA-G, PXA-B can be defined as a region where the upper surface of the anode is exposed by a light emitting opening described later. That is, in a plan view, when the anode is correspondingly positioned within the light emitting opening, the upper surface of the anode is also correspondingly positioned. In the following, there is a via that uses "exposed" in the meaning of "correspondingly positioned". The peripheral region NPXA sets the boundaries of the first to third light emitting regions PXA-R, PXA-G, PXA-B and can prevent color mixing between the first to third light emitting regions PXA-R, PXA-G, PXA-B.

[0066] A plurality of first to third light-emitting regions PXA-R, PXA-G, and PXA-B are provided, each having a predetermined array shape within the display region DA and capable of being repeatedly arranged. For example, the first and third light-emitting regions PXA-R and PXA-B can be alternately arranged along the first direction DR1 to form a 'first group'. The second light-emitting region PXA-G can be arranged along the first direction DR1 to form a'second group'. Each of a 'plurality of first groups' and a plurality of'second groups' is provided, and the plurality of 'first groups' and the plurality of'second groups' can be alternately arranged with respect to each other along the second direction DR2.

[0067] One second light-emitting region PXA-G can be arranged at a distance from one first light-emitting region PXA-R or one third light-emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 can be defined as a direction between the first and second directions DR1 and DR2. In the case of FIG. 4, the fourth direction DR4 is approximately 45° with respect to the first direction DR1 and approximately 45° with respect to the second direction DR2 between the first and second directions DR1 and DR2.

[0068] On the other hand, FIG. 4 exemplarily shows the array shape of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B, but is not limited thereto, and can be arranged in various forms. In one embodiment, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can have a pentile (PENTILE TM ) array shape as shown in FIG. 4. Alternatively, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have a stripe array form or a diamond pixel TM ) array shape.

[0069] The first to third light-emitting regions PXA-R, PXA-G, and PXA-B can have various shapes on a plane. For example, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can have shapes such as polygons, circles, or ellipses. FIG. 4 exemplarily shows the first and third light-emitting regions PXA-R and PXA-B having a square shape (or a rhomboid shape) on a plane and the second light-emitting region PXA-G having an octagonal shape.

[0070] The first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have the same shape as each other on a plane, or at least some of them may have different shapes from each other. FIG. 4 exemplarily shows the first and third light-emitting regions PXA-R and PXA-B having the same shape as each other on a plane and the second light-emitting region PXA-G having a shape different from that of the first and third light-emitting regions PXA-R and PXA-B.

[0071] At least some of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can have different areas from each other on a plane. In one embodiment, the area of the first light-emitting region PXA-R that emits red light can be larger than the area of the second light-emitting region PXA-G that emits green light and smaller than the area of the third light-emitting region PXA-B that emits blue light. However, the magnitude relationship of the areas among the first to third light-emitting regions PXA-R, PXA-G, and PXA-B according to the emitted light color is not limited to this and can vary according to the design of the display module DM (see FIG. 2). Also, without being limited to this, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have the same area as each other on a plane.

[0072] On the other hand, the shapes, areas, arrangements, etc. of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B of the display module DM (see FIG. 2) of the present invention can be variously designed according to the color of the emitted light, the size, and the configuration of the display module DM (see FIG. 2), and are not limited to the embodiment illustrated in FIG. 4.

[0073] FIG. 5 is a cross-sectional view of the display panel cut along I-I' of FIG. 3. When explaining FIG. 5, reference will be made to FIG. 2 for explanation, and the description of the same reference numerals will be omitted. FIG. 5 shows an enlarged view of a single light-emitting region PXA within the display region DA (see FIG. 4), and the light-emitting region PXA in FIG. 5 can correspond to any one of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B in FIG. 4.

[0074] Referring to FIG. 5, the display panel DP can include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE.

[0075] The display panel DP can include a plurality of insulating layers and semiconductor patterns, conductive patterns, signal lines, etc. The insulating layer, semiconductor layer, and conductive layer are formed by methods such as coating and vapor deposition. Thereafter, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned by photolithography and etching. In such a manner, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED can be formed.

[0076] The circuit element layer DP-CL can be disposed on the base layer BL. The circuit element layer DP-CL can include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40, 50, an electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0077] The buffer layer BFL can be disposed on the base layer BL. The buffer layer BFL can improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL can include silicon and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be alternately laminated.

[0078] A semiconductor pattern can be disposed on the buffer layer BFL. The semiconductor pattern can include polysilicon. However, it is not limited thereto, and the semiconductor pattern may include amorphous silicon or a metal oxide. Only some of the semiconductor patterns are exemplarily shown in FIG. 5, and semiconductor patterns can be further disposed in a plurality of light-emitting regions PXA-R, PXA-G, PXA-B (see FIG. 4). The semiconductor patterns can be arranged according to a specific rule across the plurality of light-emitting regions PXA-R, PXA-G, PXA-B. The electrical properties of the semiconductor patterns can be different depending on whether they are doped or not. The semiconductor pattern can include a first region with a high doping concentration and a second region with a low doping concentration. The first region can be doped with an N-type dopant or a P-type dopant. The P-type transistor can include a first region doped with a P-type dopant.

[0079] The first region has higher conductivity than the second region and substantially serves as an electrode or a signal line. The second region can substantially correspond to the active (or channel) of the transistor. In other words, a part of the semiconductor pattern is the active of the transistor, another part is the source or drain of the transistor, and still another part can be a conductive region.

[0080] The source S, active A, and drain D of the transistor TR1 can be formed from the semiconductor pattern. FIG. 5 shows a part of the signal transmission region SCL formed from the semiconductor pattern. Separately, the signal transmission region SCL can be connected to the drain D of the transistor TR1 on a plane.

[0081] The first to fifth insulating layers 10, 20, 30, 40, 50 can be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, 50 can be inorganic layers or organic layers.

[0082] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can cover the source S, the active region A, the drain D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 can be disposed on the first insulating layer 10. The second insulating layer 20 can be disposed on the first insulating layer 10 to cover the gate G. The electrode EE can be disposed on the second insulating layer 20. The third insulating layer 30 can be disposed on the second insulating layer 20 to cover the electrode EE.

[0083] The first connection electrode CNE1 can be disposed on the third insulating layer 30. The first connection electrode CNE1 can be connected to the signal transmission region SCL through the contact hole CNT-1 that penetrates the first to third insulating layers 10, 20, 30. The fourth insulating layer 40 can be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 can be an organic layer.

[0084] The second connection electrode CNE2 can be disposed on the fourth insulating layer 40. The second connection electrode CNE2 can be connected to the first connection electrode CNE1 through the contact hole CNT-2 that penetrates the fourth insulating layer 40. The fifth insulating layer 50 can be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 can be an organic layer.

[0085] The display element layer DP-OLED can be disposed on the circuit element layer DP-CL. The display element layer DP-OLED can include a light-emitting element ED, a sacrificial pattern SP, a pixel definition film PDL, and a partition wall PW.

[0086] The light-emitting element ED can include an anode AE (or, the first electrode), a light-emitting pattern EP, and a cathode CE (or, the second electrode). The light-emitting element ED can be disposed within the light-emitting opening OP-E and the partition wall opening OP-P described later.

[0087] The anode AE can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE can be connected to the second connection electrode CNE2 by a connection contact hole CNT-3 defined through the fifth insulating layer 50. Thus, the anode AE can be electrically connected to the signal transmission region SCL through the first and second connection electrodes CNE1 and CNE2 and can be electrically connected to the corresponding circuit element. The anode AE can include a single layer or a multilayer structure. The anode AE can include a plurality of layers including ITO and Ag. For example, the anode AE can include a layer containing ITO (hereinafter, the lower ITO layer), a layer containing Ag disposed on the lower ITO layer (hereinafter, the Ag layer), and a layer containing ITO disposed on the Ag layer (hereinafter, the upper ITO layer).

[0088] The sacrificial pattern SP can be disposed between the anode AE and the pixel definition film PDL. A sacrificial opening OP-S for exposing a part of the upper surface of the anode AE can be defined by the sacrificial pattern SP (or the sacrificial pattern SP can have the sacrificial opening OP-S). The sacrificial opening OP-S can overlap with the light-emitting opening OP-E described later.

[0089] The pixel definition film PDL can be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light-emitting opening OP-E can be defined in the pixel definition film PDL (or the pixel definition film PDL can have the light-emitting opening OP-E). The light-emitting opening OP-E can correspond to the anode AE, and the pixel definition film PDL can expose at least a part of the anode AE through the light-emitting opening OP-E.

[0090] Also, the light-emitting opening OP-E can correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to the present embodiment, the upper surface of the anode AE can be separated from the pixel definition film PDL in cross section (in cross-sectional view) via the sacrificial pattern SP, and thus, damage to the anode AE can be protected in the process of forming the light-emitting opening OP-E.

[0091] On a plane, the area of the light-emitting opening OP-E can be smaller than the area of the sacrificial opening OP-S. That is, the inner surface of the pixel definition film PDL that defines the light-emitting opening OP-E can be further adjacent to the center of the anode AE than the inner surface of the sacrificial pattern SP that defines the sacrificial opening OP-S. However, it is not limited thereto, and the inner surface of the sacrificial pattern SP that defines the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel definition film PDL that defines the light-emitting opening OP-E. At this time, the light-emitting region PXA can be regarded as the region of the anode AE exposed from the corresponding sacrificial opening OP-S.

[0092] The pixel definition film PDL can include an inorganic insulating material. For example, it can include silicon nitride (SiNx) (or silicon nitride). The pixel definition film PDL is disposed between the anode AE and the partition wall PW, and can block the anode AE and the partition wall PW from being electrically connected to each other.

[0093] The light-emitting pattern EP can be disposed on the anode AE. The light-emitting pattern EP can include a light-emitting layer containing a light-emitting substance. The light-emitting pattern EP may further include a hole injection layer (Hole Injection Layer: HIL) and a hole transport layer (Hole Transport Layer: HTL) disposed between the anode AE and the light-emitting layer, and may further include an electron transport layer (Electron Transport Layer: ETL) and an electron injection layer (Electron Injection Layer: EIL) disposed on the light-emitting layer. The light-emitting pattern EP may be referred to as an 'organic layer' or an 'intermediate layer'.

[0094] The light-emitting pattern EP can be patterned by chip portions defined in the partition wall PW. Detailed content will be described later in the explanation of the display panel manufacturing method. The light-emitting pattern EP can be disposed inside the sacrificial opening OP-S and the light-emitting opening OP-E. However, this is shown by way of example, and the light-emitting pattern EP can be disposed inside at least one or more of the sacrificial opening OP-S, the light-emitting opening OP-E, and the partition wall opening OP-P. The light-emitting pattern EP can cover a part of the upper surface of the pixel definition film PDL. In the example of FIG. 5, the light-emitting pattern EP is continuously disposed on the anode AE inside the sacrificial opening OP-S, inside the light-emitting opening OP-E, and below the opening continuous with the partition wall opening OP-P in the pixel definition film PDL. The sacrificial opening OP-S, the light-emitting opening OP-E, and the lower part of the opening continuous with the partition wall opening OP-P in the pixel definition film PDL are continuous while having a step along the third direction DR3 in a cross-sectional view. Specifically, in the example of FIG. 5, the inner surface of the light-emitting opening OP-E is adjacent to the center of the anode AE in the first direction DR1 closer than the inner surface of the sacrificial opening OP-S, and the inner surface of the lower part of the opening continuous with the partition wall opening OP-P is located farther from the center of the anode AE in the first direction DR1 than the inner surfaces of the light-emitting opening OP-E and the sacrificial opening OP-S. The light-emitting pattern EP in FIG. 5 is formed in such an opening, so that the outer surface of the light-emitting pattern EP is formed with a step along the third direction DR3. In the example of FIG. 5, the inner surface of the lower part of the opening continuous with the partition wall opening OP-P is adjacent to the center of the anode AE in the first direction DR1 closer than the outer surface of the anode AE. Also, according to the example of FIG. 5, above the third direction DR3 of the lower part, the upper part of the opening continuous with the partition opening OP-P in the pixel definition film PDL is continuous, and further above the third direction DR3 of the upper part, the partition opening OP-P is continuous. The lower part, the upper part, and the partition opening OP-P are aligned to coincide along the third direction DR3. And, a light emission pattern EP is arranged in the lower part of the opening continuous with the partition opening OP-P, while a cathode CE is arranged in the upper part of the opening continuous with the partition opening OP-P in the pixel definition film PDL. Note that the light emission pattern EP may be continuously arranged on the anode AE within the sacrificial opening OP-S, within the light emission opening OP-E, in the upper and lower parts of the opening continuous with the partition opening OP-P in the pixel definition film PDL. In this case, the upper surface of the light emission pattern EP is located at approximately the same height as the upper surface of the pixel definition film PDL. The cathode CE is arranged within the partition opening OP-P on the light emission pattern EP. Also, the light emission pattern EP may be continuously arranged on the anode AE within the sacrificial opening OP-S, within the light emission opening OP-E, in the upper and lower parts of the opening continuous with the partition opening OP-P in the pixel definition film PDL, and further in a part within the partition opening OP-P. In this case, the upper surface of the light emission pattern EP is located within the partition opening OP-P. The cathode CE is arranged within the partition opening OP-P together with a part of the light emission pattern EP.

[0095] The cathode CE can be arranged on the light emission pattern EP. The cathode CE can be patterned by a chip portion defined by the partition PW. At least a part of the cathode CE can be arranged in the partition opening OP-P. In FIG. 5, an example is illustratively shown in which the cathode CE is arranged within the partition opening OP-P and within the upper part of the opening of the pixel definition film PDL continuous with the partition opening OP-P in the third direction DR3, but it is not limited thereto. For example, the cathode CE can be arranged only within the partition opening OP-P. According to the example of FIG. 5, the partition opening OP-P is an opening formed in the partition PW (the first partition layer L1 and the second partition layer L2). That is, the partition opening OP-P includes an opening formed in the first partition layer L1 (the opening defined by the first inner surface) and an opening formed in the second partition layer L2 (the opening defined by the second inner surface). In FIG. 5, the opening formed in the first partition layer L1 is formed so as to be aligned above in the third direction DR3 with respect to the upper portion of the opening continuous with the partition opening OP-P in the aforementioned pixel definition film PDL.

[0096] The cathode CE can be formed to extend along the first inner surface of the first partition layer L1, and the end of the cathode CE can contact the first partition layer L1. In FIG. 5, an example is illustratively shown where the cathode CE contacts the first inner surface of the first partition layer L1 and the inner surface of the pixel definition film PDL, but it is not limited thereto. For example, the cathode CE can be formed to contact only the first inner surface of the first partition layer L1.

[0097] The cathode CE can have conductivity. The cathode CE can be formed of various materials as long as it has conductivity, such as a metal, a transparent conductive oxide (TCO), or a conductive polymer material. For example, the cathode CE can contain silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or a compound thereof.

[0098] In one embodiment of the present invention, the display element layer DP-OLED can further include a capping pattern CP. The capping pattern CP can be disposed within the partition opening OP-P and can be disposed on the cathode CE. The capping pattern CP can be patterned by a chip portion defined in the partition PW. In one embodiment, the capping pattern CP can be omitted.

[0099] The partition wall PW can be disposed on the pixel definition layer PDL. A partition wall opening OP-P can be defined in the partition wall PW. The partition wall opening OP-P can overlap with the light-emitting opening OP-E and expose at least a part of the anode AE. That is, in a plan view, the anode is correspondingly positioned within the partition wall opening OP-P and the light-emitting opening OP-E.

[0100] The partition wall PW can include a number of sequentially stacked layers. For example, the partition wall PW can include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 is disposed on the pixel definition layer PDL, and the second partition wall layer L2 can be disposed on the first partition wall layer L1. As shown in FIG. 5, the thickness of the first partition wall layer L1 is greater than that of the second partition wall layer L2, but it is not limited thereto.

[0101] Each of the first partition wall layer L1 and the second partition wall layer L2 can include a conductive material. For example, the conductive material can include a metal, a transparent conductive oxide (Transparent Conductive Oxide, TCO), or a combination thereof. For example, the metal can include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide can include indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (Induim Gallium Zinc Oxide, IGZO), or aluminum zinc oxide (Aluminuin Zinc Oxide).

[0102] The partition wall PW can have an undercut shape in cross-section. At least one layer among the multiple layers of the partition wall PW can be recessed compared to other layers. Thus, the partition wall PW can include a chip portion. For example, the first partition wall layer L1 can have an undercut shape with respect to the second partition wall layer L2. The second partition wall layer L2 protrudes along a first direction toward the inside of the light-emitting opening OP-E compared to the first partition wall layer L1, and thereby a chip portion, which is a portion protruding more than the first partition wall layer L1, can be formed. A portion protruding from the first partition wall layer L1 toward the light-emitting region PXA can be defined as a chip portion within the partition wall PW. That is, the second inner surface of the second partition wall layer L2 can be closer to the center of the anode AE than the first inner surface of the first partition wall layer L1. More specifically, as described above, the partition wall PW is formed to have a partition wall opening OP-P. The partition wall opening OP-P includes an opening formed in the first partition wall layer L1 (the opening defined by the first inner surface) and an opening formed in the second partition wall layer L2 (the opening defined by the second inner surface). The end surface of the opening formed in the second partition wall layer L2 (the opening defined by the second inner surface) is closer to the center of the anode AE in the first direction DR1 than the end surface of the opening formed in the first partition wall layer L1 (the opening defined by the first inner surface). Thus, the second partition wall layer L2 protrudes toward the center of the anode AE more than the first partition wall layer L1 and forms a chip portion.

[0103] In FIG. 5, it is exemplarily illustrated that each of the first inner surface of the first partition wall layer L1 and the second inner surface of the second partition wall layer L2 is perpendicular to the upper surface of the pixel defining film PDL, but it is not limited thereto. For example, the partition wall PW may have a tapered shape or an inverse tapered shape. That is, the first inner surface and / or the second inner surface, which are the inner surfaces of the partition wall PW, may be such that the interval between the opposing inner surfaces becomes narrower as it goes downward along the third direction DR3, or may widen as it goes downward.

[0104] The partition wall PW can receive a driving voltage. Thus, the cathode CE can be electrically connected to the partition wall PW to receive the driving voltage.

[0105] The thin film encapsulation layer TFE can be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE can include a lower encapsulation inorganic pattern LIL, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0106] The lower encapsulation inorganic pattern LIL can be corresponded (or, overlapped) to the light emitting opening OP-E. The lower encapsulation inorganic pattern LIL can be disposed on the capping pattern CP to cover the light emitting element ED. A part of the lower encapsulation inorganic pattern LIL can be formed within the partition opening OP-P, and another part of the lower encapsulation inorganic pattern LIL can be formed on the partition PW.

[0107] The lower encapsulation inorganic pattern LIL can include an upper surface U_LIL, a first side surface S1_LIL, a bottom surface B_LIL, and a second side surface S2_LIL. The first side surface S1_LIL can be extended from the upper surface U_LIL in the thickness direction of the base layer BL (for example, the opposite direction of the third direction DR3, that is, downward). The bottom surface B_LIL can be extended from the first side surface S1_LIL toward the center of the anode AE. The second side surface S2_LIL can be extended from the bottom surface B_LIL in the thickness direction of the base layer BL (for example, the opposite direction of the third direction DR3, that is, downward). According to the example of FIG. 5, the lower sealing inorganic pattern LIL is arranged so as to overlap with the light-emitting opening OP-E in a top view. For example, the lower sealing inorganic pattern LIL includes a lower portion of the lower sealing inorganic pattern LIL and an upper portion of the lower sealing inorganic pattern LIL. The lower portion of the lower sealing inorganic pattern LIL is the portion arranged on the partition wall PW. The lower portion of the lower sealing inorganic pattern LIL is the portion of the lower sealing inorganic pattern LIL from the portion in contact with the cathode CE and the capping pattern CP to the portion in contact with the second partition wall layer L2. Further, the upper portion of the lower sealing inorganic pattern LIL is the portion covered with the common inorganic film CLIL on the second partition wall layer L2. The upper portion of the lower sealing inorganic pattern LIL is the portion of the lower sealing inorganic pattern LIL that extends upward along the third direction DR3 with respect to the lower portion of the lower sealing inorganic pattern LIL. This will be further described below. The lower portion of the lower sealing inorganic pattern LIL is arranged to extend upward in the third direction DR3 on the capping pattern CP so as to cover the capping pattern CP while contacting the cathode CE arranged along the partition opening OP-P within the partition opening OP-P. The lower portion of the lower sealing inorganic pattern LIL has a narrower width in the first direction DR1 in a cross-sectional view at the portion in contact with the second partition wall layer L2 than at the portion in contact with the first partition wall layer L1 along the undercut shape of the partition wall PW. The upper portion of the lower sealing inorganic pattern LIL includes a part and an upper portion above that part. A part of the upper portion of the lower sealing inorganic pattern LIL extends continuously upward from the portion in contact with the second partition wall layer L2 of the lower portion of the lower sealing inorganic pattern LIL. A part of the upper portion of the lower sealing inorganic pattern LIL has the same width as the portion in contact with the second partition wall layer L2 in the lower sealing inorganic pattern LIL. The side surface of this part of the upper portion of the lower sealing inorganic pattern LIL is in contact with the common inorganic film CLIL and is the aforementioned second side surface S2_LIL. Furthermore, the remaining part of the upper portion of the lower sealing inorganic pattern LIL is continuously upward along the third direction DR3 from a part of the upper portion of the lower sealing inorganic pattern LIL. The remaining part of the upper portion of the lower sealing inorganic pattern LIL is formed to protrude with respect to a part of the upper portion of the lower sealing inorganic pattern LIL in the first direction DR1. Also, the remaining part of the upper portion of the lower sealing inorganic pattern LIL is configured to include the aforementioned upper surface U_LIL, the first side surface S1_LIL, and the lower surface B_LIL. The upper surface U_LIL, the first side surface S1_LIL, and the lower surface B_LIL are the upper surface, the side surface, and the lower surface of the remaining part of the upper portion of the lower sealing inorganic pattern LIL. The first side surface S1_LIL extends downward in the third direction DR3 from an end portion of the upper surface U_LIL in a direction away from the center of the anode AE in the first direction DR1. This first side surface S1_LIL is located in a direction away from the center of the anode AE more than the second side surface S2_LIL in the first direction DR1. The lower surface B_LIL extends along the first direction DR1 from the lower end portion of the first side surface S1_LIL in the third direction DR3 toward the center of the anode AE. The end portion on the center side of the anode AE in the first direction DR1 of the lower surface B_LIL is continuous with the upper end of the second side surface S2_LIL. Due to such a side surface shape, the remaining part of the upper portion of the lower sealing inorganic pattern LIL protrudes in the first direction DR1 with respect to a part of the upper portion of the lower sealing inorganic pattern LIL. Thus, there is a gap between the upper surface of the second partition layer L2 and the lower surface B_LIL of the remaining part of the upper portion of the lower sealing inorganic pattern LIL. An internal region ES is disposed in the portion where this gap is provided.

[0108] The common inorganic film CLIL can cover the lower sealing inorganic pattern LIL and fill the space between the partition wall PW and the lower sealing inorganic pattern LIL. The common inorganic film CLIL can cover the dried lower sealing inorganic pattern LIL. For example, the common inorganic film CLIL can cover the lower sealing inorganic pattern LIL when the surface of the lower sealing inorganic pattern LIL is dried and there is no remaining moisture.

[0109] An internal region ES can be defined in the common inorganic film CLIL. The internal region ES can be an empty region formed during the deposition process of the common inorganic film CLIL. For example, the internal region ES can be filled with gas. The internal region ES can have a shape that surrounds the light-emitting opening OP-E on a plane (in plan view). A part of the internal region ES can overlap with the lower sealing inorganic pattern LIL on a plane, and the internal region ES can overlap with the partition wall PW on a plane. That is, the internal region ES is formed between the lower sealing inorganic pattern LIL and the partition wall PW and can overlap with the lower sealing inorganic pattern LIL and the partition wall PW. In the example of FIG. 5, the internal region ES is formed in the common inorganic film CLIL so as to be located in the interval between the upper surface of the second partition wall layer L2 and the lower surface B_LIL of the upper part of the lower sealing inorganic pattern LIL.

[0110] The common inorganic film CLIL can cover the upper surface U_LIL, the first side surface S1_LIL, the lower surface B_LIL, and the second side surface S2_LIL of the lower sealing inorganic pattern LIL. That is, the common inorganic film CLIL can cover the surface of the lower sealing inorganic pattern LIL and can be formed while surrounding the internal region ES.

[0111] The common inorganic film CLIL can contain an inorganic substance. For example, the common inorganic film CLIL can contain at least one of silicon nitride (SiNx) and silicon oxynitride (SiON). That is, only an inorganic substance can exist between the upper surface of the lower sealing inorganic pattern LIL and the upper surface of the partition wall PW.

[0112] The sealing organic film OL can be disposed on the common inorganic film CLIL. The sealing organic film OL can cover the common inorganic film CLIL and can provide a flat upper surface. The upper sealing inorganic film UIL can be disposed on the sealing organic film OL. The lower sealing inorganic pattern LIL, the common inorganic film CLIL, and the upper sealing inorganic film UIL can protect the display element layer DP-OLED from moisture / oxygen, and the sealing organic film OL can protect the display element layer DP-OLED from foreign substances such as dust particles.

[0113] In FIG. 5, the thin film encapsulation layer TFE is exemplarily illustrated as including the lower encapsulation inorganic pattern LIL, the common inorganic film CLIL, the encapsulation organic film OL, and the upper encapsulation inorganic film UIL, but is not limited thereto. For example, in one embodiment, the thin film encapsulation layer TFE can further include additional encapsulation inorganic patterns ALIL1, ALIL2, ALIL3 (see FIG. 9) disposed between the lower encapsulation inorganic pattern LIL and the common inorganic film CLIL. The detailed content will be described later with reference to FIG. 9.

[0114] According to the present invention, an organic substance (the first dummy layer D1 in FIG. 7I) that absorbs moisture between the lower encapsulation inorganic pattern LIL and the partition wall PW is removed, and the remaining moisture can be removed through a drying process. Therefore, the phenomenon in which foreign substances flow into the light-emitting element ED or the like through the moisture between the lower encapsulation inorganic pattern LIL and the partition wall PW can be reduced or eliminated. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of the display panel generated by foreign substances can be reduced or eliminated.

[0115] Also, conventionally, the encapsulation organic film OL was thickened to adjust the thin film encapsulation layer TFE to have a low dielectric constant. However, since the internal region ES is defined in the common inorganic film CLIL of the present invention, the common inorganic film CLIL can have a low dielectric constant close to 1. Therefore, the thickness of the encapsulation organic film OL of the present invention can be reduced, and the touch sensitivity can be improved as the thickness of the encapsulation organic film OL is reduced.

[0116] FIG. 6 is a cross-sectional view taken along the cutting line II-II' of FIG. 4. FIG. 6 shows an enlarged view of one first light-emitting region PXA-R, one second light-emitting region PXA-G, and one third light-emitting region PXA-B. The description of one light-emitting region PXA in FIG. 5 can be similarly applied to each of the first to third light-emitting regions PXA-R, PXA-G, PXA-B in FIG. 6. In describing FIG. 6, the same / similar reference numerals are used for the same / similar configurations as those described in FIG. 5, and the repeated descriptions are omitted.

[0117] Referring to FIG. 6, the display panel DP can include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED can include light emitting elements ED1, ED2, ED3, sacrificial patterns SP1, SP2, SP3, a pixel definition film PDL, and partition walls PW.

[0118] The light emitting elements ED1, ED2, ED3 can each include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 that emit different colors. A plurality of first light emitting elements ED1, a plurality of second light emitting elements ED2, and a plurality of third light emitting elements ED3 can be provided. However, for simplicity of explanation, they are expressed in the singular below.

[0119] The first light emitting element ED1 can include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1. The second light emitting element ED2 can include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The third light emitting element ED3 can include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, AE3 can be provided in a plurality of patterns. In one embodiment, the first light emitting pattern EP1 can provide red light, the second light emitting pattern EP2 can provide green light, and the third light emitting pattern EP3 can provide blue light.

[0120] First to third light emitting openings OP1-E, OP2-E, OP3-E can be defined in the pixel definition film PDL. The first light emitting opening OP1-E can expose at least a part of the first anode AE1. The second light emitting opening OP2-E can expose at least a part of the second anode AE2. The third light emitting opening OP3-E can expose at least a part of the third anode AE3.

[0121] In this embodiment, the first light-emitting region PXA-R can be defined as the region exposed by the first light-emitting opening OP1-E in the upper surface of the first anode AE1. The second light-emitting region PXA-G can be defined as the region exposed by the second light-emitting opening OP2-E in the upper surface of the second anode AE2. The third light-emitting region PXA-B can be defined as the region exposed by the third light-emitting opening OP3-E in the upper surface of the third anode AE3.

[0122] The sacrificial patterns SP1, SP2, SP3 can include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, SP3 can be disposed on the upper surfaces of the first to third anodes AE1, AE2, AE3, respectively. The first to third sacrificial openings OP1-S, OP2-S, OP3-S that overlap the first to third light-emitting openings OP1-E, OP2-E, OP3-E, respectively, can be defined in the first to third sacrificial patterns SP1, SP2, SP3.

[0123] In this embodiment, the first to third partition openings OP1-P, OP2-P, OP3-P that overlap the first to third light-emitting openings OP1-E, OP2-E, OP3-E, respectively, can be defined in the partition wall PW.

[0124] In this embodiment, the first to third light-emitting patterns EP1, EP2, EP3 and the first to third cathodes CE1, CE2, CE3 can be formed in each light-emitting opening OP1-E, OP2-E, OP3-E and partition opening OP1-P, OP2-P, OP3-P in a state physically separated by the second partition layer L2 that forms the chip portion. That is, the first light-emitting pattern EP1 and the first cathode CE1, the second light-emitting pattern EP2 and the second cathode CE2, and the third light-emitting pattern EP3 and the third cathode CE3 can be formed in each light-emitting opening OP1-E, OP2-E, OP3-E and partition opening OP1-P, OP2-P, OP3-P in a state physically separated from each other by the second partition layer L2. Note that it can be said that the first partition layer L1 is also involved in the physical separation. Then, the light-emitting elements ED1, ED2, ED3 can be arranged in the partition openings OP1-P, OP2-P, OP3-P and the light-emitting openings OP1-E, OP2-E, OP3-E. For example, the first light-emitting element ED1 can be arranged in the first partition opening OP1-P and the first light-emitting opening OP1-E, the second light-emitting element ED2 can be arranged in the second partition opening OP2-P and the second light-emitting opening OP2-E, and the third light-emitting element ED3 can be arranged in the third partition opening OP3-P and the third light-emitting opening OP3-E, and each light-emitting element ED1, ED2, ED3 is physically separated by the partition PW.

[0125] According to the present invention, a plurality of first light-emitting patterns EP1 can be patterned and deposited in pixel units by a chip portion defined by the partition PW. That is, the first light-emitting pattern EP1 is commonly formed using an open mask, but can be easily divided in pixel units by the partition PW.

[0126] When patterning the first light-emitting pattern EP1 using a fine metal mask (FMM) on the back side, a support spacer protruding from the conductive partition wall must be provided to support the fine metal mask. Also, since the fine metal mask is separated from the base surface where patterning is performed by approximately the height of the partition wall and the spacer, there may be limitations in realizing high resolution. Further, when the fine metal mask comes into contact with the spacer, foreign matter may remain on the spacer after the patterning process of the first light-emitting pattern EP1, or the spacer may be damaged by the stamping of the fine metal mask. Therefore, a defective display panel may be formed.

[0127] According to this embodiment, by including the partition wall PW, physical separation between the light-emitting elements ED1, ED2, and ED3 can be easily achieved. Therefore, current leakage, drive errors, etc. between adjacent light-emitting regions PXA-R, PXA-G, and PXA-B can be prevented, and independent driving can be enabled for each of the light-emitting elements ED1, ED2, and ED3.

[0128] In particular, by patterning a plurality of first light-emitting patterns EP1 while suppressing contact between the internal configuration and the mask within the display area DA (see FIG. 1B), a display panel DP with a reduced defect rate and improved process reliability can be provided. Also, since patterning can be achieved without providing another support spacer protruding from the partition wall PW, the areas of the light-emitting regions PXA-R, PXA-G, and PXA-B can be miniaturized, so a display panel DP that is easy to realize high resolution can be provided.

[0129] In addition, in manufacturing a large-area display panel DP, it is possible to omit the production of a large-area mask, thereby reducing the process cost. Also, since it is not affected by defects that occur in a large-area mask, a display panel DP with improved process reliability can be provided. The description of the plurality of first light-emitting patterns EP1 can be similarly applied to the plurality of second and third light-emitting patterns EP2 and EP3.

[0130] The thin-film encapsulation layer TFE can include a lower encapsulation inorganic pattern LIL, a common inorganic film CLIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0131] The lower encapsulation inorganic pattern LIL can include a first lower encapsulation inorganic pattern LIL1 that covers the first light-emitting element ED1, a second lower encapsulation inorganic pattern LIL2 that covers the second light-emitting element ED2, and a third lower encapsulation inorganic pattern LIL3 that covers the third light-emitting element ED3. The first to third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 can overlap with the first to third light-emitting openings OP1-E, OP2-E, and OP3-E, respectively. The first to third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 can be provided in a pattern form that is spaced apart from each other.

[0132] The common inorganic film CLIL can cover the first to third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 and fill the space between the partition wall PW and the first to third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. The common inorganic film CLIL can cover the dried first to third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3. For example, the common inorganic film CLIL can cover the first to third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 when the surfaces of the first to third lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 are dried and no remaining moisture exists.

[0133] Internal regions ES1, ES2, and ES3 can be defined in the common inorganic film CLIL. The internal regions ES1, ES2, and ES3 can be the empty regions formed during the deposition process of the common inorganic film CLIL. For example, the internal regions ES1, ES2, and ES3 can be filled with gas. The internal regions ES1, ES2, and ES3 can include a first internal region ES1, a second internal region ES2, and a third internal region ES3.

[0134] The first internal region ES1 can have a shape that surrounds the first light-emitting opening OP1-E on a plane. A part of the first internal region ES1 can overlap with the first lower sealing inorganic pattern LIL1 on a plane, and the first internal region ES1 can overlap with the partition wall PW on a plane. That is, the first internal region ES1 is formed between the first lower sealing inorganic pattern LIL1 and the partition wall PW and can overlap with the first lower sealing inorganic pattern LIL1 and the partition wall PW.

[0135] The second internal region ES2 can have a shape that surrounds the second light-emitting opening OP2-E on a plane. A part of the second internal region ES2 can overlap with the second lower sealing inorganic pattern LIL2 on a plane, and the second internal region ES2 can overlap with the partition wall PW on a plane. That is, the second internal region ES2 is formed between the second lower sealing inorganic pattern LIL2 and the partition wall PW and can overlap with the second lower sealing inorganic pattern LIL2 and the partition wall PW.

[0136] The third internal region ES3 can have a shape that surrounds the third light-emitting opening OP3-E on a plane. A part of the third internal region ES3 can overlap with the third lower sealing inorganic pattern LIL3 on a plane, and the third internal region ES3 can overlap with the partition wall PW on a plane. That is, the third internal region ES3 is formed between the third lower sealing inorganic pattern LIL3 and the partition wall PW and can overlap with the third lower sealing inorganic pattern LIL3 and the partition wall PW.

[0137] The common inorganic film CLIL can cover the upper surface U_LIL (see FIG. 5), the first side surface S1_LIL (see FIG. 5), the lower surface B_LIL (see FIG. 5), and the second side surface S2_LIL (see FIG. 5) of each of the first to third lower-sealing inorganic patterns LIL1, LIL2, and LIL3. That is, the common inorganic film CLIL can cover the surfaces of the first to third lower-sealing inorganic patterns LIL1, LIL2, and LIL3 and can be formed while surrounding the first to third internal regions ES1, ES2, and ES3.

[0138] FIGS. 7A to 8E are cross-sectional views showing a part of the steps of a display panel manufacturing method according to an embodiment of the present invention. In explaining FIGS. 7A to 8E, the same / similar reference numerals are used for the same / similar configurations with reference to FIGS. 1 to 6, and repeated explanations are omitted.

[0139] A display panel manufacturing method according to an embodiment of the present invention includes providing a preliminary display panel including a base layer, a pixel definition film disposed on the base layer, and a preliminary partition wall disposed on the pixel definition film; forming a partition wall having a partition wall opening from the preliminary partition wall; etching the pixel definition film to form a light-emitting opening overlapping the partition wall opening; forming a light-emitting element and a lower-sealing inorganic pattern covering the light-emitting element in the light-emitting opening and the partition wall opening; and drying the surfaces of the partition wall and the lower-sealing inorganic pattern.

[0140] Hereinafter, through FIGS. 7A to 8E, a method for forming three light-emitting elements ED1, ED2, and ED3 and lower-sealing inorganic patterns LIL1, LIL2, and LIL3, a common inorganic film CLIL, a sealing organic film OL, and an upper-sealing inorganic film UIL covering the light-emitting elements ED1, ED2, and ED3 will be described. The display panel DP formed through FIGS. 7A to 8E can correspond to the display panel DP in FIG. 6.

[0141] Referring to FIG. 7A, the display panel manufacturing method of the present invention can include a step of providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in this embodiment includes a base layer BL, a circuit element layer DP-CL, first to third anodes AE1, AE2, AE3, first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I, a pixel definition film PDL, and a preliminary partition wall PW-I. The preliminary partition wall PW-I includes a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I.

[0142] The circuit element layer DP-CL can be formed through a normal circuit element manufacturing process of forming an insulating layer, a semiconductor layer, and a conductive layer by means such as coating and vapor deposition, and selectively patterning the insulating layer, the semiconductor layer, and the conductive layer by photolithography and etching processes to form a semiconductor pattern, a conductive pattern, signal lines, etc.

[0143] The first anode AE1 and the first preliminary sacrificial pattern SP1-I are formed by the same patterning process, the second anode AE2 and the second preliminary sacrificial pattern SP2-I are formed by the same patterning process, and the third anode AE3 and the third preliminary sacrificial pattern SP3-I can be formed by the same patterning process. The pixel definition film PDL can be disposed on the base layer BL. The pixel definition film PDL can cover all of the first to third anodes AE1, AE2, AE3 and the first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I. In an example such as FIG. 7A, the pixel definition film PDL is disposed on the circuit element layer DP-CL on the base layer BL.

[0144] The first preliminary partition layer L1-I can be disposed on the pixel definition layer PDL. The first preliminary partition layer L1-I can be formed by a vapor deposition process of a conductive material. The second preliminary partition layer L2-I can be disposed on the first preliminary partition layer L1-I. The second preliminary partition layer L2-I can also be formed by a vapor deposition process of a conductive material. The first preliminary partition layer L1-I and the second preliminary partition layer L2-I can include a metal, a transparent conductive oxide (Transparent Conductive Oxide, TCO), or a combination thereof. For example, the metal can include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy. The transparent conductive oxide can include indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (Induim Gallium Zinc Oxide, IGZO), or aluminum zinc oxide (Aluminuin Zinc Oxide). In one embodiment of the present invention, the first preliminary partition layer L1-I can include aluminum (Al), and the second preliminary partition layer L2-I can include titanium (Ti), but the materials of the first preliminary partition layer L1-I and the second preliminary partition layer L2-I are not limited thereto.

[0145] Thereafter, referring to FIG. 7B, the display panel manufacturing method of the present invention may include a step of forming a first photoresist layer PR1 on the preliminary partition wall PW-I. The first photoresist layer PR1 can be formed by forming a preliminary photoresist layer on the preliminary partition wall PW-I and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first photo opening OP-PR1, a second photo opening OP-PR2, and a third photo opening OP-PR3 can be formed in the first photoresist layer PR1. The first photo opening OP-PR1 can be superimposed on the first anode AE1, the second photo opening OP-PR2 can be superimposed on the second anode AE2, and the third photo opening OP-PR3 can be superimposed on the third anode AE3.

[0146] Thereafter, referring to FIGS. 7C and 7D, the display panel manufacturing method of the present invention may include a step of forming a partition wall PW having partition wall openings OP1-P, OP2-P, and OP3-P from the preliminary partition wall PW-I (see FIG. 7B). The step of forming the partition wall PW may include a step of etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I to form a first partition wall layer L1 and a second partition wall layer L2 in which the partition wall openings OP1-P, OP2-P, and OP3-P are defined.

[0147] First, as shown in FIG. 7C, in the step of first etching the first preliminary partition layer L1-I and the second preliminary partition layer L2-I, the first preliminary partition layer L1-I and the second preliminary partition layer L2-I can be dry-etched using the first photoresist layer PR1 as a mask. In the dry etching in this first etching, for example, although not limited thereto, reactive ion gas, plasma gas, etc. are used to mainly etch the first preliminary partition layer L1-I and the second preliminary partition layer L2-I. In this case, it is preferable that etching of the first photoresist layer PR1 is suppressed. Portions of the preliminary partition PW-I that do not overlap with the first photoresist layer PR1 can be etched and removed. For example, a first preliminary partition opening OP1-PI is formed in the portion removed by overlapping with the first photo opening OP-PR1, a second preliminary partition opening OP2-PI is formed in the portion removed by overlapping with the second photo opening OP-PR2, and a third preliminary partition opening OP3-PI can be formed in the portion removed by overlapping with the third photo opening OP-PR3.

[0148] The first dry etching process in this embodiment can be performed in an etching environment where the etching selectivity between the first preliminary partition layer L1-I and the second preliminary partition layer L2-I is substantially the same. Therefore, the inner surfaces of the first preliminary partition layer L1-I and the second preliminary partition layer L2-I that define the preliminary partition openings OP1-PI, OP2-PI, OP3-PI can be substantially aligned.

[0149] Thereafter, as illustrated in FIG. 7D, in the step of secondarily etching the first preliminary partition layer L1-I (see FIG. 7C), the first preliminary partition layer L1-I can be wet-etched using the first photoresist layer PR1 as a mask. In the wet etching in this secondary etching, although not limited thereto, for example, nitric acid, phosphoric acid, hydrofluoric acid, etc. are used to mainly etch the first preliminary partition layer L1-I. In this case, it is preferable that etching of the first photoresist layer PR1 and the second preliminary partition layer L2-I is suppressed. Therefore, a part of the first preliminary partition layer L1-I can be etched to form partition openings OP1-P, OP2-P, OP3-P. The partition openings OP1-P, OP2-P, OP3-P can include a first partition opening OP1-P, a second partition opening OP2-P, and a third partition opening OP3-P. The first partition opening OP1-P can be formed to overlap with the first anode AE1, the second partition opening OP2-P can be formed to overlap with the second anode AE2, and the third partition opening OP3-P can be formed to overlap with the third anode AE3.

[0150] The secondary wet etching process in the present invention can be performed in an environment where the etching selectivity between the first preliminary partition layer L1-I and the second preliminary partition layer L2-I (see FIG. 7C) is large. Therefore, the inner surface of the partition PW defining the partition openings OP1-P, OP2-P, OP3-P can have an undercut shape in a cross-sectional view. Specifically, since the etching rate of the first preliminary partition layer L1-I with respect to the etching solution is larger than the etching rate of the second preliminary partition layer L2-I, the first preliminary partition layer L1-I can be mainly etched. Therefore, the first inner surface of the first partition layer L1 can be formed to be further recessed inward compared to the second inner surface of the second partition layer L2. A chip portion can be formed in the partition PW by a portion of the second partition layer L2 that protrudes more than the first partition layer L1.

[0151] Thereafter, referring to FIG. 7E, the method for manufacturing a display panel of the present invention may include a step of etching the pixel definition layer PDL to form light-emitting openings OP1-E, OP2-E, and OP3-E that overlap with the partition openings OP1-P, OP2-P, and OP3-P.

[0152] In the step of etching the pixel definition layer PDL, the pixel definition layer PDL can be dry-etched using the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) as masks. In dry etching, for example, but not limited to, reactive ion gas, plasma gas, etc. can be used. Portions of the pixel definition layer PDL that do not overlap with the first photoresist layer PR1 and the partition wall PW can be etched and removed. As a result, light-emitting openings OP1-E, OP2-E, and OP3-E that overlap with the partition openings OP1-P, OP2-P, and OP3-P can be formed in the pixel definition layer PDL. The light-emitting openings OP1-E, OP2-E, and OP3-E can include a first light-emitting opening OP1-E that overlaps with the first partition opening OP1-P, a second light-emitting opening OP2-E that overlaps with the second partition opening OP2-P, and a third light-emitting opening OP3-E that overlaps with the third partition opening OP3-P. In the example of FIG. 7E, by dry-etching the pixel definition layer PDL using the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) as masks, the pixel definition layer PDL is formed to have openings continuous with the partition openings OP-P (OP1-P, OP2-P, OP3-P) and light-emitting openings OP-E (OP1-E, OP2-E, OP3-E). The inner surfaces of each of the partition openings OP1-P, OP2-P, OP3-P and the inner surfaces of the openings continuous with the partition openings OP1-P, OP2-P, OP3-P coincide in the third direction DR3. The inner surfaces of the openings continuous with the partition openings OP1-P, OP2-P, OP3-P are located farther from the centers of the anodes AE1 to AE3 in the first direction DR1 than the inner surfaces of the light-emitting openings OP1-E, OP2-E, OP3-E, respectively.

[0153] Thereafter, referring to FIG. 7F, the display panel manufacturing method of the present invention can include a step of etching the first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I (refer to FIG. 7E) to form sacrificial patterns SP1, SP2, SP3 having sacrificial openings OP1-S, OP2-S, OP3-S that overlap with the light-emitting openings OP1-E, OP2-E, OP3-E.

[0154] The step of etching the first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I can wet-etch the first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I using the first photoresist layer PR1 and the partition wall PW (for example, the second partition wall layer L2) as masks. Portions of the first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I that do not overlap with the first photoresist layer PR1 and the partition wall PW can be etched and removed. As a result, the sacrificial patterns SP1, SP2, SP3 can be formed from the first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I.

[0155] The sacrificial patterns SP1, SP2, SP3 can include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. A first sacrificial opening OP1-S that overlaps with the first light-emitting opening OP1-E is formed in the first sacrificial pattern SP1, a second sacrificial opening OP2-S that overlaps with the second light-emitting opening OP2-E is formed in the second sacrificial pattern SP2, and a third sacrificial opening OP3-S that overlaps with the third light-emitting opening OP3-E can be formed in the third sacrificial pattern SP3.

[0156] The etching process of the sacrificial patterns SP1, SP2, and SP3 can be performed in an environment where the etching selectivity between the sacrificial patterns SP1, SP2, and SP3 and the anodes AE1, AE2, and AE3 is large. Through this, it is possible to prevent the anodes AE1, AE2, and AE3 from being etched together. That is, by disposing the sacrificial patterns SP1, SP2, and SP3, which have a higher etching rate than the anodes AE1, AE2, and AE3, between the pixel definition film PDL and the anodes AE1, AE2, and AE3, it is possible to prevent the anodes AE1, AE2, and AE3 from being etched together and damaged during the etching process. Referring to FIG. 7E, the pixel definition film PDL in the portion where the first to third light-emitting openings OP1-E, OP2-E, and OP3-E are formed covers the ends of the first to third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I. When the first to third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I are wet-etched, the first to third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I that are not covered by other layers due to the positions of the first to third light-emitting openings OP1-E, OP2-E, and OP3-E are etched. Therefore, the sacrificial patterns SP1, SP2, and SP3 are formed by the ends of the first to third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I covered by the pixel definition film PDL remaining without being etched. In the example of FIG. 7F, the first to third preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I are etched in a direction away from the centers of the anodes AE1, AE2, and AE3 rather than the ends of the first to third light-emitting openings OP1-E, OP2-E, and OP3-E. That is, the sacrificial patterns SP1, SP2, and SP3 are formed such that the inner surfaces of the sacrificial patterns SP1, SP2, and SP3 are located in a direction away from the centers of the anodes AE1, AE2, and AE3 rather than the inner surfaces of the first to third light-emitting openings OP1-E, OP2-E, and OP3-E.

[0157] Thereafter, referring to FIGS. 7G to 8B, the display panel manufacturing method of the present invention can include a step of removing the first photoresist layer PR1 (see FIG. 7F) and then forming light-emitting elements ED1, ED2, ED3 and lower-sealing inorganic patterns LIL1, LIL2, LIL3 that cover the light-emitting elements ED1, ED2, ED3 in the light-emitting openings OP1-E, OP2-E, OP3-E and the partition openings OP1-P, OP2-P, OP3-P.

[0158] The step of forming the light-emitting elements ED1, ED2, ED3 and the lower-sealing inorganic patterns LIL1, LIL2, LIL3 can include a step of forming the first light-emitting element ED1 and the first lower-sealing inorganic pattern LIL1 that covers the first light-emitting element ED1, a step of forming the second light-emitting element ED2 and the second lower-sealing inorganic pattern LIL2 that covers the second light-emitting element ED2, and a step of forming the third light-emitting element ED3 and the third lower-sealing inorganic pattern LIL3 that covers the third light-emitting element ED3. The step of forming the first light-emitting element ED1 and the first lower-sealing inorganic pattern LIL1 will be described with reference to FIGS. 7G to 7I, and the steps of forming the second light-emitting element ED2 and the second lower-sealing inorganic pattern LIL2 and the third light-emitting element ED3 and the third lower-sealing inorganic pattern LIL3 will be described with reference to FIGS. 8A to 8B.

[0159] Referring to FIG. 7G, the step of forming the first light-emitting element ED1 may include the step of forming the first light-emitting pattern EP1 and the step of forming the first cathode CE1. The step of forming the first light-emitting pattern EP1 may include a step of depositing a light-emitting layer. For example, the step of forming the first light-emitting pattern EP1 may include a step of thermally evaporating the light-emitting layer. The light-emitting layer is separated by a chip portion (a chip portion formed by the second partition layer L2) formed in the partition wall PW, and can be deposited inside the first to third partition openings OP1-P, OP2-P, OP3-P and on the partition wall PW. The light-emitting layer formed inside the first partition opening OP1-P can form the first light-emitting pattern EP1, and the light-emitting layer formed inside the second and third partition openings OP2-P, OP3-P and on the partition wall PW can form the first dummy layer D1. That is, the first light-emitting pattern EP1 is formed so as to overlap the first anode AE1 on the first partition opening OP1-P, and the first light-emitting pattern EP1 can cover and be formed on the first anode AE1 and the pixel definition film PDL. In the example of FIG. 7G, in the step of forming the first light-emitting element ED1, a first light-emitting layer for forming the first light-emitting pattern EP1 is deposited through the first partition opening OP1-P. As a result, on the first anode AE1, the first light-emitting pattern EP1 is continuously arranged in the first sacrificial opening OP1-S, in the first light-emitting opening OP1-E, and in the lower part of the opening continuous with the first partition opening OP1-P in the pixel definition film PDL. Note that in the example of FIG. 7G, the first light-emitting pattern EP1 only reaches the lower part of the opening continuous with the first partition opening OP1-P. However, the first light-emitting pattern EP1 may be formed continuously from the lower part of the opening continuous with the first partition opening OP1-P to the upper part of the opening continuous with the first partition opening OP1-P. Also, in the step of forming the first light-emitting element ED1, the first light-emitting layer is deposited through the second and third partition openings OP2-P and OP3-P, so that the first dummy layer D1 is formed on the second and third anodes AE2 and AE3 at the portions corresponding to the second and third partition openings OP2-P and OP3-P. The form of the first dummy layer D1 is the same as that of the first light-emitting pattern EP1. Also, since the first light-emitting layer is deposited on the partition PW, the first dummy layer D1 is formed on the second partition layer L2.

[0160] The first dummy layer D1 formed together in the step of forming the first light-emitting pattern EP1 can contain an organic substance. For example, the first dummy layer D1 can contain the same substance as the first light-emitting pattern EP1. The first dummy layer D1 is formed simultaneously with the first light-emitting pattern EP1 through one process and is separated from the first light-emitting pattern EP1 by the undercut shape of the partition PW.

[0161] The step of forming the first cathode CE1 can include a deposition process of the cathode layer. For example, the step of forming the first cathode CE1 can include the step of sputtering the cathode layer. The cathode layer can be separated by the chip portion formed on the partition PW and deposited inside the first to third partition openings OP1-P, OP2-P, OP3-P and on the partition PW. The cathode layer formed inside the first partition opening OP1-P can form the first cathode CE1, and the cathode layer formed inside the second and third partition openings OP2-P, OP3-P and on the partition PW can form the second dummy layer D2. That is, the first cathode CE1 is formed so as to overlap the first partition opening OP1-P on the first light-emitting pattern EP1, and the first cathode CE1 can cover and be formed on the first light-emitting pattern EP1. Also, the first cathode CE1 can be formed in contact with the inner surface of the first partition layer L1 and extended along the inner surface of the first partition layer L1. In the example of FIG. 7G, in the step of forming the first cathode CE1, a first cathode layer for forming the first cathode CE1 is deposited through the first partition opening OP1-P. As a result, the first cathode CE1 is formed in the upper portion of the opening continuous with the first partition opening OP1-P. Further, the first cathode CE1 can be formed along the inner surface of the first partition layer L1. In the example of FIG. 7G, the first cathode CE1 is formed in the upper portion of the opening continuous with the first partition opening OP1-P. However, the first cathode CE1 may be formed so as to further fill a part of the first partition opening OP1-P from the upper portion of the opening continuous with the first partition opening OP1-P. Alternatively, in a state where the first light-emitting pattern EP1 is formed up to the upper portion of the opening continuous with the first partition opening OP1-P, the first cathode CE1 may be formed only in the first partition opening OP1-P on the first light-emitting pattern EP1. Also, in the step of forming the first cathode CE1, by depositing the first cathode layer through the second and third partition openings OP2-P and OP3-P, a second dummy layer D2 is formed on the first dummy layer D1 in the portions corresponding to the second and third partition openings OP2-P and OP3-P. The aspect of the second dummy layer D2 is the same as that of the first cathode CE1. Also, by depositing the first cathode layer on the partition PW, a second dummy layer D2 is formed on the first dummy layer D1 of the partition PW.

[0162] The second dummy layer D2 formed together in the step of forming the first cathode CE1 can contain a conductive substance. For example, the second dummy layer D2 can contain the same substance as the first cathode CE1. The second dummy layer D2 is formed simultaneously with the first cathode CE1 through one process and is formed separately from the first cathode CE1 by the undercut shape of the partition PW.

[0163] The first anode AE1, the first light-emitting pattern EP1, and the first cathode CE1 can be sequentially stacked along the third direction DR3. The first anode AE1, the first light-emitting pattern EP1, and the first cathode CE1 can form the first light-emitting element ED1.

[0164] The display panel manufacturing method of the present invention can include a step of forming a capping pattern CP. The step of forming the capping pattern CP can include a vapor deposition process of a capping pattern layer. The capping pattern layer can be separated by chip portions formed on the partition wall PW and can be vapor deposited inside the first to third partition wall openings OP1-P, OP2-P, OP3-P and on the partition wall PW. The capping pattern layer formed inside the first partition wall opening OP1-P can form the capping pattern CP, and the capping pattern layers formed inside the second and third partition wall openings OP2-P, OP3-P and on the partition wall PW can form the third dummy layer D3.

[0165] The third dummy layer D3 formed together in the step of forming the capping pattern CP can contain a conductive material. For example, the third dummy layer D3 can contain the same material as the capping pattern CP. The third dummy layer D3 is formed simultaneously with the capping pattern CP through one process and is formed separately from the capping pattern CP by the undercut shape of the partition wall PW. In an embodiment of the present invention, the formation process of the capping pattern CP and the third dummy layer D3 can be omitted.

[0166] Thereafter, referring to FIG. 7H, the step of forming the first lower sealing inorganic pattern LIL1 may include the step of depositing the first lower sealing inorganic layer LIL1-I. The first lower sealing inorganic layer LIL1-I can be formed through a deposition process. In one embodiment, the first lower sealing inorganic layer LIL1-I can be formed through a chemical vapor deposition (CVD) process. The first lower sealing inorganic layer LIL1-I can be formed to cover the first cathode CE1 (or the capping pattern CP) and the partition wall PW. A part of the first lower sealing inorganic layer LIL1-I can fill the first partition wall opening OP1-P. In the example of FIG. 7H, the first lower sealing inorganic layer LIL1-I is formed over the entirety of the structure after the step of FIG. 7G. That is, the first lower sealing inorganic layer LIL1-I is formed to cover the first cathode CE1, over the third dummy layer D3 within the second and third partition wall openings OP2-P, OP3-P, and over the third dummy layer D3 of the partition wall PW. Thus, the first lower sealing inorganic layer LIL1-I is formed to cover the third dummy layer D3 of the partition wall PW while filling the first to third partition wall openings OP1-P, OP2-P, OP3-P.

[0167] Thereafter, the method for manufacturing a display panel of the present invention may include the step of forming a second photoresist layer PR2. In the step of forming the second photoresist layer PR2, the second photoresist layer PR2 can be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 can be formed in a pattern form corresponding to the first light-emitting element ED1.

[0168] Referring to FIG. 7I, the step of forming the first lower sealing inorganic pattern LIL1 may include the step of removing a part of the first lower sealing inorganic layer LIL1-I (refer to FIG. 7H) that does not overlap with the first light-emitting element ED1.

[0169] The step of removing a part of the first lower encapsulation inorganic layer LIL1-I that does not overlap with the first light-emitting element ED1 is performed by dry etching the first lower encapsulation inorganic layer LIL1-I using the second photoresist layer PR2 as a mask. A portion of the first lower encapsulation inorganic layer LIL1-I that does not overlap with the second photoresist layer PR2 can be removed, and the portion that is not etched and remains in the first lower encapsulation inorganic layer LIL1-I can be formed as the first lower encapsulation inorganic pattern LIL1.

[0170] Thereafter, the method for manufacturing a display panel according to the present invention may include a step of removing the dummy layers D1, D2, and D3. Among the dummy layers D1, D2, and D3, the second and third dummy layers D2 and D3 can be removed by wet etching, and the first dummy layer D1 among the dummy layers D1, D2, and D3 can be removed by a stripper. The stripper is an etching solution capable of removing the first dummy layer D1.

[0171] Thereafter, referring to FIG. 8A, the method for manufacturing a display panel according to the present invention can form the second light-emitting element ED2, the capping pattern CP, and the second lower encapsulation inorganic pattern LIL2 after removing the second photoresist layer PR2 (see FIG. 7I). The step of forming the second light-emitting element ED2, the capping pattern CP, and the second lower encapsulation inorganic pattern LIL2 can be substantially the same as the step of forming the first light-emitting element ED1, the capping pattern CP, and the first lower encapsulation inorganic pattern LIL1 described through FIGS. 7G to 7I.

[0172] Thereafter, referring to FIG. 8B, the method for manufacturing a display panel according to the present invention can form the third light-emitting element ED3, the capping pattern CP, and the third lower encapsulation inorganic pattern LIL3. The step of forming the third light-emitting element ED3, the capping pattern CP, and the third lower encapsulation inorganic pattern LIL3 can be substantially the same as the step of forming the first light-emitting element ED1, the capping pattern CP, and the first lower encapsulation inorganic pattern LIL1 described through FIGS. 7G to 7I.

[0173] Thereafter, referring to FIG. 8C, the display panel manufacturing method of the present invention may include a step of drying the surfaces of the partition wall PW and the lower sealing inorganic patterns LIL1, LIL2, and LIL3. The step of drying the surfaces of the partition wall PW and the lower sealing inorganic patterns LIL1, LIL2, and LIL3 may be a step of providing heat HT to the surfaces of the partition wall PW and the lower sealing inorganic patterns LIL1, LIL2, and LIL3 to evaporate the remaining moisture. As a result of the above process, there may be no moisture on the surfaces of the partition wall PW and the lower sealing inorganic patterns LIL1, LIL2, and LIL3.

[0174] According to the present invention, an organic substance (the first dummy layer D1 in FIG. 7I) that absorbs moisture between the lower sealing inorganic pattern LIL and the partition wall PW can be removed, and the remaining moisture can be removed through the drying process. Therefore, the phenomenon in which foreign substances flow into the light-emitting element ED or the like through the moisture between the lower sealing inorganic pattern LIL and the partition wall PW can be reduced or eliminated. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of the display panel generated by foreign substances can be reduced or eliminated.

[0175] Thereafter, referring to FIG. 8D, the display panel manufacturing method of the present invention may include a step of forming a common inorganic film CLIL that covers the first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3.

[0176] The common inorganic film CLIL can be formed to cover the dried first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3. The common inorganic film CLIL can cover the upper surface U_LIL (see FIG. 5), the first side surface S1_LIL (see FIG. 5), the lower surface B_LIL (see FIG. 5), and the second side surface S2_LIL (see FIG. 5) of each of the first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3.

[0177] The common inorganic film CLIL can be filled between the partition wall PW and the first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3. In the process of forming the common inorganic film CLIL, the first to third internal regions ES1, ES2, and ES3, which are empty regions, can be formed. The first internal region ES1 is formed between the first lower sealing inorganic pattern LIL1 and the partition wall PW and can overlap with the first lower sealing inorganic pattern LIL1 and the partition wall PW. The second internal region ES2 is formed between the second lower sealing inorganic pattern LIL2 and the partition wall PW and can overlap with the second lower sealing inorganic pattern LIL2 and the partition wall PW. The third internal region ES3 is formed between the third lower sealing inorganic pattern LIL3 and the partition wall PW and can overlap with the third lower sealing inorganic pattern LIL3 and the partition wall PW. That is, the common inorganic film CLIL can be formed while covering the surfaces of the first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3 and surrounding the first to third internal regions ES1, ES2, and ES3. The first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3 (lower sealing inorganic pattern LIL) are formed such that the remaining part of the upper part of the lower sealing inorganic pattern LIL protrudes in the first direction DR1 with respect to a part of the upper part of the lower sealing inorganic pattern LIL. Therefore, there is a gap between the upper surface of the second partition layer L2 and the lower surface B_LIL of the upper part of the lower sealing inorganic pattern LIL. When the common inorganic film CLIL is formed as described above so as to cover the lower sealing inorganic pattern LIL having such a shape, the first to third internal regions ES1, ES2, and ES3 (internal region ES) can be formed without the common inorganic film CLIL being filled between the upper surface of the second partition layer L2 and the lower surface B_LIL of the lower sealing inorganic pattern LIL.

[0178] Conventionally, the sealing organic film OL was thickened to adjust the thin film sealing layer TFE to have a low dielectric constant. However, since the internal region ES is defined in the common inorganic film CLIL of the present invention, the common inorganic film CLIL can have a low dielectric constant close to 1. Therefore, in the present invention, the thickness of the sealing organic film OL can be reduced, and the touch sensitivity can be improved by reducing the thickness of the sealing organic film OL.

[0179] Thereafter, referring to FIG. 8E, the display panel manufacturing method of the present invention may include a step of forming a sealing organic film OL and an upper sealing inorganic film UIL to complete the display panel DP. The sealing organic film OL is formed by applying an organic substance in an inkjet method, but is not limited thereto. The sealing organic film OL provides a flattened upper surface. Thereafter, the upper sealing inorganic film UIL can be formed by vapor-depositing an inorganic substance. Through this, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE can be formed.

[0180] FIG. 9 is a cross-sectional view taken along the cutting line II-II' of FIG. 4. The cross-sectional view of FIG. 9 corresponds to the cross-sectional view of FIG. 6 and illustrates another embodiment of the present invention. In explaining FIG. 9, the same / similar reference numerals are used for the same / similar configurations as those described in FIGS. 5 and 6, and repeated explanations are omitted.

[0181] Referring to FIG. 9, the display panel DPa may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFEa. The thin film encapsulation layer TFEa may include lower sealing inorganic patterns LIL1, LIL2, LIL3, additional sealing inorganic patterns ALIL1, ALIL2, ALIL3, a common inorganic film CLILa, a sealing organic film OL, and an upper sealing inorganic film UIL.

[0182] The thin film encapsulation layer TFEa in FIG. 9 may further include additional sealing inorganic patterns ALIL1, ALIL2, ALIL3 than the thin film encapsulation layer TFE in FIG. 6. The additional sealing inorganic patterns ALIL1, ALIL2, ALIL3 may include a first additional sealing inorganic pattern ALIL1, a second additional sealing inorganic pattern ALIL2, and a third additional sealing inorganic pattern ALIL3.

[0183] The first additional sealing inorganic pattern ALIL1 can cover the dried first lower sealing inorganic pattern LIL1, the second additional sealing inorganic pattern ALIL2 can cover the dried second lower sealing inorganic pattern LIL2, and the third additional sealing inorganic pattern ALIL3 can cover the dried third lower sealing inorganic pattern LIL3. For example, each of the first to third additional sealing inorganic patterns ALIL1, ALIL2, and ALIL3 can cover the first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3 when the surfaces of the first to third lower sealing inorganic patterns LIL1, LIL2, and LIL3 are dried and there is no remaining moisture.

[0184] The first to third additional sealing inorganic patterns ALIL1, ALIL2, and ALIL3 can respectively overlap with the first to third light-emitting openings OP1-E, OP2-E, and OP3-E, and the first to third additional sealing inorganic patterns ALIL1, ALIL2, and ALIL3 can be provided in a pattern form spaced apart from each other.

[0185] The common inorganic film CLILa can be disposed on the first to third additional sealing inorganic patterns ALIL1, ALIL2, and ALIL3 to cover the first to third additional sealing inorganic patterns ALIL1, ALIL2, and ALIL3. The description of the common inorganic film CLILa can be substantially the same as the description of the common inorganic film CLIL in FIG. 6. Although the internal regions ES1, ES2, and ES3 (see FIG. 6) are not shown in FIG. 9, the internal regions ES1, ES2, and ES3 can also be defined in the common inorganic film CLILa of FIG. 9.

[0186] The process of manufacturing the display panel DPa in FIG. 9 is partially different from the process of manufacturing the display panel DP described in FIGS. 7A to 8E. The manufacturing method of the display panel DPa in FIG. 9 can further include the step of forming additional sealing inorganic patterns ALIL1, ALIL2, and ALIL3 that cover the lower sealing inorganic patterns LIL1, LIL2, and LIL3. For example, between the step of removing the dummy layers D1, D2, and D3 in FIG. 7I and the step of forming the second light-emitting element ED2 in FIG. 8A, it can further include the step of drying the surface of the partition wall PW and the first lower sealing inorganic pattern LIL1, and the step of forming the first additional sealing inorganic pattern ALIL1 that covers the first lower sealing inorganic pattern LIL1.

[0187] Also, the manufacturing method of the display panel DPa in FIG. 9 can further include, between the step of forming the second light-emitting element ED2 and the second lower sealing inorganic pattern LIL2 in FIG. 8A and the step of forming the third light-emitting element ED3 in FIG. 8B, the step of drying the surface of the partition wall PW and the second lower sealing inorganic pattern LIL2, and the step of forming the second additional sealing inorganic pattern ALIL2 that covers the second lower sealing inorganic pattern LIL2.

[0188] Also, the manufacturing method of the display panel DPa in FIG. 9 can further include, after the step of forming the third light-emitting element ED3 and the third lower sealing inorganic pattern LIL3 in FIG. 8B, the step of drying the surface of the partition wall PW and the third lower sealing inorganic pattern LIL3, and the step of forming the third additional sealing inorganic pattern ALIL3 that covers the third lower sealing inorganic pattern LIL3.

[0189] In the manufacturing method of the display panel DPa in FIG. 9, the step of drying the surface of the partition wall PW and the lower sealing inorganic patterns LIL1, LIL2, and LIL3 in FIG. 8C can be omitted. Also, the manufacturing method of the display panel DPa in FIG. 9 can include the step of forming a common inorganic film CLILa that covers the first to third additional sealing inorganic patterns ALIL1, ALIL2, and ALIL3.

[0190] According to the above-described configuration, it is possible to provide a display panel or the like with improved display quality in a display panel that forms a light-emitting element without using a metal mask. In addition, an organic substance that absorbs moisture between the lower sealing inorganic pattern and the partition wall can be removed, and the remaining moisture can be removed through a drying process. Therefore, the phenomenon in which foreign matter flows into the light-emitting element or the like through the moisture between the lower sealing inorganic pattern and the partition wall can be reduced or eliminated. As a result, pixel defects (dark spots, pixel shrinkage, etc.) of the display panel generated by foreign matter can be reduced or eliminated.

[0191] In the past, the thickness of the encapsulation organic film was increased to adjust the low dielectric constant of the thin film encapsulation layer. However, since an internal region is defined in the common inorganic film of the present invention, the common inorganic film can have a low dielectric constant close to 1. Therefore, the thickness of the encapsulation organic film of the present invention can be reduced, and the touch sensitivity can be improved by reducing the thickness of the encapsulation organic film.

[0192] The preferred embodiments of the invention have been described above with reference thereto. However, those skilled in the relevant art or those having ordinary knowledge in the relevant art can understand that the present invention can be variously modified and changed within the scope not departing from the spirit and scope of the present invention described in the claims to be described later. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

Explanation of reference numerals

[0193] DP Display panel PDL Pixel definition layer PW Partition wall AE Anode EP Light-emitting pattern CE Cathode ED1, ED2, ED3 A plurality of light-emitting elements LIL1, LIL2, LIL3 A plurality of lower sealing inorganic patterns ALIL1, ALIL2, ALIL3 First to Third Additional Sealed Inorganic Patterns CLIL Common Inorganic Film ES Inner Region OL Sealed Organic Film UIL Upper Sealed Inorganic Film

Claims

1. A base layer; a pixel defining film disposed on the base layer and having a light emitting opening; a partition disposed on the pixel defining film and having a partition opening overlapping the light emitting opening; a plurality of light emitting devices each including an anode, a light emitting pattern, and a cathode in contact with the partition wall, the light emitting device being disposed within the light emitting opening and the partition wall opening; a plurality of lower sealing inorganic patterns covering each of the plurality of light emitting devices; a common inorganic film covering the plurality of lower sealing inorganic patterns and filling spaces between the partition walls and the plurality of lower sealing inorganic patterns.

2. The plurality of light emitting elements include a first light emitting element, a second light emitting element, and a third light emitting element each emitting a different color, 2. The display panel of claim 1, wherein the plurality of lower sealing inorganic patterns include a first lower sealing inorganic pattern covering the first light-emitting element, a second lower sealing inorganic pattern covering the second light-emitting element, and a third lower sealing inorganic pattern covering the third light-emitting element.

3. The display panel of claim 2 , wherein the common inorganic film covers the first, second and third lower sealing inorganic patterns that have been dried.

4. a first additional sealing inorganic pattern covering the dried first lower sealing inorganic pattern; a second additional sealing inorganic pattern covering the dried second lower sealing inorganic pattern; The display panel of claim 2 , further comprising a third additional sealing inorganic pattern covering the dried third lower sealing inorganic pattern.

5. The display panel of claim 4 , wherein the common inorganic film covers the first, second and third additional sealing inorganic patterns.

6. The display panel of claim 1 , wherein the common inorganic film defines an interior region, the interior region being open.

7. The display panel according to claim 6 , wherein the internal region has a shape surrounding the light-emitting opening in a plan view.

8. The display panel according to claim 6 , wherein a part of the internal region overlaps with the plurality of lower sealing inorganic patterns in a plan view.

9. Each of the plurality of lower sealing inorganic patterns is The top surface and a first side extending from the top surface in a thickness direction of the base layer; a bottom surface extending from the first side toward a center of the anode; The display panel of claim 1 , further comprising: a second side extending from the lower surface in a thickness direction of the base layer.

10. The display panel of claim 9 , wherein the common inorganic film covers the upper surface, the first side surface, the lower surface, and the second side surface of each of the plurality of dried lower sealing inorganic patterns.

11. The display panel of claim 1 , wherein the common inorganic film includes an inorganic material.

12. 2. The display panel of claim 1, wherein the common inorganic film comprises at least one of silicon nitride (SiNx) and silicon oxynitride (SiON).

13. a sealing organic film covering the common inorganic film; The display panel of claim 1 , further comprising an upper sealing inorganic film covering the sealing organic film.

14. providing a preliminary display panel including a base layer, a pixel defining film disposed on the base layer, and a preliminary barrier rib disposed on the pixel defining film; forming a partition having a partition opening from the preliminary partition; forming a light emitting opening overlapping the partition opening by etching the pixel defining layer; forming a light emitting device within the light emitting opening and the partition opening and a lower sealing inorganic pattern covering the light emitting device; drying surfaces of the barrier ribs and the lower sealing inorganic pattern.

15. forming the light emitting device within the light emitting opening and the partition opening, and the lower sealing inorganic pattern covering the light emitting device, forming a first light emitting device and a first lower sealing inorganic pattern covering the first light emitting device; forming a second light emitting device and a second lower sealing inorganic pattern covering the second light emitting device; The method of claim 14 , further comprising forming a third light emitting device and a third lower sealing inorganic pattern covering the third light emitting device.

16. 16. The method of claim 15, further comprising forming a common inorganic layer covering the first, second and third lower sealing inorganic patterns.

17. The method of claim 15, further comprising forming an additional sealing inorganic pattern to cover the lower sealing inorganic pattern.

18. forming the additional sealing inorganic pattern covering the lower sealing inorganic pattern; drying surfaces of the partition wall and the first lower sealing inorganic pattern after forming the first light emitting device and the first lower sealing inorganic pattern; forming a first additional sealing inorganic pattern covering the first lower sealing inorganic pattern; drying surfaces of the partition wall and the second lower sealing inorganic pattern after forming the second light emitting device and the second lower sealing inorganic pattern; forming a second additional sealing inorganic pattern covering the second lower sealing inorganic pattern; drying surfaces of the partition wall and the third lower sealing inorganic pattern after forming the third light emitting device and the third lower sealing inorganic pattern; 20. The method of claim 17, further comprising: forming a third additional sealing inorganic pattern covering the third lower sealing inorganic pattern.

19. 20. The method of claim 18, further comprising forming a common inorganic layer covering the first, second and third additional sealing inorganic patterns.

20. A base layer; a pixel defining film disposed on the base layer and having a light emitting opening; a partition disposed on the pixel defining film and having a partition opening overlapping the light emitting opening; a plurality of light emitting devices each including an anode, a light emitting pattern, and a cathode in contact with the partition wall, the light emitting device being disposed within the light emitting opening and the partition wall opening; a plurality of lower sealing inorganic patterns covering each of the plurality of light emitting devices; The method for manufacturing a display panel, wherein only an inorganic material is disposed between the lower sealing inorganic pattern and the upper surface of the partition wall.

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