Display device

Abstract

To provide a display device.SOLUTION: The display device includes a first light emission layer including a first host in an optical area where low-resolution pixels are disposed, and a second light emission layer including a second host different from the first host. The display device is capable of reducing a difference in luminance between an area where the low-resolution pixels are disposed and an area where high-resolution pixels are disposed.SELECTED DRAWING: Figure 7a

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] With the development of technology, in addition to the image display function, a display device can also provide functions such as a photographing function and various sensing functions.

[0003] Therefore, the display device must be equipped with optoelectronic devices (also referred to as light receiving devices or sensors) such as cameras and sensing sensors.

[0004] Since the optoelectronic device must receive light on the front surface of the display device, it must be installed in a place where light reception is advantageous.

[0005] Therefore, in the conventional display device, the camera (camera lens) and the sensing sensor have to be installed so as to be exposed on the front surface.

[0006] As a result, the bezel of the display panel becomes wider, or a notch or a physical hole is formed in the display area of the display panel, and a camera or a sensing sensor is installed therein.

[0007] Therefore, even when the display device is equipped with optoelectronic devices such as a camera and a sensing sensor that receive and detect light on the front surface, it may be required to have a high transmittance in order to perform the intended function.

Summary of the Invention

Problems to be Solved by the Invention

[0008] In order to implement a full-screen display, a solution has been proposed in which an area where low-resolution pixels are arranged is provided within the screen of the display panel, and a camera and / or various sensors are arranged at positions facing the area where low-resolution pixels are arranged under the display panel.

[0009] However, since pixels are also arranged in the area where low-resolution pixels are arranged and the light-emitting area decreases, in order to maintain the same luminance, a current of 1.5 times or more the current required to drive the low-resolution pixels may be required.

[0010] As the required amount of current increases, the lifetime of the pixels may decrease. Over time, there has been a problem that the boundary of the area where the low-resolution pixels are arranged is clearly recognized because a large luminance difference occurs between the area where the low-resolution pixels are arranged and the area where the high-resolution pixels are arranged.

[0011] To address this problem, the inventors of the present specification invented a display device that can increase the lifetime only in the area where the low-resolution pixels are arranged and reduce the luminance difference between the area where the low-resolution pixels are arranged and the area where the high-resolution pixels are arranged even during long-term driving.

[0012] Embodiments of the present disclosure can provide a display device capable of reducing the luminance difference between an area where low-resolution pixels are arranged and an area where high-resolution pixels are arranged.

Means for Solving the Problem

[0013] Embodiments of the present disclosure include a substrate including a general area in which a plurality of first pixels are arranged and having a first resolution and an optical area in which a plurality of second pixels are arranged and having a second resolution smaller than the first resolution, a first electrode layer located on the substrate, a first light-emitting layer located on the first electrode layer and including a first host in the general area and the optical area, a second light-emitting layer located on the first light-emitting layer, including the first host in the general area, and including a second host different from the first host in the optical area, and a second electrode layer located on the second light-emitting layer.

[0014] Embodiments of the present disclosure include a general area where a plurality of first sub-pixels are arranged and an optical area where a plurality of second sub-pixels are arranged. The number of second sub-pixels per unit area in the optical area is less than the number of first sub-pixels per unit area in the general area. Each of the first sub-pixels in the general area and the second sub-pixels in the optical area includes a light-emitting element. The light-emitting element includes a first electrode layer on a substrate, one or more stacks, and a second electrode layer on the one or more stacks. Each of the one or more stacks is located on the first electrode layer, and includes a first light-emitting layer including a first host in the general area and the optical area and located on the first light-emitting layer, and a second light-emitting layer including a first host in the general area and a second host different from the first host in the optical area. A display device can be provided.

[0015] According to an embodiment of the present disclosure, a display device capable of reducing the luminance difference between an area where low-resolution pixels are arranged and an area where high-resolution pixels are arranged and enabling low-power driving can be provided.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

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Figure 7a

Figure 7b

Figure 8a

Figure 8b

Figure 8c

Figure 9a

Figure 9b

Figure 9c

Figure 9d

Figure 10a

Figure 10b

Figure 10c

Figure 10d

Modes for Carrying Out the Invention

[0017] Hereinafter, some embodiments of this example will be described in detail with reference to exemplary drawings. When adding reference numerals to the components of each drawing, equal components can have equal numerals as much as possible even if they are shown on other drawings. Also, in describing this example, if it is determined that a specific description of a related known configuration or function may obscure the gist of this example, the detailed description thereof can be omitted. When terms such as "including", "having", and "being made" mentioned in this specification are used, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it can include the case of including a plurality unless there is a special explicit description.

[0018] Also, when describing the components of this example, terms such as first, second, A, B, (a), (b), etc. can be used. Such terms are only for distinguishing the component from other components, and the essence, order, sequence, or number of the corresponding component is not limited by such terms.

[0019] In the description of the positional relationship of components, when two or more components are described as "connected", "coupled", or "joined", etc., it should be understood that two or more components can be directly "connected", "coupled", or "joined", but it is also possible that different components are further "interposed" and then "connected", "coupled", or "joined". Here, other components can also be included in one or more of the two or more components that are "connected", "coupled", or "joined" to each other.

[0020] In the description of the time flow relationship related to components, operation methods, manufacturing methods, etc., for example, when the time sequence relationship or flow sequence relationship is described by "after ~", "subsequent to ~", "next to ~", "before ~", etc., it can include the case where it is not continuous as long as "immediately" or "directly" is not used.

[0021] On the one hand, when a numerical value for a component or its corresponding information (e.g., level, etc.) is mentioned, even without a separate explicit description, the numerical value or its corresponding information can be interpreted as including an error range that can be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0022] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] FIG. 1 is a plan view of a display device 100 according to an embodiment of the present specification.

[0024] Referring to FIG. 1, a display device 100 according to an embodiment of the present specification can include a display panel 110 for displaying an image and one or more optoelectronic devices 11, 12.

[0025] The display panel 110 can include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed.

[0026] A plurality of sub-pixels are arranged in the display area (DA), and various signal lines for driving the plurality of sub-pixels can be arranged.

[0027] The non-display area (NDA) may be an external area of the display area (DA).

[0028] Various signal lines can be arranged in the non-display area (NDA), and various drive circuits can be connected.

[0029] The non-display area (NDA) may be bent and not visible from the front, or may be hidden by a case (not shown).

[0030] The non-display area (NDA) is also referred to as a bezel or a bezel area.

[0031] Referring to FIG. 1, in the display device 100 according to the embodiments of the present specification, one or more optoelectronic devices 11, 12 are electronic components located under the display panel 110 (opposite the viewing surface).

[0032] Light can enter through the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to one or more optoelectronic devices 11, 12 located under the display panel 110 (opposite the viewing surface).

[0033] One or more optoelectronic devices 11, 12 may be devices that receive the light transmitted through the display panel 110 and perform functions determined by the received light.

[0034] For example, one or more optoelectronic devices 11, 12 may include one or more of imaging devices such as cameras (image sensors), proximity sensors, and sensing sensors such as illuminance sensors.

[0035] Here, the illuminance sensor may be an ambient light sensor, but is not limited thereto.

[0036] When the display device 100 is in the OFF state, the illuminance sensor can be used to sense the ambient light with respect to the display device 100, and the brightness of the screen output through the display panel 110 can also be adjusted according to the brightness of the ambient light.

[0037] Referring to FIG. 1, in the display device 100 according to the embodiments of the present specification, the display area (DA) may include a general area (NA) and one or more optical areas (OA1, OA2).

[0038] Referring to FIG. 1, one or more optical areas (OA1, OA2) may be areas that overlap with one or more optoelectronic devices 11, 12.

[0039] According to the example of FIG. 1, the display area (DA) may include a general area (NA), a first optical area (OA1), and a second optical area (OA2).

[0040] In the illustration of FIG. 1, a general area (NA) exists between the first optical area (OA1) and the second optical area (OA2).

[0041] Although FIG. 1 shows a structure in which the optical areas (OA1, OA2) are circular, the shape of the optical areas (OA1, OA2) according to the embodiments of this specification is not limited to this.

[0042] The first optical area (OA1) can have various patterns such as circular, oval, square, hexagonal or octagonal.

[0043] The second optical area (OA2) can have various patterns such as circular, oval, square, hexagonal or octagonal.

[0044] The first optical area (OA1) and the second optical area (OA2) can have the same pattern or other patterns.

[0045] Hereinafter, for the sake of convenience of explanation, an example will be given in which each of the first optical area (OA1) and the second optical area (OA2) is circular for explanation.

[0046] Here, at least a part of the first optical area (OA1) can be superimposed on the first optoelectronic device 11, and at least a part of the second optical area (OA2) can be superimposed on the second optoelectronic device 12.

[0047] One or more optical areas (OA1, OA2) must have both a video display structure and a light transmission structure formed.

[0048] That is, since one or more optical areas (OA1, OA2) are part of the display area (DA), sub-pixels for video display must be arranged in one or more optical areas (OA1, OA2).

[0049] One or more optical regions (OA1, OA2) must be formed with a light transmission structure for transmitting light to one or more optoelectronic devices 11, 12.

[0050] The one or more optoelectronic devices 11, 12 are devices that require light reception, but are located behind (below, on the opposite side of the viewing surface) the display panel 110 and are configured to receive light transmitted through the display panel 110.

[0051] The one or more optoelectronic devices 11, 12 are not exposed on the front surface (viewing surface) of the display panel 110.

[0052] Therefore, when the user views the front surface of the display panel 110, the optoelectronic devices 11, 12 are not visible to the user.

[0053] For example, the first optoelectronic device 11 can be a camera, and the second optoelectronic device 12 can be a sensing sensor such as a proximity sensor or an illuminance sensor.

[0054] For example, the sensing sensor can be an infrared sensor that senses infrared rays.

[0055] Conversely, the first optoelectronic device 11 can be a sensing sensor, and the second optoelectronic device 12 can be a camera.

[0056] Hereinafter, for the sake of convenience of explanation, an example will be given in which the first optoelectronic device 11 is a camera and the second optoelectronic device 12 is a sensing sensor.

[0057] Here, the camera can be a camera lens or an image sensor.

[0058] When the first optoelectronic device 11 is a camera, this camera is located behind (below) the display panel 110, but may be a front camera that captures the front direction of the display panel 110.

[0059] Therefore, the user can take pictures through a camera that is not visible on the viewing surface while looking at the viewing surface of the display panel 110.

[0060] The general area (NA) and the one or more optical areas (OA1, OA2) included in the display area (DA) are areas where video can be displayed. The general area (NA) is an area where a light transmission structure does not need to be formed, and the one or more optical areas (OA1, OA2) are areas where a light transmission structure must be formed.

[0061] Therefore, the one or more optical areas (OA1, OA2) must have a transmittance of a certain level or higher, and the general area (NA) can have no light transmittance or a low transmittance of less than a certain level.

[0062] For example, the one or more optical areas (OA1, OA2) and the general area (NA) may differ from each other in terms of resolution, sub-pixel arrangement structure, number of sub-pixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure.

[0063] For example, the number of sub-pixels per unit area in the one or more optical areas (OA1, OA2) may be smaller than the number of sub-pixels per unit area in the general area (NA).

[0064] That is, the resolution of the one or more optical areas (OA1, OA2) may be lower than the resolution of the general area (NA).

[0065] Here, the number of sub-pixels per unit area is a unit for measuring resolution and can also be referred to as PPI (Pixels Per Inch), which means the number of pixels within 1 inch.

[0066] For example, the number of sub-pixels per unit area in the first optical area (OA1) may be smaller than the number of sub-pixels per unit area in the general area (NA).

[0067] The number of sub-pixels per unit area in the second optical region (OA2) may be greater than or equal to the number of sub-pixels per unit area in the first optical region (OA1).

[0068] In the display device 100 according to the embodiments of this specification, when the first optoelectronic device 11 hidden at the lower part of the display panel 110 and not exposed to the outside is a camera, the display device 100 according to the embodiments of this specification can be referred to as a display to which UDC (Under Display Camera) technology is applied.

[0069] According to this, in the case of the display device 100 according to the embodiments of this specification, since a notch or a camera hole for camera exposure does not need to be formed in the display panel 110, a reduction in the area of the display area (DA) does not occur.

[0070] As a result, since a notch or a camera hole for camera exposure does not need to be formed in the display panel 110, the size of the bezel area may be reduced, and design constraints may disappear, increasing the degree of freedom in design.

[0071] In the display device 100 according to the embodiments of this specification, although one or more optoelectronic devices 11, 12 are hidden behind the display panel 110, one or more optoelectronic devices 11, 12 must receive light normally and perform their determined functions normally.

[0072] Also, in the display device 100 according to the embodiments of this specification, although one or more optoelectronic devices 11, 12 are hidden behind the display panel 110 and overlap with the display area (DA), normal video display must be possible in one or more optical regions (OA1, OA2) that overlap with one or more optoelectronic devices 11, 12 in the display area (DA).

[0073] FIG. 2 is a system configuration diagram of the display device 100 according to the embodiments of this specification.

[0074] Referring to FIG. 2, the display device 100 can include a display panel 110 and a display driving circuit as components for video display.

[0075] The display driving circuit can include a data driving circuit 220, a gate driving circuit 230, a display controller 240, etc. as a circuit for driving the display panel 110.

[0076] The display panel 110 can include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed.

[0077] The non-display area (NDA) can be an outer area of the display area (DA) and can also be referred to as a bezel area.

[0078] The whole or a part of the non-display area (NDA) can be an area visible on the front surface of the display device 100, or can be bent and not visible on the front surface of the display device 100.

[0079] The display panel 110 can include a substrate (SUB) and a plurality of sub-pixels (SP) arranged on the substrate (SUB).

[0080] Also, the display panel 110 can further include various types of signal lines for driving the plurality of sub-pixels (SP).

[0081] The display device 100 according to the embodiments of the present specification can be a liquid crystal display device, etc., or the display panel 110 can be a self-emitting display device that emits light by itself.

[0082] When the display device 100 according to the embodiments of the present specification is a self-emitting display device, each of the plurality of sub-pixels (SP) can include a light-emitting element.

[0083] In one example, the display device 100 according to the embodiments of the present specification can be an organic light emitting display device in which the light emitting element is embodied as an organic light emitting diode (OLED).

[0084] In another example, the display device 100 according to the embodiments of the present specification can be an inorganic light emitting display device in which the light emitting element is embodied as a light emitting diode on an inorganic substrate.

[0085] In still another example, the display device 100 according to the embodiments of the present specification can be a quantum dot display device in which the light emitting element is embodied as a quantum dot which is a semiconductor crystal that emits light by itself.

[0086] The structure of each of the plurality of sub-pixels (SP) may vary depending on the type of the display device 100.

[0087] For example, when the display device 100 is a self-emitting type display device in which the sub-pixel (SP) emits light by itself, each sub-pixel (SP) may include a light emitting element that emits light by itself, one or more transistors, and one or more capacitors.

[0088] For example, various types of signal lines may include a plurality of data lines (DL) that transmit data signals (also referred to as data voltages or video signals) and a plurality of gate lines (GL) that transmit gate signals (also referred to as scan signals).

[0089] The plurality of data lines (DL) and the plurality of gate lines (GL) can intersect each other.

[0090] Each of the plurality of data lines (DL) can be arranged while extending in a first direction.

[0091] Each of the plurality of gate lines (GL) can be arranged while extending in a second direction.

[0092] Here, the first direction may be the column direction, and the second direction may be the row direction.

[0093] Alternatively, the first direction may be the row direction, and the second direction may be the column direction.

[0094] The data driving circuit 220 is a circuit for driving a plurality of data lines (DL), and can output data signals to the plurality of data lines (DL).

[0095] The gate driving circuit 230 is a circuit for driving a plurality of gate lines (GL), and can output gate signals to the plurality of gate lines (GL).

[0096] The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing for the plurality of data lines (DL) and the driving timing for the plurality of gate lines (GL).

[0097] The display controller 240 can supply a data driving control signal (DCS) for controlling the data driving circuit 220 to the data driving circuit 220, and supply a gate driving control signal (GCS) for controlling the gate driving circuit 230 to the gate driving circuit 230.

[0098] The display controller 240 can receive input video data from the host system 250, and supply video data (Data) to the data driving circuit 220 based on the input video data.

[0099] The data driving circuit 220 can supply data signals to the plurality of data lines (DL) under the driving timing control of the display controller 240.

[0100] The data driving circuit 220 can receive video data (Data) in digital form from the display controller 240, convert the received video data (Data) into an analog data signal, and output it to a plurality of data lines (DL).

[0101] The gate driving circuit 230 can supply a gate signal to a plurality of gate lines (GL) under the timing control of the display controller 240.

[0102] The gate driving circuit 230 receives the supply of a first gate voltage corresponding to the turn-on level voltage and a second gate voltage corresponding to the turn-off level voltage together with various gate driving control signals (GCS), generates a gate signal, and can supply the generated gate signal to a plurality of gate lines (GL).

[0103] For example, the data driving circuit 220 can be connected to the display panel 110 in a tape automated bonding (TAB) method, or connected to the bonding pads of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or implemented in a chip on film (COF) method and connected to the display panel 110.

[0104] The gate driving circuit 230 can be connected to the display panel 110 in a tape automated bonding (TAB) method, or connected to the bonding pads of the display panel 110 in a chip on glass (COG) or chip on panel (COP) method, or connected to the display panel 110 according to the chip on film (COF) method.

[0105] Alternatively, the gate driving circuit 230 can be formed in a non-display area (NDA) of the display panel 110 in a gate in panel (GIP) type.

[0106] The gate driving circuit 230 can be disposed on the substrate or can be connected to the substrate.

[0107] That is, in the case of the GIP type, the gate driving circuit 230 can be disposed in the non-display area (NDA) of the substrate.

[0108] The gate driving circuit 230 can be connected to the substrate in the case of the chip-on-glass (COG) type, the chip-on-film (COF) type, etc.

[0109] On the other hand, at least one of the data driving circuit 220 and the gate driving circuit 230 can also be disposed in the display area (DA) of the display panel 110.

[0110] For example, at least one of the data driving circuit 220 and the gate driving circuit 230 can be disposed so as not to overlap with the sub-pixel (SP), and can also be disposed so as to partially or entirely overlap with the sub-pixel (SP).

[0111] The data driving circuit 220 can also be connected to one side (for example, the upper side or the lower side) of the display panel 110.

[0112] Depending on the driving method and the panel design method, the data driving circuit 220 can be all connected to both sides (for example, the upper side and the lower side) of the display panel 110, or can also be connected to two or more sides among the four sides of the display panel 110.

[0113] The gate driving circuit 230 can also be connected to one side (for example, the left side or the right side) of the display panel 110.

[0114] Depending on the driving method, the panel design method, etc., the gate driving circuit 230 can be all connected to both sides (for example, the left side and the right side) of the display panel 110, or can also be connected to two or more sides among the four sides of the display panel 110.

[0115] The display controller 240 can be implemented as a separate component from the data driving circuit 220, or can be integrated with the data driving circuit 220 and implemented as an integrated circuit.

[0116] The display controller 240 can be a timing controller commonly used in display technology, or a control device that includes a timing controller and can further perform other control functions, or can be both a timing controller and other control devices, or can be a circuit within the control device.

[0117] The display controller 240 can be implemented with various circuits and electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or a processor.

[0118] The display controller 240 is mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data driving circuit 220 and the gate driving circuit 230 through a printed circuit board, a flexible printed circuit, etc.

[0119] The display controller 240 can transmit and receive signals with the data driving circuit 220 through one or more predetermined interfaces.

[0120] For example, the interface can include an LVDS (Low Voltage Differential Signaling) interface, an EPI interface, an SP (Serial Peripheral) interface, etc.

[0121] The display device 100 according to the embodiments of this specification can further provide a touch sensing function in addition to the video display function, and thus can include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch is generated by a touch object such as a finger or a pen, or to detect a touch position.

[0122] The touch sensing circuit can include a touch driving circuit 260 that drives and senses the touch sensor to generate and output touch sensing data, and a touch controller 270 that can utilize the touch sensing data to sense touch generation or detect a touch position.

[0123] The touch sensor can include a plurality of touch electrodes.

[0124] The touch sensor can further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit 260.

[0125] The touch sensor can exist in the form of a touch panel outside the display panel 110 or inside the display panel 110.

[0126] When the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor is referred to as an external type.

[0127] When the touch sensor is of the external type, the touch panel and the display panel 110 can be separately manufactured and combined in the assembly process.

[0128] The external type touch panel can include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0129] When the touch sensor exists inside the display panel 110, the touch sensor can be formed on the substrate (SUB) together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0130] The touch driving circuit 260 can supply a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0131] The touch sensing circuit can perform touch sensing in a self - capacitance sensing method or a mutual - capacitance sensing method.

[0132] When the touch sensing circuit performs touch sensing in the self - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.).

[0133] According to the self - capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode.

[0134] The touch driving circuit 260 can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0135] When the touch sensing circuit performs touch sensing in the mutual - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0136] According to the mutual - capacitance sensing method, the plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes.

[0137] The touch driving circuit 260 can drive the driving touch electrodes to sense the sensing touch electrodes.

[0138] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit can be implemented as separate devices or as a single device.

[0139] Also, the touch driving circuit 260 and the data driving circuit 220 can be implemented as separate devices or as a single device.

[0140] The display device 100 can further include a power supply circuit that supplies various power supplies to the display driving circuit and / or the touch sensing circuit.

[0141] The display device 100 according to the embodiments of the present specification can be a mobile terminal such as a smartphone or a tablet, or can be a monitor or a television (TV) of various sizes, and is not limited thereto, and can be a display of various types and sizes capable of presenting information and images.

[0142] As described above, in the display panel 110, the display area (DA) can include a general area (NA) and one or more optical areas (OA1, OA2).

[0143] The general area (NA) and one or more optical areas (OA1, OA2) are areas where video display is possible.

[0144] However, the general area (NA) is an area where a light transmission structure does not need to be formed, and one or more optical areas (OA1, OA2) are areas where a light transmission structure must be formed.

[0145] As described above, in the display panel 110, the display area (DA) can include one or more optical areas (OA1, OA2) together with the general area (NA). For the sake of convenience of explanation, a case where the display area (DA) includes all of the first optical area (OA1) and the second optical area (OA2) will be taken as an example for explanation.

[0146] Figure 3 is an equivalent circuit of a sub-pixel (SP) in the display panel 110 according to an embodiment of the present specification.

[0147] Each of the sub-pixels (SP) arranged in the general area (NA), the first optical area (OA1), and the second optical area (OA2) included in the display area (DA) of the display panel 110 can include a light-emitting element (ED), a driving transistor (DRT) for driving the light-emitting element (ED), a scan transistor (SCT) for transmitting a data voltage (Vdata) to the first node (N1) of the driving transistor (DRT), a storage capacitor (Cst) for maintaining a constant voltage during one frame, and the like.

[0148] The driving transistor (DRT) can include a first node (N1) to which a data voltage can be applied, a second node (N2) electrically connected to the light-emitting element (ED), and a third node (N3) to which a driving voltage (ELVDD) is applied from a driving voltage line (DVL).

[0149] In the driving transistor (DRT), the first node (N1) can be a gate node, the second node (N2) can be a source node or a drain node, and the third node (N3) can be a drain node or a source node.

[0150] The light-emitting element (ED) can include a first electrode layer (AE), a light-emitting layer (EL), and a second electrode layer (CE).

[0151] The first electrode layer (AE) can be a pixel electrode disposed in each sub-pixel (SP), and can be electrically connected to the second node (N2) of the driving transistor (DRT) of each sub-pixel (SP).

[0152] The second electrode layer (CE) can be a common electrode commonly disposed in a plurality of sub-pixels (SP), and a base voltage (ELVSS) can be applied thereto.

[0153] For example, the first electrode layer (AE) can be a pixel electrode, and the second electrode layer (CE) can be a common electrode.

[0154] Conversely, the first electrode layer (AE) can be a common electrode, and the second electrode layer (CE) can be a pixel electrode.

[0155] Hereinafter, for the sake of convenience of explanation, it is assumed that the first electrode layer (AE) is a pixel electrode and the second electrode layer (CE) is a common electrode.

[0156] The light-emitting element (ED) can be an organic light-emitting diode (OLED; Organic Light Emitting Diode), an inorganic light-emitting diode, or a quantum dot (QD; Quantum Dot) light-emitting element, etc.

[0157] In this case, when the light-emitting element (ED) is an organic light-emitting diode, the light-emitting layer (EL) in the light-emitting element (ED) can include an organic light-emitting layer containing an organic substance.

[0158] The scan transistor (SCT) is turned on and off by a scan signal (SCAN) which is a gate signal applied through a gate line (GL), and can be electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL).

[0159] The storage capacitor (Cst) can be electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT).

[0160] Each subpixel (SP) can have a 2T (Transistor) 1C (Capacitor) structure including two transistors (DRT, SCT) and one capacitor (Cst) as shown in FIG. 3, and optionally can further include one or more transistors or one or more capacitors.

[0161] The storage capacitor (Cst) is not a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor existing between the first node (N1) and the second node (N2) of the driving transistor (DRT), but can be an externally designed external capacitor outside the driving transistor (DRT).

[0162] Each of the driving transistor (DRT) and the scan transistor (SCT) can be an n-type transistor or a p-type transistor.

[0163] Also, each of the driving transistor (DRT) and the scan transistor (SCT) can be composed of low-temperature polycrystalline silicon transistors.

[0164] However, it is not limited to this and at least one can be composed of oxide thin film transistors.

[0165] Since the circuit elements (especially the light-emitting element (ED)) in each subpixel (SP) are vulnerable to external moisture, oxygen, etc., a sealing layer (ENCAP) for preventing external moisture and oxygen from penetrating into the circuit elements (especially the light-emitting element (ED)) can be arranged in a form covering the light-emitting element (ED).

[0166] FIG. 4 is an arrangement diagram of sub-pixels (SP) in three regions (NA, OA1, OA2) included in the display region of the display device 100 according to an embodiment of the present specification.

[0167] Referring to FIG. 4, a plurality of sub-pixels (SP) can be arranged in each of the general region (NA), the first optical region (OA1), and the second optical region (OA2) included in the display region (DA).

[0168] For example, the plurality of sub-pixels (SP) can include a red sub-pixel (Red SP) that emits red light, a green sub-pixel (Green SP) that emits green light, and a blue sub-pixel (Blue SP) that emits blue light.

[0169] Accordingly, each of the general region (NA), the first optical region (OA1), and the second optical region (OA2) can include a light-emitting region (EA) of the red sub-pixel (Red SP), a light-emitting region (EA) of the green sub-pixel (Green SP), and a light-emitting region (EA) of the blue sub-pixel (Blue SP).

[0170] Referring to FIG. 4, the general region (NA) can include a light-emitting region (EA) without including a light-transmitting structure.

[0171] At this time, the first optical region (OA1) and the second optical region (OA2) must not only include the light-emitting region (EA), but also include a light-transmitting structure.

[0172] Therefore, the first optical region (OA1) can include the light-emitting region (EA) and the first transmission region (TA1), and the second optical region (OA2) can include the light-emitting region (EA) and the second transmission region (TA2).

[0173] The light-emitting region (EA) and the transmission regions (TA1, TA2) can be distinguished by how light-transmissive they are.

[0174] That is, the light-emitting region (EA) can be a region where light transmission is impossible, and the transmission regions (TA1, TA2) can be regions where light transmission is possible.

[0175] Also, the light-emitting region (EA) and the transmission regions (TA1, TA2) can be distinguished by the presence or absence of the formation of the second electrode layer (CE).

[0176] For example, the second electrode layer (CE) may be formed in the light-emitting region (EA), and the second electrode layer (CE) may not be formed in the transmission regions (TA1, TA2).

[0177] On the other hand, a light-shielding layer (LSL; Light Shield Layer) may be formed in the light-emitting region (EA), and the light-shielding layer may not be formed in the transmission regions (TA1, TA2).

[0178] Since the first optical region (OA1) includes the first transmission region (TA1) and the second optical region (OA2) includes the second transmission region (TA2), all of the first optical region (OA1) and the second optical region (OA2) are regions where light can transmit.

[0179] The transmittance (degree of transmission) of the first optical region (OA1) and the transmittance (degree of transmission) of the second optical region (OA2) may be substantially equal.

[0180] In this specification, being substantially equal means being equal considering minute differences due to process errors.

[0181] In this case, the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) may be substantially equal in pattern or size.

[0182] Alternatively, even if the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) differ in pattern or size, the ratio of the first transmission region (TA1) within the first optical region (OA1) and the ratio of the second transmission region (TA2) within the second optical region (OA2) may be substantially equal.

[0183] However, it is not limited to this, and the transmittance (degree of transmission) of the first optical region (OA1) and the transmittance (degree of transmission) of the second optical region (OA2) may be different from each other.

[0184] In this case, the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) may differ in pattern or size.

[0185] Alternatively, even if the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) are substantially the same in pattern and size, the ratio of the first transmission region (TA1) within the first optical region (OA1) and the ratio of the second transmission region (TA2) within the second optical region (OA2) may be different from each other.

[0186] For example, when the first optoelectronic device 11 over which the first optical region (OA1) is superimposed is a camera and the second optoelectronic device 12 over which the second optical region (OA2) is superimposed is a sensing sensor, the camera may require a larger amount of light than the sensing sensor.

[0187] Therefore, the transmittance (degree of transmission) of the first optical region (OA1) may be higher than the transmittance (degree of transmission) of the second optical region (OA2).

[0188] In this case, the first transmission region (TA1) of the first optical region (OA1) can have a larger area than the second transmission region (TA2) of the second optical region (OA2).

[0189] Alternatively, even if the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) are substantially the same in size, the ratio of the first transmission region (TA1) within the first optical region (OA1) may be larger than the ratio of the second transmission region (TA2) within the second optical region (OA2).

[0190] On the other hand, as shown in FIG. 4, the first transmission region (TA1) of the first optical region (OA1) can be circular in cross-section, but the cross-sectional structure of the first transmission region (TA1) in the embodiments of this specification is not limited thereto.

[0191] In one example, the shape of the first transmission region (TA1) of the first optical region (OA1) may be octagonal on a plane, and in other examples, it may be elliptical or polygonal.

[0192] In this way, while changing the shape of the first transmission region (TA1) to adjust the transmittance of the first transmission region (TA1), the area of the light-emitting region of the first optical region (OA1) can be adjusted.

[0193] Hereinafter, for the sake of convenience of explanation, a case where the transmittance (degree of transmission) of the first optical region (OA1) is higher than the transmittance (degree of transmission) of the second optical region (OA2) will be taken as an example for explanation.

[0194] Also, as shown in FIG. 4, in the embodiments of this specification, the transmission regions (TA1, TA2) can also be referred to as transparent regions, and the transmittance can also be referred to as transparency.

[0195] Also, as shown in FIG. 4, assume a case where in the embodiments of this specification, the first optical region (OA1) and the second optical region (OA2) are located at the upper end of the display region (DA) of the display panel 110 and are arranged side by side left and right.

[0196] Referring to FIG. 4, the horizontal display area where the first optical region (OA1) and the second optical region (OA2) are arranged is referred to as the first horizontal display area (HA1), and the second horizontal display area (HA2) where the first optical region (OA1) and the second optical region (OA2) are not arranged is referred to.

[0197] Referring to FIG. 4, the first horizontal display area (HA1) can include the general area (NA), the first optical region (OA1), and the second optical region (OA2).

[0198] The second horizontal display area (HA2) can include only the general area (NA).

[0199] FIGS. 5 and 6 are cross-sectional views of the light-emitting element (ED) included in the display device 100 according to the embodiments of the present specification.

[0200] Referring to FIG. 5, the light-emitting element (ED) according to an embodiment includes a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B) that emit different hues from each other on the substrate 10.

[0201] The light-emitting element (ED) can include a first electrode layer 51 disposed on the substrate 10, a second electrode layer 58 disposed to face the first electrode layer 51, and a light-emitting layer 55 formed between the first electrode layer 51 and the second electrode layer 58.

[0202] The first electrode layer 51 may be an anode (positive electrode), and the second electrode layer 58 may be a cathode (negative electrode), but the embodiments of the present invention are not limited thereto.

[0203] For example, in the case of an inverter type, the first electrode layer 51 can be a cathode, and the second electrode layer 58 can be an anode.

[0204] However, in the embodiments described below, the description will be centered on the configuration in which the first electrode layer 51 of the light-emitting element (ED) is an anode (positive electrode) and the second electrode layer 58 is a cathode (negative electrode).

[0205] The first electrode layer 51 can be electrically connected through a contact hole formed in an insulating film with either one of the source and drain of a transistor including a source, a drain, a gate, an active layer, etc.

[0206] The first electrode layer 51 can be made of a material with a relatively high work function.

[0207] The first electrode layer 51 is an example, and can be made of a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), AZO (Al-doped zinc oxide), In2O3 (indium oxide), or SnO2 (tin oxide), but is not limited thereto.

[0208] For the second electrode layer 58, a metal, an alloy, an electrically conductive compound, or a mixture of two or more thereof having a relatively low work function can be used.

[0209] As an example, lithium (Li), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), etc. can be formed into a thin film to obtain a transmissive electrode.

[0210] On the other hand, in the embodiments of the present invention, it can be variously modified, such as forming a transmissive electrode using ITO or IZO to obtain a top emitting device.

[0211] On the second electrode layer 58, a capping layer (not shown) can be included to improve optical characteristics and maximize luminous efficiency.

[0212] As an example, it can be made of a metal oxide layer, a metal nitride layer, or a metal oxynitride layer.

[0213] For example, it can be made of MoOx (x = 2 to 4), Al2O3, Sb2O3, BaO, CdO, CaO, Ce2O3, CoO, Cu2O, DyO, GdO, HfO2, La2O3, Li2O, MgO, NbO, NiO, Nd2O3, PdO, Sm2O3, ScO, SiO2, SrO, TA2O3, TiO, WO3, VO2, YbO, Y2O3, ZnO, ZrO, AlN, BN, NbN, SiN, TAN, TiN, VN, YbN, ZrN, SiON, AlON or a mixture thereof, but is not limited thereto.

[0214] The light-emitting layer 55 can include a red light-emitting layer 55R disposed in the red sub-pixel (R), a green light-emitting layer 55G disposed in the green sub-pixel (G), and a blue light-emitting layer 55B disposed in the blue sub-pixel (B).

[0215] At this time, the wavelength of the emitted light is large in the order of the red light-emitting layer 55R, the green light-emitting layer 55G, and the blue light-emitting layer 55B.

[0216] The red light-emitting layer 55R can include a red host and a red dopant.

[0217] As the red host, Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more thereof can be used, but is not limited thereto.

[0218] As the red dopant, a compound containing PtOEP, Ir(piq)3, Btp2Ir(acac), Ir(2-phq)2(acac), Ir(2-phq)3, Ir(flq)2(acac), Ir(fliq)2(acac), DCM, or DCJTB can be used, but is not limited thereto.

[0219] The green light-emitting layer 55G can include a green host and a green dopant.

[0220] The green host can use, but is not limited to, Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more thereof.

[0221] The green dopant can utilize, but is not limited to, Ir(ppy)3 tris(2-phenylpyridine)iridium, Ir(ppy)2(acac) (Bis(2-phenylpyridine)(Acetylacetonato)iridium(III), Ir(mppy)3 (tris(2-(4-tolyl)phenylpiridine)iridium, C545T 10-(2benzothiazolyl)-1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-[1]benzopyrano[6,7,8-ij]-quinolizin11-one, etc.

[0222] The blue light-emitting layer 55B can include a blue host and a blue dopant.

[0223] The blue host can use, but is not limited to, Alq3, CBP(4,4'-N,N'-dicabazole-biphenyl), PVK(poly(n-vinylcabazole)), ADN(9,10-di(naphthalene-2-yl)anthracene), TCTA, TPBI 1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene), TBADN(3-tert-butyl-9,10-di(naphth-2-yl)anthracene), E3, DSA(distyrylarylene), or a mixture of two or more thereof.

[0224] As the blue dopant, compounds such as F2Irpic, (F2ppy)2Ir(tmd), Ir(dfppz)3, ter-fluorene, DPAVBi (4,4'-bis(4-diphenylaminostyryl)biphenyl), and TBPe can be used, but it is not limited thereto.

[0225] The light-emitting device (ED) can include a hole transport layer 53 disposed between the first electrode layer 51 and the light-emitting layer 55.

[0226] The hole transport layer 53 can include a common hole transport layer 53C disposed on the hole injection layer 52.

[0227] The hole transport layer 53 can include a light-emission assisting layer disposed between the hole transport layer 53 and the common hole transport layer 53C.

[0228] The light-emission assisting layer can include a red light-emission assisting layer 53R, a green light-emission assisting layer 53G, and a blue light-emission assisting layer (not shown) disposed on the common hole transport layer 53C.

[0229] The light-emission assisting layer is an example and can play a hole transport role and can be made of a hole transport material. Each of the light-emission assisting layers can be made of the same substance or compound as each other or can be made of different substances or compounds from each other.

[0230] As an example, the hole transport layer 53, the common hole transport layer 53C, the red light-emission assisting layer 53R, the green light-emission assisting layer 53G, and the blue light-emission assisting layer (not shown) can include substances containing a tertiary amine or a tertiary amine containing fluorine, but it is not limited thereto.

[0231] The light-emitting device (ED) can include a hole injection layer 52 disposed on the first electrode layer 51, a hole transport layer 53 disposed on the hole injection layer 52, a light-emitting layer 55 disposed on the hole transport layer 53, and an electron transport layer 57 disposed on the light-emitting layer 55, but it is not limited thereto.

[0232] When a voltage is applied to the first electrode layer 51 and the second electrode layer 58 of the light-emitting device (ED), holes that have passed through the hole transport layer 53 and electrons that have passed through the electron transport layer 57 move to the light-emitting layer 55 to form excitons, and visible light can be emitted from the light-emitting layer 55.

[0233] The light-emitting device (ED) can include an electron blocking layer 54 between the hole transport layer 53 and the light-emitting layer 55.

[0234] However, it is not necessarily limited to this, and the light-emitting device (ED) may not include the electron blocking layer 54.

[0235] The electron blocking layer 54 can include at least one of Tris(phenylpyrazole)iridium, BPAPF(9,9-bis[04-(N,N-bis-biphenyl-4-ylamino)phenyl]-9H-fluorene), Bis[04-(p,p-dITOlylamino)phenyl]diphenylsilane, NPD(4,4'-bis[0N-1-napthyl)-N-phenyl-amino]biphenyl), mCP(N,N'-dicarbazolyl-3,5-benzene), MPMP(bis[04-(N,N-diethylamino)-2-methylphenyl](4-methylphenyl)methane) or a combination thereof, and is not limited thereto.

[0236] In addition, the electron blocking layer 54 can include an inorganic compound. In one example, the electron blocking layer 144 can include at least one of halide compounds such as LiF, NaF, KF, RbF, CsF, FrF, MgF2, CaF2, SrF2, BaF2, LiCl, NaCl, KCl, RbCl, CsCl, FrCl and oxides such as Li2O, Li2O2, Na2O, K2O, Rb2O, Rb2O2, Cs2O, Cs2O2, LiAlO2, LiBO2, LiTaO3, LiNbO3, LiWO4, Li2CO, NaWO4, KAlO2, K2SiO3, B2O5, Al2O3, SiO2 or a combination thereof, but is not limited thereto.

[0237] The electron blocking layer 54 serves as a buffer layer that blocks the direct contact between the hole transport layer 53 and the light emitting layer 55, and can prevent electrons from easily flowing into the hole transport layer 53.

[0238] That is, the electron blocking layer 54 can adjust the injection, movement, and combination with holes of electrons to improve the efficiency and lifespan of the light emitting device 50.

[0239] The electron transport layer 57 can be disposed on the light emitting layer 55.

[0240] The electron transport layer 57 can adjust the movement speed of electrons so that electrons and holes meet in the light emitting layer 55 to emit light.

[0241] The electron transport layer 57 can contain a material with an electron movement speed several times greater than that of other substances.

[0242] The electron transport layer 57 is an example, and can include at least one of Alq3 (tris(8-hydroxyquinolino)aluminum), PBD, TAZ, spiro-PBD, BAlq, and SAlq, or a combination thereof, but is not limited thereto.

[0243] An electron injection layer (not shown) can be disposed on the electron transport layer 57.

[0244] The electron injection layer (not shown) can transfer the electrons flowing in from the second electrode layer 58 to the electron transport layer 57.

[0245] The light emitting device (ED) can include a hole blocking layer 56 between the light emitting layer 55 and the electron transport layer 57.

[0246] However, it is not necessarily limited thereto, and the light emitting device (ED) may not include the hole blocking layer 56.

[0247] The hole blocking layer 56 serves as a buffer layer that blocks the direct contact between the electron transport layer 57 and the light-emitting layer 55, and can prevent holes from easily flowing into the hole electron transport layer 57.

[0248] The hole blocking layer 56 can adjust the injection, movement of holes, and the combination with electrons to improve the efficiency and lifespan of the light-emitting device (ED).

[0249] As described above, with reference to FIG. 5, the case where the light-emitting device has a single stack structure has been described by way of example.

[0250] Hereinafter, with reference to FIG. 6, the case where the light-emitting device (ED) has a multi-stack structure will be described by way of example.

[0251] Referring to FIG. 6, the light-emitting device (ED) can have a multi-stack structure including a first stack light-emitting layer 651 and a second stack light-emitting layer 652. Each of the light-emitting devices (ED) can include a first electrode layer 61 disposed on the substrate 10, a hole injection layer 62 on the first electrode layer 61, and a second electrode layer 68 disposed on the side opposite to the first electrode layer 61.

[0252] Here, the first stack light-emitting layer 651 and the second stack light-emitting layer 652 can include light-emitting materials of the same hue.

[0253] Referring to FIG. 6, the light-emitting device (ED) can be composed of a first stack structure including the first stack light-emitting layer 651 and a second stack structure including the second stack light-emitting layer 652.

[0254] The matters regarding the first hole transport layers 631, 631C, 6331G, and 631R included in the first stack structure, the first electron blocking layer 641, the first stack light-emitting layers 651, 651R, 651G, and 651B included, and the first hole blocking layer 661 and the first electron transport layer 671 may be substantially equal to the matters regarding the hole transport layer 53, the electron blocking layer 54, the light-emitting layer 55, the hole blocking layer 56, and the electron transport layer 57 described in FIG. 5.

[0255] In the case of the second stack structure, a charge generation layer 69, second hole transport layers 632, 632R, 632G, and 632B are included between the second electrode layer 68 and the first electron transport layer 671), a second electron blocking layer 642, second stack light emitting layers 652, 652R, 652G, and 652B are included), and a second hole blocking layer 662 and a second electron transport layer 672 can be arranged.

[0256] Specifically, the charge generation layer 69 is located on the first electron transport layer 671, the second hole transport layer 632 is located on the charge generation layer 69, the second electron blocking layer 642 is located on the second hole transport layer 632, the second stack light emitting layer 652 is located on the second electron blocking layer 642, the second hole blocking layer 662 is located on the second stack light emitting layer 652, and the second electron transport layer 672 can be arranged on the second hole blocking layer 662.

[0257] The second electron transport layer 672 is arranged to be in contact with the second stack light emitting layer 652 and can transfer electrons to the second stack light emitting layer 652 side.

[0258] The charge generation layer 69 is arranged between the first electron transport layer 671 and the second hole transport layer 632 and can transfer electrons to the first electron transport layer 671.

[0259] The first hole transport layer 671 is arranged to be in contact with the first stack light emitting layer 651 and can transfer holes to the first stack light emitting layer 651 side.

[0260] In FIG. 6, a light emitting element having a two-stack structure is taken as an example for explanation, but the present disclosure is not limited thereto, and the embodiments of the present disclosure can be equally applied to multi-stack structures such as three-stack and four-stack.

[0261] FIGS. 7a and 7b are cross-sectional views of light emitting elements (ED) located in the general area (NA) and the optical area (OA) of a display device according to an embodiment of the present specification.

[0262] Figures 7a and 7b illustrate a light-emitting element having a single stack structure for convenience of explanation, but the present invention is not limited thereto and can be equally applied to a case of a multiple stack structure.

[0263] In addition, for convenience of explanation, in FIGS. 7a and 7b, a part of the material constituting the light-emitting layer 75 can be shown in a particulate form. For example, a first host (H1) and a second host (H2) which are part of the material constituting the light-emitting layer 75 can be shown in a particulate form.

[0264] Referring to FIG. 7a, matters regarding the first electrode layer 71, hole injection layer 72, common hole transport layer 73C, hole transport layer 73, electron blocking layer 74, light-emitting layer 75, hole blocking layer 76, electron transport layer 77, and second electrode layer 78 in the general region (NA) and the optical region (OA) may be substantially the same as those regarding the first electrode layer 51, hole injection layer 52, common hole transport layer 53C, hole transport layer 53, electron blocking layer 54, light-emitting layer 55, hole blocking layer 56, electron transport layer 57, and second electrode layer 58 described in FIG. 5.

[0265] Referring to FIG. 7a, the light-emitting layer 75 in the general region (NA) and the optical region (OA) may include a first light-emitting layer 751 and a second light-emitting layer 752.

[0266] The first light-emitting layer 751 may be located on the electron blocking layer 74, and the second light-emitting layer 752 may be located on the first light-emitting layer 751.

[0267] At this time, in the case of the general region (NA), the first light-emitting layer 751 and the second light-emitting layer 752 may include the first host (H1).

[0268] In the general region (NA), the first light-emitting layer 751 and the second light-emitting layer 752 are shown as being separated by layers, but the present invention is not limited thereto. When the first light-emitting layer 751 and the second light-emitting layer 752 are made of the same material including the first host (H1), the first light-emitting layer 751 and the second light-emitting layer 752 can also be regarded as one layer.

[0269] In the case of the optical region (OA), the first light-emitting layer 751 may include a first host (H1), and the second light-emitting layer 752 may include a second host (H2).

[0270] At this time, the second host (H2) may be different from the first host (H1).

[0271] In FIG. 7a, the number of particles of the first host (H1) and the second host (H2) illustrated in the general region (NA) and the optical region (OA) is merely exemplary for the convenience of explanation, and is not limited thereto. The amount of particles may vary due to process errors.

[0272] On the other hand, in the case of the general region (NA), the first light-emitting layer 751 and the second light-emitting layer 752 may include the same type of dopant.

[0273] Also, in the case of the optical region (OA), the first light-emitting layer 751 may include a first dopant (not shown), and the second light-emitting layer 752 may include a second dopant (not shown). Referring to FIG. 7a, the thickness of the first light-emitting layer 751 in the optical region (OA) is greater than the thickness of the first light-emitting layer 751 in the general region (NA), and the thickness of the second light-emitting layer 752 in the optical region (OA) is greater than the thickness of the second light-emitting layer 752 in the general region (NA). Thus, the emitting area and efficiency increase.

[0274] At this time, the second dopant and the first dopant may be different.

[0275] However, it is not limited thereto, and in the case of the optical region (OA), the first light-emitting layer 751 and the second light-emitting layer 752 may also include the same type of dopant.

[0276] Different from the general region (NA), by adjusting the types and amounts of the host and dopant in the first light-emitting layer 751 and the second light-emitting layer 752 in the optical region (OA), the lifetime of the light-emitting element (ED) disposed in the optical region (OA) can be increased.

[0277] Referring to FIG. 7a, by increasing the number of light-emitting layers, the light-emitting layer 75 can be divided into a first light-emitting layer 751 and a second light-emitting layer 752, and the thicknesses (B1, B2) of the light-emitting layer 75 can be increased.

[0278] Thus, in order to compensate for the increased thicknesses (B1, B2) of the light-emitting layer 75, the thicknesses (A1, A2) of the hole transport layer 73 or the common hole transport layer 73C can be adjusted. The combination of the hole transport layer 73 and the common hole transport layer 73C can also be referred to as the hole transport layer 73. Also, the common hole transport layer 73C can be omitted.

[0279] Referring to FIG. 7a, in order to compensate for the fact that the thickness (B2) of the light-emitting layer 75 in the optical region (OA) is increased compared to the thickness (B1) of the light-emitting layer 75 in the general region (NA), the thicknesses (A2) of the hole transport layer 73 and the common hole transport layer 73C in the optical region (OA) can be decreased compared to the thicknesses (A1) of the hole transport layer 73 and the common hole transport layer 73C in the general region (NA).

[0280] Desirably, the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, and the second light-emitting layer 752 in the general region (NA) may be equal to the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, and the second light-emitting layer 752 in the optical region (OA).

[0281] On the other hand, for the first light-emitting layer 751 and the second light-emitting layer 752 of the light-emitting element (ED), a phosphorescent host and a phosphorescent dopant, or a fluorescent host and a fluorescent dopant can be used depending on the application.

[0282] Above, the case where the light-emitting layer 75 has two layers has been described with reference to FIG. 7a as an example.

[0283] Hereinafter, the case where the light-emitting layer 75 has three layers will be described with reference to FIG. 7b as an example.

[0284] Referring to Fig. 7b, matters regarding the first electrode layer 71, hole injection layer 72, common hole transport layer 73C, hole transport layer 73, electron blocking layer 74, light-emitting layer 75, hole blocking layer 76, electron transport layer 77, and second electrode layer 78 in the general region (NA) and the optical region (OA) may be substantially equal to those regarding the first electrode layer 51, hole injection layer 52, common hole transport layer 53C, hole transport layer 53, electron blocking layer 54, light-emitting layer 55, hole blocking layer 56, electron transport layer 57, and second electrode layer 58 described in Fig. 5.

[0285] Referring to Fig. 7b, the light-emitting layer 75 in the general region (NA) and the optical region (OA) may include a first light-emitting layer 751, a second light-emitting layer 752, and a third light-emitting layer 753.

[0286] The first light-emitting layer 751 may be located on the electron blocking layer 74, the second light-emitting layer 752 may be located on the first light-emitting layer 751, and the third light-emitting layer 753 may be located on the second light-emitting layer 752.

[0287] At this time, in the case of the general region (NA), the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 may include a first host (H1).

[0288] In the general region (NA), the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 are shown as being divided into layers, but it is not limited thereto. When the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 include the first host (H1) and are composed of the same substance, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 may also be regarded as one layer.

[0289] In the case of the optical region (OA), the first light-emitting layer 751 and the third light-emitting layer 753 may include the first host (H1), and the second light-emitting layer 752 may include a second host (H2).

[0290] At this time, the second host (H2) may be different from the first host (H1).

[0291] In FIG. 7b, the number of particles of the first host (H1) and the second host (H2) illustrated in the general region (NA) and the optical region (OA) is merely exemplary for convenience of explanation, and is not limited thereto. The amount of particles may vary due to process errors.

[0292] On the other hand, in the case of the general region (NA), the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 can contain the same type of dopant.

[0293] Also, in the case of the optical region (OA), the first light-emitting layer 751 and the third light-emitting layer 753 can contain a first dopant, and the second light-emitting layer 752 can contain a second dopant.

[0294] At this time, the second dopant and the first dopant may be different.

[0295] However, without being limited thereto, in the case of the optical region (OA), the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 can also contain the same type of dopant.

[0296] Different from the general region (NA), by adjusting the types and amounts of the host and the dopant in the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the optical region (OA), the lifetime of the light-emitting element (ED) disposed in the optical region (OA) can be increased.

[0297] Referring to FIG. 7b, by increasing the number of light-emitting layers in the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753, the thicknesses (B1, B2) of the light-emitting layer 75 can be increased.

[0298] Thus, in order to compensate for the increased thicknesses (B1, B2) of the light-emitting layer 75, the thicknesses (A1, A2) of the hole transport layer 73 or the common hole transport layer 73C can be adjusted.

[0299] Referring to FIG. 7b, in order to compensate for this by increasing the thickness (B2) of the light-emitting layer 75 in the optical region (OA) compared to the thickness (B1) of the light-emitting layer 75 in the general region (NA), the thickness (A2) of the hole transport layer 73 and the common hole transport layer 73C in the optical region (OA) can be decreased compared to the thickness (A1) of the hole transport layer 73 and the common hole transport layer 73C in the general region (NA).

[0300] Desirably, the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the general region (NA) may be equal to the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the optical region (OA).

[0301] On the other hand, for the first light-emitting layer 751 and the second light-emitting layer 752 of the light-emitting element (ED), a phosphorescent host and a phosphorescent dopant, or a fluorescent host and a fluorescent dopant can be used depending on the application.

[0302] FIGS. 8a to 8c are drawings showing the triplet state energy levels of the light-emitting element (ED) according to the examples of the present specification.

[0303] FIGS. 8a and 8b show the case where the light-emitting layer 85 of the light-emitting element (ED) according to the examples of the present specification is composed of a first light-emitting layer 851 and a second light-emitting layer 852, and there are two light-emitting layers arranged between the electron blocking layer 84 and the hole blocking layer 86.

[0304] FIG. 8c shows the case where the light-emitting layer 85 of the light-emitting element (ED) according to the examples of the present specification is composed of a first light-emitting layer 851, a second light-emitting layer 852, and a third light-emitting layer 853, and there are three light-emitting layers arranged between the electron blocking layer 84 and the hole blocking layer 86.

[0305] Referring to FIG. 8a, the second light-emitting layer 852 can be arranged between the hole blocking layer 86 and the first light-emitting layer 851 to prevent triplet polaron quenching (TPQ).

[0306] The thickness of the second light-emitting layer 852 may desirably be 2 nm or more and 5 nm or less.

[0307] At this time, the first light-emitting layer 851 may be the main light-emitting layer, and the second light-emitting layer 852 may be the auxiliary light-emitting layer.

[0308] That is, the second light-emitting layer 852 can transfer the energy generated by combining the holes accumulated at the interface of the hole-blocking layer 86 and the electrons transmitted through the hole-blocking layer 86 to the first light-emitting layer 851.

[0309] Here, for stable electron transfer and hole blocking, it can also satisfy Equation 1 in the optical region (OA) and at least one of Equation 2 or Equation 3.

[0310] (Equation 1) T1 < T2 < T HB

[0311] In Equation 1, T HB is the triplet state energy level of the hole-blocking layer, T1 is the triplet state energy level of the first light-emitting layer, and T2 is the triplet state energy level of the second light-emitting layer.

[0312] (Equation 2) L HB < L2 < L1

[0313] In Equation 2, L HB is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the hole-blocking layer, L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, and L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0314] (Equation 3) |H2 - H1| ≤ 0.1 eV

[0315] In Formula 3, H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, and H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0316] If the light-emitting device (ED) satisfies Formula 1 and at least one of Formula 2 or Formula 3, the phosphorescence efficiency can be increased.

[0317] Referring to FIG. 8b, a second light-emitting layer 852 can be disposed between the hole blocking layer 86 and the first light-emitting layer 851 to prevent triplet-triplet annihilation (TTA).

[0318] The thickness of the first light-emitting layer 851 may desirably be 2 nm or more and 5 nm or less.

[0319] At this time, the second light-emitting layer 852 may be the main light-emitting layer, and the first light-emitting layer 851 may be the auxiliary light-emitting layer.

[0320] That is, the first light-emitting layer 851 can transfer the energy generated by combining the electrons accumulated at the interface of the electron blocking layer 84 and the holes transmitted through the electron blocking layer 84 to the second light-emitting layer 852.

[0321] Here, for stable hole transfer and electron blocking, in the optical region (OA), Formula 4 can be satisfied and at least one of Formula 5 or Formula 6 can also be satisfied.

[0322] (Formula 4) T2 < T1 < T EB

[0323] In Formula 4, TEB is the triplet state energy level of the electron blocking layer, T1 is the triplet state energy level of the first light-emitting layer, and T2 is the triplet state energy level of the second light-emitting layer.

[0324] (Formula 5) L2 < L1 < L EB

[0325] In Formula 5, L EB is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the electron blocking layer, L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, and L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0326] (Formula 6) H2 < H1 < H EB

[0327] In Formula 6, H EB is the HOMO (Highest Occupied Molecular Orbital) energy level of the electron blocking layer, H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, and H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0328] If the light-emitting device (ED) satisfies Formula 4 and at least one of Formula 5 or Formula 6, the fluorescence efficiency can be increased.

[0329] Referring to FIG. 8c, in order to prevent triplet polaron quenching (TPQ) in the light-emitting layer 85 and the hole blocking layer 86, the third light-emitting layer 853 can be disposed between the hole blocking layer 86 and the second light-emitting layer 852.

[0330] The thicknesses of the first light-emitting layer 851 and the third light-emitting layer 853 may desirably be 2 nm or more and 5 nm or less.

[0331] At this time, the second light-emitting layer 852 may be the main light-emitting layer, and the first light-emitting layer 851 and the third light-emitting layer 853 may be auxiliary light-emitting layers.

[0332] Here, the first light-emitting layer 851 may have a lower electron transport ability compared to the second light-emitting layer 852 and the third light-emitting layer 853, but may have excellent hole transport ability.

[0333] Here, in order to achieve stable energy transfer and light emission, it is possible to satisfy Equation 7 and Equation 8 in the optical region (OA).

[0334] (Equation 7) T1>T2

[0335] (Equation 8) T3>T2

[0336] In Equation 7 and Equation 8, T1 is the triplet state energy level of the first light-emitting layer, T2 is the triplet state energy level of the second light-emitting layer, and T3 is the triplet state energy level of the third light-emitting layer.

[0337] When the light-emitting device (ED) satisfies Equation 7 and Equation 8, the triplet state energy level (T2) of the second light-emitting layer 852 becomes lower than the triplet state energy level (T1) of the first light-emitting layer 851 and the triplet state energy level (T3) of the third light-emitting layer 853, so that energy can be transferred from the auxiliary light-emitting layers 851 and 853 to the main light-emitting layer 852.

[0338] At this time, in order to achieve stable energy transfer and light emission, it is desirably possible to satisfy at least one of Equation 9, Equation 10, Equation 11, and Equation 12.

[0339] (Equation 9) T EB >T1>T2

[0340] In Formula 9, T1 is the triplet state energy level of the first light-emitting layer, T2 is the triplet state energy level of the second light-emitting layer, and T EB is the triplet state energy level of the electron blocking layer.

[0341] (Formula 10) T HB >T3>T2

[0342] T2 is the triplet state energy level of the second light-emitting layer, T3 is the triplet state energy level of the third light-emitting layer, and T HB is the triplet state energy level of the hole blocking layer.

[0343] (Formula 11) L1>L2

[0344] In Formula 11,

[0345] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, and L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0346] (Formula 12) H1>H2

[0347] In Formula 12,

[0348] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, and H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0349] The values of HOMO, LUMO, and T described in FIGS. 8a to 8c are the values measured by cyclic voltammetry.

[0350] Luminescence production evaluation

[0351] (Example 1) After a 2-TNATA film was vacuum-deposited on an ITO (Indium tin oxide) layer (anode) formed on a glass substrate to form a hole injection layer, NPD was vacuum-deposited on the hole injection layer to form a hole transport layer.

[0352] Thereafter, a first light-emitting layer with a thickness of 5 nm containing a first host material and a dopant material was deposited on the hole transport layer, and then a second light-emitting layer with a thickness of 17.5 nm containing a second host material and a dopant material was deposited on the first light-emitting layer.

[0353] Next, BAlq was vacuum-deposited on the second light-emitting layer to form a hole blocking layer, and Alq3 was formed on the hole blocking layer to form an electron transport layer.

[0354] Thereafter, LiF was deposited on the electron transport layer to form an electron injection layer, and then Al was deposited on the electron injection layer to form a cathode.

[0355] (Example 2) A light-emitting device was manufactured in the same manner as in Example 1 except that a second light-emitting layer with a thickness of 17.5 nm containing a second host material and a dopant material was deposited on the hole transport layer, and then a first light-emitting layer with a thickness of 5 nm containing a first host material and a dopant material was deposited on the second light-emitting layer.

[0356] (Comparative Example) A light-emitting device was manufactured in the same manner as in Example 1 except that a light-emitting layer with a thickness of 22.5 nm containing a second host material and a dopant material was deposited on the hole transport layer.

[0357] A pure bias DC voltage was applied to the light-emitting elements manufactured according to Examples 1 to 2 and Comparative Examples of the present invention to measure the electroluminescence (EL) characteristics, and the T95 life was measured through a life measurement equipment. The measurement results are as shown in Table 1 below.

[0358] Table 1 JPEG2025105445000002.jpg59170

[0359] Figures 9a to 9d are graphs showing a comparison between Example 1 and the Comparative Example, and Figures 10a to 10d are graphs showing a comparison between Example 2 and the Comparative Example. As can be seen from the results in Table 1 above, when a first light-emitting layer is incorporated between the electron blocking layer and the second light-emitting layer as in Example 1, it can be confirmed that the efficiency increases and the life (T95) increases compared to the Comparative Example.

[0360] Also, when a first light-emitting layer is incorporated between the hole blocking layer and the second light-emitting layer as in Example 2, it can be confirmed that the life (T95) increases compared to the Comparative Example.

[0361] Briefly described, the embodiments of the present disclosure described above are as follows.

[0362] A display device according to an embodiment of the present disclosure includes a substrate including a general area in which a plurality of first pixels are arranged and having a first resolution, and an optical area in which a plurality of second pixels are arranged and having a second resolution smaller than the first resolution, a first electrode layer positioned on the substrate, a first light-emitting layer positioned on the first electrode layer and including a first host in the general area and the optical area, a second light-emitting layer positioned on the first light-emitting layer, including the first host in the general area, and including a second host different from the first host in the optical area, and a second electrode layer positioned on the second light-emitting layer.

[0363] In the display device according to an embodiment of the present disclosure, in the optical area, the first light-emitting layer and the second light-emitting layer each include a first dopant and a second dopant, and the first dopant and the second dopant may be equal or different.

[0364] In the display device according to an embodiment of the present disclosure, the first host and the second host may be a phosphorescent host or a fluorescent host, and the first dopant and the second dopant may be a phosphorescent dopant or a fluorescent dopant.

[0365] In the display device according to an embodiment of the present disclosure, the total thickness of the first light-emitting layer and the second light-emitting layer in the optical region may be greater than the total thickness of the first light-emitting layer and the second light-emitting layer in the general region.

[0366] In the display device according to an embodiment of the present disclosure, a hole transport layer between the first electrode layer and the first light-emitting layer may be further included.

[0367] In the display device according to an embodiment of the present disclosure, the total thickness of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the general region may be equal to the total thickness of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the optical region.

[0368] In the display device according to an embodiment of the present disclosure, a third light-emitting layer on the second light-emitting layer may be further included, and the third light-emitting layer may include the first host in the general region and the optical region.

[0369] In the display device according to an embodiment of the present disclosure, the third light-emitting layer in the optical region may include a third dopant, and the third dopant may be the same as or different from the first dopant and the second dopant.

[0370] In the display device according to an embodiment of the present disclosure, the total thickness of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region may be greater than the total thickness of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region.

[0371] In the display device according to an embodiment of the present disclosure, a hole transport layer between the first electrode layer and the first light-emitting layer may be further included.

[0372] In the display device according to an embodiment of the present disclosure, the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region may be equal to the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region.

[0373] In the display device according to an embodiment of the present disclosure, an electron blocking layer between the hole transport layer and the first light-emitting layer and a hole blocking layer on the second light-emitting layer may be further included.

[0374] In the display device according to an embodiment of the present disclosure, an electron blocking layer between the hole transport layer and the first light-emitting layer and a hole blocking layer on the third light-emitting layer may be further included.

[0375] In the display device according to an embodiment of the present disclosure, in the optical region, the following formula 1 may be satisfied, or at least one of the following formula 2 or formula 3 may be satisfied.

[0376] (Formula 1) T1 < T2 < T HB

[0377] In the formula 1,

[0378] T HB is the triplet state energy level of the hole blocking layer,

[0379] T1 is the triplet state energy level of the first light-emitting layer,

[0380] T2 is the triplet state energy level of the second light-emitting layer.

[0381] (Formula 2) L HB < L2 < L1

[0382] In the formula 2,

[0383] L HBis the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the hole blocking layer,

[0384] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer,

[0385] L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0386] (Equation 3) |H2 - H1| ≤ 0.1 eV

[0387] In Equation 3,

[0388] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer,

[0389] H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0390] In the display device according to the embodiment of the present disclosure, the thickness of the second light-emitting layer may be 2 nm or more and 5 nm or less.

[0391] In the display device according to the embodiment of the present disclosure, in the optical region, the following Equation 4 may be satisfied, or at least one of the following Equation 5 or Equation 6 may be satisfied.

[0392] (Equation 4) T2 < T1 < T EB

[0393] In Equation 4,

[0394] T EB is the triplet state energy level of the electron blocking layer,

[0395] T1 is the triplet state energy level of the first light-emitting layer,

[0396] and T2 is the triplet state energy level of the second light-emitting layer.

[0397] (Equation 5) L 2< L1 < L EB

[0398] In Equation 5,

[0399] L EB is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the electron blocking layer,

[0400] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer,

[0401] and L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0402] (Equation 6) H2 < H1 < H EB

[0403] In Equation 6,

[0404] H EB is the HOMO (Highest Occupied Molecular Orbital) energy level of the electron blocking layer,

[0405] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer,

[0406] H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0407] In the display device according to an embodiment of the present disclosure, the thickness of the first light-emitting layer may be 2 nm or more and 5 nm or less.

[0408] In the display device according to an embodiment of the present disclosure, in the optical region, the following formula 7 and the following formula 8 may be satisfied, or at least one of the following formula 9, the following formula 10, the following formula 11, and the following formula 12 may be satisfied.

[0409] (Formula 7) T1>T2

[0410] (Formula 8) T3>T2

[0411] In the above formulas 7 and 8,

[0412] T1 is the triplet state energy level of the first light-emitting layer,

[0413] T2 is the triplet state energy level of the second light-emitting layer,

[0414] T3 is the triplet state energy level of the third light-emitting layer.

[0415] (Formula 9) T EB >T1>T2

[0416] In the above formula 9,

[0417] T1 is the triplet state energy level of the first light-emitting layer,

[0418] T2 is the triplet state energy level of the second light-emitting layer,

[0419] TEB is the triplet state energy level of the electron blocking layer.

[0420] (Equation 10) T HB >T3>T2

[0421] In the above Equation 10,

[0422] T2 is the triplet state energy level of the second light-emitting layer,

[0423] T3 is the triplet state energy level of the third light-emitting layer,

[0424] T HB is the triplet state energy level of the hole blocking layer.

[0425] (Equation 11) L1>L2

[0426] In the above Equation 11,

[0427] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer,

[0428] L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0429] (Equation 12) H1>H2

[0430] In the above Equation 12,

[0431] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer,

[0432] H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0433] In the display device according to an embodiment of the present disclosure, the thicknesses of the first light-emitting layer and the third light-emitting layer may each be 2 nm or more and 5 nm or less.

[0434] The display device according to an embodiment of the present disclosure includes a general area in which a plurality of first sub-pixels are arranged and an optical area in which a plurality of second sub-pixels are arranged. The number of the second sub-pixels per unit area in the optical area is less than the number of the first sub-pixels per unit area in the general area. Each of the first sub-pixels in the general area and each of the second sub-pixels in the optical area includes a light-emitting element. The light-emitting element includes a first electrode layer on a substrate, one or more stacks, and a second electrode layer on the one or more stacks. The one or more stacks are located on the first electrode layer and include a first light-emitting layer including a first host in the general area and the optical area, and a second host different from the first host in the optical area and including the first host in the general area may be included on the first light-emitting layer.

[0435] The above description merely exemplarily explains the technical idea of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs can make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not for limiting the technical idea of the present disclosure but for explanation. Therefore, the scope of the technical idea of the present disclosure is not limited by such embodiments.

Claims

1. A substrate including a general region in which a plurality of first pixels are arranged and which has a first resolution, and an optical region in which a plurality of second pixels are arranged and which has a second resolution smaller than the first resolution; A first electrode layer located on the substrate; A first light-emitting layer located on the first electrode layer and including a first host in the general region and the optical region; A second light-emitting layer located on the first light-emitting layer, including the first host in the general region, and including a second host different from the first host in the optical region; A display device including a second electrode layer located on the second light-emitting layer.

2. The display device according to claim 1, wherein in the optical region, the first light-emitting layer and the second light-emitting layer each include a first dopant and a second dopant, and the first dopant and the second dopant are the same or different.

3. The display device according to claim 2, wherein the first host and the second host are phosphorescent hosts or fluorescent hosts, and the first dopant and the second dopant are phosphorescent dopants or fluorescent dopants.

4. The display device according to claim 1, wherein the total thickness of the first light-emitting layer and the second light-emitting layer in the optical region is greater than the total thickness of the first light-emitting layer and the second light-emitting layer in the general region.

5. The display device according to claim 1, further including a hole transport layer between the first electrode layer and the first light-emitting layer.

6. The display device according to claim 5, wherein the total thickness of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the general region is equal to the total thickness of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the optical region.

7. Further including a third light-emitting layer on the second light-emitting layer, The display device according to claim 2, wherein the third light-emitting layer includes the first host in the general region and the optical region.

8. The display device according to claim 7, wherein in the optical region, the third light-emitting layer includes a third dopant, and the third dopant is the same as or different from the first dopant and the second dopant.

9. The display device according to claim 7, wherein the total thickness of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region is greater than the total thickness of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region.

10. The display device according to claim 9, further comprising a hole transport layer between the first electrode layer and the first light-emitting layer.

11. The display device according to claim 10, wherein the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region is equal to the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region.

12. An electron blocking layer between the hole transport layer and the first light-emitting layer, The display device according to claim 5, further comprising a hole blocking layer on the second light-emitting layer.

13. An electron blocking layer between the hole transport layer and the first light-emitting layer, The display device according to claim 10, further comprising a hole blocking layer on the third light-emitting layer.

14. The display device according to claim 12, wherein in the optical region, the following formula 1 is satisfied, or at least one of the following formula 2 or formula 3 is satisfied: (Formula 1) T １ <T ２ <T ＨＢ In the formula 1, T ＨＢ is the triplet state energy level of the hole blocking layer, T １ is the triplet state energy level of the first light-emitting layer, T ２ is the triplet state energy level of the second light-emitting layer, (Formula 2) L ＨＢ <L ２ <L １ In the formula 2, L ＨＢ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the hole blocking layer, L １ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, L ２ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer, (Formula 3) |H ２ -H １ |≤0.1 eV In the formula 3, H １ is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, H ２ is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

15. The display device according to claim 14, wherein the thickness of the second light-emitting layer is 2 nm or more and 5 nm or less.

16. The display device according to claim 12, wherein in the optical region, the following formula 4 is satisfied, or at least one of the following formula 5 or formula 6 is satisfied: (Formula 4) T ２ <T １ <T ＥＢ In the formula 4, T ＥＢ is the triplet state energy level of the electronic blocking layer, T １ is the triplet state energy level of the first light-emitting layer, T ２ is the triplet state energy level of the second light-emitting layer, (Formula 5) L ２ <L １ <L ＥＢ In the formula 5, L ＥＢ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the electron blocking layer, L １ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, L ２ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer, (Formula 6) H ２ <H １ <H ＥＢ In the formula 6, H ＥＢ is the HOMO (Highest Occupied Molecular Orbital) energy level of the electronic blocking layer, H １ is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, H ２ is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

17. The display device according to claim 16, wherein the thickness of the first light-emitting layer is 2 nm or more and 5 nm or less.

18. The display device according to claim 13, wherein in the optical region, the following formula 7 and formula 8 are satisfied, or at least one of the following formula 9, formula 10, formula 11, and formula 12 is satisfied: (Formula 7) T １ >T ２ (Formula 8) T ３ > T ２ In the formula 7 and formula 8, T １ is the triplet state energy level of the first light-emitting layer, T ２ is the triplet state energy level of the second light-emitting layer, T ３ is the triplet state energy level of the third light-emitting layer, (Formula 9) T ＥＢ > T １ > T ２ In the formula 9, T １ is the triplet state energy level of the first light-emitting layer, T ２ is the triplet state energy level of the second light-emitting layer, T ＥＢ is the triplet state energy level of the electron blocking layer, (Formula 10) T ＨＢ >T ３ >T ２ In the formula 10, T ２ is the triplet state energy level of the second light-emitting layer, T ３ is the triplet state energy level of the third light-emitting layer, T ＨＢ is the triplet state energy level of the hole blocking layer, (Formula 11) L １ > L ２ In the formula 11, L １ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, L ２ is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer, (Formula 12) H １ >H ２ In the formula 12, H １ is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, H ２ is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

19. The display device according to claim 18, wherein the thicknesses of the first light-emitting layer and the third light-emitting layer are each 2 nm or more and 5 nm or less.

20. A general region in which a plurality of first sub-pixels are arranged, An optical region in which a plurality of second sub-pixels are arranged, and In the optical region, the number of the second sub-pixels per unit area is less than the number of the first sub-pixels per unit area in the general region, Each of the first sub-pixels in the general region and each of the second sub-pixels in the optical region includes a light-emitting element, The light-emitting element is A first electrode layer on a substrate, one or more stacks, and a second electrode layer on the one or more stacks, and includes each of the one or more stacks is located on the first electrode layer, and includes a first light-emitting layer including a first host in the general region and the optical region, a display device including a second light-emitting layer located on the first light-emitting layer, including the first host in the general region, and including a second host different from the first host in the optical region.

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