System and method for mitigating overlay distortion patterns caused by wafer bonding tool

Abstract

To solve the problem in which models used to adjust a bonding tool cannot take into account new ways in which the bonding tool can be adjusted to prevent distortion.SOLUTION: A system includes a wafer shape metrology sub-system configured to perform shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller obtains a bonder control model, receives a set of proposed bonder tool adjustments for a bonded wafer pair, applies the bonder control model to proposed bonder tool adjustments to determine a set of predicted overlay distortion signatures for the bonded wafer pair, determines whether the set of predicted overlay distortion signatures is outside tolerance limits, and provides feedback adjustments to the bonder tool to adjust a bonder tool regulator when the set is outside the tolerance limits.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present invention generally relates to the field of wafer shape measurement, and more particularly to systems and methods for modeling and minimizing overlay distortion patterns induced by bonding tools.

Background Art

[0002] Cross - reference to related applications This application claims the benefit of U.S. Provisional Application No. 63 / 226,635 (July 28, 2021) under 35 U.S.C. § 119(e), which is hereby incorporated by reference in its entirety.

[0003] Bonding tools used in the manufacture of bonded wafer pairs have long been known to introduce distortion in the overlay between features of various bonded wafers. These distortions in the overlay can lead to concerns about reliability over long - term use or, in extreme cases, a lack of electrical conductivity. Therefore, there is a need for the ability of bonding tools to provide corrections to minimize distortion in the overlay.

[0004] Conventional methods of controlling bonding tools to minimize overlay distortion are rapidly becoming obsolete as new techniques for adjusting bonding tools are being developed. The models used to adjust bonding tools can no longer consider new ways of adjusting the bonding tools to prevent distortion.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Therefore, it would be desirable to provide a system and method that solves the drawbacks of the previously identified approaches described above.

Means for Solving the Problems

[0007] A system according to one or more embodiments of the present disclosure is disclosed. In one embodiment, the system includes a wafer shape measurement subsystem configured to perform one or more shape measurements on two pre-bonding (before bonding) wafers and corresponding post-bonding (after bonding) pairs of wafers. In another embodiment, the system includes a controller communicatively coupled to the wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory. In another embodiment, the set of program instructions is configured to cause the one or more processors to perform the following. Receiving a set of measured bonding strains; applying a bonder control model to the set of measured bonding strains, the bonder control model associating a set of bonder tool adjustments with a set of overlay strain signatures between a first wafer and a second wafer of a bonding wafer pair; determining whether the set of overlay strain signatures associated with the measured bonding strains is outside an acceptable limit; and providing one or more feedback adjustments to the bonder tool to adjust one or more bonder tool adjusters when the set of overlay strain signatures is outside the acceptable limit.

[0008] A method according to one or more embodiments of the present disclosure is disclosed. In one embodiment, for the purpose of calibrating a bonder, the method can include performing a set of wafers having a set of known bonder adjustments. Through measurement of the wafer shapes before and after pre-bonding and post-bonding, the resulting distortion is extracted. The obtained distortion pattern is stored as a numerical vector pattern or described through an analytical description of a vector map. This analytical description can use the wafer position as a descriptor. It can also describe the distortion induced by the actuator in the form of a relative correction of an existing pattern. In another embodiment, the method can include applying a bonder control model to the proposed bonder tool adjustment to determine a set of overlay distortion signatures between a first wafer and a second wafer of a bonding wafer pair. The bonder control model is an orthogonal set of wafer signatures that associates a set of adjustments of the bonder tool with a set of overlay distortion signatures between a first wafer and a second wafer of a bonding wafer pair.

[0009] In another embodiment, the method can include determining whether a set of overlay distortion signatures associated with the proposed bonder tool adjustment is outside an acceptable limit. In another embodiment, the method can include providing feedback adjustment to the bonder tool to adjust one or more regulators of the bonder tool when the set of overlay distortion signatures is outside the acceptable limit.

[0010] It should be understood that both the foregoing summary and the following detailed description are exemplary and explanatory only and are not necessarily limiting of the claimed invention. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention.

Brief Description of the Drawings

[0011] Many advantages of the present disclosure can be better understood by those skilled in the art by referring to the accompanying drawings.

Fig. 1A

Fig. 1B

Fig. 2

Fig. 3

[0012] The present disclosure has been specifically shown and described with respect to particular embodiments and specific features thereof. The embodiments described herein are to be construed as illustrative and not restrictive. It should be readily apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present disclosure. Here, reference is made in detail to the disclosed subject matter shown in the accompanying drawings.

[0013] Generally referring to FIGS. 1-3, a system and method for reducing an overlay distortion pattern induced by a wafer bonding tool according to one or more embodiments of the present disclosure are described.

[0014] Embodiments of the present disclosure are directed to systems and methods for modeling overlay distortion patterns induced by a bonding tool during the bonding of a pair of wafers. Embodiments of the present disclosure can implement a bond control model to determine whether a post-bonding distortion pattern is within an acceptable tolerance level. For example, embodiments of the present disclosure can implement a bonder control model to minimize a post-bonding induced distortion pattern. Embodiments of the present disclosure can generate a bonder control model by using one or more algorithms to analyze an overlay distortion pattern from a bonded pair of wafers. Additional embodiments of the present disclosure can provide feedback to the bonding tool if a given set of distortion patterns is not within an acceptable tolerance range. Feedback to the bonding tool may be in the form of one or more adjustments to one or more regulators on the bonding tool.

[0015] Embodiments of the present disclosure can be implemented to achieve stringent overlay requirements on two wafers after a wafer-to-wafer bonding process (e.g., hybrid or fusion bonding). For example, embodiments of the present disclosure can be utilized to minimize / reduce overlay in a wafer-to-wafer bonding process including: manufacturing of image sensors (e.g., backlit image sensor technology); 3D NAND technology where a device wafer and a memory wafer are bonded; and in a backside power rail process in a logic device, where a device wafer is bonded to a carrier wafer. In all of these examples, stringent overlay tolerance requirements exist. In image sensors and 3D NAND technology, the overlay requirements are implemented to ensure a reliable connection between Cu pads on one wafer and Cu pads on the other wafer for direct electrical connection. In the case of backside power rail technology, it is desirable to achieve low wafer distortion to ensure that subsequent lithographic exposure of through-silicon vias can achieve the overlay tolerance required assuming typical correction capabilities of a scanner (e.g., correction per field (CPE) correction).

[0016] Processes for modeling and minimizing the distortion controlled by a bonding tool may include, but are not limited to, the following: i) receiving a set of measured distortion patterns; ii) applying a bonder control model to the measured distortion patterns; iii) determining whether the bonding tool adjustment is within an acceptable tolerance range; and iv) providing feedback adjustment to the bonding tool if it is not within the acceptable tolerance range. In the case of feedback adjustment, the adjustment can be used to optimize the bonder settings for subsequent wafers.

[0017] FIG. 1 shows a simplified block diagram of a wafer shape measurement system illustrating feedback control of a bonding tool according to one or more embodiments of the present disclosure.

[0018] In an embodiment, system 100 includes a wafer shape measurement subsystem 102. System 100 can also include a controller 104 communicatively coupled to the detector output of wafer shape measurement subsystem 102. Controller 104 can include one or more processors 106 and a memory 108. One or more processors 106 of controller 104 can be configured to execute a set of program instructions stored in memory 108. The set of program instructions can be configured to cause one or more processors 106 to perform various steps and processes of the present disclosure.

[0019] The wafer shape measurement subsystem 102 can include any wafer measurement tool or system known in the art that can acquire one or more shape parameters from one or more wafers. In an embodiment, the wafer shape measurement subsystem 102 can include an interferometer subsystem configured to perform one or more measurement and / or characterization processes on one or more wafers. For example, the wafer shape measurement subsystem 102 can include a dual interferometer system (e.g., a dual Fizeau interferometer) configured to perform measurements on both sides of a wafer. For example, the wafer shape measurement subsystem 102 can include a first interferometer subsystem 105a configured to generate a first illumination beam 101a to perform one or more measurements on a first surface of a wafer, and a second interferometer subsystem 105b configured to generate a second illumination beam 101b to perform one or more measurements on a second surface of the wafer on the opposite side of the first surface. The wafer shape measurement subsystem 102 can include a patterned wafer geometry (PWG) tool such as a PWG tool manufactured by KLA INC. The use of interferometry for wafer characterization is generally described in U.S. Patent No. 6,847,458, filed January 15, 2013 (March 20, 2003); U.S. Patent No. 8,949,057, filed October 27, 2011; and U.S. Patent No. 9,121,684, which are hereby incorporated by reference in their entirety.

[0020] Note that additional or alternative embodiments of the wafer shape measurement subsystem 102 are described in detail in U.S. Patent Application No. 17 / 161,369, filed January 28, 2021, which is hereby incorporated by reference in its entirety.

[0021] It is further noted that the scope of the present disclosure is not limited to the dual interferometer system of the PWG implementation, and can be extended to include any wafer shape measurement subsystem or tool known in the art, including but not limited to a single-sided interferometer system.

[0022] In an embodiment, as shown in FIG. 1B, the wafer shape measurement subsystem 102 can perform (1) shape measurement on a first wafer to be pre-bonded, (2) shape measurement on a second wafer for pre-bonding, and (3) shape measurement of the post-bonded wafer pair. Note that based on the shape mismatch between the first and second wafers and the effects of the bonder and bonding process on the post-bonded pair, the measured values for the pre-bonded first and second wafers can be used to predict the shape of the post-bonded wafer pair.

[0023] In an embodiment, the wafer shape measurement subsystem 102 can perform a first shape measurement on a first wafer 110 and then transmit the shape measurement data to the controller 104 via the data signal 103a. The wafer shape measurement subsystem 102 can perform a second shape measurement on a second wafer 110 and then transmit the shape measurement data to the controller 104 via the data signal 103b. Then, the first wafer 110 and the second wafer 110 can undergo a bonding process via the bonding tool 112 to form a post-bonded wafer pair 110. The wafer shape measurement subsystem 102 can perform a third shape measurement on the post-bonded wafer pair 110 and then transmit the shape measurement data to the controller 104 via the data signal 103c.

[0024] In an embodiment, the bonding tool 112 can include one or more regulators 114, and the one or more regulators 114 correspond to one or more actuators on the bonding tool 112. For example, the bonding tool 112 can include three regulators 114a, 114b, and 114c, each of which corresponds to a single actuator. In an embodiment, the regulator 114 may be automatically changed or manually changed. In some embodiments, one or more actuators can be a controlled heater for adjusting the temperature of one of the wafers relative to the other wafers during the bonding process. For example, one wafer experiences greater thermal expansion relative to the other wafer, generating a strain pattern. Similarly, one controlled arcuate deformation of the chuck results in a strain pattern. The resulting strain pattern can be modeled using a standard model that describes the vector map using a linear function of wafer coordinates. In another example, a strain pattern is generated when the bonding process is initiated by contacting and pressing the wafer through pins. The resulting strain pattern is a strain pattern that depends on the gap between the wafers, the pressure applied to the pins, and the distance at which the wafers are held. In this case, it is necessary to apply a new modeling pattern to generate an adjustment.

[0025] In an embodiment, the controller 104 can generate a bond control model of the overlay strain pattern. For example, the controller 104 can determine a set of overlay strain patterns from the wafer shape measurement subsystem and extract the differences in the overlay strain patterns that correlate with the adjustments made using the actuators. By analyzing the differences in the overlay strain patterns that correlate with the adjustments (i.e., signatures) made using the actuators, a set of orthogonal wafer signatures can be generated that can be indirectly or directly mapped to the regulators 114 on the bonding tool 112.

[0026] In an embodiment, a set of orthogonal wafer signatures may be generated using one or more algorithms. In additional embodiments, the set of orthogonal wafer signatures can be mapped to one or more regulators 114 on the bonding tool 112. For example, changes induced by the regulators can be analyzed using principal component analysis (PCA) to generate an orthogonal set of wafer signatures, and the output of the PCA is a new set of strain signatures. The set of strain signatures can capture the observed variations and represent a set of orthogonal signatures, where the signatures represent bonding tool adjustments. In further embodiments, the bonding tool adjustments can be mapped to virtual actuators. Additional steps may be required to convert the virtual actuator adjustments to actual actuator adjustments.

[0027] The following example demonstrates the use of one or more algorithms for generating a set of orthogonal wafer signatures. For example, a number of wafer bonding experiments are performed, each run representing a particular setting of the bonder actuator. The resulting strain patterns are measured using wafer shape measurements on the pre-bonding wafer and the post-bonding wafer. The obtained strain signatures are collected as individual observations and analyzed using principal component analysis (PCA). The output of the PCA is a new set of optimal strain signatures. In this example, optimal refers to the fact that the strain signatures capture the observed variations and at the same time represent a set of orthogonal signatures. These signatures represent combinations of bonder actuators. In an embodiment, the bonder actuators can be "virtual actuators", which means that they no longer represent the adjustment of a single actuator; rather, they represent the coordinated adjustment of two or more bonder actuators. Therefore, additional steps are required to convert the virtual actuator settings to actual actuator adjustments.

[0028] Advantages of the present disclosure include generating a set of orthogonal wafer signatures that can be mapped indirectly or directly to the regulator 114 on the bonding tool 112. The orthogonal set of wafer signatures generates a unique set of bonder tool adjustments. This has been found to be advantageous for advanced process control that predicts new adjustments by averaging results generated from multiple consecutive lots.

[0029] In an embodiment, the controller 104 can provide one or more control signals 113 to one or more regulators 114 on one or more bonding tools 112. For example, the controller 104 can generate one or more feedforward and / or feedback control signals corresponding to one or more regulators 114. In an embodiment, the controller 104 can apply the generated bonder control model to the measured strain pattern and extract the type and magnitude of the overlay strain signature between the first wafer and the second wafer of the bonded wafer pair. Next, the controller 104 can determine a set of bonding tool adjustments based on the determined type and magnitude of the signatures. For example, the controller 104 may determine a new set of actuator conditions based on the determined type and magnitude of the signatures. These settings may be transferred directly to the bonder (in the case of rework) or transferred to the APC system, where the corrections are stored and potentially combined with other results to determine the actuator settings for the next lot. The controller can also determine whether the proposed set of bonder tool adjustments is within an acceptable overlay strain tolerance. If the overlay strain signature determined from applying the bonder control model to the proposed set of bonder tool adjustments is not within the acceptable overlay strain tolerance, the controller 104 can provide one or more feedback adjustments to the bonding tool 112 to adjust one or more regulators 114. In a further embodiment, the controller 104 may then determine a new set of actuator conditions based on the determined type and magnitude of the signatures. These settings may be transferred directly to the bonder or the APC system, where the corrections are stored and potentially combined with other results to determine the actuator settings for future wafer bonding.

[0030] One or more processors 106 of the controller 104 can include any processor or processing element known in the art. For the purposes of the present disclosure, the terms “processor” or “processing element” can be broadly defined to include any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGA), or one or more digital signal processors (DSP)). In this sense, one or more processors 106 can include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in memory). In one embodiment, one or more processors 106 can be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a network-connected computer, or any other computer system configured to execute a program that operates or is configured to operate with the measurement system 100 as described throughout the present disclosure. Further, different subsystems of the system 100 can include processors or logic elements suitable for performing at least a portion of the steps described in the present disclosure. Accordingly, the above description should not be construed as a limitation on the embodiments of the present disclosure, but should be construed as merely illustrative. Further, the steps described throughout the present disclosure can be executed by a single controller or, alternatively, by a plurality of controllers. Further, the controller 104 can include one or more controllers housed within a common housing or a plurality of housings. In this way, any controller or combination of controllers can be separately packaged as a module suitable for integration into the measurement system 100. Further, the controller 104 can analyze data received from the wafer-shaped measurement subsystem 102 and supply the data to additional components within or external to the measurement system 100.

[0031] The memory medium 108 can include any storage medium known in the art suitable for storing program instructions executable by one or more associated processors 106. For example, the storage medium 108 may include a non-transitory storage medium. As another example, the storage medium 108 can include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (such as disks), magnetic tapes, solid state drives, etc. Further, it should be noted that the memory medium 108 can be housed within a common controller housing together with one or more processors 106. In one embodiment, the memory medium 108 can be located remotely with respect to the physical location of one or more processors 106 and the controller 104. For example, one or more processors 106 of the controller 104 can access a remote memory (such as a server) accessible via a network (such as the Internet, an intranet, etc.).

[0032] It should be noted that in this specification, one or more components of the disclosed system 100 can be communicatively bonded to various other components of the system in any manner known in the art. For example, the wafer shape measurement subsystem 102, the controller 104, the bonding tool 112, and the user interface can be communicatively bonded to each other and to other components via a wireline (such as a copper wire, an optical fiber cable, etc.) or a wireless connection (such as RF bonding, IR bonding, data network communication (such as WiFi, WiMax, 3G, 4G, 4G LTE, 5G, Bluetooth®)).

[0033] FIG. 2 shows a flowchart of a method 200 for generating a bonder control model according to one or more embodiments of the present disclosure. Note that in this specification, the steps of method 200 may be implemented in whole or in part by system 100. However, it is further recognized that method 200 is not limited to system 100 in that additional or alternative system-level embodiments may perform all or some of the steps of method 200.

[0034] In step 202, a set of wafer pairs having different settings of bonding actuators are bonded to generate a set of overlay distortion patterns. In an embodiment, one or more regulators 114 on the bonding tool 112 can be adjusted with respect to a control set of the regulators 114 as well as the first wafer 110 and the second wafer 110 bonded to the wafer pair 110.

[0035] In step 204, the overlay distortion pattern is measured using a wafer shape measurement subsystem. In an embodiment, as illustrated in FIG. 1B, the wafer shape measurement subsystem 102 may be used to measure the first wafer 110a, the second wafer 110b, as well as the bonding wafer pairs 110a and 110b. For example, the wafer shape measurement subsystem 102 may measure the bonded wafer pairs 110a, 110b and then provide one or more measurement values to the controller 104.

[0036] In step 206, the regulator-induced change is extracted as the difference between the overlay distortion patterns. In an embodiment, the overlay distortion pattern may be related to a known set of actuator settings. In an embodiment, the regulator-induced change may be compared to a set of control regulator positions to extract the difference between the overlay distortion patterns. For example, as shown in FIG. 1A, the difference between a first overlay distortion pattern generated by the regulator 114a at a first position and a second overlay distortion pattern generated by the regulator 114a at a second position may be extracted.

[0037] In step 208, a set of orthogonal wafer signatures is generated by analyzing the changes induced by the regulators. In an embodiment, the set of orthogonal wafer signatures may be generated using various algorithms. In additional embodiments, the set of orthogonal wafer signatures can be mapped to one or more regulators 114 on the bonding tool 112. For example, the changes induced by the regulators represent achievable control modes and can be analyzed using PCA to generate an orthogonal set of wafer signatures that map to one or more regulators 114 on the bonding tool 112. The use of PCA can be beneficial in that the resulting wafer signatures are orthogonal by structure. The use of PCA eliminates the need for additional algorithms to establish orthogonality. In additional embodiments, non-orthogonal signatures can be prioritized during the optimization process so that a unique set of controls can be generated.

[0038] FIG. 3 shows a flowchart of a method 300 for utilizing a bonder control model to report feedback to a bonding tool, according to one or more embodiments of the present disclosure. Note that the steps of method 300 may be implemented, in whole or in part, by system 100 herein. However, it is further recognized that method 300 is not limited to system 100 in that additional or alternative system-level embodiments may perform all or some of the steps of method 300.

[0039] In step 302, a set of proposed bonder tool adjustments is received by the controller. For example, the controller 104 can receive a set of proposed bonder tool adjustments from one or more bonding tools 112, and the bonder tool adjustments correspond to one or more regulators 114 on the one or more bonding tools 112.

[0040] In step 304, the bonder control model is applied to the set of measured wafer distortions to determine a set of overlay distortion signatures between the first wafer and the second wafer of the bonded wafer pair. For example, the controller 104 can apply the bonder control model to the set of measured wafer distortions received from one or more bonding tools 112 to determine a set of overlay distortion signatures between the first wafer and the second wafer of the bonded wafer pair.

[0041] For example, the controller 104 can collect and store pre-bonding shape measurements and then combine them with the shape measurements of the post-bonding measurements to obtain the overlay distortion induced by one or more bonding tools 112. The controller then attempts to minimize the measured distortion signature by using the stored distortion signature and modeling the type and magnitude of the distortion signature, and to minimize the achievable predicted signature.

[0042] In step 306, it is determined whether the set of overlay distortion signatures associated with the proposed bonder tool adjustment is outside the tolerance limit. For example, the controller 104 can determine whether the set of overlay distortion signatures associated with the proposed bonder tool adjustment is outside the acceptable tolerance by referring to the acceptable tolerance data stored in the memory 108.

[0043] In step 308, feedback adjustment is provided to the bonder tool to adjust one or more actuators of the bonder tool. For example, the controller 104 can send feedback adjustment to the bonding tool 112 corresponding to one or more regulators 114. In another embodiment, the correction may be sent to an advanced process control system, and the control system may generate the bonder tool adjustment.

[0044] Those skilled in the art will recognize that the components, operations, devices, objects, and the accompanying discussions described herein are used as examples for conceptual clarity and that various configuration modifications are contemplated. Thus, as used herein, the specific examples and the accompanying discussions described are intended to be representative of their more general classes. Generally, the use of any specific example is intended to represent that class, and the exclusion of specific components, operations, devices, and objects should not be construed as a limitation.

[0045] These can also be performed using various processes and / or systems and / or other technologies that will be understandable to those skilled in the art (e.g., hardware, software, and / or firmware). In a preferred implementation, the context of the various processes and / or systems and / or other technologies used varies. For example, if the implementer determines that speed and accuracy are most important, the implementer can primarily select hardware and / or firmware implementation means; alternatively, if flexibility is of utmost importance, the implementer can primarily select a software implementation; or, still alternatively, the implementer can select some combination of hardware, software, and / or firmware. Thus, there are several possible implementation means by which the processes and / or devices and / or other technologies described herein can be achieved, and any implementation means utilized is a choice that depends on the context in which it is deployed and the specific concerns of the implementer (e.g., speed, flexibility, or predictability), none of which is inherently superior to the others in that they can all vary.

[0046] The foregoing description is presented to enable a person skilled in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, terms indicating directions such as "above", "below", "upper", "lower", "on", "over", "under", "beneath" are intended to provide a relative position for purposes of explanation and are not intended to indicate an absolute reference system. Various modifications to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Accordingly, the invention is not limited to the specific embodiments illustrated and described, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0047] Regarding the use of substantially any plural and / or singular terms herein, one of ordinary skill in the art can convert from plural to singular and / or from singular to plural as appropriate to the context and / or application. Various singular / plural substitutions are not explicitly set forth herein for clarity of understanding.

[0048] All of the methods described herein may include storing the results of one or more steps of a method embodiment in a memory. The results may include any of the results described herein and may be stored in any manner known in the art. The memory may include any memory described herein or any other suitable storage medium known in the art. After the results are stored, the results may be accessed within the memory and used by any of the methods or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, etc. Further, the results may be stored "permanently", "semi-permanently", "temporarily", or over a period of time. For example, the memory may be random access memory (RAM), and the results need not necessarily persist indefinitely within the memory.

[0049] It is further contemplated that each of the embodiments of the above-described method may include any other step of any other method described herein. Additionally, each of the embodiments of the above-described method can be executed by any of the systems described herein.

[0050] The subject matter described herein, in some cases, illustrates different components that are included within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and in fact, many other architectures that achieve the same functionality can be implemented. In a conceptual sense, any arrangement of components for achieving the same function is effectively "associated" so that the desired function is achieved. Thus, any two components herein combined to achieve a particular function can be considered "associated" with each other so that the desired function is achieved, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered "connected" or "bonded" to each other to achieve the desired functionality, and any two components that can be so associated can also be considered "bondable" to each other to achieve the desired functionality. Specific examples of bondable include, but are not limited to, components that are physically bondable and / or physically interact and / or wirelessly interact and / or wirelessly interact and / or logically interact and / or logically interactable components.

[0051] Furthermore, it should be understood that the present invention is defined by the appended claims. In general, the terms used in this specification and particularly in the appended claims (e.g., the body of the appended claims) are generally intended to be "open" terms (e.g., the term "including" should be construed as "including but not limited to", the term "having" should be construed as "having at least", the term "includes" should be construed as "includes but not limited to", etc.). It will be understood by those skilled in the art that where a specific number of claim recitations is intended, such intention will be explicitly recited in the claim, and where there is no such recitation, no such intention exists. For example, for purposes of illustration, the following appended claims may include introducing claim recitations using introductory phrases "at least one" and "one or more". However, the use of such phrases should not be construed to mean that the introduction of a claim recitation by the indefinite article "a" or "an" limits any particular claim that includes such introduced claim recitation to an invention that includes only one such recitation. The same holds true for the use of definite articles used to introduce claim recitations, even where the same claim includes an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should typically be construed to mean "at least one" or "one or more"). Also, it will be recognized by those skilled in the art that even where a specific number of introduced claim recitations is explicitly enumerated, such recitation should typically be construed to mean at least the enumerated number (e.g., a bare enumeration of "two" without other modifiers typically means at least two, or two or more).Furthermore, in cases where conventional expressions similar to “at least one of A, B, and C” are used, generally, such a configuration is intended in the sense that one of ordinary skill in the art would understand the conventional expression (e.g., “a system having at least one of A, B, and C” includes, but is not limited to, a system having only A, only B, only C, A and B together, A and C together, B and C together, and / or A, B, and C together). In cases where conventional expressions similar to “at least one of A, B, or C” are used, generally, such a configuration is intended in the sense that one of ordinary skill in the art would understand the conventional expression (e.g., “a system having at least one of A, B, or C” includes, but is not limited to, a system having only A, only B, only C, A and B together, A and C together, B and C together, and / or A, B, and C together). It will be further understood by one of ordinary skill in the art that virtually any disjunctive words and / or phrases presenting two or more alternative terms, anywhere in the description, claims, or drawings, are intended to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” would be understood to include the possibilities of “A” or “B” or “A and B”.

[0052] It will be appreciated that many of the aspects of the present disclosure and its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes may be made in the form, structure, and arrangement of the components without departing from the disclosed subject matter or sacrificing all of its material advantages. The forms described are merely illustrative, and it is the intention of the following claims to embrace and include such changes. Further, it should be understood that the invention is defined by the appended claims.

Claims

1. A system comprising: a wafer shape measurement subsystem configured to perform one or more shape measurements on a pair of pre-bonding wafers and a corresponding pair of post-bonding wafers; a controller communicatively coupled to the wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to: obtain a bond control model, the bond control model associating a set of bond tool adjustments with a set of overlay distortion signatures; receive a set of proposed bond tool adjustments for a bonded wafer pair; apply the bond control model to the proposed bond tool adjustments to determine a set of predicted overlay distortion signatures for the bonded wafer pair; determine whether the set of predicted overlay distortion signatures is outside an acceptable limit; when the set of predicted overlay distortion signatures is outside the acceptable limit, provide one or more feedback adjustments to the bond tool to adjust one or more bond tool regulators; a controller configured to perform the above steps; A system comprising the above components.

2. The step of obtaining the bond control model includes: generating the bond control model. The system according to claim 1, characterized in that the step of obtaining the bond control model includes generating the bond control model.

3. The step of generating the bond control model includes: bonding wafer pairs with different settings of the one or more bond tool regulators to generate a set of overlay distortion patterns; measuring at least some of the overlay distortion patterns in the set of overlay distortion patterns using the wafer shape measurement subsystem; extracting actuator-induced changes as differences in the overlay distortion patterns with respect to a set of control regulator positions; generating a set of stored orthogonal wafer signatures based on the actuator-induced changes. The system according to claim 2, characterized in that the step of generating the bond control model includes the above steps.

4. The step of providing one or more feedback adjustments when the set of predicted overlay distortion signatures is outside the acceptable limit includes: Providing one or more feedback adjustments to the one or more bond tool adjusters to minimize the predicted overlay distortion signature The system according to claim 1, characterized in that it comprises **Claim 5** The system according to claim 4, characterized in that the one or more bond tool adjusters are communicatively coupled to one or more actuators on the bond tool **Claim 6** The system according to claim 1, characterized in that the wafer shape measurement subsystem comprises a first interferometer subsystem and a second interferometer subsystem **Claim 7** A system comprising A controller communicatively coupled to a wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to Obtain a bond control model, the bond control model associating a set of bond tool adjustments with a set of overlay distortion signatures Receive a set of proposed bond tool adjustments for a bonded wafer pair Apply the bond control model to the proposed bond tool adjustments to determine a set of predicted overlay distortion signatures for the bonded wafer pair Determine whether the set of predicted overlay distortion signatures is outside an acceptable limit When the set of predicted overlay distortion signatures is outside the acceptable limit, provide one or more feedback adjustments to the bond tool to adjust the one or more bond tool adjusters A controller configured to perform A system comprising **Claim 8** The step of obtaining the bond control model comprises Generating the bond control model The system according to claim 7, characterized in that it comprises **Claim 9** The step of generating the bond control model comprises Bonding wafer pairs with different settings of the one or more bond tool adjusters to generate a set of overlay distortion patterns Measuring at least some of the overlay distortion patterns in the set of overlay distortion patterns using the wafer shape measurement subsystem extracting actuator-induced changes as the difference in the overlay distortion pattern with respect to a set of control regulator positions; generating a set of stored orthogonal wafer signatures based on the actuator-induced changes; The system according to claim 8, characterized by including the above.

10. The step of providing one or more feedback adjustments when the set of predicted overlay distortion signatures is outside the tolerance limits includes: providing the one or more feedback adjustments to the one or more bond tool regulators to minimize the predicted overlay distortion signature. The system according to claim 7, characterized by including the above.

11. The system according to claim 7, characterized in that the one or more bond tool regulators are communicatively coupled to one or more actuators on the bond tool.

12. The system according to claim 7, characterized in that the wafer shape measurement subsystem includes a first interferometer subsystem and a second interferometer subsystem.

13. A method comprising: obtaining a bond control model, the bond control model associating a set of bond tool adjustments with a set of overlay distortion signatures; receiving a set of proposed bond tool adjustments for a bonded wafer pair; applying the bond control model to the proposed bond tool adjustments to determine a set of predicted overlay distortion signatures for the bonded wafer pair; determining whether the set of predicted overlay distortion signatures is outside the tolerance limits; providing one or more feedback adjustments to the bond tool to adjust the one or more bond tool regulators when the set of predicted overlay distortion signatures is outside the tolerance limits. A method comprising the above.

14. The step of obtaining the bond control model includes: generating the bond control model. The method according to claim 13, characterized by including the above.

15. The step of generating the bond control model includes: bonding wafer pairs with different settings of the one or more bond tool regulators to generate a set of overlay distortion patterns. Measuring at least some of the overlay distortion patterns of the set of overlay distortion patterns using the wafer shape measurement subsystem; Extracting actuator-induced changes as differences in the overlay distortion patterns for a set of control regulator positions; Generating a set of orthogonal wafer signatures stored based on the actuator-induced changes; The method according to claim 14, characterized by including the above steps.

16. Generating a regulator control group by bonding a wafer pair with known regulator settings; The method according to claim 13, further including the above step.

17. The method according to claim 13, characterized in that the step of generating the set of orthogonal wafer signatures is achieved by principal component analysis.

18. The method according to claim 13, characterized in that the orthogonal wafer signatures are mapped to the one or more bond tool regulators.

19. The method according to claim 18, characterized in that the one or more bond tool regulators are manually controlled.

20. The method according to claim 18, characterized in that the one or more bond tool regulators are controlled via a computer system.

21. The step of extracting actuator-induced changes as differences in the overlay distortion patterns for a set of control regulator positions includes: Comparing the actuator-induced changes with a regulator control group; The method according to claim 13, characterized by including the above step.

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