Information processor, information processing method, and program

Abstract

To provide an information processor, an information processing method, and a program that execute a program with memory saving.SOLUTION: An information processor includes at least one processor. The at least one processor evaluates, on the basis of information about a chunk, for processing in which a plurality of chunks are allocated to a storage medium, a plurality of permutations of the chunks with respect to at least an amount of memory used, and searches, on the basis of the evaluation of the plurality of permutations, for chunk arrangement that satisfies a predetermined condition.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an information processing device, an information processing method, and a program. [Background technology]

[0002] Dynamic memory allocation dynamically allocates and frees memory areas for each piece of data while a program is running. Dynamic memory allocation dynamically plans the addresses of the allocated memory areas, so it is thought to be able to prevent memory fragmentation. Generally, when a program is running, the amount of memory allocated often increases or decreases drastically during the program's execution, so fragmentation is relatively unlikely to occur even without highly accurate address planning.

[0003] To conserve memory, it is possible to achieve both suppression of fragmentation and memory conservation by planning in advance the addresses of memory areas to be secured for each piece of data before the program is executed. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] MS Johnstone, et.al., "The Memory Fragmentation Problem: Solved?", Proc. of OOPSRA 1997, Workshop on Garbage Collection and Memory Management 1997, [internet]https: / / dl.acm.org / doi / pdf / 10.1145 / 301589.286864, accessed December 1, 2023 Summary of the Invention [Problem to be solved by the invention]

[0005] One non-limiting problem that embodiments of the present disclosure attempt to solve is memory optimization in process execution. [Means for solving the problem]

[0006] According to one embodiment, an information processing device includes at least one processor, which, for a process in which a plurality of chunks are allocated to a storage medium, evaluates a plurality of permutations of the chunks with respect to at least the amount of memory used based on information about the chunks, and searches for a chunk arrangement that satisfies a predetermined condition based on the evaluation of the plurality of permutations. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of representation of a memory area in the present disclosure. [Figure 2] FIG. 10 is a diagram showing the memory amount of a chunk used for explanation in an embodiment. [Figure 3] 10 is a flowchart showing information processing according to an embodiment. [Figure 4] 10 is a flowchart showing information processing according to an embodiment. [Figure 5] FIG. 2 is a diagram showing an example of a memory arrangement in information processing according to an embodiment; [Figure 6] FIG. 2 is a diagram showing an example of a memory arrangement in information processing according to an embodiment; [Figure 7] FIG. 2 is a diagram showing an example of a memory arrangement in information processing according to an embodiment; [Figure 8] FIG. 2 is a diagram showing an example of a memory arrangement in information processing according to an embodiment; [Figure 9] FIG. 2 is a diagram showing an example of a memory arrangement in information processing according to an embodiment; [Figure 10] FIG. 1 is a block diagram showing an implementation example of an information processing device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The problems to be solved by the embodiments of the present disclosure are not limited to the problems described above, and as further examples of some problems that are not limited to these, problems corresponding to the effects described in the embodiments can also be considered. In other words, a problem corresponding to at least one of the effects described in the description of the embodiments of the present disclosure can be considered to be a problem to be solved by the present disclosure.

[0009] In this disclosure, terms may be defined as follows. Note that these definitions are not intended to be unique and may be interpreted as having a general meaning depending on the context.

[0010] A "chunk" refers to a block of memory area (e.g., memory area) reserved in a storage medium (e.g., memory, cache memory, storage, etc.) during processing. For example, it refers to an area for temporarily storing variables, arrays, etc. required at a certain timing during processing. Allocating a chunk refers to reserving memory area for the chunk. One chunk may be defined as, for example, a single contiguous area. As a non-limiting example, a chunk may refer to a memory area whose address does not change from allocation to release. In this disclosure, an example in which the storage medium is memory will be described first, but the memory address of the chunk may be optimized with respect to memory usage or other indicators. Furthermore, in this disclosure, "memory" may be appropriately interpreted as "memory area," and "memory allocation" and "memory release" may be appropriately interpreted as "memory area allocation" and "memory release."

[0011] A "permutation" refers to the arrangement of chunks, for example, a set of chunks rearranged according to a predetermined rule. This permutation is, for example, a set that satisfies a partial order. More specifically, a permutation satisfies a topological order, but does not exclude permutations that follow orders other than a topological order. The permutation of chunks defines the order that determines the location (address) of each chunk within the permutation. For example, in the process illustrated in FIG. 4, as can be seen from the fact that processes S202 to S208 for one chunk are repeated up to the last chunk in the permutation, the location of each chunk within the permutation is determined in accordance with the order defined by the permutation, that is, from the first chunk in the permutation to the last chunk in the permutation. The order defined by the permutation is not limited to the order from the beginning to the end of the permutation.

[0012] In addition, the timing for securing and releasing chunks is described, but this only needs to be shown in a manner that clearly distinguishes whether different chunks are secured at the same timing, and may be defined based on a unit time from the start of processing, or, if there are no overlapping chunks at the same timing, the timing when there are no overlapping chunks may be omitted.

[0013] In other words, the timing may be defined in any way as long as it can be determined whether or not the chunks are allocated at the same time. Note that, for ease of understanding, the embodiment will be described using a time defined by a unit time from the start of processing.

[0014] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The drawings and the description of the embodiment are shown as an example and are not intended to limit the present invention. The embodiment optimizes the memory allocation of chunks (addresses of each chunk for storing data), but can also be applied to other fields. The technique according to the embodiment can also be applied to cases with decimal values, for example, packing flat cargo.

[0015] Assume that chunks A, B, C, and D are required to execute a certain process. In this case, it is desirable to determine the chunk allocation (memory allocation of chunks and addresses where chunks are allocated) within a storage medium based on the memory usage of each chunk at each timing. More specifically, it is desirable to ensure that memory areas do not overlap between chunks at each timing and to minimize the amount of memory used throughout the process. Note that the memory amount refers to the capacity of the memory area reserved for the chunks and does not limit the type of storage medium (memory, cache memory, storage, etc.) on which the memory area is reserved. Note that in this disclosure, "minimizing the memory amount" is not limited to the smallest memory amount that can be achieved, but also conceptually includes the smallest memory amount found in optimization (searching for memory allocation of chunks) performed to reduce the memory amount.

[0016] A chunk is associated with the amount of memory allocated for that chunk and data on the allocation timing of that chunk. The memory amount of a chunk is the size of the memory area allocated for the chunk during processing execution. The data on the allocation timing of a chunk is data that indicates the period from when a chunk is allocated to when it is released during processing execution, and may be defined, for example, by data on the timing of when the chunk is allocated and the timing of when the chunk is released.

[0017] Figure 1 illustrates the relationship between the address of each chunk and the timing of allocation and release of each chunk, i.e., the concept of memory allocation of chunks in memory space taking into account the time direction. As shown in the figure, this memory space is expressed for one memory, for example, with the horizontal axis representing memory addresses and the vertical axis representing time. The shaded area indicates the memory area allocated for a certain chunk, and shows the memory address occupied (allocated) for that memory area and its occupation period (allocation period).

[0018] The memory area indicated by diagonal lines in the upper left indicates, for example, an area reserved for consecutive memory addresses 1 to 3 from time 2 to time 3. The memory area indicated by diagonal lines in the lower right indicates, for example, an area reserved for consecutive memory addresses 6 to 8 from time 5 to time 9.

[0019] In the present disclosure, similarly to this example, a memory area in the memory space allocated by a chunk is expressed using a time and a memory address corresponding to the address area to be allocated.

[0020] The definition of a memory address can be arbitrary. For example, the expressed memory location may be the start address of a memory space that can be allocated in a process, excluding areas used by the system.

[0021] Furthermore, one cell of a memory address (hereinafter referred to as one block) may be expressed in units such as bits, bytes, shorts, longs, or long longs, but is defined in a common way for all chunks. For example, it may be expressed as allocating xx bytes for each chunk. If it is not common, it can be converted into a common expression in advance in the information processing device.

[0022] 2 is a diagram showing an example of memory space allocation of memory amounts set for each chunk in one embodiment. The memory amounts and allocation timings shown in this diagram will be used to explain the embodiment.

[0023] Chunk A uses four blocks of memory between times 1 and 2. The memory amount of chunk A can be expressed as four blocks.

[0024] Chunk B uses two blocks of memory at times 2 to 7. Similarly, the memory amount of chunk B is two blocks.

[0025] Chunk C uses one block of memory at time 4. Similarly, the memory amount of chunk C is one block.

[0026] Chunk D uses 5 blocks of memory at time 6. Similarly, the memory amount of chunk D is 5 blocks.

[0027] Next, processing of the information processing device according to this embodiment will be described. Unless otherwise specified, when referring to processing of the information processing device, a processor included in the information processing device executes processing based on data stored in a storage area included in the information processing device.

[0028] An information processing device according to one embodiment statically searches for a chunk allocation that satisfies a predetermined condition (e.g., a memory allocation of chunks that minimizes the amount of memory used throughout the process) based on, for example, an evaluation of the permutation of chunks (e.g., an evaluation of the amount of memory used). That is, the information processing device searches for the optimal memory allocation of each chunk before the target process is executed. If necessary, the memory address for each chunk based on this memory allocation information can be specified in the program, executable file, etc. for the target process.

[0029] FIG. 3 is a flowchart showing an example of processing for searching for memory allocation of chunks.

[0030] The information processing device first acquires information required for the search (S100). The information required for the search is information related to chunks used throughout the process for which memory allocation is to be optimized. The information related to the chunks (also referred to as chunk information) is data related to the amount of memory used by the chunks and the timing for allocating this memory amount. The data related to the timing may be data on the time when memory is allocated (alloc) and the time when memory is released (release). The chunk information may be used when evaluating the permutation of chunks, which will be described later.

[0031] For example, this information may be prepared in advance, and the information processing device may acquire the prepared information.

[0032] The information processing device may extract this information from, for example, an assembly, an executable file, or the like related to the target process.

[0033] Furthermore, the information processing device may extract this information from, for example, a source file describing the target process, an intermediate language, or the like.

[0034] The information processing device defines a connection based on the acquired information (S102). A connection indicates a relationship between chunks. If the timing at which two chunks allocate memory overlaps at least partially, the information processing device defines a connection between the two chunks. The information processing device extracts all pairs of chunks across the target process that have even a partial overlap in the timing at which memory is allocated, and defines a connection between the chunks. At this point, the connection has no direction.

[0035] For example, in chunks A to D illustrated in FIG. 2, the information processing device sets connections between chunks A and B, between chunks B and C, and between chunks B and D.

[0036] The information processing device generates a permutation of the chunks (hereinafter also referred to as a chunk permutation) (S104). The information processing device uses the permutation to optimize the memory allocation of the chunks. In the process of S104, the information processing device initializes the permutation for this optimization. The process of S104 corresponds to selecting multiple chunks allocated in a storage medium (for example, a memory) and setting a permutation of those chunks. The memory allocation of the chunks may be optimized by repeatedly setting and evaluating different permutations according to a predetermined procedure, starting from the permutation set here. As a result, the optimal allocation of the multiple chunks in the storage medium (optimal addresses of the chunks) is obtained.

[0037] The information processing device may generate a permutation by rearranging chunks in the order of memory allocation, for example. In this case, the permutation is [A, B, C, D].

[0038] The information processing device may generate a permutation by rearranging the chunks in descending order of memory capacity, for example. In this case, the permutation becomes [D, A, B, C].

[0039] Furthermore, the information processing device may generate a permutation by rearranging chunks in a random order, for example.

[0040] The information processing device may generate permutations by rearranging chunks using various optimization methods, for example. The information processing device may generate initial permutations using methods with relatively low processing costs, such as hill climbing or steepest descent.

[0041] The information processing device assigns an order relation to the connections established in S102 based on the permutation established in S104 (S106). Hereinafter, the order is represented by the inequality sign "<". For example, the information processing device assigns an order relation to the connections from the chunk at the front of the permutation to the chunk at the back.

[0042] For example, when the permutation is initialized to [A, B, C, D], the information processing device assigns an order relation to each connection, such as A<B, B<C, B<D.

[0043] For example, when the permutation is initialized as [D, A, B, C], the information processing device assigns an order relation to each connection, such as D<B, A<B, and B<C.

[0044] When the permutation is expressed as a partial order, according to the transitive law, that is, if A < B and B < C, then A < C holds for chunks A and C that are not directly connected.

[0045] After the above-mentioned assignment of precedence / successor relationships has been completed, the information processing device executes an optimization process (S108). The information processing device can execute optimization by optimizing the permutation of chunks using various optimization methods, for example, to minimize the amount of memory used throughout the target process. In other words, the process of S108 obtains the optimal chunk permutation.

[0046] After obtaining the optimal chunk permutation (for example, a permutation of chunks that minimizes memory usage) as described above, the information processing device outputs the memory addresses associated with each chunk, thereby determining and outputting the optimal memory allocation of each chunk that satisfies a predetermined condition, for example, that minimizes memory usage throughout the processing (S110). The output may be output to a storage area within the information processing device, or may be output to the outside of the information processing device via an interface (including a user interface).

[0047] FIG. 4 is a diagram illustrating an example of the optimization process shown in S108 according to an embodiment.

[0048] The information processing device first performs initialization (S200). This initialization is to initialize the pointer of the selected chunk in the current permutation (also called the permutation of interest). The information processing device selects, for example, the chunk at the beginning of the permutation.

[0049] The information processing device acquires information about the selected chunk (S202). The chunk information includes at least the amount of memory used by the chunk, data related to the allocation timing, and data about the order relationship between the chunk and the chunks to which it is connected. The data about the order relationship may be acquired for each chunk, but is not limited to this. It may also be acquired as data indicating the permutation, for example, data expressed as [A, B, C, D] above, and the connection to the selected chunk may be read each time.

[0050] The information processing device determines whether there is a connection that precedes the selected chunk in order (S204). The process of S204 corresponds to the process of determining whether there is another chunk that will be allocated at the same time as the selected chunk.

[0051] If there is a previous connection (S204: YES), the information processing device calculates an address range that does not overlap with chunks that have already been allocated at the same time (S206). The process of S206 corresponds to the process of calculating an address range of a contiguous memory area that does not overlap with memory addresses where other chunks allocated at the same time are allocated and that can allocate more memory than the amount of memory of the chunk being selected.

[0052] After the process of S206, the information processing device places the selected chunk at the memory address with the smallest address in the range (S208). Also, if there is no previous connection (S204: NO), the information processing device similarly places the selected chunk from the memory address with the smallest address, i.e., address 1 (S208). The process of S208 corresponds to the process of left-justifying the selected chunk in the memory space, assuming that the direction of decreasing memory addresses is left and the direction of increasing memory addresses is right.

[0053] The information processing device determines whether the currently selected chunk is the last chunk in the current sequence (S210). If it is not the last chunk in the sequence (S210: NO), it selects the next chunk in the sequence and repeats the process from S202.

[0054] If it is the last chunk in the sequence (S210: YES), the information processing device obtains the maximum memory usage across the target process from the state of the allocated chunk (S212). For example, the information processing device adds the memory size to the memory address of each chunk and obtains the largest value as the memory usage. This process in S212 corresponds to the process of evaluating the current sequence in terms of memory usage.

[0055] In the process of S212, the information processing device may store the calculated memory usage amount in a storage unit. The information processing device may store the permutation under consideration and the memory usage amount associated with this permutation.

[0056] Furthermore, when the amount of memory usage is the smallest ever, the information processing device may store the selected permutation as the permutation that minimizes the amount of memory usage. This minimum value may be stored in the storage unit at least until a permutation with the next minimum value is found.

[0057] Furthermore, without being limited to these, the information processing device may store a predetermined number of recent permutations and the corresponding memory usage amounts as history.

[0058] Furthermore, without being limited to these, the information processing device may store a predetermined number of permutations in ascending order of memory usage amounts and the corresponding memory usage amounts as history.

[0059] It should be noted that these storage methods should be appropriately selected based on the optimization technique used.

[0060] The information processing device determines whether the optimization is complete (S214). The determination of the completion of the optimization may be performed using a common method. For example, the information processing device may select a completion condition such as the evaluation value (e.g., the amount of memory used obtained in S212) being smaller than a predetermined value, the process of S216 being executed a predetermined number of times or more, the optimization process being executed for a predetermined time, or the minimum value of the amount of memory used obtained in S212 being maintained a predetermined number of times in succession. The information processing device is not limited to these, and other appropriate completion conditions may be selected.

[0061] When the information processing device determines that the optimization is complete (S214: YES), it ends the optimization process. That is, based on the evaluation of the chunk permutations (S200 to S212), it searches for a chunk permutation that satisfies a predetermined condition (YES in S214).

[0062] As can be understood from the above, the evaluation of the permutation of chunks is performed based on chunk information, at least with respect to the amount of memory used, and includes a process of determining the placement of chunks in the order specified by the permutation based on the chunk placements determined up to that point, and a process of evaluating the permutation for which the chunk placements have been determined based on the amount of memory used by the determined chunk placements. For example, in the evaluation of the permutation of a certain chunk, the placement of each chunk in the permutation is determined in order starting from the first chunk in the permutation, and in determining the placement of each chunk, the placement of a certain chunk is determined based on the placements of other chunks determined up to that point.

[0063] That is, for a certain chunk permutation, the information processing device determines the placement of each chunk, starting from the top of the permutation, based on the chunk placements determined up to that point. The information processing device may evaluate the permutation for which the chunk placement has been determined, for example, based at least on the memory usage amount resulting from the determined chunk placement. The information processing device may search for a permutation that satisfies a predetermined condition by performing such evaluation on multiple permutations.

[0064] Then, in S110, a chunk placement is determined and output based on the searched chunk permutation, so that the information processing device can be said to search for a chunk placement in the storage medium that satisfies a predetermined condition based on the evaluation of the chunk permutation. Note that the process of S216 does not necessarily have to be performed before the optimization is completed. For example, if optimization is performed in the permutation generation process in S104 of Figure 3 and the generated permutation satisfies the completion condition, the process can be completed without actually performing the optimization process of S108.

[0065] If the information processing device determines that the optimization is not complete (S214: NO), it rearranges the permutations, redefines the order associated with the rearrangement (S216), and repeats the process from S200 onward. The process of S216 corresponds to a process of rearranging at least a part of the order of the current permutation to obtain a different permutation.

[0066] The information processing device can store, for example, a permutation that minimizes memory usage, and use the memory allocation based on this stored permutation as the optimal memory allocation. In addition, if necessary for optimization, at least one other permutation can be stored in addition to the permutation that minimizes memory usage, and can be used in the optimization process (for example, the replacement process of S216).

[0067] For example, when using simulated annealing, the information processing device can perform permutation replacement processing based on the selected permutation with a predetermined probability, even if the amount of memory used for the selected permutation increases.

[0068] The information processing device can set the selection of the completion condition in S214 and the permutation processing in S216 based on various optimization techniques. The information processing device can set the processing in S214 and S216 using, for example, a heuristic technique.

[0069] As the heuristic method, a metaheuristic method may be selected. As the metaheuristic method, the Metropolis method may be selected. As the Metropolis method, simulated annealing may be selected. These are shown as non-limiting examples and do not exclude the application of other methods.

[0070] As described above, the information processing device may perform evaluation of chunk permutations based on chunk information (S200 to S212) while changing the chunk permutation (S216). In other words, it may set multiple chunk permutations according to a predetermined algorithm, and evaluate each of these multiple chunk permutations based on chunk information with respect to at least the amount of memory used, thereby searching for an optimal chunk permutation that satisfies predetermined conditions.

[0071] 4, the permutation of the current chunk is evaluated (S200 to S212), followed by setting a permutation of another chunk (S216) and evaluating that permutation (next S200 to S212). However, information obtained in the evaluation of the permutation of the current chunk may be used to evaluate not only the current permutation but also another permutation. In other words, information obtained in the evaluation of the permutation of one chunk may be reused in the evaluation of the permutation of another chunk.

[0072] The information processing device may perform the search using, as non-limiting examples, a greedy search, a beam search, or a full search, or a combination of these, or a method similar to these.

[0073] As yet another example, the processes from S200 to S212 may be implemented in the non-limiting example described above and executed in parallel. The information processing device may simultaneously execute evaluations of multiple permutations for processes using the same chunk. In this case, the information processing device may perform parallel processing, including the process of S216, or may consolidate the evaluations performed by parallel computation after completing the processes up to S212, generate multiple new permutations in the process of S216, and execute the processes from S200 onward as parallel processing.

[0074] An example in which the initial permutation is [A, B, C, D] and the initial order relationships are A < B, B < C, B < D will be described below with reference to Figures 5 to 8. Figures 5 to 8 are diagrams sequentially showing the memory allocation according to this example.

[0075] In S200, the information processing device selects chunk A.

[0076] In S202, the information processing device acquires information relating to chunk A, ie, 4 blocks as the memory amount, time 1 to time 2 as the timing, and A<B as the order relationship.

[0077] In S204, the information processing device determines whether there is a connection that precedes chunk A. The determination is NO.

[0078] In S208, the information processing device allocates chunk A to memory addresses 1 to 4 at times 1 and 2, which are the smallest addresses. It may store 1 to 4 as the memory addresses for chunk A, or it may store 1 and calculate that chunk A will use memory addresses 1 to 4, taking into account that the memory amount will be 4 blocks when the next chunk A information is needed. Figure 5 is a diagram showing the memory space after this processing.

[0079] In S210, since chunk A is not the last chunk in the sequence, the information processing device selects the next chunk B and repeats the process from S202.

[0080] While chunk B is being selected, in S204 the information processing device determines that there is a connection that precedes it in the order because A<B, and executes the process of S206.

[0081] In S206, the information processing device determines that chunk A uses memory addresses 1 to 4, and that the memory amount (2 blocks) used by chunk B can be secured from memory address 5 onwards, so that memory addresses 5 onwards are available.

[0082] In S208, the information processing device can allocate chunk B from memory addresses 5 to 6, which are the smallest among times 2 to 7. Fig. 6 is a diagram showing the memory space after this process.

[0083] In S210, since chunk B is not the last chunk in the sequence, the information processing device selects the next chunk C and repeats the process from S202.

[0084] In this iteration, since chunk C is in the order B < C, chunk C is placed at memory address 7 at time 4, resulting in the state shown in Figure 7. Furthermore, in the next iteration, since chunk D is in the order B < D, chunk D is placed at memory addresses 7 to 11 at time 6, as shown in Figure 8.

[0085] In S212, the information processing device calculates the memory usage amount from the result of the above arrangement. The memory usage amount is maximum at time 6, and the specified memory amount for the target process in the permutation is 11 blocks (the amount represented by memory address 11).

[0086] In this way, the information processing device sets memory addresses according to the permutation so as not to allocate overlapping memory areas for multiple chunks.

[0087] In S214, if the information processing device determines that the optimization is complete in the state shown in Fig. 8 (S214: YES), it completes the process and returns the permutation [A, B, C, D] as the optimization result. Then, in S110, it outputs data based on this result.

[0088] The information processing device may output, for example, data relating to the permutation itself, or may output the memory allocation shown in a drawing as in Figure 8. The information processing device may also output, as text data or binary data, each chunk and a memory address, for example, the start address of the chunk in the memory allocation (the minimum address value of the memory area).

[0089] If it is determined in S214 that the optimization is not complete (S214: NO), the information processing device rearranges the permutations based on an arbitrary optimization method and obtains a new ordering relationship from the generated new permutation in S216. As described above, this rearrangement process can be performed using any appropriate algorithm from various optimization algorithms, and can perform conversion according to the algorithm.

[0090] In S216, for example, the information processing device replaces the permutation [A, B, C, D] with the permutation [D, A, B, C]. According to this permutation, the information processing device executes the same process as above. According to the permutation, the information processing device processes memory allocation for chunks, arranging chunk D and then chunk A.

[0091] Next, in processing chunk B, the information processing device focuses on chunks A and D, which precede chunk B, and compares memory areas 1 to 4 of chunk A with memory areas 1 to 5 of chunk D, determining that memory addresses 6 and onward are usable. Based on this result, the information processing device allocates chunk B to memory addresses 6 to 7.

[0092] After this, the information processing device similarly allocates chunk C to memory address 8. In accordance with this allocation, the information processing device calculates that the memory usage amount of the permutation [D, A, B, C] is 8.

[0093] In this case, in S214, the permutation [D, A, B, C] uses less memory than the permutation [A, B, C, D]. The information processing device can store data relating to the permutation and data on the memory usage amount relating to the permutation in the storage unit based on an appropriate method from among the several methods described above.

[0094] As described above, according to this embodiment, the information processing device can quickly optimize memory allocation by statically searching for a target process and by reducing the search space for searching combinations of memory addresses compared to when permutations are not used.

[0095] The above-described form can also be represented as a graph. The information processing device can realize the same processing as above by considering a directed acyclic graph (DAG) in which chunk data is the node of the graph, connections are the edges of the graph, and order is the direction of the edges. The information processing device can efficiently obtain multiple chunk permutations by sorting the permutations of chunks represented in this graph using a topological sorting algorithm.

[0096] In other words, the information processing device can achieve the above processing by storing chunk information in nodes, connecting nodes that allocate memory at the same time, setting a permutation, and directing the nodes based on this permutation.

[0097] Although the above-described embodiment describes an example of optimizing the memory allocation of chunks in one memory, the optimization of chunk memory allocation using permutations disclosed in the present disclosure may also be applied to memory allocation of chunks in multiple memories. That is, a process of evaluating the permutation of chunks in each memory based on information about the chunks allocated in each memory may be repeated while changing the permutation of chunks in each memory or changing the chunks allocated in each memory, and an optimal chunk allocation in multiple memories may be determined based on this repeated evaluation. When evaluating the permutation of chunks in multiple memories, the evaluation may be performed based on the total or maximum memory usage of each memory. For example, if the chunks allocated in Memory 1 are chunks A, B, C, and D in the permutation [A, B, C, D], and the chunks allocated in Memory 2 are E, F, G, and H in the permutation [E, F, G, H], the evaluation value is the sum of the memory usage amount for the chunk permutation [A, B, C, D] and the memory usage amount for the permutation [E, F, G, H]. Similarly, if the chunks allocated in Memory 1 are chunks A, B, and D in the permutation [A, D, B], and the chunks allocated in Memory 2 are C, E, F, G, and H in the permutation [E, C, F, H, G], the evaluation value is the sum of the memory usage amount for the chunk permutation [A, D, B] and the memory usage amount for the permutation [E, C, F, G, H]. Based on these two evaluation values, the memory allocation of the chunks with the least memory usage amount may be adopted as the optimal one. In this way, even in a form applied to multiple memories, the permutation of chunks secured in the memory, which is the storage medium, may be evaluated, and the memory allocation of chunks in the storage medium may be optimized based at least on the evaluation.

[0098] The optimization of chunk memory allocation using permutations disclosed herein may be applied to the memory allocation of chunks in a cache memory. That is, a process of evaluating the permutation of chunks in a cache memory based on information about chunks allocated in the cache memory may be repeated while changing the permutation of chunks in the cache memory or changing the chunks allocated in the cache memory, and an optimal chunk allocation in the cache memory may be obtained based on the repeated evaluation. When evaluating the permutation of chunks in a cache memory, the evaluation may be performed based on the amount of memory used in the cache memory as well as the reduction in memory access time achieved by allocating chunks in the cache memory. For example, if chunks A, B, C, and D are allocated in the cache memory and their permutation is [A, B, C, D], the evaluation value is calculated by subtracting the reduction in memory access time multiplied by a predetermined coefficient from the amount of memory used by the chunk permutation [A, B, C, D]. Furthermore, if the chunks allocated to the cache memory are C, E, F, G, and H and their permutation is [E, C, F, H, G], the evaluation value is calculated by subtracting the memory usage amount for the permutation [E, C, F, G, H] from the amount of memory used by the permutation [E, C, F, G, H] multiplied by a predetermined coefficient. Then, based on these two evaluation values, the memory allocation of the chunks with the smaller evaluation value may be adopted as the optimal one. In this way, even in the case of application to a cache memory, the permutation of the chunks allocated to the cache memory, which is a storage medium, may be evaluated, and the memory allocation of the chunks within the storage medium may be optimized based at least on the evaluation.

[0099] By replacing memory with storage in the chunk memory allocation optimization using permutations disclosed in the present disclosure, it is possible to optimize the addresses of chunks allocated in the storage. In this way, even in a form applied to storage, the permutations of chunks allocated in the storage, which is a storage medium, may be evaluated, and the chunk allocation (chunk addresses) within the storage medium may be optimized at least based on the evaluation.

[0100] As described above, according to the embodiments described in the present disclosure, the information processing device can optimize the placement of entities in any type of space, with the size of the space being one axis and the size of the space being related to one or more other axes. As an example, as used in the description of the embodiments, the any type of space is a memory space, one axis of the size of the space is the memory amount, and the other axis is an axis indicating time, and entities occupying the space can be defined as chunks.

[0101] Although an example using a directed acyclic graph has been described above, this can be used for the various storage capacities mentioned above, and of course can also be applied to other examples. The information processing device can connect nodes containing data of magnitudes on two or more axes in any of the above types of spaces using a method based on a directed acyclic graph, and optimize the order of the connections, thereby optimizing the arrangement of things related to the nodes in any space using a graph.

[0102] The information processing device can, for example, set any type of space as a memory space and chunks as nodes. The information processing device can optimize the placement of chunks in the memory space by defining connections between nodes as valid edges based on data about the amount of memory occupied by the chunks and timing, thereby optimizing the order.

[0103] The above-described embodiments can be summarized as follows.

[0104] (1) at least one processor; The at least one processor, in a process of reserving a plurality of chunks in a storage medium, Evaluating a plurality of permutations of the chunks with respect to at least memory usage based on the information of the chunks; searching for a chunk arrangement that satisfies a predetermined condition based on the evaluation of the plurality of permutations; Information processing device.

[0105] (2) The at least one processor: A plurality of permutations of chunks are set according to a predetermined algorithm; Evaluating permutations of each chunk based on the chunk information, at least with respect to memory usage; searching for a chunk arrangement that satisfies the predetermined condition based on the evaluation of the permutation of each chunk; An information processing device according to (1).

[0106] (3) The process of evaluating a permutation of chunks with respect to at least the amount of memory used based on chunk information includes a process of determining an arrangement of chunks in an order defined by the permutation based on chunk arrangements determined up to that point, and a process of evaluating the permutation in which chunk arrangements have been determined based on the amount of memory used by the determined chunk arrangements. An information processing device according to (1) or (2).

[0107] (4) The at least one processor: Acquire data on the memory amount and allocation timing of each chunk as chunk information; Based on the allocation timing, an unordered connection is defined between chunks that allocate memory at the same timing; setting an initial permutation of the plurality of chunks; assigning an order relation to the connections based on the permutation; obtaining a memory usage amount across the process in which the chunks are arranged in a memory space according to the connection, and optimizing the permutation based on the memory usage amount; determining memory addresses at which the plurality of chunks are to be allocated as chunk allocations that satisfy the predetermined conditions; An information processing device according to any one of (1) to (3).

[0108] (5) The at least one processor: extracting the plurality of chunks from the information related to the processing; (4) An information processing device according to the present invention.

[0109] (6) The at least one processor: determining memory addresses of the plurality of chunks before the process of reserving the plurality of chunks on the storage medium is executed; An information processing device according to (4) or (5).

[0110] (7) The at least one processor: The initial permutation is set randomly. An information processing device according to any one of (4) to (6).

[0111] (8) The at least one processor: The initial permutation is set by sorting the permutations in descending order of the memory amount. An information processing device according to any one of (4) to (6).

[0112] (9) The at least one processor: The initial permutation is set by an optimization method. An information processing device according to any one of (4) to (6).

[0113] (10) The at least one processor: assigning the order relation to the connections according to the order of the chunks in the permutation; An information processing device according to any one of (4) to (9).

[0114] (11) The at least one processor: setting the memory addresses according to the permutation and the order so that the plurality of chunks do not reserve overlapping memory areas; An information processing device according to any one of (4) to (10).

[0115] (12) The at least one processor: optimizing the permutations so as to minimize the amount of memory used; An information processing device according to any one of (1) to (11).

[0116] (13) The at least one processor: optimizing the permutations using heuristic techniques; (12) An information processing device according to (12).

[0117] (14) The at least one processor: optimizing the permutations by Monte Carlo methods; (13) An information processing device according to (13).

[0118] (15) The at least one processor: Each chunk is a node, For each of the nodes, obtain data on how much and when the chunks occupy space; based on the timing, forming undirected edges between nodes that occupy the space at the same timing; setting an initial permutation for the nodes; directing the edges to become directed edges based on the permutation; obtaining a memory usage amount throughout the process of arranging the chunks corresponding to the nodes in a memory space according to the directed edges, and optimizing the permutation based on the memory usage amount; determining memory addresses at which to place the chunks; An information processing device according to any one of (1) to (14).

[0119] (16) Regarding the process of allocating multiple chunks to a storage medium, At least one processor has Evaluating a plurality of permutations of the chunks with respect to at least memory usage based on the information of the chunks; searching for a chunk arrangement that satisfies a predetermined condition based on the evaluation of the plurality of permutations; Information processing methods.

[0120] (17) Regarding the process of allocating multiple chunks to a storage medium, At least one processor has Evaluating a plurality of permutations of the chunks with respect to at least memory usage based on the information of the chunks; searching for a chunk arrangement that satisfies a predetermined condition based on the evaluation of the plurality of permutations; A program that executes information processing sales.

[0121] Some or all of the devices (information processing devices) in the above-described embodiments may be configured as hardware, or may be configured as software (programs) executing information processing by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), etc. When software information processing is configured, software that realizes at least some of the functions of each device in the above-described embodiments may be stored on a non-transitory storage medium (non-transitory computer-readable medium) such as a CD-ROM (Compact Disc-Read Only Memory) or a USB (Universal Serial Bus) memory, and the software information processing may be executed by loading the software into a computer. The software may also be downloaded via a communications network. Furthermore, all or part of the software processing may be implemented in a circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array), thereby allowing the software information processing to be executed by hardware.

[0122] The storage medium that stores the software may be a removable medium such as an optical disk, or a fixed medium such as a hard disk or memory. The storage medium may be located inside the computer (such as a main memory or auxiliary memory), or may be located outside the computer.

[0123] 10 is a block diagram showing an example of the hardware configuration of each device (information processing device) in the above-described embodiment. Each device may be realized as a computer 7 including, for example, a processor 71, a main storage device 72 (memory), an auxiliary storage device 73 (memory), a network interface 74, and a device interface 75, all of which are connected via a bus 76.

[0124] Although the computer 7 in FIG. 10 includes one of each component, it may include multiple of the same component. Also, while FIG. 10 shows one computer 7, the software may be installed on multiple computers, and each of the multiple computers may execute the same or different parts of the software. In this case, a distributed computing configuration may be used in which each computer communicates with the other computers via a network interface 74 or the like to execute the processing. In other words, each device (information processing device) in the above-described embodiment may be configured as a system in which one or more computers execute instructions stored in one or more storage devices to achieve its functions. Furthermore, the system may be configured such that information sent from a terminal is processed by one or more computers located on a cloud, and the processing results are sent to the terminal.

[0125] The various calculations of each device (information processing device) in the above-described embodiments may be executed in parallel using one or more processors, or using multiple computers connected via a network. Furthermore, the various calculations may be distributed to multiple processor cores within a processor and executed in parallel. Furthermore, some or all of the processes, means, etc. disclosed herein may be implemented by at least one processor and storage device provided on a cloud that can communicate with computer 7 via a network. Thus, each device in the above-described embodiments may be implemented in the form of parallel computing using one or more computers.

[0126] The processor 71 may be an electronic circuit (processing circuit, processing circuitry, CPU, GPU, FPGA, ASIC, etc.) that at least controls or performs calculations on a computer. The processor 71 may also be a general-purpose processor, a dedicated processing circuit designed to perform a specific calculation, or a semiconductor device that includes both a general-purpose processor and a dedicated processing circuit. The processor 71 may also include an optical circuit or a calculation function based on quantum computing.

[0127] The processor 71 may perform arithmetic processing based on data or software input from each device, etc., configured inside the computer 7, and may output the calculation results or control signals to each device, etc. The processor 71 may control each component constituting the computer 7 by executing the OS (Operating System) of the computer 7, applications, etc.

[0128] Each device (information processing device) in the above-described embodiments may be realized by one or more processors 71. Here, the processor 71 may refer to one or more electronic circuits arranged on one chip, or may refer to one or more electronic circuits arranged on two or more chips or two or more devices. When multiple electronic circuits are used, the electronic circuits may communicate with each other via wire or wirelessly.

[0129] The main memory device 72 may store instructions executed by the processor 71 and various data, etc., and information stored in the main memory device 72 may be read by the processor 71. The auxiliary memory device 73 is a memory device other than the main memory device 72. Note that these memory devices refer to any electronic component capable of storing electronic information and may be semiconductor memory. The semiconductor memory may be either volatile memory or non-volatile memory. The memory device for saving various data, etc. in each device (information processing device) in the above-described embodiments may be realized by the main memory device 72 or the auxiliary memory device 73, or may be realized by an internal memory built into the processor 71. For example, the memory unit 102 in the above-described embodiment may be realized by the main memory device 72 or the auxiliary memory device 73.

[0130] When each device (information processing device) in the above-described embodiments is configured with at least one storage device (memory) and at least one processor connected (coupled) to this at least one storage device, at least one processor may be connected to one storage device. At least one storage device may be connected to one processor. A configuration in which at least one processor among multiple processors is connected to at least one storage device among multiple storage devices may also be included. This configuration may also be realized by storage devices and processors included in multiple computers. Furthermore, a configuration in which a storage device is integrated with a processor (for example, a cache memory including an L1 cache and an L2 cache) may also be included.

[0131] The network interface 74 is an interface for connecting to the communication network 8 wirelessly or via a wire. The network interface 74 may be an appropriate interface, such as one that conforms to an existing communication standard. The network interface 74 may exchange information with an external device 9A connected via the communication network 8. The communication network 8 may be any one of a WAN (Wide Area Network), a LAN (Local Area Network), a PAN (Personal Area Network), etc., or a combination thereof, as long as information is exchanged between the computer 7 and the external device 9A. An example of a WAN is the Internet, an example of a LAN is IEEE 802.11 or Ethernet (registered trademark), and an example of a PAN is Bluetooth (registered trademark) or NFC (Near Field Communication), etc.

[0132] The device interface 75 is an interface such as USB that directly connects to the external device 9B.

[0133] The external device 9A is a device connected to the computer 7 via a network. The external device 9B is a device directly connected to the computer 7.

[0134] For example, the external device 9A or the external device 9B may be an input device. The input device may be a device such as a camera, a microphone, a motion capture device, various sensors, a keyboard, a mouse, or a touch panel, and provides acquired information to the computer 7. Alternatively, the external device 9A or the external device 9B may be a device equipped with an input unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0135] Furthermore, the external device 9A or the external device 9B may be, for example, an output device. The output device may be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) panel, or a speaker that outputs sound or the like. Alternatively, the external device 9A or the external device 9B may be a device including an output unit, a memory, and a processor, such as a personal computer, a tablet terminal, or a smartphone.

[0136] Furthermore, the external device 9A or the external device 9B may be a storage device (memory). For example, the external device 9A may be a network storage or the like, and the external device 9B may be a storage such as an HDD.

[0137] Furthermore, the external device 9A or the external device 9B may be a device having some of the functions of the components of each device (information processing device) in the above-described embodiment. That is, the computer 7 may transmit some or all of the processing results to the external device 9A or the external device 9B, or may receive some or all of the processing results from the external device 9A or the external device 9B.

[0138] In this specification (including the claims), when the expression "at least one of a, b, and c" or "at least one of a, b, or c" (including similar expressions) is used, it includes any of a, b, c, a-b, a-c, b-c, or a-b-c. It may also include multiple instances of any element, such as a-a, a-b-b, a-a-b-b-c-c, etc. It also includes the addition of elements other than the listed elements (a, b, and c), such as having d, as in a-b-c-d.

[0139] In this specification (including claims), when expressions such as "using data as input / based on / according to / in response to" (including similar expressions) are used, unless otherwise specified, this includes cases where the data itself is used, or where data that has been processed in some way (e.g., data with noise added, normalized data, features extracted from data, intermediate representations of data, etc.) is used. Furthermore, when a statement is made that a result is obtained "using data as input / based on / according to / in response to" (including similar expressions), this includes cases where the result is obtained based solely on the data, or where the result is influenced by other data, factors, conditions, and / or states other than the data, unless otherwise specified. Furthermore, when a statement is made that "data is output" (including similar expressions), this includes cases where the data itself is used as output, or where data that has been processed in some way (e.g., data with noise added, normalized data, features extracted from data, intermediate representations of data, etc.) is used as output, unless otherwise specified.

[0140] When the terms "connected" and "coupled" are used in this specification (including the claims), they are intended as open-ended terms that encompass any of direct connection / coupling, indirect connection / coupling, electrically connection / coupling, communicatively connection / coupling, functionally connection / coupling, and physically connection / coupling. These terms should be interpreted appropriately according to the context in which they are used, but should be interpreted without limitation to include any form of connection / coupling that is not intentionally or naturally excluded.

[0141] In this specification (including the claims), the expression "A configured to B" may include the physical structure of element A having a configuration capable of performing operation B, and the permanent or temporary setting / configuration of element A being configured / set to actually perform operation B. For example, if element A is a general-purpose processor, it is sufficient that the processor has a hardware configuration capable of performing operation B, and is configured to actually perform operation B by setting a permanent or temporary program (instruction). Also, if element A is a dedicated processor or dedicated arithmetic circuit, it is sufficient that the circuit structure of the processor is implemented to actually perform operation B, regardless of whether control instructions and data are actually attached to it.

[0142] When used in this specification (including the claims), terms implying containing or possessing (e.g., "comprising" or "including" and "having"), they are intended to be open-ended terms that include containing or possessing things other than the object designated by the object of the term. When the object of such terms implies no quantity or a singular number (e.g., expressions using the articles "a" or "an"), the expression should be construed as not being limited to a specific number.

[0143] In this specification (including the claims), although expressions such as "one or more" or "at least one" are used in some places and expressions that do not specify a quantity or that imply a singular number (expressions using the articles a or an) are used in other places, the latter expressions are not intended to mean "one." In general, expressions that do not specify a quantity or that imply a singular number (expressions using the articles a or an) should be interpreted as not necessarily being limited to a specific number.

[0144] In this specification, when a particular advantage / result is described as being obtained from a particular configuration of an embodiment, it should be understood that the same advantage / result can also be obtained from one or more other embodiments having the same configuration, unless otherwise stated. However, it should be understood that the presence or absence of the effect generally depends on various factors, conditions, and / or circumstances, and that the effect is not necessarily obtained by the configuration. The effect is merely obtained by the configuration described in the embodiment when various factors, conditions, and / or circumstances are satisfied, and the effect does not necessarily occur in a claimed invention that defines the same or a similar configuration.

[0145] When terms such as "maximize" are used in this specification (including the claims), they include finding a global maximum, finding an approximation of a global maximum, finding a local maximum, and finding an approximation of a local maximum, and should be interpreted accordingly according to the context in which the term is used. They also include finding approximations of these maxima probabilistically or heuristically. Similarly, when terms such as "minimize" are used, they include finding a global minimum, finding an approximation of a global minimum, finding a local minimum, and finding an approximation of a local minimum, and should be interpreted accordingly according to the context in which the term is used. They also include finding approximations of these minima probabilistically or heuristically. Similarly, when terms such as "optimize" are used, they include finding a global optimum, finding an approximation of a global optimum, finding a local optimum, and finding an approximation of a local optimum, and should be interpreted accordingly according to the context in which the term is used. It also includes finding approximations of these optimum values probabilistically or heuristically.

[0146] In this specification (including claims), when multiple pieces of hardware perform a predetermined process, the pieces of hardware may cooperate to perform the predetermined process, or some of the hardware may perform all of the predetermined process. Furthermore, some of the hardware may perform part of the predetermined process, and other hardware may perform the rest of the predetermined process. In this specification (including claims), when expressions such as "one or more pieces of hardware perform a first process, and the one or more pieces of hardware perform a second process" (including similar expressions) are used, the hardware performing the first process and the hardware performing the second process may be the same or different. In other words, it is sufficient that the hardware performing the first process and the hardware performing the second process are included in the one or more pieces of hardware. Note that hardware may also include an electronic circuit or a device including an electronic circuit.

[0147] In this specification (including the claims), when multiple storage devices (memories) store data, each of the multiple storage devices may store only a portion of the data, or may store the entire data. Also, a configuration in which only some of the multiple storage devices store data may be included.

[0148] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the individual embodiments described above. Various additions, modifications, substitutions, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the content defined in the claims and their equivalents. For example, when numerical values or formulas are used in the above-described embodiments, they are shown for illustrative purposes and do not limit the scope of the present disclosure. Furthermore, the order of each operation shown in the embodiments is also illustrative and does not limit the scope of the present disclosure.

Claims

1. at least one processor; The at least one processor, in a process of reserving a plurality of chunks in a storage medium, Evaluating a plurality of permutations of the chunks with respect to at least memory usage based on the information of the chunks; searching for a chunk arrangement that satisfies a predetermined condition based on the evaluation of the plurality of permutations; Information processing device.

2. The at least one processor: A plurality of permutations of chunks are set according to a predetermined algorithm; Evaluating permutations of each chunk based on the chunk information, at least with respect to memory usage; searching for a chunk arrangement that satisfies the predetermined condition based on the evaluation of the permutation of each chunk; The information processing device according to claim 1.

3. The process of evaluating a permutation of chunks with respect to at least the amount of memory used based on chunk information includes a process of determining an arrangement of chunks in an order defined by the permutation based on chunk arrangements determined up to that point, and a process of evaluating the permutation in which chunk arrangements have been determined based on the amount of memory used by the determined chunk arrangements. The information processing device according to claim 1.

4. The at least one processor: Acquire data on the memory amount and allocation timing of each chunk as chunk information; Based on the allocation timing, an unordered connection is defined between chunks that allocate memory at the same timing; setting an initial permutation of the plurality of chunks; assigning an order relation to the connections based on the permutation; obtaining a memory usage amount across the process in which the chunks are arranged in a memory space according to the connection, and optimizing the permutation based on the memory usage amount; determining memory addresses at which the plurality of chunks are to be allocated as chunk allocations that satisfy the predetermined conditions; The information processing device according to claim 1.

5. The at least one processor: extracting the plurality of chunks from the information related to the processing; The information processing device according to claim 4.

6. The at least one processor: determining memory addresses of the plurality of chunks before the process of reserving the plurality of chunks on the storage medium is executed; The information processing device according to claim 4.

7. The at least one processor: The initial permutation is set randomly. The information processing device according to claim 4.

8. The at least one processor: The initial permutation is set by sorting the permutations in descending order of the memory amount. The information processing device according to claim 4.

9. The at least one processor: The initial permutation is set by an optimization method. The information processing device according to claim 4.

10. The at least one processor: assigning the order relation to the connections according to the order of the chunks in the permutation; The information processing device according to claim 4.

11. The at least one processor: setting the memory addresses according to the permutation and the order so that the plurality of chunks do not reserve overlapping memory areas; The information processing device according to claim 4.

12. The at least one processor: optimizing the permutations so as to minimize the amount of memory used; The information processing device according to claim 1.

13. The at least one processor: optimizing the permutations using heuristic techniques; The information processing device according to claim 12.

14. The at least one processor: optimizing the permutations by Monte Carlo methods; The information processing device according to claim 13.

15. The at least one processor: Each chunk is a node, For each of the nodes, obtain data on how much and when the chunks occupy space; based on the timing, forming undirected edges between nodes that occupy the space at the same timing; setting an initial permutation for the nodes; directing the edges to become directed edges based on the permutation; obtaining a memory usage amount throughout the process of arranging the chunks corresponding to the nodes in a memory space according to the directed edges, and optimizing the permutation based on the memory usage amount; determining memory addresses at which to place the chunks; The information processing device according to claim 1.

16. Regarding the process of allocating multiple chunks to a storage medium, At least one processor has Evaluating a plurality of permutations of the chunks with respect to at least memory usage based on the information of the chunks; searching for a chunk arrangement that satisfies a predetermined condition based on the evaluation of the plurality of permutations; Information processing methods.

17. Regarding the process of allocating multiple chunks to a storage medium, At least one processor has Evaluating a plurality of permutations of the chunks with respect to at least memory usage based on the information of the chunks; searching for a chunk arrangement that satisfies a predetermined condition based on the evaluation of the plurality of permutations; A program that executes information processing sales.

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