Display device

Abstract

To provide a semiconductor device having a structure in which a parasitic capacitance between wirings can be sufficiently reduced, and provide a manufacturing method thereof.SOLUTION: In a thin film transistor 448 having a bottom-gate structure in which an oxide semiconductor layer is used, an oxide insulating layer 426a serving as a channel protective layer is formed on and in contact with a part of an oxide semiconductor layer 442 which overlaps with a gate electrode layer 421a, and an oxide insulating layer 426b is formed to cover a peripheral part (including a side surface) of a lamination layer of the oxide semiconductor layer when the oxide insulating layer is formed. A source electrode layer 425a and a drain electrode layer 425b are formed so as not to overlap with the channel protective layer, and an insulating layer 428 over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer 426a.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology for constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. There are many types of metal oxides and they are used for various purposes. Indium oxide is a well-known material that is needed in LCD displays and other applications. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides with excellent semiconductor properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] When a plurality of thin film transistors are fabricated on an insulating surface, for example, gate wiring and source wiring are At the intersection, there is a gate wiring and a gate line having a different potential. An insulating layer is provided between the source wirings, and the insulating layer acts as a dielectric to form a capacitance. The capacitance is also called parasitic capacitance between wirings, and there is a risk that the signal waveform may become distorted. High raw capacitance can slow down signal transmission.

[0007] Furthermore, an increase in parasitic capacitance can cause crosstalk, where electrical signals leak between wiring, and can also increase power consumption. This leads to increased power.

[0008] In an active matrix display device, the signal wiring for supplying a video signal is If a large parasitic capacitance is formed between the wiring or the electrode, the display quality may be deteriorated. There is.

[0009] Furthermore, when miniaturizing circuits, the spacing between wires becomes narrower, and the parasitic capacitance between wires increases. There is a risk of this occurring.

[0010] One embodiment of the present invention provides a semiconductor device having a structure capable of sufficiently reducing parasitic capacitance between wirings. One of the goals is to

[0011] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel portion must have excellent switching characteristics. For example, a large on-off ratio is required for thin film transistors used in drive circuits. High operating speed is required. In particular, the higher the resolution of the display device, Since the time required to write the display image is shortened, the thin film transistors used in the driver circuit operate quickly. Preferably, it is speed.

[0012] In addition, it is possible to prevent the process from becoming complicated, prevent increases in manufacturing costs, and produce multiple types of circuits on the same substrate. It forms a circuit and has multiple types of thin film transistors that are respectively matched to the characteristics of multiple types of circuits. It is also an object of the present invention to provide a semiconductor device. [Means for solving the problem]

[0013] In a bottom-gate thin film transistor, the oxide semiconductor layer overlapping the gate electrode layer An oxide insulating layer is formed to serve as a channel protection layer in contact with a part of the An oxide insulating layer is formed to cover the periphery (including the side surface) of the oxide semiconductor layer.

[0014] The oxide insulating layer covering the periphery (including the side surface) of the oxide semiconductor layer is formed by the gate electrode layer and the oxide insulating layer thereon. Increase the distance to the wiring layers (source wiring layer, capacitance wiring layer, etc.) formed on the side or in the vicinity. The oxide insulating layer covering the periphery of the oxide semiconductor layer serves as a channel protection layer. Since it is formed in the same process as the layer, the parasitic capacitance can be reduced without increasing the number of processes.

[0015] The oxide insulating layer covering the periphery (including the side surfaces) of the oxide semiconductor layer reduces parasitic capacitance. This makes it possible to suppress distortion of the signal waveform.

[0016] In order to reduce parasitic capacitance, an insulating layer with a small dielectric constant is used as the oxide insulating layer sandwiched between the wiring. It is preferred to use a rim material.

[0017] One embodiment of the present invention disclosed in this specification is a method for manufacturing a semiconductor device comprising: a gate electrode layer on an insulating surface; a gate insulating layer, an oxide semiconductor layer on the gate insulating layer, and an oxide semiconductor layer on the oxide semiconductor layer. an insulating layer, a source electrode layer or a drain electrode layer formed on the oxide insulating layer, and a source electrode layer or a drain electrode layer formed on the oxide insulating layer; the drain electrode layer has an insulating layer over it, and the oxide semiconductor layer has a first insulating layer in contact with the oxide insulating layer. a second region in contact with the source electrode layer or the drain electrode layer; and a third region in contact with the insulating layer. and a region of the first region that overlaps with the gate electrode layer via the gate insulating layer. is a channel forming region, and a third region is provided between the channel forming region and the second region. It is a semiconductor device.

[0018] The above configuration solves at least one of the above problems.

[0019] The drain electrode layer, which is made of a metal electrode such as Ti, is in contact with a part of the top surface of the oxide semiconductor layer. The oxygen-deficient high-resistivity drain region (HRD) overlaps the gate electrode layer. The source electrode layer is also called the oxidized drain region. a high-resistivity source region that is oxygen-deficient and that contacts a portion of the top surface of the compound semiconductor layer and overlaps with the source electrode layer; (also called HRS (High Resistance Source) region) is formed. do.

[0020] The source electrode layer and the drain electrode layer overlap with a channel formation region of the oxide semiconductor layer. The area of ​​the overlapping region between the gate electrode layer and the gate insulating layer is also extremely small. Since the area is extremely small or does not overlap with the gate electrode layer, the parasitic capacitance is also reduced. In addition, the width of the oxide insulating layer that functions as a channel protection layer is larger than the width of the side surface of the source electrode layer. The distance between the side surface and the side surface of the drain electrode layer facing the side surface is wider. To increase the operating speed of the capacitor, the width of the oxide insulating layer (channel When trying to design a small width (width in the longitudinal direction of the panel), the side of the source electrode layer and the The distance between the side of the drain electrode layer and the source electrode layer is also reduced. A large spacing distance is useful because of the risk of short circuits.

[0021] In the above structure, the oxide insulating layer functioning as the channel protective layer is formed by a sputtering method. The inorganic insulating film is typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, Alternatively, an aluminum oxynitride film or the like is used.

[0022] In the above structure, the oxide semiconductor layer includes an oxide insulating layer on a top surface of the oxide semiconductor layer. There is a region that does not overlap with the drain electrode layer and the source electrode layer, i.e., a third region. The width of the region in the channel length direction is determined by the patterning position of the oxide semiconductor layer and the drain electrode layer. and the patterning position of the source electrode layer. If the width in the longitudinal direction is increased, the off-state current of the thin film transistor can be reduced. In addition, if the width of the third region in the channel length direction is narrowed, the operating speed of the thin film transistor is reduced. This can increase the speed of the process.

[0023] The insulating layer in contact with the third region is also made of an inorganic insulating film using a sputtering method, typically an oxide film. silicon nitride film, silicon oxide nitride film, aluminum oxide film, aluminum oxynitride film, etc. Note that the insulating layer in contact with the third region is an oxide insulating layer functioning as a channel protective layer. When the same material is used as the first oxide insulating layer, the oxide insulating layer that functions as the channel protection layer is The insulating layer in contact with the third region can be called the second oxide insulating layer, and the first oxide semiconductor The boundary between the first oxide insulating layer and the second oxide insulating layer becomes unclear.

[0024] The oxide semiconductor layer may be, for example, InMO3(ZnO) m (m>0) A thin film is formed, and a thin film transistor is manufactured using the thin film as an oxide semiconductor layer. M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M can be Ga, or Ga and Ni, or Ga and F. In addition to Ga, the above-mentioned metal elements such as Ga may be contained in the oxide semiconductor. In addition to the metal elements contained as M, Fe, Ni and other transition metal elements are contained as impurity elements. In this specification, InM O3(ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), Ga is used as M. The oxide semiconductor with the structure containing In-Ga-Zn-O is called an In-Ga-Zn-O oxide semiconductor, and the thin film of this oxide semiconductor is called an In-Ga-Zn-O oxide semiconductor. It is also called Ga-Zn-O based non-single crystal film.

[0025] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based metal oxides can be used. The oxide semiconductor layer made of the material may contain silicon oxide.

[0026] In the above structure, the source electrode layer and the drain electrode layer are made of Ti, Mo, W, Al, C An element selected from r, Cu, Ta, or an alloy containing the above elements, or The source electrode layer and the drain electrode layer are made of an alloy or the like in which the above-mentioned elements are combined. The layer is not limited to a single layer containing the above, and a laminate of two or more layers can be used.

[0027] Furthermore, one embodiment of the present invention for realizing the above structure is to form a gate electrode on a substrate having an insulating surface. forming an electrode layer, forming a gate insulating layer on the gate electrode layer, and forming an oxide layer on the gate insulating layer; A semiconductor layer is formed, and the oxide semiconductor layer is dehydrated or dehydrogenated, and then exposed to the air. The oxide semiconductor layer is not exposed to the heat of the insulating layer, and water or hydrogen is prevented from being re-mixed into the oxide semiconductor layer. An oxide insulating layer is formed to cover the periphery and side surfaces of the oxide semiconductor layer, and a solder is formed on the oxide insulating layer. A source electrode layer and a drain electrode layer are formed, and an oxide insulating layer, a source electrode layer, a drain electrode layer, and a and a method for manufacturing a semiconductor device in which an insulating layer in contact with an oxide semiconductor layer is formed.

[0028] Dehydration or dehydrogenation is carried out using an inert gas such as nitrogen or a noble gas (argon, helium, etc.). Heating in an atmosphere at 400°C or higher but lower than the strain point of the substrate, preferably 420°C or higher and 570°C or lower This heat treatment reduces impurities such as moisture contained in the oxide semiconductor layer.

[0029] Heat treatment is carried out under an inert gas atmosphere such as nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient by heat treatment, resulting in low resistance, that is, N-type ( N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer, and a process for forming the oxide insulating film is performed. By performing heat treatment, the oxide semiconductor layer is made into an oxygen-excess state, which increases the resistance, i.e., I In addition, solid-phase oxidation is performed to place the oxide semiconductor layer in an oxygen-excess state. This allows us to obtain thin film transistors with good electrical characteristics and high reliability. Therefore, it is possible to manufacture and provide a semiconductor device that can achieve this.

[0030] The oxide semiconductor layer that has been dehydrated or dehydrogenated is Even when TDS measurements were performed on the body layer up to 450°C, two peaks of water were observed, and at least 300 The heat treatment conditions should be such that a peak that appears around 100°C is not detected. Thin film transistors using oxide semiconductor layers that have been hydrogenated or dehydrogenated are 45% or less in TDS. Even when measurements are taken down to 0°C, the water peak that appears around 300°C is not detected.

[0031] Then, the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated. When dehydrating or dehydrogenating, the same furnace is used to prevent exposure to the atmosphere. It is important to prevent hydrogen from re-entering the oxide semiconductor. The body layer is made low resistance, i.e., N-type (N - After that, the oxide semiconductor is made high-resistive and becomes I-type. When a thin film transistor is fabricated using a conductor layer, the threshold voltage value of the thin film transistor can be projected. This allows realization of a so-called normally-off switching element. The channel is formed when the gate voltage of the transistor is as positive as possible to the threshold voltage of 0V. It is desirable for semiconductor devices (display devices) that the threshold voltage value of the thin film transistor is negative, current flows between the source and drain electrodes even when the gate voltage is 0V. In an active matrix display device, The electrical characteristics of the thin film transistors that make up the circuit are important, and these electrical characteristics determine the performance of the display device. In particular, the threshold voltage (Vth) is an important electrical characteristic of thin film transistors. Even if the field effect mobility is high, the threshold voltage is high, or the threshold voltage is If the threshold voltage is high, it is difficult to control it as a circuit. In the case of a thin film transistor with a large absolute value of the voltage, when the driving voltage is low, The N-channel type In the case of a thin film transistor, a channel is formed only when a positive voltage is applied to the gate. A transistor in which the drain current flows out is desirable. There are transistors in which a channel is not formed, and transistors in which a channel is formed even under negative voltage conditions and the drain current is A transistor that conducts current is not suitable as a thin film transistor for use in a circuit.

[0032] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. It is also possible to switch to a gas atmosphere, for example, by switching to air in the same furnace where dehydration or dehydrogenation was performed. The furnace is filled with high-purity oxygen gas, N2O gas, or ultra-dry air (dew point Cooling is carried out by filling the container with a temperature of -40°C or less, preferably -60°C or less.

[0033] The moisture content in the film is reduced by heat treatment for dehydration or dehydrogenation, and then the film containing moisture is Cool slowly (or cool) in an atmosphere that is free from dew (dew point is -40°C or less, preferably -60°C or less). By using the oxide semiconductor film, the electrical characteristics of thin film transistors can be improved and mass production can be achieved. This will realize thin-film transistors that are both reliable and high-performance.

[0034] In this specification, the method is carried out under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). This heat treatment is called a heat treatment for dehydration or dehydrogenation. Dehydrogenation does not only mean that hydrogen is released as H2 by the hydrogenation process, but also means that hydrogen is released as H For convenience, this term is used to refer to the elimination of OH and other groups.

[0035] Heat treatment is carried out under an inert gas atmosphere such as nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient by heat treatment, resulting in low resistance, that is, N-type ( N - To make something (such as a product).

[0036] In addition, the oxygen-deficient high-resistivity drain region (HRD region) overlaps with the drain electrode layer. In addition, a high-resistance source region (H The nucleus is then formed into a nucleus called the RS region.

[0037] Specifically, the carrier concentration in the high-resistance drain region is 1×10 18 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least 1×10 18 / cm 3 (less than) The carrier concentration in this specification is determined by Hall effect measurement at room temperature. This refers to the carrier concentration value measured.

[0038] Then, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into an oxygen-excess state. By doing so, the resistance is further increased, that is, the I-type is formed, and a channel forming region is formed. The treatment for bringing the hydrated or dehydrogenated oxide semiconductor layer into an oxygen-excess state is as follows: forming an oxide insulating film in contact with the oxide semiconductor layer by sputtering or by oxidation; Heat treatment after deposition of an insulating film, or heat treatment in an oxygen-containing atmosphere after deposition of an oxide insulating film Alternatively, after forming an oxide insulating film, the film is heated in an inert gas atmosphere and then cooled in an oxygen atmosphere. After processing, or after forming an oxide insulating film, the film is heated in an inert gas atmosphere and then dried in ultra-dry air (dew point This is done by cooling the mixture to a temperature of -40°C or lower, preferably -60°C or lower.

[0039] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (a part overlapping with the gate electrode layer) is The high-resistance region is formed by selectively creating an oxygen-excess state in the channel formation region. It is also possible to make it into a type I structure.

[0040] This allows the fabrication of a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. and can be provided.

[0041] Note that a high-resistance drain region is formed in the oxide semiconductor layer overlapping with the drain electrode layer. This makes it possible to improve the reliability of the drive circuit when it is formed. By forming a resistive drain region, the drain electrode layer, the high-resistive drain region, and the channel It is possible to form a structure in which the conductivity can be changed stepwise over the formation region. Therefore, when the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD, Even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high resistance drain region acts as a buffer. This prevents localized high electric fields from being applied, improving the breakdown voltage of the transistor. can be done.

[0042] In addition, a high-resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region, leakage in the channel formation region when forming a drive circuit is reduced. Specifically, by forming a high-resistance drain region, the drain current can be reduced. The drain electrode layer and the source electrode layer are connected as a path for the leakage current of the transistor. Drain electrode layer, high-resistance drain region on the drain electrode layer side, channel formation region, source electrode The high-resistance source region on the side of the source electrode layer is formed in this order. The leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region is The transistor is concentrated near the interface between the gate insulating layer and the channel formation region, which has high resistance when turned off. The back channel portion (the surface of the channel forming region away from the gate electrode layer) can be formed. This can reduce the leakage current in the

[0043] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices that use electrophoretic display elements and are also called electronic paper. .

[0044] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel In the element part, the gate electrode of a thin film transistor and the source wiring of another transistor, The light-emitting device has a portion to which a drain wiring is connected. In the driving circuit of the thin film transistor, the gate electrode of the thin film transistor and the source The gate electrode has a portion for connecting a wiring or a drain wiring.

[0045] In addition, thin film transistors are easily damaged by static electricity, so the gate line or source A protection circuit for protecting the thin film transistors in the pixel area can be provided on the same substrate as the line. The protection circuit is preferably configured using a nonlinear element using an oxide semiconductor layer. It's nice.

[0046] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate [Effects of the Invention]

[0047] The peripheral portion of the oxide semiconductor layer is covered with an oxide insulating layer to form a thin film transistor with reduced parasitic capacitance. In addition, by increasing the distance between the source electrode layer and the drain electrode layer, This makes it possible to realize a thin film transistor with reduced off-state current. [Brief explanation of the drawings]

[0048] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 5] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 7] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a semiconductor device. [Figure 10] 1A to 1C illustrate a semiconductor device. [Figure 11] 1A to 1C illustrate a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 13] 1A to 1C illustrate a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating an operation thereof; [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 1A and 1B are diagrams and timing charts illustrating the operation of a shift register; [Figure 18] 1A to 1C illustrate a semiconductor device. [Figure 19] 1A to 1C illustrate a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Figure 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C illustrate a semiconductor device. [Figure 25] 1A to 1C illustrate a semiconductor device. [Figure 26] 1A to 1C illustrate a semiconductor device. [Figure 27] 1A to 1C illustrate a semiconductor device. [Figure 28] 1A to 1C illustrate a semiconductor device. [Figure 29] 1A to 1C illustrate a semiconductor device. [Figure 30] 1A to 1C illustrate a semiconductor device. [Figure 31] 1A to 1C illustrate a semiconductor device. [Figure 32] 1A to 1C illustrate a semiconductor device. [Figure 33] 1A to 1C illustrate a semiconductor device. [Figure 34] 1A to 1C illustrate a semiconductor device. [Figure 35] 1A to 1C illustrate a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0049] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0050] (Embodiment 1) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. and explain.

[0051] FIG. 1A is a plan view of a channel protective thin film transistor 448 disposed in a pixel. 1(B) is a cross-sectional view taken along line D1-D2 in FIG. 1(A) and a cross-sectional view taken along line D5 in FIG. 1(A). FIG. 1C is a cross-sectional view taken along line D3-D4 in FIG. 1A. It is a cross-sectional view. Note that Fig. 2(E) is the same as Fig. 1(B).

[0052] The thin film transistor 448 disposed in the pixel is a channel protection type (also called a channel stop type). 4) is a thin film transistor, and a gate electrode layer 421 is formed on a substrate 400 having an insulating surface. a, a gate insulating layer 402, an oxide semiconductor layer 442 including a channel formation region 423, The oxide insulating layer 426a serving as a protective layer, the source electrode layer 425a, and the drain electrode layer 426b are The thin film transistor 448 is covered with an oxide insulating layer 426a, a silicon oxide layer 425b, and a silicon dioxide layer 426c. An insulating layer 428 and a protective insulating layer 429 are provided in contact with the source electrode layer 425a and the drain electrode layer 425b. A planarization insulating layer 403 and a planarization insulating layer 404 are stacked. A pixel electrode layer 427 is provided in contact with the drain electrode layer 425b. 48 is electrically connected.

[0053] The pixel thin film transistor 448 includes a high resistance source region 424a overlapping the source electrode layer, The high-resistance drain region 424b overlaps with the drain electrode layer, and the high-resistance drain region 424b does not overlap with the source electrode layer. a source region 424e, a high-resistance drain region 424f that does not overlap with the drain electrode layer, and The source electrode layer 422 includes an oxide semiconductor layer 442 including a channel formation region 423. A high-resistance source region 424a is formed in contact with the bottom surface of the drain electrode 25a. A high-resistance drain region 424b is formed in contact with the lower surface of the layer 425b. The saturator 448 has two highly resistive drain regions or two highly resistive source regions, which remain stable even when a high electric field is applied. The buffer region prevents localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is composed of:

[0054] In FIG. 1B, the oxide insulating layer 426a serving as a channel protective layer and the gate electrode The region of the oxide semiconductor layer where the electrode layer overlaps with the gate insulating layer via the gate insulating layer is called a channel formation region. Therefore, the channel length L of the thin film transistor 448 is The channel length L of the thin film transistor 448 is equal to the width in the channel length direction. The length at the interface with the insulating layer 426a, that is, the length at the interface with the oxide insulating layer 426b in the cross-sectional view shown in FIG. The edge layer 426a is shown as a trapezoid, and is the length of the base of the trapezoid.

[0055] In addition, the gate wiring and source wiring crossing portion are designed to reduce parasitic capacitance. Between the gate electrode layer 421b and the source electrode layer 425a, the gate insulating layer 402 and the oxide insulating layer The oxide insulating layer 426b is provided in a region overlapping with the channel formation region 423. The oxide insulating layer 426a and the oxide insulating layer 426b in a region that does not overlap with the channel formation region 423 are different from each other. Although the layers are shown with different reference numerals, they are made of the same material and are formed in the same process.

[0056] 2A to 2E, a thin film transistor 448 and a wiring crossover are formed on the same substrate. The process of manufacturing the difference part will be explained. In addition to the pixel part, the thin film transistor of the driver circuit will also be They may be formed on the same substrate in the same process.

[0057] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. Gate electrode layers 421a and 421b are formed in the pixel area. The capacitor wiring layer is formed using the same material as 421a and 421b and the same first photolithography process. In addition, when forming a driver circuit in addition to the pixel portion, the driver circuit may require capacitance. In this case, a capacitance wiring layer is also formed on the drive circuit. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0058] The conductive film forming the gate electrode layers 421a and 421b may be Al, Cr, Ta, Ti, An element selected from Mo, W, or an alloy containing the above elements, or a combination of the above elements Also, a conductive film forming the gate electrode layers 421a and 421b may be used. The conductive film may be a light-transmitting conductive film, such as indium oxide (In2O3) or oxide Indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO) This can be done.

[0059] In this specification, a film that is transparent to visible light is a film that has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes As a metal oxide applied to the wiring layer, a conductive film that is semi-transparent to visible light is used. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0060] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point will be 730°C or higher. For the glass substrate, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boron oxide, it is more practical. Therefore, a glass substrate containing more BaO than B2O3 is used. It is preferable that

[0061] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, crystallized glass or the like may also be used.

[0062] In addition, an insulating film serving as a base film is provided between the substrate 400 and the gate electrode layers 421a and 421b. The base film has a function of preventing diffusion of impurity elements from the substrate 400, and is preferably made of silicon nitride. a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film; The insulating film can be formed by a laminated structure.

[0063] Next, the gate insulating layer 402 is formed over the gate electrode layers 421a and 421b.

[0064] The gate insulating layer 402 is formed by depositing a silicon oxide layer using a plasma CVD method, a sputtering method, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer may be formed as a single layer or a stacked layer. For example, the plasma CVD method can be performed using SiH4, oxygen, and nitrogen as the deposition gas. The thickness of the gate insulating layer 402 is 100 nm or more and 500 nm or less. In the case of a laminate, for example, the first gate electrode has a thickness of 50 nm to 200 nm. a gate insulating layer, and a second gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer; The edge layer is laminated.

[0065] In this embodiment, a silicon nitride layer having a thickness of 200 nm or less is formed by plasma CVD. This is referred to as insulating layer 402.

[0066] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed on the gate insulating layer 402. The oxide semiconductor film 430 is formed to a thickness of 20 nm or less (see FIG. 2A). Even if a heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 430, the oxide semiconductor film In order to make the oxide semiconductor amorphous, it is preferable to make the film thickness as thin as 50 nm or less. By thinning the film thickness, when a heat treatment is performed after the formation of the oxide semiconductor layer, the film is crystallized. This can prevent the item from getting dirty.

[0067] The oxide semiconductor film 430 is an In—Ga—Zn—O based non-single crystal film, an In—Sn—Zn—O based , In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O In this embodiment, an In-Ga-based, Sn-O-based, or Zn-O-based oxide semiconductor film is used. -The film is formed by sputtering using a Zn-O-based oxide semiconductor target. The semiconductor film 430 is heated under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. It can be formed by sputtering in an atmosphere of oxygen (typically argon). In addition, when using the sputtering method, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less is used. The oxide semiconductor film 430 is formed using a SiO x (X>0) This causes crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is preferable to inhibit caries.

[0068] The oxide semiconductor is preferably an oxide semiconductor containing In, more preferably an oxide semiconductor containing In and In order to make the oxide semiconductor layer i-type (intrinsic), dehydration is performed. It is effective to subject the product to a hydrogenation or dehydrogenation process.

[0069] In this embodiment, an In—Ga—Zn—O-based oxide semiconductor film is used.

[0070] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1 [molar ratio]) and set the distance between the substrate and the target at 1 00mm, pressure 0.2Pa, direct current (DC) power supply 0.5kW, argon and oxygen (argon The film is formed in an atmosphere of oxygen (oxygen flow rate: 40%). The use of a pulsed direct current (DC) power supply is preferable because it can reduce dust and make the film thickness distribution uniform. The thickness of the In-Ga-Zn-O based non-single crystal film is preferably 5 nm to 200 nm. In this embodiment, an In-Ga-Zn-O based oxide semiconductor target is used as the oxide semiconductor film. A 20 nm thick In-Ga-Zn-O non-single crystal film is formed by sputtering using .

[0071] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0072] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0073] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0074] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0075] Next, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0076] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than the distortion point of the substrate, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. For example, the heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is prevented from being exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. In this embodiment, a semiconductor layer is obtained by a heating method for dehydrating or dehydrogenating an oxide semiconductor layer. From temperature T, use the same furnace to a temperature high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below T. First, dehydration or dehydrogenation is performed under a rare gas atmosphere such as helium, neon, or argon. cormorant.

[0077] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0078] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. It may also be a crystalline or polycrystalline film.

[0079] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 430 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0080] Before the oxide semiconductor film 430 is formed, an inert gas atmosphere (nitrogen, helium, or neodymium) is used. Heat treatment (400°C or higher but below the distortion point of the substrate) in an oxygen atmosphere (e.g., argon) ) to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0081] Next, an oxide insulating film was formed over the gate insulating layer 402 and the oxide semiconductor layer by a sputtering method. After the formation of the resist mask, a third photolithography process is performed to selectively etch the resist mask. After that, the resist mask is removed. At this stage, a region in contact with the oxide insulating layer is formed in the oxide semiconductor layer. Among these, the oxide insulating layer 426a overlaps with the gate electrode layer with the gate insulating layer interposed therebetween. The oxide insulating layer covering the periphery and side surfaces of the oxide semiconductor layer becomes a channel formation region. An area overlapping layer 426b is also formed.

[0082] The oxide insulating film should have a thickness of at least 1 nm. The film can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the film. In this embodiment, a silicon oxide film with a thickness of 300 nm is deposited as an oxide insulating film by sputtering. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. The silicon oxide film is formed by sputtering using a rare gas (typically argon). In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used under an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering. The oxide insulating film formed in contact with the layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as An inorganic insulating film is used to block these substances from entering from the outside. A bare film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. do.

[0083] Next, a second heat treatment (preferably 2) is carried out under an inert gas atmosphere or a nitrogen gas atmosphere. The heating is performed at a temperature of 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower (see FIG. 2(B)). For example, the second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. As a result, an end portion of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426b and an end portion of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426c are A part of the oxide semiconductor layer 442 overlapping with the oxide insulating layer 426a is heated while being in contact with the oxide insulating layer. Note that when the second heat treatment is performed, a part of the oxide semiconductor layer 442 that does not overlap with the oxide insulating layer is The exposed portion of the oxide semiconductor layer 442 is heated. When heat treatment is performed in an inert gas atmosphere or an inert gas atmosphere, the exposed portion of the oxide semiconductor layer 442 is The high resistance (I-type) region can be made low resistance. The layer 426a is provided over and in contact with a region that serves as a channel formation region of the oxide semiconductor layer 442. It functions as a channel protection layer.

[0084] Next, the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer 4 After forming a conductive film on 42, a resist mask is formed by a fourth photolithography process. The source electrode layer 425a and the drain electrode layer 425 are formed by selectively etching the source electrode layer 425a and the drain electrode layer 425b. The conductive film is formed by sputtering or vacuum deposition (electron The method used is the arc discharge ion plating method, or the spray method. The conductive film is made of an element selected from Ti, Mo, W, Al, Cr, Cu, and Ta, or The conductive film is made of an alloy containing the above elements or an alloy combining the above elements. The layer is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers. In this embodiment, a conductive film having a three-layer structure of a titanium film, an aluminum film, and another titanium film is formed. A titanium nitride film may be used in place of the Ti film.

[0085] In the fourth photolithography step, only the conductive film in contact with the oxide semiconductor layer is formed. Therefore, only the conductive film in contact with the oxide semiconductor layer is selectively removed. To effectively remove the oxides, an alkaline etchant containing ammonia and hydrogen peroxide (31% by weight) was used. By using hydrogen water: 28% by weight ammonia water: water = 5:2:2, the conductive film can be selectively and leaving an oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor. can be done.

[0086] Note that a resist mask for forming the source electrode layer 425a and the drain electrode layer 425b is used. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0087] Next, the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 An insulating layer 428 and a protective insulating layer 403 are formed over 5b. In this embodiment, a sputtering method is used. The insulating layer 428 of a silicon oxide film and the protective insulating layer 403 of a silicon nitride film are laminated using the above method. .

[0088] Note that the boundary between the oxide insulating layer 426a and the insulating layer 428 is not shown in the drawing for clarity. Although shown in the figure, in reality, the difference is unclear because both are silicon oxide films formed by the same sputtering method.

[0089] The RF sputtering method is suitable for mass production and is therefore preferable as a method for forming the protective insulating layer 403. The protective insulating layer 403 is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as The inorganic insulating film blocks the penetration of silicon nitride, aluminum nitride, A silicon nitride oxide film, an aluminum oxynitride film, or the like is used. It is an insulating film having such properties.

[0090] Next, a planarization insulating layer 404 is formed over the protective insulating layer 403. Examples include polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant organic materials such as grease can be used. Dielectric materials (low-k materials), siloxane resins, PSG (phosphor glass), BPSG (phosphor glass) In addition, insulating films made of these materials can be used in multiple layers. The planarization insulating layer 404 may be formed by stacking several layers.

[0091] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0092] The method for forming the planarization insulating layer 404 is not particularly limited, and may be a sputtering method, a SO 4 method, or the like, depending on the material. G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing machines, such as offset printing, doctor knives, roll coaters, curtain coaters, A knife coater or the like can be used.

[0093] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 4, the insulating layer 428 and the protective insulating layer 403 are etched to form the drain electrode layer 425b. Then, a contact hole 441 is formed, which reaches the substrate 41, and the resist mask is removed (see FIG. 2(D)). As shown in FIG. 2(D), an oxide insulating layer 426b is provided below the contact hole. This reduces the amount of heat generated by the oxide insulating layer provided below the contact hole compared to when no oxide insulating layer is provided below the contact hole. The thickness of the planarization insulating layer to be removed can be reduced, and the etching time can be shortened. The contact hole has a larger insulating oxide layer than when no insulating oxide layer is provided below the contact hole. The depth of the contact hole 441 can be made shallow, and in the area overlapping with the contact hole 441, The coverage of a light-transmitting conductive film formed in a later step can be improved. In addition, a contact hole reaching the gate electrode layer 421b is also formed by this etching. In addition, a resist pattern is formed to form a contact hole that reaches the drain electrode layer 425b. The resist mask may be formed by an ink-jet method. When formed, no photomask is used, thereby reducing manufacturing costs.

[0094] Next, a light-transmitting conductive film is formed. Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT The transparent conductive film (abbreviated as O) is formed by sputtering or vacuum deposition. As another material for the conductive film, a nitrogen-containing Al-Zn-O-based non-single crystal film, i.e., Al-Zn- ON-based non-single crystal film, Zn-ON-based non-single crystal film, Sn-Zn-ON-based non-single crystal film The composition ratio (atomic %) of zinc in the Al-Zn-ON non-single crystal film may be: The composition ratio (atomic %) of aluminum in the non-single crystal film is 47 atomic % or less, which is larger than the composition ratio (atomic %) of aluminum in the non-single crystal film. The aluminum composition ratio (atomic %) in the crystalline film is the same as the nitrogen composition ratio (atomic %) in the non-single-crystalline film. The etching process for such materials is carried out with a hydrochloric acid-based solution. ITO etching tends to leave residue, so we used an oxidizing agent to improve etching processability. An indium zinc oxide alloy (In2O3-ZnO) may also be used.

[0095] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0096] Next, a sixth photolithography step is performed to form a resist mask, and then etching is performed. Then, unnecessary portions are removed to form a pixel electrode layer 427, and the resist mask is removed (FIG. 2( See E). ).

[0097] By the above steps, a thin film transistor 448 and a semiconductor device 449 are formed on the same substrate using six masks. It is possible to fabricate wiring intersections with reduced parasitic capacitance. 8 is a high-resistance source region 424a overlapping the source electrode layer, a high-resistance drain region 424b overlapping the drain electrode layer, a drain region 424b, a high-resistance source region 424e that does not overlap with the source electrode layer, and a drain The high-resistance drain region 424f, which does not overlap with the electrode layer, and the oxide including the channel forming region 423 The thin film transistor is a channel-protective thin film transistor including a nitride semiconductor layer 442. Resistor 448 has two highly resistive drain regions or two highly resistive solenoids that remain stable even under high electric fields. The source region acts as a buffer, preventing the application of a localized high electric field, improving the breakdown voltage of the thin film transistor. In addition, by increasing the distance between the source electrode layer and the drain electrode layer, As a result, the off-state current of the thin film transistor is reduced.

[0098] In addition, the storage capacitor formed by the capacitance wiring layer and the capacitance electrode with the gate insulating layer 402 as a dielectric is The thin film transistor 448 and the storage capacitor can be formed on the same substrate. The pixels are arranged in a matrix to form an active matrix display device. For convenience, this specification will refer to such a substrate as an This is called an active matrix substrate.

[0099] In addition, thin film transistors of the driver circuits can be provided on the same substrate. By forming the driving circuit and the pixel section, the wiring connecting the driving circuit and the external signal can be shortened, This allows for miniaturization and cost reduction of semiconductor devices.

[0100] The oxide semiconductor layer 442 of the pixel thin film transistor 448 shown in FIG. 1B is an oxide semiconductor layer. The first region 424c and the second region 424d overlapping the oxide insulating layer 426b are located at the periphery. The first region 424c and the second region 424d, which are peripheral portions of the oxide semiconductor layer 442, are The same oxygen-excess state as the channel formation region 423 is present, and there are wiring and oxide semiconductors with different potentials nearby. When a conductor layer is disposed, it is possible to reduce leakage current and parasitic capacitance.

[0101] In particular, in the driver circuit, in order to achieve high integration, the spacing between multiple wirings and multiple oxide semiconductor layers is The oxide insulating layer 426b is preferably disposed so as to overlap the first region 424c and the second region 424d. It is effective to provide the second region 424d to reduce leakage current and parasitic capacitance. In addition, when multiple thin film transistors are arranged in series or in parallel, The oxide semiconductor layer of each element is made into one island, and each element is isolated by an oxide insulating layer 42. The region overlapping with the oxide insulating layer 426b is used as an element isolation region. In this way, it is possible to arrange multiple thin film transistors in a small area. Therefore, the driver circuit can be highly integrated.

[0102] (Embodiment 2) In this embodiment mode, the thin film transistor described in Embodiment Mode 1 is used to form a pixel on the same substrate. An example of forming a pixel portion and a driver circuit to fabricate an active matrix liquid crystal display device will be shown.

[0103] An example of the cross-sectional structure of an active matrix substrate is shown in FIG.

[0104] In the first embodiment, the thin film transistors and the wiring intersections of the pixel portion are illustrated. In this state, in addition to the thin film transistors and wiring intersections, the thin film transistors of the drive circuit and the storage capacitors The capacitor, gate wiring, and source wiring terminals are also shown in the figure. The terminal portion of the wire can be formed by the same manufacturing process as that shown in Embodiment Mode 1.

[0105] In FIG. 3A, the thin film transistor 220 electrically connected to the pixel electrode layer 227 is This is a channel protection type thin film transistor provided in a pixel portion. The same structure as the thin film transistor 448 of the first embodiment is used.

[0106] The gate electrode layer of the thin film transistor 220 is formed of the same material and in the same process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is connected to the capacitor electrode 231 via the gate insulating layer 202 which serves as a dielectric. The capacitor electrode 231 overlaps with the source of the thin film transistor 220. It is formed from the same metal material and in the same process as the source electrode layer or the drain electrode layer.

[0107] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is connected to the pixel electrode layer 2 27 is electrically connected to the

[0108] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping the gate insulating layer therebetween.

[0109] In addition, in FIG. 3A, the storage capacitor forms a large capacitance, so the capacitance wiring layer and the capacitance voltage Only the gate insulating layer 202 is provided between the electrodes, and the wiring intersections are The gate insulating layer 202 and the oxide insulating layer 203 are formed between the gate electrode layer 421b and the wiring formed thereon. In the storage capacitor, a gate insulating layer 266b is provided between the capacitor wiring layer and the capacitor electrode. If only the edge layer 202 is left, the etching to remove the oxide insulating layer 266b is selectively Select etching conditions or a material for the gate insulating layer so that only the gate insulating layer 202 remains. In this embodiment, the oxide insulating layer 266b is formed using a silicon oxide film, a silicon dioxide film, or a silicon dioxide film obtained by a sputtering method. Since the gate insulating layer 202 is a silicon nitride film obtained by the plasma CVD method, it can be selectively removed. Note that the oxide insulating layer 266b and the gate insulating layer 202 can be etched under the same etching conditions. When using a material that can be removed under certain conditions, a portion of the gate insulating layer is thinned by etching. Even if the gate insulating layer is removed, at least the gate insulating layer remains and a capacitance can be formed. In order to increase the storage capacitance, it is preferable to make the thickness of the gate insulating layer thin. Therefore, the gate insulating layer on the capacitance wiring is selectively etched during the selective etching of the oxide insulating layer 266b. A thin film configuration may also be used.

[0110] The thin film transistor 260 is a channel protection type thin film transistor provided in the drive circuit. The channel length L is shorter than that of the thin film transistor 220, and the operating speed is increased. The channel length of the channel protection type thin film transistor provided in the drive circuit is It is preferable that L is 0.1 μm or more and 2 μm or less. has a structure different from that of the thin film transistor 220, and has a source electrode layer 265a and a drain electrode layer An electrode layer 265b is formed to overlap the oxide insulating layer 266a.

[0111] The thin film transistor 260 is formed by forming a gate electrode layer 261, a gate electrode layer 262, a gate electrode layer 263, a gate electrode layer 264, a gate electrode layer 265, a gate electrode layer 266, a gate electrode layer 267, a gate electrode layer 268, a gate electrode layer 269 ... a source insulating layer 202, at least a channel forming region 263, a high resistance source region 264a, and the oxide semiconductor layer having the high-resistance drain region 264b, the source electrode layer 265a, and the drain electrode layer The oxide insulating layer 26 6a is provided.

[0112] In addition, the gate electrode layer of the thin film transistor 260 of the driving circuit is provided above the oxide semiconductor layer. In this case, the thin film transistor 264 may be electrically connected to the conductive layer 267. A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227. Using the same photomask as the tact hole, the planarization insulating layer 204, the insulating layer 216, and the protective insulating layer The layer 203, the oxide insulating layer 266b, and the gate insulating layer 202 are selectively etched to form contact A contact hole is formed between the conductive layer 267 and the thin film contact of the drive circuit through this contact hole. The gate electrode layer 261 of the transistor 260 is electrically connected.

[0113] The insulating layer 216 is made of an inorganic insulating film, such as a silicon oxide film, an aluminum oxide film, or an oxynitride film. A silicon film, an aluminum oxynitride film, or the like is used. In this embodiment, a film obtained by sputtering is used. A silicon oxide film is used.

[0114] The protective insulating layer 203 is made of an inorganic insulating film, such as a silicon nitride film, an aluminum nitride film, or a silicon nitride oxide film. In this embodiment, a bare film, an aluminum oxynitride film, or the like is used. A silicon nitride film is used.

[0115] In addition, the thin film transistor 260 has a width of the gate electrode layer 261 (width in the channel length direction) ) is wider than the oxide semiconductor layer. The oxide semiconductor layer 261 overlaps with the peripheral edge of the oxide semiconductor layer 261 . The oxide insulating layer 266b widens the gap between the drain electrode layer 265b and the gate electrode layer 261. , reducing the parasitic capacitance formed between the drain electrode layer 265b and the gate electrode layer 261. In addition, the first region 2 of the oxide semiconductor layer overlapping with the oxide insulating layer 266b The second region 264c and the second region 264d are in the same oxygen-excess state as the channel formation region 263. It also serves to reduce the leakage current and parasitic capacitance.

[0116] Also, a plurality of gate wirings, source wirings, and capacitance wiring layers are provided depending on the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate wiring, a source wiring, a second terminal electrode having the same potential as the capacitor wiring layer, a third terminal electrode having the same potential as the capacitor wiring layer, and so on are arranged in a row. The number of each terminal electrode may be any number. The contractor should make the appropriate decision.

[0117] In the terminal portion, the first terminal electrode having the same potential as the gate wiring is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good conductivity. The contact hole is electrically connected to the gate wiring. The wiring electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that used for the contact holes for connecting the planarization insulating layer 204 and the insulating layer 216, the protective insulating layer 203, the oxide insulating layer 266b, and the gate insulating layer 202 are selectively etched. Mix and form.

[0118] The second terminal electrode 255, which has the same potential as the source line 254 of the terminal portion, is connected to the pixel electrode layer 227. The second terminal electrode 255 can be formed of a material having the same light-transmitting property as the source wiring. The source wiring is electrically connected to the source wiring through a contact hole that reaches the line 254. The line is a metal wiring, and is made of the same material as the source electrode layer 265a of the thin film transistor 260. They are formed in the process and are at the same potential.

[0119] The third terminal electrode, which has the same potential as the capacitor wiring layer 230, has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitor wiring layer 230 can be formed of a material having the above-mentioned properties. The contact holes are formed at the same time as the contact holes for electrically connecting the capacitor electrodes 231 to the pixel electrode layer 227. The same photomask can be used in the same process.

[0120] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between the substrate and the counter substrate on which the counter electrode is provided, and an active matrix The substrate and the counter substrate are fixed together. The counter electrode is electrically connected to the counter substrate. A common electrode is provided on the active matrix substrate, and a fourth terminal is electrically connected to the common electrode. The fourth terminal electrode is provided at the terminal portion. This fourth terminal electrode is connected to the common electrode at a fixed potential, for example, GND, 0 The fourth terminal electrode is a terminal for setting V, etc. The fourth terminal electrode has the same light-transmitting property as the pixel electrode layer 227. The insulating film may be formed of a material having the following properties:

[0121] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the wiring layers, a common sputtering target and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gases, resulting in reduced manufacturing costs. It is possible.

[0122] In the structure of FIG. 3A, a photosensitive resin material is used as the planarization insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0123] FIG. 3(B) shows a cross-sectional structure that is partially different from that shown in FIG. 3(A). A) The absence of the planarization insulating layer 204 at the terminal portion and the structure of the thin film transistor of the driving circuit Since the same parts are the same except for the difference in In FIG. 3B, a thin film transistor 270 using metal wiring is disposed. Furthermore, the terminal electrodes are formed using the same material and process as the metal wiring.

[0124] In the structure of FIG. 3(B), a photosensitive resin material is used as the planarization insulating layer 204. Therefore, the step of forming a resist mask can be omitted. In this case, the planarization insulating layer 204 may not be present in the terminal portion. The absence of a planarizing insulating layer makes it easier to make a good connection with the FPC.

[0125] The thin film transistor 270 is formed by forming a gate electrode layer 271, a gate electrode layer 272, a gate electrode layer 273, a gate electrode layer 274, a gate electrode layer 275, a gate electrode layer 276, a gate electrode layer 277, a gate electrode layer 278, a gate electrode layer 279 ... The source insulating layer 202, at least the channel forming region 273, the high resistance source region 274a, and the oxide semiconductor layer having the high-resistance drain region 274b, the source electrode layer 275a, and the drain electrode layer The drain electrode layer 275b is also an oxide insulating layer 27 6a is provided on the source electrode layer 275a and the drain electrode layer 275b. An insulating layer 216 and a protective insulating layer 203 are provided.

[0126] In addition, the first region 274c and the second region 274d of the oxide semiconductor layer overlap with the oxide insulating layer 276b. 4d is in the same oxygen-excess state as the channel formation region 273, and is effective in reducing leakage current and reducing parasitic The insulating layer 216 also serves to reduce parasitic capacitance. The third region 274e is provided between the channel forming region 273 and the high resistance source region 274a. The fourth region 274f of the oxide semiconductor layer in contact with the insulating layer 216 is a channel formation region. The oxide layer 216 is formed between the high-resistance drain region 273 and the high-resistance drain region 274b. The third region 274e and the fourth region 274f of the semiconductor layer can reduce the off current. do.

[0127] In addition, the channel protection type thin film transistor has a channel length L of the channel formation region shortened. To achieve this, the width of the oxide insulating layer is narrowed, and the source electrode layer and the drain electrode layer are formed on the narrow oxide insulating layer. If an oxide electrode layer is provided, there is a risk of short-circuiting on the oxide insulating layer. The source electrode layer 275a and the drain electrode layer 275b are formed at positions away from the insulating layer 276a. This is a configuration in which

[0128] In addition, the gate electrode layer of the thin film transistor 270 of the driving circuit is provided above the oxide semiconductor layer. Alternatively, the insulating layer 274 may be electrically connected to the conductive layer 277 .

[0129] The second terminal electrode 257, which has the same potential as the source line 256 of the terminal portion, is connected to the pixel electrode layer 227. The source wiring is a metal wiring, and can be formed of a thin film. The source electrode layer 275a of the transistor 270 is formed of the same material and in the same process, and has the same potential. be.

[0130] In addition, thin film transistors are easily damaged by static electricity, etc. It is preferable that a protection circuit be provided over the same substrate as the protection circuit. It is preferable to configure it using a nonlinear element. For example, the protection circuit is In this embodiment, a plurality of protection circuits are provided between the terminal and the signal line input terminal. In this case, a surge voltage is applied to the scanning lines, signal lines, and capacitance bus lines due to static electricity, etc., and the pixel transistors are turned off. It is designed to prevent damage to transistors, etc. Therefore, the protection circuit has a surge current When a voltage is applied, the charge is released to the common wiring or the common wiring. The protection circuit is composed of nonlinear elements arranged in parallel with the scanning lines. The element consists of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it is possible to form it in the same process as the thin film transistor 220 in the pixel portion. For example, by connecting the gate terminal and the drain terminal, it can have the same characteristics as a diode. It is possible.

[0131] Note that the step of forming the planarization insulating layer 204 may be omitted, and a structure without the planarization insulating layer 204 may be used. In this case, the pixel electrode layer 227 and the second terminal electrode 255 may be formed on the protective insulating layer 203. It is placed adjacent to the

[0132] This embodiment mode can be freely combined with Embodiment Mode 1.

[0133] (Embodiment 3) In this embodiment, one of the configurations of the terminal portion provided on the same substrate as the thin film transistor is In the second embodiment, an example of the terminal portion of the source wiring is shown. Illustrated are the terminal portions of the source wiring and the gate wiring, which have different configurations from those of the second embodiment. In FIG. 4, the same parts as those in FIG. 3(A) or 3(B) are designated by the same reference numerals. explain.

[0134] 4(A1) and 4(A2) are a cross-sectional view and a top view of the gate line terminal portion, respectively. FIG. 4(A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 4(A2). In (A1), the conductive layer 225 formed on the lamination of the insulating layer 216 and the protective insulating layer 203 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, the first terminal 221 is formed of the same material as the gate electrode layer 421b in FIG. and a connection electrode layer 223 formed of the same material as the source wiring, with the gate insulating layer 202 interposed therebetween. The two overlap and are electrically connected by a conductive layer 225 .

[0135] 4(B1) and 4(B2) are different from the source line terminal portion shown in FIG. 3(B). 4(B1) shows a cross-sectional view and a top view of the source wiring terminal portion. This corresponds to a cross-sectional view taken along the line C3-C4 in FIG. 4(B2). The conductive layer 225 formed on the stack of the layer 216 and the protective insulating layer 203 functions as an input terminal. In FIG. 4(B1), the terminal portion is a terminal electrode for connection with the gate wiring. An electrode layer 226 made of the same material is formed on the second terminal 22 which is electrically connected to the source line. The electrode layer 226 is electrically connected to the second terminal 222. The electrode layer 226 is not electrically connected to the second terminal 222, and is at a different potential from the second terminal 222, for example, a floating potential. Setting the input to GND, 0V, etc. will allow you to set capacitance for noise prevention or static electricity prevention. The second terminal 222 is electrically connected to the insulating layer 216 and the protective insulating layer 218. The layer 203 is electrically connected to the conductive layer 225 through a contact hole formed in the stack of layers. There are.

[0136] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0137] This embodiment mode can be freely combined with Embodiment Mode 1 or 2.

[0138] (Fourth embodiment) Here, in a liquid crystal display device in which a liquid crystal layer is sealed between a first substrate and a second substrate, A common connection portion is formed on the first substrate for electrically connecting with the counter electrode provided on the second substrate. An example in which a thin film transistor is formed as a switching element on the first substrate is shown. The manufacturing process of the common connection part is made common to the manufacturing process of the switching element of the pixel part. This allows the formation without complicating the process.

[0139] The common connection portion is disposed at a position overlapping the sealant for bonding the first substrate and the second substrate. The sealing material is electrically connected to the counter electrode via conductive particles contained in the sealing material. The common connection part is provided in a place where it does not overlap with the sealing material (excluding the pixel part), and the common connection part A paste containing conductive particles is provided separately from the sealing material so as to overlap the opposing electrode. A connection is made.

[0140] FIG. 5A is a cross section of a semiconductor device in which a thin film transistor and a common connection portion are fabricated on the same substrate. FIG.

[0141] In FIG. 5A, the thin film transistor 220 electrically connected to the pixel electrode layer 227 is This is a channel protection type thin film transistor provided in a pixel portion. The same structure as the thin film transistor 448 of the first embodiment is used.

[0142] FIG. 5B is a diagram showing an example of a top view of the common connection portion, and the chain line C5-C6 in the diagram This corresponds to the cross section of the common connection part in Fig. 5(A). The same reference numerals will be used for the parts.

[0143] The common potential line 205 is provided on the gate insulating layer 202 and is connected to the source of the thin film transistor 220. It is made of the same material and in the same process as the source electrode layer and the drain electrode layer.

[0144] The common potential line 205 is covered with a laminate of an insulating layer 216 and a protective insulating layer 203. The laminate of the insulating layer 203 and the common potential line 205 has a plurality of openings at positions where the insulating layer 203 overlaps the common potential line 205. This opening is connected to the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The contact holes are fabricated in the same process as the contact holes that connect the electrodes.

[0145] In this case, the area size is significantly different, so the contact hole in the pixel area and the common area are In addition, in FIG. 5(A), the pixel section and the common connection section are For example, the length of the chain line C5-C6 at the common connection is 500 mm. The width of a thin film transistor is less than 50 μm, and in fact it is about 10 The area size is more than twice as large, but for ease of understanding, the pixel section and common connection section are shown in Figure 5(A). The figures are shown at different scales.

[0146] The common electrode layer 206 is provided on the lamination of the insulating layer 216 and the protective insulating layer 203. It is made of the same material and in the same process as the pixel electrode layer 227 in the other region.

[0147] In this way, the manufacturing process of the common connection portion is performed in common with the manufacturing process of the switching element of the pixel portion. conduct.

[0148] A first substrate on which a pixel section and a common connection section are provided and a second substrate having an opposing electrode are then Secure it in place using a sealant.

[0149] When the sealing material contains conductive particles, the sealing material and the common connection part are overlapped with each other. For example, in a small LCD panel, the diagonal corners of the pixel area are aligned. Two common connection parts are placed over the sealing material. In addition, in large LCD panels, Four or more common connections are arranged overlapping the sealant.

[0150] The common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material. The electrode is electrically connected to the counter electrode of the substrate.

[0151] When using the liquid crystal injection method, a pair of substrates are fixed together with a sealant, and then liquid crystal is injected between the pair of substrates. In addition, when the liquid crystal dropping method is used, a sealing material is applied to the second substrate or the first substrate. After the liquid crystal is dropped, the pair of substrates are bonded together under reduced pressure.

[0152] In this embodiment, an example of a common connection portion electrically connected to the counter electrode is shown. It is not limited to, but is used for connecting parts to other wiring or connecting parts to external connection terminals, etc. It is possible.

[0153] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 3.

[0154] (Embodiment 5) In the first and second embodiments, an example in which the gate insulating layer is a single layer is shown. An example of lamination is shown below. In FIG. 6, the same parts as in FIG. 3(A) or FIG. 3(B) are will be explained using the same symbols.

[0155] In FIG. 6A, a thin film transistor 280 is a channel protective type thin film transistor provided in a pixel portion. This is an example of a thin film transistor with two gate insulating layers. It is the same as thin film transistor 220 except for one point.

[0156] In this embodiment, a first gate insulating layer 282a having a film thickness of 50 nm or more and 200 nm or less, a second gate insulating layer 282b having a thickness of 50 nm or more and 300 nm or less; The first gate insulating layer 282a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. The second gate insulating layer 282b is a silicon oxide film having a thickness of 100 nm. A bare membrane is used.

[0157] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is connected to the pixel electrode layer 2 27 is electrically connected to the

[0158] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. .

[0159] In addition, in FIG. 6(A), the storage capacitor forms a large capacitance, so the capacitance wiring and the capacitance electrode Only the gate insulating layer is provided between them.

[0160] In this embodiment, a silicon oxide film obtained by a sputtering method is used as the oxide insulating layer 282b. When removing the oxide insulating layer overlapping the capacitor wiring layer 230, the second gate insulating layer, which is a silicon oxide film, is removed. In this example, the insulating layer is also thinned by etching to form the third gate insulating layer 282c. The first gate insulating layer 282a is a silicon nitride film or a silicon nitride oxide film, and is formed by etching. It functions as a topper to prevent etching damage to the gate electrode layer and substrate.

[0161] By making the third gate insulating layer 282c thin, it is possible to increase the storage capacitance. can.

[0162] FIG. 6B shows a cross-sectional structure that is partially different from that shown in FIG. 6A.

[0163] In the thin film transistor 290 shown in FIG. 6B, the first a first gate insulating layer 292a and a second gate insulating layer 292b having a thickness of 1 nm to 50 nm; The first gate insulating layer 292a is a 100 nm thick oxide film. The second gate insulating layer 292b is a silicon nitride film having a thickness of 10 nm. A bare film or a silicon nitride oxide film is used.

[0164] The thin film transistor 290 is a channel protection type thin film transistor provided in the pixel portion. This is an example of a thin film transistor with two gate insulating layers. It is the same as Transistor 220.

[0165] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 4.

[0166] (Embodiment 6) In this embodiment, an example in which a part of the manufacturing process of a thin film transistor is different from that in Embodiment 1 is shown in FIG. 7 and 8 are the same as those in FIGS. 1 and 2 except for some differences in the process. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted.

[0167] First, according to the first embodiment, a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer are formed on a substrate. The film 430 is formed, and the steps up to the step shown in FIG. 2(A) in the first embodiment are carried out. This is the same as Figure 8(A).

[0168] Then, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. Process into body layers.

[0169] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than the distortion point of the substrate, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. For example, the heat treatment time is longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is prevented from being exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. After that, the same furnace is filled with high-purity oxygen gas, high-purity N2O gas, or ultra-dry Cooling is performed by introducing air (dew point below -40°C, preferably below -60°C). Oxygen gas Alternatively, it is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the or 7N (99.99999%) or more (i.e., impurity concentration in oxygen gas or N2O gas) It is preferable to set the concentration of the HCl-containing compound to 1 ppm or less, preferably 0.1 ppm or less.

[0170] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0171] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 430 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0172] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance It transforms it into an anti-type, i.e., type I.

[0173] Next, an oxide insulating film was formed over the gate insulating layer 402 and the oxide semiconductor layer by a sputtering method. After the formation of the resist mask, a third photolithography process is performed to selectively etch the resist mask. After that, the resist mask is removed. (See Figure 8(B)).

[0174] Next, the gate insulating layer 402, the oxide insulating layers 426a and 426b, and the oxide semiconductor layer 4 After forming a conductive film on the substrate 22, a resist mask is formed by a fourth photolithography process. The source electrode layer 425a and the drain electrode layer 425 are formed by selectively etching the source electrode layer 425a and the drain electrode layer 425b. b is formed (see FIG. 8(C)).

[0175] Next, in order to reduce the variation in the electrical characteristics of the thin film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is carried out in a nitrogen gas atmosphere. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0176] Next, the oxide insulating layers 426a and 426b, the source electrode layer 425a, and the drain electrode layer 42 An insulating layer 428 and a protective insulating layer 403 are formed on 5b.

[0177] Next, a planarization insulating layer 404 is formed over the protective insulating layer 403 .

[0178] Next, a fifth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, the protective insulating layer 403 and the insulating layer 428 are etched to form the drain electrode layer 425b Then, a contact hole 441 is formed, and the resist mask is removed (see FIG. 8(D)). .).

[0179] Next, a light-transmitting conductive film is formed.

[0180] Next, a sixth photolithography step is performed to form a resist mask, and then etching is performed. Then, unnecessary portions are removed to form a pixel electrode layer 427, and the resist mask is removed (FIG. 8( See E). ).

[0181] Through the above steps, the thin film transistor 420 and the side film 421 are formed on the same substrate using six masks. Wire crossings with reduced raw capacitance can be created.

[0182] The pixel thin film transistor 420 includes an oxide semiconductor layer 422 including a channel formation region. It is a channel-protected thin-film transistor.

[0183] FIG. 7A is a plan view of a channel protection type thin film transistor 420 disposed in a pixel. 7(B) is a cross-sectional view taken along line D7-D8 in FIG. 7(A) and a cross-sectional view taken along line D7-D8 in FIG. 7(A) is a cross-sectional view taken along line D9-D10 in FIG. It should be noted that Fig. 8(E) is the same as Fig. 7(B).

[0184] This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 5.

[0185] (Embodiment 7) In this embodiment, an example of the configuration of the storage capacitor that is different from that of the second embodiment is shown in FIG. 9(A) and This is shown in Figure 9(B). Figure 9(A) is the same as Figure 3(A) except for the configuration of the storage capacitor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor in the pixel portion.

[0186] FIG. 9(A) shows a structure in which the dielectric is a protective insulating layer 203 and a planarizing insulating layer 204, and the pixel electrode layer 2 27 and the capacitor wiring layer 250 overlapping the pixel electrode layer 227 form a storage capacitor. The capacitor wiring layer 250 is made of a material different from that of the drain electrode layer of the thin film transistor 220 in the pixel portion. The capacitor wiring layer 250 is also formed of the oxide semiconductor layer of the thin film transistor 220. The capacitor wiring layer 250 is formed using a light-transmitting conductive film. In addition, compared to the second embodiment, the photomask for patterning the capacitance wiring layer 250 is In addition, the thin film exposed by etching to form the capacitor wiring layer 250 is The etching is performed under the condition that the oxide semiconductor layer of the film transistor 220 is not removed.

[0187] The storage capacitor shown in FIG. 9A has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The storage capacitor has a light-transmitting property as a whole. By making the storage capacitor light-transmitting, the aperture ratio can be improved. do.

[0188] FIG. 9B shows an example of a storage capacitor configuration different from that shown in FIG. 9A. Since this is the same as 3(A) except for the different configuration of the storage capacitor, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0189] FIG. 9B shows a structure in which the dielectric is a gate insulating layer 202, a capacitance wiring layer 230, and the capacitance wiring layer 2 In this example, a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap with the oxide semiconductor layer 30. In addition, the capacitance electrode 231 is laminated on the oxide semiconductor layer 251 in contact therewith, and the storage capacitance The oxide semiconductor layer 251 functions as one electrode of the thin film transistor 22. The capacitor wiring layer 230 is formed of the same material and in the same process as the oxide semiconductor layer of the first embodiment. Since it is formed using the same material and process as the gate electrode layer of the transistor 220, The capacitor electrode 23 is laid out so as not to overlap with the gate wiring layer of the resistor 220. 1 is electrically connected to the pixel electrode layer 227.

[0190] The capacitor wiring layer 230 is also made of a material different from the oxide semiconductor layer of the thin film transistor 220. The capacitor electrode 231 is formed using a light-transmitting conductive film. Compared to the second embodiment, one photomask is added to pattern the capacitance electrode 231. In addition, the thin film transistor 22 exposed by etching for forming the capacitor electrode 231 is The etching is performed under the condition that the oxide semiconductor layer of SiO 2 is not removed.

[0191] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0192] The storage capacitors shown in FIGS. 9A and 9B are transparent and have the number of gate wirings. In order to increase the resolution of the displayed image by increasing the number of pixels, it is necessary to provide sufficient capacity even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0193] This embodiment mode can be freely combined with other embodiment modes.

[0194] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0195] The thin film transistors arranged in the pixel portion are formed according to the first, second, fifth and sixth embodiments. In addition, since the thin film transistors shown in the first, second, fifth and sixth embodiments are n-channel TFTs, Among the driver circuits, a part of the driver circuit that can be configured with an n-channel TFT is The thin film transistor is formed on the same substrate as the thin film transistor.

[0196] An example of a block diagram of an active matrix display device is shown in FIG. On a substrate 5300, a pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a The pixel portion 5301 has a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0197] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0198] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. The driver circuit 5304 is provided with a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), Each clock signal is a multiple of clock signals with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0199] In FIG. 14B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, thin-film transistors have lower field-effect mobility than transistors using single-crystal semiconductors. The driving circuit formed on the substrate 5300 can be configured by the film transistor. Therefore, it is possible to increase the size of the display device, reduce costs, or improve yields. do.

[0200] The thin film transistors shown in the first, second, fifth and sixth embodiments are n-channel TFTs. 15(A) and 15(B) show the configuration of a signal line driver circuit configured with n-channel TFTs. An example of the operation will be described below.

[0201] The signal line driver circuit has a shift register 5601 and a switching circuit portion 5602. The switching circuit unit 5602 includes switching circuits 5602_1 to 5602_N (N is The switching circuits 5602_1 to 5602_N are Each of the thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example where

[0202] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0203] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0204] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function of controlling the conduction state of the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 560 has a function of supplying a potential to the signal lines S1 to Sk. 3_1 to 5603_k each have a function as a switch.

[0205] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0206] Next, the operation of the signal line driver circuit of FIG. 15(A) will be explained with reference to the timing chart of FIG. 15(B). 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0207] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0208] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0209] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0210] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. It is possible to use a circuit configured with thin film transistors shown in 2, 5, and 6. In this case, the polarity of all the transistors in the shift register 5601 is set to N-channel type or P-channel type. The channel type can be configured with only one polarity.

[0211] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 16 and 17.

[0212] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, a buffer is required. The capacitor used is one that can pass a large current.

[0213] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), The signal from the path (called the previous signal OUT(n-1)(SR)) (n is a natural number between 2 and N) ) is input to the first pulse output circuit 10_1. Similarly, the signal from the n-th pulse output circuit 10_3 in the second stage or later is input. In _n, the signal from the (n+2)th pulse output circuit 10_(n+2) in the second stage (later stage Therefore, the pulse output circuit of each stage outputs a signal OUT(n+2)(SR). These generate a first output signal (O UT(1)(SR) to OUT(N)(SR)) and a second output signal input to another circuit, etc. As shown in FIG. 16(A), the signal (OUT(1) to OUT(N)) is output. Since the last two stages of the soft register do not receive the next stage signal OUT(n+2), As an example, a second start pulse SP2 and a third start pulse SP3 are separately generated. The configuration may be such that the above is input.

[0214] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0215] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H ... The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2 has The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the wiring 13, and the third input terminal 24 is electrically connected to the fourth wiring 14. are.

[0216] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 16B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0217] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are three-terminal thin film transistors. In addition to transistors (also called TFTs: Thin Film Transistors), The four-terminal thin film transistor described in the above embodiment can be used. 1 shows a symbol of the four-terminal thin film transistor 28 described in the above embodiment. The symbol of the thin film transistor 28 shown in FIG. 16(C) is the same as that of the first, second, fifth and sixth embodiments. This term refers to a four-terminal thin film transistor described in any one of the above, and will be used hereinafter in drawings etc. In this specification, a thin film transistor has two gate electrodes via a semiconductor layer. In this case, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. The gate electrode of the thin film transistor 28 is also called the upper gate electrode. a first control signal G1 input to the gate electrode and a second control signal G2 input to the gate electrode above This is an element that can perform electrical control between the In terminal and the Out terminal.

[0218] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, A configuration that allows the threshold voltage to be controlled is preferable. The threshold voltage of the thin film transistor 28 is controlled by gate electrodes above and below the channel forming region of the thin film transistor 28. A gate electrode is provided through a gate insulating film, and the potential of the upper and / or lower gate electrodes is controlled. By doing so, it is possible to control the temperature to a desired value.

[0219] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 16(B) will be described with reference to FIG. This is explained in (D).

[0220] The pulse output circuit shown in FIG. 16(D) includes the first transistor 31 to the thirteenth transistor. 16(D)). In addition, the first input terminal 21 to the fifth input terminal 43 are connected to the first input terminal 21. In addition to the input terminal 25, the first output terminal 26, and the second output terminal 27, a first high power supply potential A power supply line 51 to which VDD is supplied, a power supply line 52 to which a second high power supply potential VCC is supplied, The first transistor 31 to the thirteenth transistor are connected to the power supply line 53 to which the source potential VSS is supplied. A signal or a power supply potential is supplied to the power supply line 43. The magnitude relationship of the power supply potentials is such that the first power supply potential VDD is equal to or greater than the second power supply potential VCC, The second power supply potential VCC is set to a potential higher than the third power supply potential VSS. The fourth clock signal (CK1) to the fourth clock signal (CK4) change between H level and L level at regular intervals. It is a signal that repeats a cycle, and when it is H level it is VDD and when it is L level it is VSS. By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, The potential applied to the gate electrode of the transistor can be kept low without affecting the operation. This can reduce the shift in the threshold voltage of the transistor and suppress deterioration. Of the first transistor 31 to the thirteenth transistor 43, the first transistor 3 1. The sixth transistor 36 to the ninth transistor 39 are four-terminal thin-film transistors. It is preferable to use the first transistor 31, the sixth transistor 36 to the sixth transistor 28. The operation of the ninth transistor 39 is such that one of the electrodes serving as the source or drain is connected to A transistor that requires the node potential to be switched by a control signal from the gate electrode. The response to the control signal input to the gate electrode is fast (the rise time of the on-current This transistor can reduce malfunctions in pulse output circuits by reducing the Therefore, the threshold voltage can be controlled by using a four-terminal thin film transistor. This makes it possible to provide a pulse output circuit that can further reduce malfunctions.

[0221] In FIG. 16(D), the first terminal of the first transistor 31 is electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal the gate electrode of the ninth transistor 39 is electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. and the gate electrode of the fourth transistor 34, the gate electrode of which is electrically connected to the fourth The sixth transistor 36 has a first terminal electrically connected to the input terminal 24. 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the fourth transistor The gate electrode (the lower gate electrode and the upper gate electrode) of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (lower gate electrode and upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrodes (lower gate electrode and upper gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor 33 are electrically connected to each other. The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the twelfth transistor 42. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5. 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 are electrically connected. are electrically connected.

[0222] In FIG. 16(D), the gate electrode of the third transistor 33, the gate electrode of the tenth transistor The connection point of the gate electrode of the ninth transistor 40 and the second terminal of the ninth transistor 39 is defined as node A. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point between the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is called a node Let's call it B.

[0223] FIG. 17(A) shows the pulse output circuit described in FIG. 16(D) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the signals input to or output from the second output terminal 27.

[0224] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a second input terminal CK3 is input. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0225] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0226] In FIG. 16(D) and FIG. 17(A), the node A is set to the floating state. A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0227] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 17(B). In this case, the period 61 in FIG. 17(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0228] As shown in FIG. 17A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0229] If the ninth transistor 39 having the second potential VCC applied to its gate electrode is not present, the boot When the potential at node A rises due to the strapping operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, rises and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source are electrically connected to each other, and the gate and drain are electrically connected to each other. In addition, a large bias voltage is applied, which causes a large stress and leads to transistor deterioration. Therefore, the ninth transistor, to whose gate electrode the second power supply potential VCC is applied, By providing transistor 39, the potential of node A is However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This can suppress the deterioration of the transistor 31.

[0230] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0231] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and This allows for increased field effect mobility and reduced degradation. In addition, a transistor using an oxide semiconductor, Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is This allows the number of power supply lines to be reduced, thereby enabling the circuit to be made smaller.

[0232] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 the clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38 The voltage supplied to the gate electrodes (lower gate electrode and upper gate electrode) by the second input terminal 22 is The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). a clock signal provided by the second input terminal 22 to the gate electrode of the eighth transistor; The gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode 38 are connected to the third input terminal 23. Therefore, the same effect can be achieved by rearranging the wiring so that the clock signal is supplied. At this time, in the shift register shown in FIG. 17(A), the seventh transistor 37 and The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 The potential at node B decreases as a result of the potential at node B decreasing. due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, when the shift register shown in FIG. 17(A) is operated in the period of FIG. 17(B), As shown in 61, the seventh transistor 37 and the eighth transistor 38 are both in an on state. Then, the seventh transistor 37 is turned on and the eighth transistor 38 is turned off. By turning off the seventh transistor 37 and the eighth transistor 38, , the potential of the second input terminal 22 and the third input terminal 23 decreases, The potential drop is reduced once by the drop in the potential of the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 (the lower gate electrode and A clock signal is supplied to the upper gate electrode of the eighth transistor from the third input terminal 23. The second input terminal 22 is connected to the gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode 38. to It is preferable to have a wired connection in which a clock signal is supplied from the node B. This is because the number of times the potential changes can be reduced and noise can also be reduced.

[0233] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, It is possible to suppress malfunction of the output circuit.

[0234] (Embodiment 9) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. The transistor and part or the whole of the driver circuit are formed on the same substrate as the pixel section, On-panel formation is possible.

[0235] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) luminescence elements, organic EL elements, etc. Also, electronic ink A display medium whose contrast changes due to an electrical effect can also be applied.

[0236] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after the film is formed and before the pixel electrode is formed by etching, All forms apply.

[0237] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0238] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 10(A1) and 10(A2) show the thin film transistors 4010 and 4011 and the liquid crystal display device. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. 10(A1) and 10(A2) are plan views of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0239] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0240] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 10(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0241] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The insulating layers 4041a and 4041b are formed on the thin film transistors 4010 and 4011. 41b, 4042a, 4042b, 4020, and 4021 are provided.

[0242] The thin film transistors 4010 and 4011 are made of the oxide semiconductor shown in the first, second, fifth and sixth embodiments. A highly reliable thin film transistor including a dielectric layer can be applied. The transistor 4011 is the thin film transistor 26 shown in the first, second, fifth and sixth embodiments. 0, 270, and the thin film transistor 4010 for the pixel is a thin film transistor 420, 4 In this embodiment, thin film transistors 48, 220, 280, and 290 can be used. The transistors 4010 and 4011 are n-channel thin film transistors.

[0243] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0244] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0245] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film A room can be used.

[0246] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0247] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0248] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0249] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In this example, the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment, and the materials of the polarizing plate and the colored layer and The conditions may be appropriately set depending on the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0250] The thin film transistor 4011 includes an insulating layer 4041a which functions as a channel protection layer and an oxide film. An insulating layer 4041b is formed to cover the peripheral portion (including the side surface) of the compound semiconductor layer. The thin film transistor 4010 includes an insulating layer 4042a that functions as a channel protection layer and an oxide film. An insulating layer 4042b is formed to cover the peripheral portion (including the side surface) of the compound semiconductor layer.

[0251] Insulating layers 4041b and 4041c are oxide insulating layers that cover the periphery (including the side surfaces) of the oxide semiconductor layer. 042b is a gate electrode layer and a wiring layer (such as a source wiring layer) formed above or around the gate electrode layer. The distance between the insulating layer 40 and the capacitor wiring layer can be increased, thereby reducing the parasitic capacitance. 41a, 4041b, 4042a, and 4042b are the oxide insulating layers 42 shown in the first embodiment. The same materials and methods as those for the thin film transistors 6a and 426b may be used. In order to reduce unevenness, the surface is covered with an insulating layer 4021 that functions as a planarizing insulating film. Here, the insulating layers 4041a, 4041b, 4042a, and 4042b are Using Form 1, a silicon oxide film is formed by sputtering.

[0252] In addition, an insulating layer 4020 is formed on the insulating layers 4041a, 4041b, 4042a, and 4042b. The insulating layer 4020 is formed by the insulating layer 428 and the protective insulating layer 403 shown in Embodiment 1. Although the single layer is shown in FIG. 10(B), , an insulating layer 428 and a protective insulating layer 403 made of a different material from the insulating layer 428. As the insulating layer 4020, a silicon oxide film and a silicon nitride film are formed by sputtering. The base film is laminated.

[0253] An insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using the same material and method as the planarization insulating layer 404 shown in Embodiment 1. , acrylic resin, benzocyclobutene resin, polyamide, epoxy resin, etc. In addition to the above organic materials, low dielectric constant materials (low -k materials), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass) It is possible to use a plurality of insulating films made of these materials. Then, the insulating layer 4021 may be formed.

[0254] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0255] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a baking machine. By using both, it becomes possible to manufacture a semiconductor device efficiently.

[0256] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0257] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0258] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0259] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0260] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0261] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0262] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0263] FIG. 19 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0264] FIG. 19 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0265] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0266] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0267] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0268] (Embodiment 10) An example of electronic paper will be shown as one mode of the semiconductor device.

[0269] Electronic paper that uses elements electrically connected to switching elements to drive electronic ink Electronic paper is also called an electrophoretic display. It has the same readability as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0270] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0271] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0272] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0273] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by thin film transistors can be used.

[0274] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0275] Figure 18 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiment 1. The thin film transistor can be fabricated in the same manner as the oxide semiconductor layer, and is highly reliable. The thin film transistors shown in the second, fifth and sixth embodiments may also be used as the thin film transistor 581 of this embodiment. It can also be applied.

[0276] The electronic paper in Figure 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0277] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The first electrode layer 587 and the insulating layer 585 are formed as a source electrode layer or a drain electrode layer. The first electrode layer 587 and the substrate 596 are in contact with each other through the opening and are electrically connected. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided that includes a cavity 594 that is filled with a liquid, The area around the pixel 589 is filled with a filler 595 such as resin. The second electrode layer 588 corresponds to a thin film transistor. It is electrically connected to a common potential line provided on the same substrate as the transistor 581. The second electrode layer 588 and the common electrode layer 589 are connected to each other via conductive particles disposed between the pair of substrates. The position line can be electrically connected.

[0278] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0279] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0280] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0281] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0282] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0283] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0284] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0285] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows an n-channel transistor using an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0286] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6402. 402, a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) The second electrode (one of the source and drain electrodes) is connected to a signal line 6405, and the second electrode (the other of the source and drain electrodes) is connected to a signal line 6405. The other end is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 through a capacitor element 6403. The first electrode is connected to a power supply line 6407, and the second electrode is connected to a first electrode (pixel The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0287] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0288] The capacitor 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 Alternatively, a capacitance may be formed between the channel region and the gate electrode.

[0289] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is either fully turned on or off. In other words, the driving transistor 6402 is in the linear region. The light emitting element driving transistor 6402 is operated in a linear region. A voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to a power supply line voltage and a light emitting element driving transistor 6402. Apply a voltage equal to or higher than the Vth of the transistor.

[0290] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0291] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply a voltage equal to or greater than the forward voltage of 6404 and the Vth of the light-emitting element driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage required to achieve a desired luminance. At least the forward threshold voltage is included. By inputting a video signal that operates in the region, a current is passed to the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in the saturation region, The potential of the transistor 407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal flows to the light emitting element 6404, Analog gray scale driving is possible.

[0292] Note that the pixel configuration shown in Fig. 12 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0293] Next, the configuration of the light emitting element will be described with reference to FIG. 13. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 13(A), (B), and (C). The TFTs 7001, 7011, and 7021, which are driving TFTs used in semiconductor devices, are actually The thin film transistor can be fabricated in the same manner as in the first embodiment, and has high reliability including an oxide semiconductor layer. The thin film transistors shown in the second, fifth and sixth embodiments are also referred to as TF It can also be applied as T7001, 7011, 7021.

[0294] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0295] A light emitting element with a top emission structure will be described with reference to FIG.

[0296] In FIG. 13A, a TFT 7001 for driving a light emitting element is an n-type TFT, and a light emitting element 700 13(A) shows a cross-sectional view of a pixel when light emitted from the cathode 2 exits to the anode 7005 side. ) the cathode 7003 of the light emitting element 7002 and the TFT 7001 which is the driving TFT are flattened. Contact holes formed in the insulating layer 7007, the protective insulating layer 7000, and the insulating layer 7006 The contact holes are electrically connected to each other through the contact holes, and a partition wall 7009 is provided on the contact holes. A light-emitting layer 7004 and an anode 7005 are stacked in this order on a cathode 7003. The cathode 7003 is Various materials can be used as long as they have a small work function and are conductive and reflective. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 is It can be made up of a single layer or multiple layers stacked together. When the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, and a light emitting layer are arranged on the cathode 7003. The layer, the hole transport layer, and the hole injection layer are laminated in this order. The anode 7005 is formed using a light-transmitting conductive material, for example, an oxide film. Tungsten-containing indium oxide, tungsten oxide-containing indium zinc oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, and indium oxide with silicon oxide added A light-transmitting conductive film such as a tin oxide film may also be used.

[0297] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 13(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0298] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. The TFT 7011 is n-type, and light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side. FIG. 13(B) shows a cross-sectional view of a pixel in the case where a light-emitting element driving TFT 7011 and a The cathode 7013 of the light-emitting element 7012 is formed on the electrically conductive film 7017 having light-transmitting properties. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 is light-transmitting, a light-reflecting or light-blocking layer is provided so as to cover the anode. A shielding film 7016 for shielding may be formed on the cathode 7013. As in the case of the first embodiment, various conductive materials with small work functions can be used. However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer or a plurality of layers, as in FIG. The anode 7015 is a light-transmitting layer. Although not necessary, the insulating film 11 may be formed using a light-transmitting conductive material as in FIG. 13(A). The shielding film 7016 can be made of, for example, a metal that reflects light. The material is not limited to a metal film, and for example, a resin to which a black pigment is added may also be used.

[0299] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 13B, light emitted from the light-emitting element 7012 corresponds to As shown by the arrow, the light is emitted to the cathode 7013 side. In this example, a light-transmitting conductive film is used. , and are emitted through the gate electrode layer.

[0300] Next, a light emitting element with a dual emission structure will be described with reference to FIG. In the example, a light-transmitting conductive film 702 electrically connected to a light-emitting element driving TFT 7021 is A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. 7024 and an anode 7025 are laminated in this order. The cathode 7023 is the same as in FIG. Similarly, various conductive materials with small work functions can be used. The thickness of the cathode 702 is set to a level that allows light to pass through. For example, Al having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be formed as a single It may be configured as a layer or as a laminate of multiple layers. The anode 7025 is made of a light-transmitting conductive material, similar to that shown in FIG. 13(A). It can be formed by

[0301] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 13C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0302] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0303] In addition, a thin film transistor (TFT for driving light-emitting elements) that controls the driving of light-emitting elements and a light-emitting element In the example shown, the current control TFT is electrically connected between the driving TFT and the light emitting element. The configuration may also be such that FT is connected.

[0304] The semiconductor device is not limited to the configuration shown in FIG. 13, and may be any of the semiconductor devices disclosed in this specification. Various modifications based on the technical concept are possible.

[0305] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 11. FIG. 11(A) shows a thin film formed on a first substrate. A panel in which a film transistor and a light-emitting element are sealed between a second substrate and the panel by a sealant. 11(B) is a plan view of the device, and FIG. 11(B) corresponds to a cross-sectional view taken along line HI in FIG. 11(A).

[0306] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0307] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0308] The thin film transistors 4509 and 4510 are made of the oxide semiconductor shown in the first, second, fifth, and sixth embodiments. A highly reliable thin film transistor including a dielectric layer can be applied. The transistor 4509 may be the thin film transistor 26 shown in the first, second, fifth and sixth embodiments. 0, 270, and the thin film transistor 4510 for the pixel is the thin film transistor 420, 4 In this embodiment, thin film transistors 48, 220, 280, and 290 can be used. Transistors 4509 and 4510 are n-channel thin film transistors.

[0309] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the channel forming region. By placing the gate electrode at a position overlapping the channel formation region of the semiconductor layer, the The amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a metal or a silicon dioxide film, and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0310] The thin film transistor 4509 has an insulating layer 4541a functioning as a channel protective layer and an oxide film. An insulating layer 4541b is formed to cover the peripheral portion (including the side surface) of the compound semiconductor layer. The thin film transistor 4510 includes an insulating layer 4542a serving as a channel protection layer and an oxide film. An insulating layer 4542b is formed to cover the peripheral portion (including the side surface) of the compound semiconductor layer.

[0311] Insulating layers 4541b and 4541c are oxide insulating layers covering the periphery (including the side surfaces) of the oxide semiconductor layer. 542b is a gate electrode layer and a wiring layer (such as a source wiring layer) formed above or around the gate electrode layer. The distance between the insulating layer 45 and the capacitor wiring layer can be increased, thereby reducing the parasitic capacitance. 41a, 4541b, 4542a, and 4542b are the oxide insulating layers 42 shown in Embodiment 1. The same materials and methods as those for the thin film transistors 6a and 426b may be used. In order to reduce unevenness, the insulating layer 4543 is covered, which functions as a planarizing insulating film. Here, the insulating layers 4541a, 4541b, 4542a, and 4542b are Using Form 1, a silicon oxide film is formed by sputtering.

[0312] In addition, an insulating layer 4543 is formed on insulating layers 4541a, 4541b, 4542a, and 4542b. The insulating layer 4543 is formed by combining the insulating layer 428 described in Embodiment 1 and the protective insulating layer 40 10(B) is shown as a single layer, but it may be formed by the same material and method as in 3. The laminate is made of an edge layer 428 and a protective insulating layer 403 made of a different material from the insulating layer 428. As the insulating layer 4543, a silicon oxide film and a silicon nitride film are formed by sputtering. and are laminated.

[0313] An insulating layer 4544 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using a material and a method similar to those of the planarization insulating layer 404 described in Embodiment 1. Acrylic is used as the insulating layer 4544 .

[0314] In this embodiment, a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film. The insulating layer 4543 and the gate insulating layer may be formed using a nitride insulating film. In order to achieve this, an insulating layer 4543 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. The structure may be such that a region is provided in which the gate insulating layer is in contact with the gate insulating layer. This makes it possible to prevent moisture from entering from the outside. This prevents moisture from entering from the outside for a long period of time even after the device is completed. This can improve the long-term reliability of the device.

[0315] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0316] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0317] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0318] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0319] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0320] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0321] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0322] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 must be light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0323] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0324] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0325] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0326] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0327] This embodiment mode may be appropriately combined with the configurations described in Embodiments 1 to 4 and 6 to 8. It is possible to implement.

[0328] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0329] FIG. 20 shows an example of an electronic book 2700. For example, the electronic book 2700 has a housing 2 It consists of two housings, housing 2701 and housing 2703. 03 is integrated with a shaft portion 2711, and performs opening and closing operations around the shaft portion 2711. This configuration allows the device to operate like a paper book. .

[0330] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 20) and An image can be displayed on the display unit 2707 in FIG.

[0331] 20 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a board, a pointing device, etc. Also, the back and sides of the housing may be On the front, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration includes a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. Good too.

[0332] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0333] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0334] FIG. 21(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0335] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0336] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0337] FIG. 21B shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0338] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0339] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0340] FIG. 22(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 22(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 22(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0341] FIG. 22(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is The present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. , and other auxiliary equipment may be provided as appropriate.

[0342] FIG. 23A is a perspective view showing an example of a portable computer.

[0343] The portable computer of FIG. 23(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0344] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0345] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is used as a panel, input operations can be performed by touching part of the retractable display portion 9307. can.

[0346] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0347] The portable computer shown in FIG. 23(A) is configured with a receiver and the like, and is also used for television broadcasting. It is possible to receive broadcasts and display images on the display unit. The display unit 9307 is slid open while the hinge unit connecting the display unit 9307 to the body 9302 is kept closed. The entire screen is exposed by tilting the screen, and the user can watch TV broadcasts by adjusting the screen angle. In this case, the hinge unit is opened to prevent the display unit 9303 from displaying anything. It only activates the circuitry to display the TV broadcast, so it consumes the minimum amount of power. This is useful in portable computers with limited battery capacity.

[0348] FIG. 23(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0349] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band part 9204 for attaching the body to the arm, an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0350] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, for example, when you press a button, a program for the Internet Each function can be associated with another function, such as being started.

[0351] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 23(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0352] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0353] The mobile phone shown in FIG. 23(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0354] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0355] Although FIG. 23B illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape.

[0356] (Embodiment 14) In this embodiment, as one mode of a semiconductor device, the thin film transistor shown in the first, second, fifth and sixth embodiments is used. An example of a display device having a transistor will be described with reference to FIGS. 24 to 35. An example of a liquid crystal display device using a liquid crystal element as a display element will be described with reference to FIGS. 24 to 35. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistors shown in the first, second, fifth and sixth embodiments can be applied. It is a thin film transistor with excellent electrical properties and high reliability that can be fabricated in the same manner as in the process shown in 6. The TFT 628 has a channel protection layer 608, and the TFT 629 has a channel protection layer 611. The transistor is a bottom-gate thin film transistor having a semiconductor layer film as a channel formation region.

[0357] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type LCD devices are a type of LCD panel that controls the alignment of liquid crystal molecules. In a VA type LCD device, when no voltage is applied, the liquid crystal molecules are in contact with the panel surface. In this embodiment, the pixels are arranged in a vertical direction. It is designed to be divided into areas (sub-pixels) and tilt the molecules in different directions in each area. This is called multi-domain or multi-domain design. A liquid crystal display device that takes into consideration the design will be described.

[0358] 25 and 26 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of a substrate on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. 24. Also, FIG. 26 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these figures.

[0359] FIG. 24 shows a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 and an opposing substrate 601 on which an opposing electrode 640 and the like are formed are superimposed on each other. , shows the state in which liquid crystal is injected.

[0360] Although not shown, a first colored film, a second colored film, and a third colored film are formed on the opposing substrate 601 at positions where spacers are to be formed. The second colored film, the third colored film, and the counter electrode 640 are formed. The height of the protrusion 644 for controlling the alignment and the spacer are made different. An alignment film 648 is formed on the counter electrode 640, and an alignment film 646 is formed on the counter electrode 640 as well. A liquid crystal layer 650 is formed between them.

[0361] The spacers may be formed as columnar spacers or bead spacers. In this case, it may be formed on the pixel electrode 624 formed on the substrate 600 .

[0362] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. The pixel electrode 624 includes a TFT 628, a wiring 616, and a storage capacitor 630. The insulating film 620 covers the first insulating film 621, and the third insulating film 622 covers the second insulating film 621. The insulating film 620 is a laminate of an insulating layer and a protective insulating layer. The insulating layer in contact with the semiconductor layer is a silicon oxide film formed by sputtering, and the protective insulating layer on top of it is For simplification, the insulating film 62 is a laminated film. The TFT 628 is a thin film transistor shown in the first, second, fifth and sixth embodiments. The storage capacitor 630 is connected to the gate of the TFT 628. The first capacitor wiring 604 formed at the same time as the wiring 602, the gate insulating film 606, and the wiring 61 6, 618 and a second capacitance wiring 617 formed at the same time.

[0363] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0364] 25 shows the structure on the substrate 600. The pixel electrode 624 is made of the material shown in the first embodiment. The pixel electrode 624 is provided with a slit 625. The slit 625 is formed by This is to control the

[0365] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. The TFT 628 and the TFT 629 are both connected to the wiring 616. This liquid crystal display panel The pixel is composed of a pixel electrode 624 and a pixel electrode 626. The electrode 624 and the pixel electrode 626 are sub-pixels.

[0366] 26 shows the structure on the opposing substrate side. An opposing electrode 640 is formed on a light-shielding film 632. The counter electrode 640 is preferably formed using the same material as the pixel electrode 624. On the electrode 640, a protrusion 644 is formed to control the alignment of the liquid crystal.

[0367] The equivalent circuit of this pixel structure is shown in Figure 27. Both TFT628 and TFT629 have gate electrodes. The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the liquid crystal elements 651 and 652 can be made to operate differently. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, the liquid crystal The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0368] When a voltage is applied to the pixel electrode 624 in which the slit 625 is provided, The slit 625 and the protrusion 6 on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 44 so that they interdigitate with each other, a diagonal electric field is effectively generated, and the alignment of the liquid crystal is By controlling the orientation, the orientation of the liquid crystal is made different depending on the location. The multi-domain structure widens the viewing angle of the LCD panel.

[0369] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. do.

[0370] 28 and 29 show the pixel structure of a VA type liquid crystal display panel. FIG. 28 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0371] This pixel structure has multiple pixel electrodes in one pixel, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independently The system has a configuration for controlling the temperature.

[0372] The pixel electrode 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. The pixel electrode 626 is connected to the TFT through a contact hole 627 by a wiring 619. The gate wiring 602 of the TFT 628 and the gate wiring 629 of the TFT 629 are connected. 603 are separated so that different gate signals can be applied. The wiring 616 functioning as a data line is used in common by the TFT 628 and the TFT 629. The thin film transistors shown in the first, second, fifth and sixth embodiments are suitably used for the TFT 628 and the TFT 629. In addition, a capacitance wiring 690 is provided. The insulating film 620 is an insulating film. The insulating layer in contact with the semiconductor layer is a silicon oxide film formed by sputtering. The protective insulating layer on top of that is a silicon nitride film formed by sputtering. The insulating film 620, which is a laminated layer, is illustrated as a single layer.

[0373] The pixel electrode 624 and the pixel electrode 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. The timing of the voltages applied to the pixel electrodes 624 and 626 is controlled by the TFT 628. The orientation of the liquid crystal is controlled by varying the polarity of the TFT 629. The equivalent circuit is shown in Figure 31. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate The gate wiring 602 and the gate wiring 603 are connected to different gate signals. By giving a signal, the operation timing of TFT628 and TFT629 can be made different. Cut.

[0374] On the counter substrate 601, a second colored film 636 and a counter electrode 640 are formed. A flattening film 637 is formed between the colored film 636 and the counter electrode 640, and the alignment of the liquid crystal is prevented from being disturbed. The structure of the counter substrate side is shown in FIG. 30. The counter electrode 640 is common to different pixels. The electrode is made of a glass, but a slit 641 is formed. The pixel electrodes 624 and the slits 625 on the pixel electrode 626 side are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, widening the viewing angle.

[0375] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a first liquid crystal element. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 are overlapped with each other. The first liquid crystal element and the second liquid crystal element are formed in one pixel. It is a multi-domain structure with multiple children.

[0376] Next, we will explain about the in-plane switching type liquid crystal display device. In the in-plane switching type, the liquid crystal molecules in the cell This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be widened to approximately 180 degrees. The liquid crystal display device used will be described below.

[0377] FIG. 32 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, and The opposing substrate 601 is overlaid and liquid crystal is injected. The pixel electrode is formed on the substrate 600 side. Therefore, it is not provided on the opposing substrate 601 side. A crystal layer 650 is formed.

[0378] On the substrate 600, a first pixel electrode 607 and a capacitance wiring connected to the first pixel electrode 607 are provided. 604, and the TFT 628 shown in the first, second, fifth and sixth embodiments are formed. The pixel electrode 607 can be formed using a material similar to that of the pixel electrode layer 427 described in Embodiment 1. The first pixel electrode 607 is formed in a shape that is partitioned into approximately the shape of a pixel. A gate insulating film 606 is formed on the first pixel electrode 607 and the capacitance wiring 604 .

[0379] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain of the second pixel. This is a wire that connects to the electrode 624.

[0380] A second insulating film 620 is formed on the wiring 616 and the wiring 618. The insulating film 620 is an insulating layer The insulating layer in contact with the semiconductor layer is a silicon oxide film formed by sputtering. The protective insulating layer on top of this is a silicon nitride film made by sputtering. The insulating film 620 is shown as a single layer. In the contact hole formed in 20, the second pixel electrode 62 connected to the wiring 618 The pixel electrode 624 is formed using the same material as the pixel electrode layer 427 described in Embodiment Mode 1. It is formed using

[0381] In this manner, the TFT 628 and the pixel electrode 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the pixel electrode 607 and the pixel electrode 624.

[0382] 33 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 32. A slit 625 is provided in the pixel electrode 624. The gate 625 is for controlling the orientation of the liquid crystal. In this case, the electric field is applied to the pixel electrode 607 and The pixel electrode 607 is located between the pixel electrode 624. The gate insulating film is located between the pixel electrode 607 and the pixel electrode 624. The thickness of the gate insulating film 606 is 50 to 200 nm, and the thickness of the gate insulating film 606 is 2 to 100 nm. Since the thickness is sufficiently small compared to the thickness of the liquid crystal layer, which is 10 μm, the direction substantially parallel to the substrate 600 An electric field is generated in the horizontal direction. This electric field controls the orientation of the liquid crystal. The liquid crystal molecules are rotated horizontally using a parallel electric field. Because the display is horizontal even in this state, the viewing angle has little effect on contrast and other aspects, resulting in a wider viewing angle. In addition, since both the pixel electrode 607 and the pixel electrode 624 are light-transmitting electrodes, The aperture ratio can be improved.

[0383] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0384] Figures 34 and 35 show the pixel structure of an IPS type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0385] FIG. 34 shows a substrate 600 on which a TFT 628 and a pixel electrode 624 connected thereto are formed, and The opposing substrate 601 is overlaid and liquid crystal is injected. The pixel electrode 624 is formed on the substrate 600. The substrate 600 and the counter substrate 601 are not provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between them.

[0386] On the substrate 600, a common potential line 609 and the TFT 62 shown in the first, second, fifth and sixth embodiments are provided. The common potential line 609 is formed at the same time as the gate wiring 602 of the TFT 628. It is possible.

[0387] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain of the second pixel. This is a wire that connects to the electrode 624.

[0388] A second insulating film 620 is formed on the wiring 616 and the wiring 618. is connected to the wiring 618 through a contact hole 623 formed in the insulating film 620. The pixel electrode 624 is formed. The insulating film 620 is a laminate of an insulating layer and a protective insulating layer. The insulating layer in contact with the body layer is a silicon oxide film formed by sputtering, and the protective insulating layer on top of that is formed by sputtering. For simplification, the insulating film 620 is shown as a single layer. The pixel electrode 624 is formed using the same material as the pixel electrode layer 427 described in Embodiment 1. As shown in FIG. 35, the pixel electrode 624 is formed at the same time as the common potential line 609. The pixel electrode 624 is formed so as to generate a horizontal electric field together with the comb-shaped electrode formed on the pixel electrode 624. The teeth are formed so as to alternately interdigitate with the comb-shaped electrodes formed at the same time as the common potential line 609. can be.

[0389] When an electric field is generated between the potential applied to the pixel electrode 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by the electric field in the direction approximately parallel to the substrate. In this case, the liquid crystal molecules are horizontal in any state, so the This has little effect on contrast and results in a wider viewing angle.

[0390] In this manner, the TFT 628 and the pixel electrode 624 connected thereto are formed on the substrate 600. The storage capacitor is provided with a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitor electrode 615 and the pixel electrode 624 are formed by this. are connected via

[0391] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device is a highly reliable liquid crystal display device. [Explanation of symbols]

[0392] 10 Pulse output circuit 11 First Wire 12 Second wiring 13 Third Wire 14 Fourth Wire 15 The fifth wire 21 First input terminal 22 Second input terminal 23 Third input terminal 24 4th input terminal 25 5th input terminal 26 First output terminal 27 Second output terminal 28 Thin-film transistor 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 42 transistors 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 200 boards 202 Gate insulating layer 203 Protective insulation layer 204 Planarization insulating layer 205 Common potential line 206 Common electrode layer 207 Oxide semiconductor layer 208 Oxide insulating layer 209 Common potential line 216 Insulating Layer 220 Thin-film transistor 221 terminal 222 terminal 223 Connection electrode layer 225 Conductive Layer 226 Electrode layer 227 Pixel electrode layer 230 Capacitive wiring layer 231 Capacitive electrode 236 Metal wiring layer 237 Metal wiring layer 241 Metal wiring layer 242 Metal wiring layer 243 Metal wiring layer 244 Metal wiring layer 250 capacitive wiring layer 251 Oxide semiconductor layer 254 source wiring 255 Terminal electrode 256 source wiring 257 Terminal electrode 260 Thin-Film Transistor 261 Gate electrode layer 263 Channel formation region 264a High-resistance source region 264b High-resistivity drain region 264c area 264d area 265a Source electrode layer 265b Drain electrode layer 266a Oxide insulating layer 266b oxide insulating layer 267 Conductive Layer 270 Thin-Film Transistors 271 Gate electrode layer 273 Channel formation region 274a High-resistance source region 274b High-resistivity drain region 274c area 274d area 274e area 274f area 275a Source electrode layer 275b Drain electrode layer 276a Oxide insulating layer 276b oxide insulating layer 277 Conductive Layer 280 Thin Film Transistor 282a first gate insulating layer 282b second gate insulating layer 282c Gate insulating layer 286b oxide insulating layer 290 Thin-Film Transistors 292a first gate insulating layer 292b second gate insulating layer 400 boards 402 Gate insulating layer 403 Protective Insulation Layer 404 Planarization insulating layer 420 Thin Film Transistor 421a Gate electrode layer 421b Gate electrode layer 422 Oxide semiconductor layer 423 Channel formation region 424a High-resistance source region 424b High-resistivity drain region 424c area 424d area 424e High-resistance source region 424f high resistivity drain region 425a Source electrode layer 425b Drain electrode layer 426a Oxide insulating layer 426b Oxide insulating layer 427 Pixel electrode layer 428 Insulating Layer 429 Oxide semiconductor layer 441 Contact Hole 442 Oxide semiconductor layer 448 Thin Film Transistor 580 board 581 Thin-film transistor 583 Insulating Film 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 PCB 600 boards 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating film 607 Electrode layer 608 Channel Protection Layer 609 Common potential line 611 Channel Protection Layer 615 Capacitive electrode 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 insulating film 621 Insulating film 622 insulating film 623 Contact Hole 624 pixel electrode 625 Slit 626 Pixel electrode 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 632 Light-shielding film 633 Contact Hole 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Alignment Film 648 Alignment Film 650 LCD layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4041a Insulation layer 4041b insulating layer 4042a Insulation layer 4042b insulating layer 4501 Circuit Board 4502 Pixel section 4503a, 4503b Signal line driver circuit 4504a, 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a, 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4541a Insulating layer 4541b Insulating layer 4542a Insulating layer 4542b Insulating layer 4543 Insulation layer 4544 Insulation layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin-film transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Light-emitting element driving transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7000 protective insulation layer 7001 TFT 7002 Light-emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7006 Insulation layer 7007 Planarization insulating layer 7009 Bulkhead 7011 Light-emitting element driving TFT 7012 Light-emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7021 Light-emitting element driving TFT 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9201 Display section 9202 Display button 9203 Operation switch 9204 Band Club 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Input means (operation keys) 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

[Claim 1] a gate electrode layer on the insulating surface; a gate insulating layer on the gate electrode layer; an oxide semiconductor layer on the gate insulating layer; an oxide insulating layer on the oxide semiconductor layer; a source electrode layer and a drain electrode layer provided on the oxide insulating layer; an insulating layer on the source electrode layer and the drain electrode layer, the oxide semiconductor layer has a first region in contact with the oxide insulating layer, a second region in contact with the source electrode layer, a third region in contact with the drain electrode layer, a fourth region in contact with the insulating layer, and a fifth region in contact with the insulating layer; the first region has a channel formation region, the oxide semiconductor layer contains In, Ga, and Zn, the fourth region is provided between the first region and the second region, The semiconductor device, wherein the fifth region is provided between the first region and the third region.

Images