Liquid crystal display device

Abstract

To reduce consumption power.SOLUTION: A liquid crystal display device includes a pixel portion, a selection signal output circuit that outputs a selection signal in a first operation mode and stops output of the selection signal in a second operation mode, a pixel data signal output circuit that generates and outputs a pixel data signal on the basis of the input image signal, and a backlight unit including a cold cathode tube and irradiating the pixel portion with light. The pixel portion includes a transistor in which the selection signal is input to a gate electrode in the first operation mode, the pixel data signal is input to one of a source electrode and a drain electrode, and the off state is kept in the second operation mode, and liquid crystal including a plurality of liquid crystal molecules to which voltage is applied by a first electrode and a second electrode electrically connected to the other of the source electrode and the drain electrode of the transistor. The transistor includes an oxide semiconductor layer where a channel is formed and the carrier concentration is less than 1×1014 / cm3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a liquid crystal display device. [Background technology]

[0002] In recent years, progress has been made in the development of techniques for reducing power consumption in liquid crystal display devices.

[0003] One method for reducing the power consumption of a liquid crystal display device is to reduce the pixel count when displaying moving images. When a still image is displayed, the interval at which the image is rewritten is By lengthening the interval between redraws, unnecessary redrawing of images can be reduced when displaying still images. There are techniques for reducing the power consumption of liquid crystal display devices by reducing the power consumption (for example, Patent Document 1 ). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-283775 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the conventional power consumption reduction method such as that in Patent Document 1 only works when displaying a still image. Since the interval between image rewrites in the pixels is short, power consumption can be reduced sufficiently. It cannot be said that this is the case.

[0006] Furthermore, the brightness of the displayed image of the liquid crystal display device changes with temperature changes, making it difficult to display a still image. Even when the display is turned on, the brightness gradually changes over time, It is difficult to extend the rewrite interval because the quality will be reduced. The brightness of the displayed image changes due to an increase in the off-state current of the transistor provided in the pixel caused by the change. To become.

[0007] The temperature change of the liquid crystal display device occurs due to, for example, light emitted from a backlight unit. For example, a backlight unit that uses a cold cathode fluorescent lamp as a light source may Backlight unit using ED (Light Emitting Diode) as the light source Compared to knitted devices, it has a higher luminous efficiency and is easily applicable to large-area liquid crystal display devices. However, backlight units that use cold cathode fluorescent lamps as light sources generate a large amount of heat, so they are difficult to use on LCD displays. Therefore, the temperature change of the display device becomes significant. In a liquid crystal display device having a pixel, it is possible to improve the image quality of the pixel without deteriorating the display quality. It is difficult to extend the interval between image rewrites, and power consumption cannot be reduced sufficiently. In the case of a full-color liquid crystal display device, one pixel is composed of a plurality of unit pixels. Therefore, the influence of changes in display quality is less than that of a monochrome LCD display with the same number of pixels. For this reason, it is important to increase the interval between image rewrites in pixels. It is difficult to reduce power consumption sufficiently.

[0008] An object of one embodiment of the present invention is to reduce power consumption of a liquid crystal display device. [Means for solving the problem]

[0009] One aspect of the present invention has a first operation mode and a second operation mode as operation modes, A circuit that outputs a selection signal to select the pixel to which pixel data is written in operation mode 1. a selection signal is output from the pixel memory 100 to select a pixel to which pixel data is to be written in the second operation mode. This stops the operation of the circuit that outputs the selection signal.

[0010] One aspect of the present invention is a pixel unit that outputs a selection signal in a first operation mode and a second operation mode. A selection signal output circuit that stops outputting the selection signal during operation mode and a selection signal output circuit that stops outputting the selection signal during operation mode. a pixel data signal output circuit that generates and outputs a pixel data signal based on an input image signal; and a backlight unit that has a cold cathode fluorescent lamp as a light source and emits light to the pixel portion. The pixel portion has a source electrode, a drain electrode, and a gate electrode, and in a first operation mode When a selection signal is input to the gate electrode, a pixel is connected to one of the source electrode and the drain electrode. a transistor that receives a data signal and maintains an off state in a second operation mode; a first electrode electrically connected to the other of the source electrode and the drain electrode of the transistor; A second electrode and a plurality of liquid crystal molecules to which a voltage is applied via the first electrode and the second electrode. and a liquid crystal having a carrier concentration of 1×10 14 / cm 3 The liquid crystal display device includes an oxide semiconductor layer having a thickness of less than 100 nm.

[0011] One aspect of the present invention includes a pixel unit, and in a first operation mode, X selections (X is a natural number) are In the second operation mode, the output of X selection signals is stopped. The circuit receives an image signal and generates Y pixel data (Y is a natural number) based on the input image signal. A pixel data signal output circuit generates and outputs a pixel data signal, and a cold cathode fluorescent lamp is provided to irradiate the pixel with light. and a backlight unit that emits light. Each pixel portion has a source electrode, a drain electrode, and a and a gate electrode, and in a first operation mode, each of the gate electrodes is provided with a A selection signal is input, and one pixel element is connected to one of the source electrode and the drain electrode. In the second operation mode, N ( N is a natural number greater than or equal to 3) and each of the N transistors N transistors electrically connected to the other of the source and drain electrodes of the different transistors. A first electrode, a second electrode, and a voltage across each of the N first electrodes and the second electrode. A liquid crystal having a plurality of liquid crystal molecules to which a voltage is applied, and N first electrodes, K color filters (K is a natural number between 3 and N) overlapping different first electrodes; Each of the N transistors has a carrier concentration as a layer in which a channel is formed. Degrees are 1 x 10 14 / cm 3 The liquid crystal display device includes an oxide semiconductor layer having a thickness of less than 100 nm. [Effects of the Invention]

[0012] According to one embodiment of the present invention, the interval between image redraws can be lengthened as needed. For example, a backlight unit equipped with a cold cathode fluorescent lamp can be used. Even in the case of a liquid crystal display device equipped with the image rewriting function, the interval between images may be lengthened as necessary. Therefore, power consumption can be reduced. [Brief explanation of the drawings]

[0013] [Figure 1] 1A to 1C illustrate a liquid crystal display device according to Embodiment 1. [Figure 2]FIG. 10 is a block diagram showing a configuration example of a control signal generating circuit according to a second embodiment. [Figure 3] FIG. 10 illustrates a configuration example of a shift register according to Embodiment 3. [Figure 4] 10 is a timing chart for explaining an example of the operation of the shift register according to the third embodiment. [Figure 5] 10A and 10B are schematic cross-sectional views illustrating a structural example of a transistor in Embodiment 4. [Figure 6] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing a transistor in Embodiment 4. [Figure 7] 10A to 10C are schematic cross-sectional views illustrating a method for manufacturing a transistor in Embodiment 4. [Figure 8] FIG. 2 is a circuit diagram showing the configuration of a characteristic evaluation circuit. [Figure 9] 9 is a timing chart for explaining a leakage current measurement method using the characteristic evaluation circuit shown in FIG. 8 . [Figure 10] 10 is a graph showing the relationship between the elapsed time Time and the output voltage Vout in measurements under conditions 4, 5, and 6. FIG. [Figure 11] FIG. 10 is a diagram showing the relationship between the elapsed time Time related to the measurement and the leakage current calculated by the measurement. [Figure 12] FIG. 10 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 13] FIG. 10 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 14] FIG. 10 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 15] FIG. 10 is a graph showing the relationship between the voltage and leakage current at node A estimated by measurement. [Figure 16] FIG. 13 is a diagram showing an example of the structure of an active matrix substrate in a unit pixel according to a fifth embodiment. [Figure 17] FIG. 13 is a diagram showing an example of the structure of a unit pixel according to a fifth embodiment. [Figure 18] FIG. 22 is a schematic diagram showing a configuration example of a backlight unit according to a sixth embodiment. [Figure 19] FIG. 20 is a schematic diagram showing a configuration example of an electronic device according to a seventh embodiment. [Figure 20] FIG. 20 is a schematic diagram showing a configuration example of an electronic device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] An example of an embodiment for explaining the present invention will be described below with reference to the drawings. The present invention is not limited to the following description, and any modifications thereto are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the form and details of the present invention. The present invention should not be construed as being limited to the following description of the embodiments. .

[0015] The contents of each embodiment can be combined with each other as appropriate. The contents of the above can be substituted for each other as appropriate.

[0016] In addition, the term "kth (k is a natural number)" used in this specification is used to avoid confusion of the components. The numbers are added for the purpose of convenience and are not intended to be limiting.

[0017] (Embodiment 1) In this embodiment, a liquid crystal display device capable of selectively stopping a rewriting operation is described. I will explain.

[0018] An example of a liquid crystal display device according to the present embodiment will be described with reference to FIG. 1A and 1B are diagrams illustrating an example of a liquid crystal display device according to the embodiment.

[0019] First, a structural example of a liquid crystal display device of this embodiment will be described with reference to FIG. 1(A) is a block diagram showing an example of the configuration of a liquid crystal display device according to the present embodiment. FIG.

[0020] The liquid crystal display device shown in FIG. 1A includes a selection signal output circuit (also referred to as SELOUT) 101x a pixel data signal output circuit (also called PXDOUT) 101y, and a backlight unit The image sensor 100 includes a light source (also called LIGHT) 102 and a pixel (also called PX) 103.

[0021] The selection signal output circuit 101x has a function of outputting X selection signals SEL (X is a natural number). The selection signal output circuit 101x outputs, for example, a start signal, a clock signal, and a power supply voltage By inputting X selection signals SEL, the output operation of X selection signals SEL is performed. For example, The circuit 101x is configured to include a shift register, and a start signal, A clock signal and a power supply voltage are input, and the shift register generates a signal that becomes a selection signal SEL. By outputting the pulse signal, X selection signals SEL can be output.

[0022] Generally, voltage refers to the difference in electric potential (also called potential difference) between two points. However, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams, etc. Therefore, in this specification, unless otherwise specified, The potential difference between the potential at a point and the reference potential (also called the reference potential) is called the voltage at that point. It may be used.

[0023] The pixel data signal output circuit 101y receives the image signal IMG. The output circuit 101y generates Y pixel data signals (Y is a natural number) based on the input image signal IMG. The pixel data signal PXD is generated and output as Y pixel data signals PXD. The data signal output circuit 101y receives, for example, a start signal, a clock signal, and a power supply voltage. When the pixel data signal PXD is input, the pixel data signal PXD is output. The output circuit 101y is configured to include a shift register, a memory circuit, and an analog switch. Furthermore, a start signal, a clock signal, and a power supply voltage are input to the shift register. A pulse signal is output from the shift register, and an image signal IMG is generated in accordance with the pulse signal. The data is stored in the memory circuit and the analog switch is turned on. The data signal output circuit 101y converts the stored image signal IMG data into Y pixel data signals. It can be output as PXD.

[0024] As shown in FIG. 1(A), a display control circuit (also called DCTL) 101w is used. This controls the operation of the selection signal output circuit 101x and the pixel data signal output circuit 101y. It should be noted that the display control circuit 101w does not necessarily have to be provided.

[0025] The display control circuit 101w includes a selection signal output circuit 101x and a pixel data signal output circuit 101 It has the function of controlling whether to output a start signal, clock signal, and power supply voltage to the The display control circuit 101w also outputs the image signal IMG to the pixel data signal output circuit 101y. For example, the display control circuit 101w may have a function of controlling whether or not to output the When a control signal is input, a start signal, a clock signal, and the like are generated in accordance with the input control signal. Image signal IMG, start signal, clock signal, and power supply voltage, or image signal IMG, start signal, clock signal, and power supply Outputs voltage.

[0026] The control signal is generated, for example, in accordance with an input image signal IMG or a command signal from a user. When a control signal is generated in accordance with an image signal IMG, for example, The image signal IMG data is compared with the image signal IMG data, and a control signal with a pulse set according to the comparison result is generated. In addition, when a control signal is generated in accordance with a command signal, for example, input devices (e.g., keyboard or pointing device (e.g., mouse or touch Detects input from a panel, etc., and sets the pulse according to whether or not the user has performed an input operation. The control signal can be generated.

[0027] The backlight unit 102 is a light-emitting unit equipped with a light source. The light source 102 is provided with a cold cathode fluorescent lamp as a light source and has the function of emitting light. The light control circuit is provided in the light unit 102, and the light control circuit controls the brightness or light of the emitted light. The lighting timing may be controlled.

[0028] The pixel 103 is provided in a pixel section 104. The pixel section 104 receives an input pixel data signal In the liquid crystal display device of this embodiment, the image is displayed in accordance with the PXD. A configuration including a plurality of elements 103 may also be used.

[0029] Here, an example of the configuration of the pixel unit 104 will be described.

[0030] The pixel 103 is composed of N (N is a natural number of 3 or more) unit pixels (also called PXU) 103p. Also, N transistors and N pixel electrodes as N first electrodes are configured. A common electrode as a second electrode, a liquid crystal, and K color filters (K is a natural number between 3 and N) a filter, and a transistor, a first electrode, a second electrode, a liquid crystal, and a K N unit pixels 103p are configured using N color filters. The number of N unit pixels in the image sensor is not limited to N, and the image sensor has at least one unit pixel. In this case, the number of pixel data signals input to the pixel 103 is at least one. That's fine.

[0031] In the liquid crystal display device, the transistor is a field effect transistor, and Except in some cases, the semiconductor device has at least a source electrode, a drain electrode, and a gate electrode.

[0032] A selection signal SEL is input to the gate electrodes of the N transistors. One of the source electrode and drain electrode of each of the transistors is connected to one of the pixel data. If X is 2 or more, at least two or more transponders are input. Different selection signals SEL may be input to the gate electrodes of the transistors. The same selection signal SEL may be input to the gate electrodes of two or more transistors. , when Y is 2 or more, the source and drain of two or more transistors are connected to each other. Different pixel data signals PXD may be input, and the source of two or more transistors may be The same pixel data signal PXD may be input to either the source or the drain.

[0033] Each of the N transistors is a transistor containing a semiconductor layer with an extremely small number of carriers. A transistor including an oxide semiconductor layer can be used. The oxide semiconductor layer is a layer in which a channel is formed (also referred to as a channel formation layer). The oxide semiconductor layer has a function as an intrinsic (also referred to as I-type) or substantially It is a semiconductor layer that is essentially intrinsic, with an extremely small number of carriers, and the carrier concentration is 1×1 0 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 is less than.

[0034] Further, the present invention provides an oxide semiconductor layer of a transistor having the above-described oxide semiconductor layer functioning as a channel formation layer. The current is 10 aA (1 × 10 -17 A) The following is preferably 1aA (1×10 -18 A) or less, more preferably a channel width of 1 10zA per μm (1×10 -20 A) or less, more preferably per channel width of 1 μm 1zA(1×10 -21 A) or less, more preferably 100 y per 1 μm of channel width A(1×10 -22 A) The following:

[0035] In addition, since the oxide semiconductor layer has a low carrier concentration, the transistor including the oxide semiconductor layer Even if the temperature changes, the off-state current of the transistor remains within the above range. For example, even if the temperature of a transistor is 150°C, the off-state current of the transistor is It is preferable that the resistance is 100 zA or less per μm.

[0036] By using the above transistor as the transistor of the pixel 103, This suppresses fluctuations in the display state of pixels caused by current, so The retention period of the unit pixel corresponding to the write can be extended. For example, the interval between writing pixel data can be increased to 10 It can be set to 2 seconds or more, preferably 30 seconds or more, and more preferably 1 minute or more. When pixel data is not being written, the circuits that operate when writing pixel data are stopped. Therefore, the longer the interval between writing pixel data, the more power consumption is reduced. can be reduced.

[0037] Each of the N pixel electrodes is connected to a different transistor among the N transistors. The N pixel electrodes and the common electrode are electrically connected to the other of the source electrode and the drain electrode. The conducting electrode may be light-transmitting.

[0038] Each of the K color filters overlaps a different pixel electrode among the N pixel electrodes. For example, K color filters filter light that exhibits at least red, green, and blue colors. Also, color filters that transmit red, green, and blue light are included. The present invention is not limited to filters, but may also include other colors such as cyan, magenta, and yellow. A color filter that transmits light of a desired color may be used in combination with or in place of the color filter.

[0039] The liquid crystal has a plurality of liquid crystal molecules. The plurality of liquid crystal molecules are connected to each of the N pixel electrodes and A voltage is applied by the common electrode.

[0040] As the liquid crystal, for example, electrically controlled birefringent liquid crystal (also called ECB type liquid crystal), dichroic color Liquid crystals with added dyes (also called GH liquid crystals), polymer dispersed liquid crystals, or discotic liquid crystals The liquid crystal may be a liquid crystal that exhibits a blue phase. The liquid crystal exhibiting the blue phase is obtained by a liquid crystal composition containing a liquid crystal exhibiting the blue phase and a chiral agent. The liquid crystal that shows the blue phase has a short response time of 1 msec or less and is optically isotropic. Therefore, alignment treatment is not required and the viewing angle dependency is small. By using the above, the operation speed can be improved.

[0041] For example, as shown in FIG. 1A, a unit pixel 103p corresponding to red, a unit pixel 103b corresponding to green, The pixel 103p is composed of three unit pixels 103p, one corresponding to blue and one corresponding to green. The unit pixel 103p corresponding to red transmits light exhibiting red color. The unit pixel 103p corresponding to green includes a color filter that transmits light that exhibits green color. The unit pixel 103p corresponding to blue includes a color filter that transmits blue light. In this case, the N and K are 3. By configuring the pixel 103 with three unit pixels 103p, in the pixel 103, In addition, for example, the three unit pixels 103p are set to white. The pixel 103 may be configured by four unit pixels 103p, each of which corresponds to a unit pixel 103p. The unit pixel 103p corresponding to white does not include a color filter. is 4 and the above K is 3. Generally, when white is obtained by additively mixing red, green, and blue, When a color filter is not included, the light is attenuated by the color filter. By using a unit pixel 103p that is small to generate white, Since the light incident on pixel 103p can be used for display without being attenuated, The display brightness of the pixel 103 can be improved. Although it is not necessary to provide a color filter, full color display can be achieved by providing a color filter. This can be done.

[0042] The liquid crystal display device shown in FIG. 1A may be implemented in a Twisted Nematic (TN) mode. Nematic mode, IPS (In Plane Switching) mode, STM (Super Twisted Nematic) mode, VA (Vertica) l Alignment) mode, ASM (Axially Symmetric Alignment) mode, Ignition Micro-cell mode, OCB (Optically Comp Insulated Birefringence mode, FLC (Ferrerolector ic Liquid Crystal) mode, AFLC (AntiFerroelec tric Liquid Crystal) mode, MVA (Multi-Domain Vertical Alignment mode, PVA (Patterned Ve Vertical Alignment mode, ASV (Advanced Super View) mode or FFS (Fringe Field Switching) mode In addition, the display method of the liquid crystal display device may be such that the pixel electrodes and A driving method that inverts the polarity of the voltage applied between the common electrodes (also called inversion driving) By using the inversion drive, image burn-in can be prevented. do.

[0043] It should be noted that an image refers to a video image formed by pixels in a pixel portion.

[0044] The selection signal output circuit 101x and the pixel 103 may be provided on the same substrate. In addition, at least a part of the selection signal output circuit 101x and the pixel data signal output circuit 101y The pixel 103 may be formed on the same substrate. 103 and other circuits can be formed.

[0045] Furthermore, an equivalent circuit of the unit pixel 103p will be described with reference to FIG. 1(B). ) is a diagram showing an equivalent circuit of the unit pixel shown in FIG.

[0046] The equivalent circuit of the unit pixel shown in FIG. 1B is formed by a transistor 131 and a liquid crystal element 132. It is composed.

[0047] A selection signal SEL is input to the gate of the transistor 131. A pixel data signal PXD is input to one of the source and drain.

[0048] The liquid crystal element 132 has a first terminal and a second terminal. The first terminal of the liquid crystal element 132 is connected to a transistor. The liquid crystal element 132 is electrically connected to the other of the source and drain of the transistor 131. A common voltage may be input to the second terminal of the power supply. When the switching element is turned on, the common voltage is applied to the second terminal of the liquid crystal element 132. The liquid crystal element 132 is included in the pixel 103 and has a first terminal. one of the N pixel electrodes having the function of the first terminal; a common electrode having the function of the second terminal; and liquid crystal.

[0049] The source refers to a part or all of the source electrode, or a part or all of the source wiring. In addition, the source electrode and the source wiring are referred to as the source electrode and the source wiring without distinction. A conductive layer having both of the above functions may be called a source.

[0050] The drain may refer to a part or all of the drain electrode, or a part or all of the drain wiring. In addition, the drain electrode and the drain wiring are not distinguished from each other. A conductive layer having both functions as a drain wiring and a gate wiring may be referred to as a drain.

[0051] The term "gate" refers to a part or all of a gate electrode, or a part or all of a gate wiring. In addition, the gate electrode and the gate wiring are not distinguished from each other and are referred to as the gate electrode and the gate wiring. A conductive layer having both of the above functions is sometimes called a gate.

[0052] Also, depending on the transistor structure and operating conditions, the source and drain of the transistor , may be interchangeable.

[0053] As shown in FIG. 1B, a capacitor 133 may be provided in the unit pixel 103p. The capacitance element 133 has a first terminal and a second terminal, and the first terminal of the capacitance element 133 is connected to a transistor. The second terminal of the capacitor 133 is electrically connected to the other of the source and drain of the capacitor 131. A common voltage is input to the input terminals 1 and 2. A switching element is also provided separately, and the switching element When the capacitor 133 is turned on, the common voltage is input to the second terminal of the capacitor 133. You may do so.

[0054] The capacitor 133 functions as a storage capacitor and functions as a part or the whole of the first terminal. a first electrode having a function as a part or the whole of the second terminal; The capacitance of the capacitor 133 is determined in consideration of the off-state current of the transistor 131 and the like. In this embodiment, the capacitance of the liquid crystal element in each display circuit (liquid crystal capacitance) A retention capacity having a capacity of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the It is sufficient to provide the capacitor element 133. The capacitor element 133 may not be provided in the unit pixel. The aperture ratio of the unit pixel can be further improved, and the aperture ratio of the pixel can be further improved. .

[0055] Next, as an example of a method for driving the liquid crystal display device of this embodiment, the liquid crystal display device shown in FIG. An example of a driving method will be described with reference to FIGS. 1(C) and 1(D). 1(D) is a timing chart for explaining an example of a method for driving the liquid crystal display device shown in FIG. 1(A). It is a chart.

[0056] The liquid crystal display device shown in FIG. 1A has a first operation mode and a second operation mode. The first operation mode and the second operation mode are controlled by, for example, a control signal in a control circuit or a separately provided The operation modes can be changed using the switches provided. , as explained below.

[0057] First, as an example, when specific pixel data is written to pixel 103 in the first operation mode, At this time, as shown in the period PD1 in FIG. 1(C) and FIG. 1(D), The selection signal output circuit 101x is in a signal output state (also called the OUTPUT state). At this time, the selection signal output circuit 101x outputs X selection signals SEL to the pixels 103.

[0058] A selection signal SEL is input to the gate electrode of the transistor in each unit pixel 103p. The unit pixel 103p to which the pulse of the selection signal SEL is input has its transistor turned on. By entering the ON state, the write state (also called state WRT) is entered. At this time, the pixel data signal PXD is written to the unit pixel 103p. When one pixel data signal PXD is input to the pixel electrode of the liquid crystal element in 03p, The display of the unit pixel 103p is controlled in accordance with the data (voltage) of the input pixel data signal PXD. The display state of each unit pixel 103p is set, and the display state of the pixel 103p is set. The display state is set.

[0059] By writing pixel data to each unit pixel 103p, the pixel 103 is in a holding state (state The transistors of the unit pixels 103p are turned off, and the set It should be noted that maintaining the display state means maintaining the display state of the N pixels in the pixel 103. The amount of change from the initial value of the voltage applied between each of the element electrodes and the common electrode is greater than the reference value. The reference value is a voltage value that is set appropriately. For example, when a user views a display image, the image is recognized as the same image. At this time, it is preferable to set the common electrode of the pixel 103 to a floating state. This makes it possible to suppress fluctuations in the voltage of the common electrode.

[0060] Furthermore, when repeatedly operating in the first operation mode, the period PD 2 and PD3, the selection signal output circuit 101x outputs X selection signals SEL. The signal is output to element 103.

[0061] The unit pixel 103p to which the pulse of the selection signal SEL is input is put into a write state. One pixel data signal PXD is input to the pixel 103p. The display state of the unit pixel 103p is set according to the data (voltage) of the signal PXD. At this time, the display state of the pixel provided in the pixel unit 104 during a certain period is set to 3. The pixel data signal PXD input to 103 and the pixel data signal PXD input to the same pixel 103 in the previous period are If the absolute value of the difference between the input pixel data signal PXD and the data (voltage) is less than the reference value, The image of the pixel unit 104 in the continuous period is a still image, and if it is larger than the reference value, The image of the pixel unit 104 during this period is a moving image. For example, when a user views a display image, the displayed image is the same as the image when viewed visually. It is preferable to set the value within a range that can be recognized as a

[0062] The pixel 103 into which the pixel data has been written is in a holding state and maintains the set display state. do.

[0063] In the second operation mode, as shown in the period PD2 in FIG. 1(D), The output circuit 101x is in a stopped state (also called a STOP state). The output of the selection signal SEL in the circuit 101x is stopped. For example, the selection signal output circuit 10 By stopping the input of the start signal, clock signal, and power supply voltage to 1x, the selection The selection signal output circuit 101x is in a stopped state. For example, maintaining the voltage of a signal within a certain range of values ​​or This refers to leaving the wiring floating.

[0064] At this time, the pixel data signal PXD is not input to the pixel 103, so that each unit pixel 10 The transistor 131 of 3p remains in the off state. The display state during operation mode 1 (period PD1 in FIG. 1(D)) is maintained. , the state held in the previous first operation mode is maintained.

[0065] During the period PD2, the pixel data signal output circuit 101y may be stopped. For example, the image signal IMG, the start signal, the clock signal, and the like are input to the pixel data signal output circuit 101y. By stopping the input of the clock signal and the power supply voltage, the pixel data signal output circuit 101y The output of the pixel data signal PXD in the selection signal output circuit 101x is stopped. By stopping the pixel data signal output circuit 101y at this time, power consumption can be further reduced. It can be reduced.

[0066] Furthermore, after the selection signal output circuit 101x is put into a stopped state, the pixel data of the pixel is rewritten. In this case, as shown in the period PD3 in FIG. 1(D), the selection signal output circuit 101x The selection signal output circuit 101x restarts the output operation of the selection signal SEL in EL to the pixel 103. For example, a start signal, By inputting a clock signal and a power supply voltage, the selection signal output circuit 101x outputs a selection signal. The output operation of the signal SEL is resumed. When the pixel data signal output circuit 101y is stopped, the pixel data signal is output during the period PD3. The pixel data signal output circuit 101y resumes outputting the pixel data signal PXD. The pixel data signal output circuit 101y receives the pixel data signal PXD, the start signal, and the clock signal CLK. By inputting the clock signal and the power supply voltage, the pixel data signal output circuit 101y outputs the pixel data signal. The output operation of the raw data signal PXD is resumed.

[0067] The unit pixel 103p to which the pulse of the selection signal SEL is input is put into a write state, and each unit When one pixel data signal PXD is input to a pixel, the input pixel data signal The display state of the unit pixel 103p is set according to the data (voltage) of the PXD, and each unit pixel 1 By setting the display state of 03p, the display state of pixel 103 is set.

[0068] The pixel 103 into which the pixel data has been written is in a holding state and maintains the set display state. The above is an example of the operation of the liquid crystal display device shown in FIG.

[0069] In addition, when the liquid crystal display device shown in FIG. 1A is a transmission type, the first operation mode and In the second operating mode, the backlight unit 102 emits light to the pixels 103 .

[0070] As described with reference to FIG. 1, an example of the liquid crystal display device according to the present embodiment is a first operation mode in which pixel data is written to the pixel to perform a display operation, and a second operation mode in which pixel data is not written to the pixel to perform a display operation. a liquid crystal display device that can selectively switch to a second operation mode in which a display operation is performed only in the first operation mode; Therefore, by switching to the second operation mode as needed, the pixels can display the image while At least the output of the selection signal from the selection signal output circuit can be stopped. As a result, during a period when pixel data does not need to be written to the pixel, the selection signal output circuit Since it can be stopped, power consumption can be reduced.

[0071] In addition, an example of the liquid crystal display device according to the present embodiment includes a transistor in a unit pixel. A transistor using a highly purified oxide semiconductor layer as a channel formation layer was used. Therefore, fluctuations in the display state of a liquid crystal element due to the off-state current of a transistor can be suppressed. This allows for longer retention of the image corresponding to one pixel data write. Therefore, the interval between writing pixel data can be extended, and power consumption can be reduced. It is possible to reduce power consumption. In addition, cold cathode fluorescent lamps are used as the light source for the backlight unit. Even if the temperature of the transistor changes, the display state of the pixel is suppressed from fluctuating. This allows the retention period of the image corresponding to one pixel data write to be extended. This allows the interval between writing pixel data to be longer, reducing power consumption. Furthermore, a full-color display having three or more unit pixels in one pixel can be used. In the case of a monochrome LCD display, if the number of pixels is the same, the In addition, the number of unit pixels is large, so power consumption can be further reduced.

[0072] (Embodiment 2) In this embodiment, an example of a method for generating a control signal will be described.

[0073] When a control signal is used in the liquid crystal display device according to the above embodiment, for example, a control signal generating circuit Therefore, the control signal can be generated using the following configuration example of the control signal generation circuit. This will be explained with reference to Fig. 2. Fig. 2 shows an example of the configuration of the control signal generating circuit in this embodiment. FIG.

[0074] The control signal generating circuit shown in FIG. 2 includes a memory circuit (also called MEMORY) 201 and a comparison circuit (also called COMP) 202 and an output selection circuit (also called OSEL) 203. .

[0075] An image signal IMG is input to the memory circuit 201. The memory circuit 201 stores the input image signal IMG. The memory circuit 201 has a function of sequentially storing the data of the signal IMG. a plurality of frame memories 20 for storing data of image signals IMG corresponding to images between the The frame memory 201_FM has a memory area for one frame period. The memory circuit 201 stores images for a plurality of frame periods. It is sufficient to store the data of the image signal IMG corresponding to the image data. The number of frame memories 201_FM to be used is not particularly limited. The memory 201_FM is, for example, a DRAM (Dynamic Random Access Memory). Memory), or SRAM (Static Random Access Memory It is composed of memory elements such as

[0076] The comparison circuit 202 stores the data of the image signal IMG corresponding to the images of successive frame periods. The data of the image signal IMG is read out from the memory circuit 201, compared, and the result of the comparison is used to A circuit for generating a control signal CTL in which a pulse is set by the It is a road.

[0077] For example, it is checked whether there is a difference in the data (voltage) of the compared image signals IMG. It is determined whether the image corresponding to the data of the image signal IMG is a moving image or a still image.

[0078] The absolute value of the difference between the data of the image signal IMG corresponding to the images in the consecutive frame periods is equal to or greater than the reference value. In the case below, the comparison circuit 202 determines the image corresponding to the data of the compared image signal IMG as a still image. It is judged that:

[0079] In addition, the absolute value of the difference between the data of the image signal IMG corresponding to the images in the consecutive frame periods is used as a basis. If it is greater than the reference value, the comparison circuit 202 determines whether the image signal IMG is a pixel value corresponding to the compared image signal IMG. The image is judged to be a video.

[0080] The reference value for comparison is a voltage value that is set appropriately, for example, when a user views a display image. It is preferable to set the value within a range that allows the images to be recognized as the same when viewed.

[0081] The output selection circuit 203 receives a control signal CTL and selects , a circuit that reads out and outputs the data of the image signal IMG stored in the memory circuit 201. Although the output selection circuit 203 is not necessarily provided, it is preferable to provide the output selection circuit 203. As a result, the image data to the pixel data signal output circuit in the liquid crystal display device of the above embodiment is The output of the signal IMG can be selectively stopped.

[0082] For example, if an image based on the data of the image signal IMG compared by the comparison circuit 202 is determined to be a moving image, When the signal is cut off, the output selection circuit 203 reads the data of the image signal IMG from the memory circuit 201. The image signal IMG is output by reading and outputting the image signal IMG.

[0083] In addition, the image based on the data of the image signal IMG compared by the comparison circuit 202 is determined to be a still image. If the number of times the image is judged to be a still image is less than or equal to a reference value, the output selection circuit 2 03 stops reading out the data of the image signal IMG from the memory circuit 201 and The output of the MG is stopped. The reference value can be set appropriately.

[0084] The output selection circuit 203 is configured by a circuit including, for example, a plurality of switches. For example, a transistor can be used.

[0085] It is also possible to provide a counter circuit in the control signal generating circuit. The number of frame periods that are determined to be data for displaying a still image is counted, and the counted value is used as the reference value. When the value is exceeded, the same action is taken as when the data is determined to be for displaying a video. It is also possible to do so.

[0086] The control signal generating circuit may be provided in the liquid crystal display device of the above embodiment, or may be provided separately. A control signal generating circuit may be prepared and electrically connected to the liquid crystal display device of the above embodiment. .

[0087] As explained with reference to FIG. 2, the control signal generating circuit of this embodiment generates a control signal for successive frame periods. The pixel data between them is judged as being either a video or a still image, and the control generated based on the judgment result is This allows the pulse of the control signal CTL to be set. When a pulse is input, in the liquid crystal display device of the above embodiment, the selection signal output circuit It can also be set to output a selection signal.

[0088] (Embodiment 3) In this embodiment, the selection signal output circuit and pixel detector in the liquid crystal display device of the above embodiment are An example of a shift register applicable to a data signal output circuit will be described.

[0089] First, a configuration example of a shift register of this embodiment will be described with reference to FIG. FIG. 3A is a diagram showing an example of the configuration of a shift register.

[0090] The shift register shown in FIG. 3(A) is a sequential circuit (also called FF) consisting of P (P is a natural number equal to or greater than 3). The device is equipped with a P-stage sequential circuit configured using a P-stage sequential circuit.

[0091] A start signal SP is input to the shift register shown in FIG. 3(A). , as clock signals, clock signal CLK1, clock signal CLK2, clock signal C LK3 and clock signal CLK4 are input. By using multiple clock signals, This makes it possible to improve the speed of the signal output operation in the shift register.

[0092] In addition, as a signal in the shift register of this embodiment, for example, a signal using a voltage As a signal using a voltage (also called a voltage signal), at least the first The first voltage and the second voltage can be an analog signal or a digital signal. For example, a binary digital signal such as a clock signal can be either low or high. As a result, the signal becomes a first voltage (low level voltage) and a second voltage (high level voltage). In addition, the high-level voltage and the low-level voltage are constant values. However, in electronic circuits, there are effects such as noise, so high-level voltages are The high-level voltage and the low-level voltage are not constant values, but can be considered to be substantially equivalent. Any value within a certain range may be used.

[0093] Further, each sequential circuit will be explained below.

[0094] Each of the sequential circuits 300_1 to 300_P is provided with a set signal ST, a reset signal The signal RE, the clock signal CK1, the clock signal CK2, and the clock signal CK3 are input. In addition, each of the sequential circuits 300_1 to 300_P outputs the signals OUT1 and OUT2. and signal OUT2.

[0095] The clock signals CK1, CK2, and CK3 are sequentially clocked at 1 / 4 cycle. The waveforms of the clock signals CK1, CK2, and CK3 are delayed by one another. The signal CK3 may be, for example, one of the clock signals CLK1 to CLK4. Any three clock signals can be used. It is assumed that the same combination of clock signals is not input.

[0096] Furthermore, the circuit configuration of the sequential circuit shown in FIG. 3A will be described with reference to FIG. FIG. 3B is a circuit diagram showing the circuit configuration of the sequential circuit shown in FIG.

[0097] The sequential circuit shown in FIG. 3B includes a transistor 301a, a transistor 301b, and a transistor a transistor 301c, a transistor 301d, a transistor 301e, and a transistor 301f, transistor 301g, transistor 301h, and transistor 301i , a transistor 301j, and a transistor 301k.

[0098] A voltage Va is input to one of the source and drain of the transistor 301a. A set signal ST is input to the gate of the starter 301a.

[0099] One of the source and drain of the transistor 301b is connected to the source and drain of the transistor 301a. and the other of the source and drain of the transistor 301b. A voltage Vb is input to one side.

[0100] One of the source and drain of the transistor 301c is connected to the source and drain of the transistor 301a. The gate of the transistor 301c is electrically connected to the other of the drain and the gate of the transistor 301d. is entered.

[0101] A voltage Va is input to one of the source and drain of the transistor 301d. The clock signal CK3 is input to the gate of the starter 301d.

[0102] One of the source and drain of the transistor 301e is connected to the source and drain of the transistor 301d. and the other of the source and drain of the transistor 301e. One is electrically connected to the gate of transistor 301b and the other is electrically connected to the gate of transistor 301e. A clock signal CK2 is input to the output.

[0103] A voltage Va is input to one of the source and drain of the transistor 301f. A reset signal RE is input to the gate of the starter 301f.

[0104] One of the source and drain of the transistor 301g is connected to the gate of the transistor 301b. and the other of the source and drain of the transistor 301f. The voltage Vb is input to the other of the source and drain of the transistor 301g. A set signal ST is input to the gate of g.

[0105] The clock signal CK1 is input to one of the source and drain of the transistor 301h. The gate of the transistor 301h is connected to the other of the source and drain of the transistor 301c. is electrically connected to

[0106] One of the source and drain of the transistor 301i is connected to the source and drain of the transistor 301h. and the other of the source and drain of the transistor 301i. On the other hand, a voltage Vb is input, and the gate of the transistor 301i is connected to the gate of the transistor 301b. is electrically connected to the gate of the

[0107] The clock signal CK1 is input to one of the source and drain of the transistor 301j. The gate of the transistor 301j is connected to the other of the source and drain of the transistor 301c. is electrically connected to

[0108] One of the source and drain of the transistor 301k is connected to the source and drain of the transistor 301j. and the other of the source and drain of the transistor 301k. On the other hand, a voltage Vb is input, and the gate of the transistor 301k is connected to the gate of the transistor 301b. is electrically connected to the gate of the

[0109] One of the voltages Va and Vb is the high power supply voltage Vdd, and the other of the voltages Va and Vb is the high power supply voltage Vdd. The other is the low power supply voltage Vss. The high power supply voltage Vdd is relatively higher than the low power supply voltage Vss. The low power supply voltage Vss is a voltage with a value relatively lower than the high power supply voltage Vdd. The values ​​of voltage Va and voltage Vb are mutually input depending on, for example, the polarity of the transistors. The potential difference between voltage Va and voltage Vb is the power supply voltage.

[0110] In addition, in FIG. 3B, the gate of the transistor 301b and the gate of the transistor 301e the other of the source and drain of the transistor 301f, One of the source and drain of the transistor 301g, the gate of the transistor 301i, The electrical connection point with the gate of the transistor 301k is also called a node NA. The other of the source and drain of the transistor 301a and the other of the source and drain of the transistor 301b The electrical connection point between one of the inputs and one of the source and drain of the transistor 301c is The other of the source and the drain of the transistor 301c is also referred to as a node NB. The electrical connection between the gate of the transistor 301h and the gate of the transistor 301j is The other of the source and drain of the transistor 301h is also called a gate NC. The electrical connection point with one of the source and drain of the transistor 301i is also called a node ND. In addition, the other of the source and drain of the transistor 301j and the source of the transistor 301k The point of electrical connection between the source and the drain is also called a node NE.

[0111] The sequential circuit shown in FIG. 3B outputs the voltage of node ND as a signal OUT1, and The voltage at E is output as signal OUT2.

[0112] In addition, the gate and the transistor 301a in the first stage sequential circuit 300_1 The start signal SP is input to the gate of the starter 301g as a set signal ST.

[0113] In addition, in the sequential circuit 300_Q+2 of the Q+2th stage (Q is a natural number of 1 or more and P-2 or less), The gate of the transistor 301a and the gate of the transistor 301g are connected to the Q+1th stage. The other of the source and drain of the transistor 301h in the circuit 300_Q+1 is electrically connected. At this time, the signal OUT1 in the sequential circuit 300_Q+1 is connected to the This becomes the set signal ST at 0_Q+2.

[0114] Also, the transistor in the U-th stage (U is a natural number of 3 or more and P or less) sequential circuit 300_U The other of the source and drain of 301h is The gate of the transistor 301f is electrically connected to the gate of the transistor 301f. The signal OUT1 in the signal OUT1 serves as a reset signal RE for the sequential circuit 300_U-2.

[0115] In addition, the gate of the transistor 301f in the sequential circuit 300_P-1 at the P-1th stage is , a signal RP1 is input as a reset signal. The signal OUT2 output from -1 does not need to be used to operate other circuits.

[0116] The gate of the transistor 301f in the P-th stage sequential circuit 300_P is connected to a reset terminal. The signal RP2 is input as a start signal. The signal OUT2 does not need to be used to operate other circuits.

[0117] In addition, the transistors 301a to 301k are made to have the same conductivity type. The transistors 301a to 301k can be, for example, The layer in which the channel is formed is a semiconductor from group 14 of the periodic table (such as silicon). or a pixel in the liquid crystal display device of Embodiment 1. A transistor applicable to 103 can be used.

[0118] Furthermore, an example of the operation of the sequential circuit shown in FIG. 3B will be described with reference to FIG. 4A. 4(A) is a timing chart for explaining an example of the operation of the sequential circuit shown in FIG. 3(B). As an example, transistors 301a to 301b in the sequential circuit shown in FIG. The transistors 301k and 301h are all of N-type conductivity. The threshold voltage of the transistor 301j is set to the same voltage Vth, and the voltage Va is set to the high power supply voltage Vdd. is input, and the low power supply voltage Vss is input as the voltage Vb.

[0119] First, at time T61, the clock signal CK1 goes low, and the clock signal CK 2 goes low, clock signal CK3 goes high, and set signal ST goes high. The reset signal RE goes to low level.

[0120] At this time, the sequential circuit is in a set state. 301g is turned on, and the transistors 301e and 301f are turned off. Therefore, the voltage at node NA (V NA voltage Vb, and the The transistor 301b, the transistor 301i, and the transistor 301k are turned off. Also, the transistor 301a is turned on and the transistor 301b is turned off. Therefore, the voltage of node NB (V NB Also, the voltage Va is equal to the voltage Va. Since the resistor 301c is turned on, the voltage of the node NC (V NC (also called) is the voltage Va and the transistor 301h and the transistor 301j are turned on. When the voltage at the node NC becomes equal to the voltage Va, the transistor 301c is turned off. Also, the transistor 301h is turned on and the transistor 301i is turned off. Since the signal OUT1 is in the low level state, the transistor 301j is turned on. The transistor 301k is turned off, and the signal OUT2 is at a low level. become.

[0121] Next, at time T62, the clock signal CK1 goes high, and the clock signal CK 2 remains low, the clock signal CK3 goes low, and the set signal ST remains at a high level, and the reset signal RE remains at a low level.

[0122] At this time, the transistor 301d is turned off, and the transistor 301e Since the transistors 301f and 301g remain in the off state, the voltage at the node NA remains equal to the voltage Vb, and the transistors 301b, 301i, The transistor 301k remains in the off state. Since the transistor 301c remains in the off state, the voltage at the node NB The voltage remains equal to the voltage Va. Also, the transistor 301c remains in the off state. Therefore, the node NC is in a floating state. Since the transistor 301i remains in the off state, the voltage of the node NC rises. rises, transistor 301j remains on, and transistor 301k remains off. As a result, the voltage at the node ND rises. Parasitic elements that occur between the gate and the other of the source and drain of transistor 301j The voltage at node NC rises due to capacitive coupling, a phenomenon known as bootstrap. The voltage at the node NC is greater than the sum of the voltages Va and Vth, i.e. , the voltage of the transistor 301h rises to Va+Vth+Vx. At this time, the signals OUT1 and OUT2 are high level. Become Bell.

[0123] Next, at time T63, the clock signal CK1 remains at a high level. The clock signal CK2 goes high, the clock signal CK3 remains low, and the set signal The reset signal ST goes to low level, and the reset signal RE remains low level.

[0124] At this time, the transistor 301e is turned on and the transistor 301g is turned off. The transistors 301d and 301f remain in the off state. The voltage of the node NA remains equal to the voltage Vb, and the transistor 301b The transistors 301i and 301k remain in the off state. 301a turns off, transistor 301b remains off, and transistor Since 301c remains in the off state, the voltage at node NB remains equal to voltage Va. Also, since the transistor 301c remains off, the voltage at the node NC is V a+Vth+Vx, and the transistor 301h and the transistor 301j are turned on. Also, the transistor 301h remains on, and the transistor Since 301i remains in the off state, the signal OUT1 remains at a high level. Transistor 301j remains on and transistor 301k remains off. Therefore, the signal OUT2 remains at a high level.

[0125] Next, at time T64, the clock signal CK1 goes low, and the clock signal CK 2 remains high, the clock signal CK3 goes high, and the set signal ST remains at a low level, and the reset signal RE goes to a high level.

[0126] At this time, the sequential circuit is in a reset state. When the capacitor 301j is in the ON state, the signals OUT1 and OUT2 are at a low level. In addition, the transistors 301d and 301f are turned on, and the transistor 3 Since transistor 301e remains on and transistor 301g remains off, The voltage of the node NA becomes equal to the voltage Va, and the transistors 301b and 301c are turned on. 1i and transistor 301k are turned on. Also, transistor 301b is turned on. The transistors 301a and 301c remain in the off state. Therefore, the voltage of the node NB becomes equal to the voltage Vb, and the transistor 301c is turned on. In addition, since the transistor 301c is turned on, the voltage of the node NC becomes the voltage Vb and the transistor 301h and the transistor 301j are turned off. Also, the transistor 301h is turned off and the transistor 301i is turned on. Therefore, the signal OUT1 goes low, and the transistor 301j goes off. Since the transistor 301k is turned on, the signal OUT2 goes low.

[0127] Next, at time T65, the clock signal CK1 remains at a low level. The clock signal CK2 goes low, the clock signal CK3 remains high, and the set signal The signal ST remains at a low level, and the reset signal RE remains at a high level.

[0128] At this time, the transistor 301e is turned off, and the transistors 301d and Since transistor 301f remains on and transistor 301g remains off, Therefore, the voltage at the node NA remains at a value equivalent to the voltage Va, and the transistor 301b The transistor 301i and the transistor 301k remain in the on state. The transistor 301a remains in the off state, and the transistors 301b and 301c remains in the on state, and the voltage of the node NB remains equal to the voltage Vb. Since the transistor 301c remains on, the voltage at the node NC is equal to the voltage Vb. The transistor 301h and the transistor 301j remain in the off state. Also, the transistor 301h remains in the off state, and the transistor 301i remains in the on state. Since the transistor remains in the on state, the signal OUT1 remains at a low level. 301j remains off and transistor 301k remains on, The signal OUT2 remains at a low level.

[0129] As described above, the sequential circuit can output the signals OUT1 and OUT2. The above is an example of the operation of the sequential circuit shown in Figure 3(B).

[0130] Furthermore, an example of the operation of the shift register shown in FIG. 3(A) will be explained with reference to FIG. 4(B). FIG. 4B is a diagram for explaining an example of a method for driving the shift register shown in FIG. 1 is a timing chart of the above.

[0131] The shift register shown in FIG. 3A is a first operation register in the liquid crystal display device of the above embodiment. The operation can be switched according to the first and second operation modes. The actual operation will be described below.

[0132] First, as an example, the operation when the first operation mode is entered will be described. As shown in period 311 of (B), the start signal SP, the power supply voltage Vp, and the clock signal The clock signals CLK1 to CLK4 are input, and the pulses of the start signal SP are input in the order of the first stage. By inputting the clock signals CLK1 to CL According to K4, the signals OUT1 and OUT2 of the first-stage sequential circuit 300_1 to the P-stage sequential circuit 300_2 are The sequential circuit 300_P outputs pulses in sequence for the signals OUT1 and OUT2. That is, the signals OUT1 and OUT2 of the first-stage sequential circuit 300_1 to the P-th-stage sequential circuit The signal OUT1 and the signal OUT2 of the circuit 300_P are output.

[0133] Next, the operation when switching from the first operation mode to the second operation mode will be described. At this time, as shown in period 312 of FIG. 4(B), the power supply voltage Vp to the shift register, the clock The output of the clock signals CLK1 to CLK4 and the start signal SP is stopped.

[0134] At this time, first, the output of the start signal SP to the shift register is stopped, and then the shift register Stop the output of clock signal CLK1 to the shift register and turn on clock signal CLK2 to the shift register. The output of the clock signal CLK3 to the shift register is stopped, and the shift register is The output of the clock signal CLK4 to the shift register is stopped, and the output of the power supply voltage Vp to the shift register is stopped. When the shift register stops outputting a signal, This can suppress malfunctions.

[0135] The power supply voltage Vp to the shift register, the clock signals CLK1 to CLK4, and When the output of the start signal SP is stopped, the signals OUT1 and OUT2 of the first-stage sequential circuit 300_1 are and signals OUT2 to the signals OUT1 and OUT2 of the P-th stage sequential circuit 300_P. That is, the signal OUT1 and the signal OUT2 of the first-stage sequential circuit 300_1 are turned off. The outputs of the signals OUT1 and OUT2 of the P-th stage sequential circuit 300_P to the signals OUT2 are stopped. As a result, the liquid crystal display device enters the second operation mode.

[0136] Furthermore, after the signal output in the shift register is stopped, the signal in the shift register is When the output of the signal is to be resumed, as shown in the period 313 of FIG. 4(B), the shift register start signal SP to the clock signal CLK1 to the clock signal CLK4, and the power supply voltage Resume Vp output.

[0137] At this time, first, the output of the power supply voltage Vp to the shift register is restarted, and then the clock to the shift register is The output of clock signal CLK1 is resumed and the output of clock signal CLK2 to the shift register is started. The output of the clock signal CLK3 to the shift register is resumed. The output of the clock signal CLK4 is resumed, and the output of the start signal SP is resumed. When the clock signals CLK1 to CLK4 are output, a high power supply voltage V It is preferable to output the clock signals CLK1 to CLK4 after applying the dd. Desirable.

[0138] Start signal SP to the shift register, clock signals CLK1 to CLK4 , and the output of the power supply voltage Vp is resumed, and the pulse of the start signal SP is input to the first-stage sequential circuit 30 0_1, the clocks are clocked according to the clock signals CLK1 to CLK4. The signals OUT1 and OUT2 of the first-stage sequential circuit 300_1 to the P-th-stage sequential circuit 300_P outputs pulses in sequence in the signals OUT1 and OUT2. The signals OUT1 and OUT2 of the first-stage sequential circuit 300_1 to the P-th-stage sequential circuit 30 The output of the signals OUT1 and OUT2 of the first row 0_P is resumed. It goes into operation mode.

[0139] As described with reference to FIGS. 3(A) and 3(B) and FIGS. 4(A) and 4(B), The shift register of this embodiment is configured using a plurality of sequential circuits. Each of the first transistor, the second transistor, and the third transistor, A set signal is input to the gate of the first transistor, and the first transistor has a function of controlling whether or not the second transistor is turned on according to the set signal. A clock signal is input to one of the source and drain of the second transistor. The transistor 2 sets the voltage of the output signal of the sequential circuit to a value that corresponds to the voltage of the clock signal. A reset signal is input to the gate of the third transistor. The third transistor turns off the second transistor in accordance with the reset signal. By using the above configuration, the shift register The output of the signal can be easily stopped.

[0140] Furthermore, by using the shift register of this embodiment, the liquid crystal display device of the above embodiment can be Therefore, the period during which the output of the selection signal is stopped can be set. In addition, by using the above configuration, the start signal to the shift register can be By stopping the output of the clock signal and the power supply voltage, the signal in the shift register The output of the signal can be stopped, and the output of the selection signal can be stopped.

[0141] Furthermore, by using the shift register of this embodiment, the liquid crystal display device of the above embodiment can be A pixel data signal output circuit can be configured. Therefore, the output of the pixel data signal can be stopped. Furthermore, by using the above configuration, it is possible to provide a period during which the shift register By stopping the output of the start signal, clock signal, and power supply voltage, the shift register The output of the signal in the pixel data converter can be stopped, thereby stopping the output of the pixel data signal.

[0142] (Fourth embodiment) In this embodiment, the oxide semiconductor layer can be applied to the liquid crystal display device described in the above embodiment. This section describes a transistor.

[0143] The transistor including the oxide semiconductor layer described in this embodiment can be highly purified to obtain a pure oxide semiconductor layer. a transistor having an oxide semiconductor layer that is made intrinsic (also called i-type) or substantially intrinsic The high purification means removing hydrogen from the oxide semiconductor layer as much as possible and and reducing defects due to oxygen deficiency in the oxide semiconductor layer by supplying oxygen to the oxide semiconductor layer. It is a concept that includes the other.

[0144] Structural examples of the transistor of this embodiment will be described with reference to FIGS. 5A to 5D are schematic cross-sectional views illustrating structural examples of transistors.

[0145] The transistor shown in FIG. 5A is a bottom-gate transistor. It is also called a tag transistor.

[0146] The transistor illustrated in FIG. 5A includes a conductive layer 401a, an insulating layer 402a, and an oxide semiconductor The conductive layer 403a includes a conductive layer 405a and a conductive layer 406a.

[0147] The conductive layer 401a is provided on the substrate 400a, and the insulating layer 402a is provided on the conductive layer 401a. The oxide semiconductor layer 403a is provided on the conductive layer 401a with the insulating layer 402a interposed therebetween. The conductive layer 405a and the conductive layer 406a are provided over part of the oxide semiconductor layer 403a. are provided respectively.

[0148] Furthermore, in FIG. 5A, part of the top surface of the oxide semiconductor layer 403a of the transistor (top surface The oxide insulating layer 407 is formed on the insulating film 404 (a portion where the conductive layer 405a and the conductive layer 406a are not provided). In addition, a protective insulating layer 409a is provided over the oxide insulating layer 407a.

[0149] The transistor shown in FIG. 5B is a channel-protected transistor (CFT), which is a type of bottom-gate structure. It is a transistor (also called a "nel-stop type") and is also called an inverted staggered transistor.

[0150] The transistor illustrated in FIG. 5B includes a conductive layer 401b, an insulating layer 402b, and an oxide semiconductor layer 403b, insulating layer 427, conductive layer 405b, and conductive layer 406b.

[0151] The conductive layer 401b is provided on the substrate 400b, and the insulating layer 402b is provided on the conductive layer 401b. The oxide semiconductor layer 403b is provided on the conductive layer 401b with the insulating layer 402b interposed therebetween. The insulating layer 427 is electrically conductive through the insulating layer 402b and the oxide semiconductor layer 403b. The conductive layer 405b and the conductive layer 406b are provided on the insulating layer 427. The conductive layer 401b is formed on a part of the oxide semiconductor layer 403b. The conductive layer 401b may be made of an oxide semiconductor layer 403b. By forming a structure in which the oxide semiconductor layer 403b is entirely overlapped, the light reaching the oxide semiconductor layer 403b is Furthermore, the conductive layer 401b is not limited to this, and may be made of an oxide semiconductor. It may also be configured so that it overlaps part of the body layer 403b.

[0152] Furthermore, in FIG. 5B, the top of the transistor is in contact with a protective insulating layer 409b.

[0153] The transistor shown in FIG. 5C is one of bottom-gate transistors.

[0154] The transistor illustrated in FIG. 5C includes a conductive layer 401c, an insulating layer 402c, and an oxide semiconductor layer 403c, conductive layer 405c, and conductive layer 406c.

[0155] The conductive layer 401c is provided on the substrate 400c, and the insulating layer 402c is provided on the conductive layer 401c. The conductive layer 405c and the conductive layer 406c are provided on a part of the insulating layer 402c. The oxide semiconductor layer 403c is formed between the insulating layer 402c, the conductive layer 405c, and the conductive layer 406. The conductive layer 401c is provided on the oxide semiconductor layer 401c via the oxide semiconductor layer 401c. Alternatively, the conductive layer 401c may overlap the entire oxide semiconductor layer 403. By forming a structure in which the oxide semiconductor layer 403c overlaps the entire oxide semiconductor layer 403c, the incidence of light into the oxide semiconductor layer 403c can be suppressed. Furthermore, without being limited thereto, the conductive layer 401c can be formed by forming a conductive film on the oxide semiconductor layer 403c. It is also possible to make it have a structure in which it overlaps with a part of the other.

[0156] 5C, the top and side surfaces of the oxide semiconductor layer 403c in the transistor are The oxide insulating layer 407c has a protective insulating layer on the top thereof. Layer 409c is provided.

[0157] The transistor shown in FIG. 5D is one of top-gate transistors.

[0158] The transistor illustrated in FIG. 5D includes a conductive layer 401d, an insulating layer 402d, and an oxide semiconductor layer 403d, conductive layer 405d, and conductive layer 406d.

[0159] The oxide semiconductor layer 403d is provided on the substrate 400d via the insulating layer 447. The oxide semiconductor layer 403d is partially covered with the conductive layer 405d and the conductive layer 406d. The insulating layer 402d is a layer between the oxide semiconductor layer 403d, the conductive layer 405d, and the conductive layer 406d. The conductive layer 401d is provided on the oxide semiconductor layer 403d with the insulating layer 402d interposed therebetween. It will be established in.

[0160] The substrates 400a to 400d are made of, for example, barium borosilicate glass or aluminophore. A glass substrate such as silicate glass can be used.

[0161] The substrates 400a to 400d may be ceramic substrates, quartz substrates, or sapphire substrates. Alternatively, a substrate made of an insulating material such as a silicon substrate may be used. Crystallized glass can also be used as the substrate 400a to the substrate 400d. A plastic substrate can also be used as the substrate 400a to the substrate 400d. A semiconductor substrate such as silicon can also be used as the substrate.

[0162] The insulating layer 447 functions as a base layer that prevents the diffusion of impurity elements from the substrate 400d. The insulating layer 447 may be, for example, a silicon nitride layer, a silicon oxide layer, or a silicon nitride oxide layer. A silicon layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer is used. The insulating layer 447 can be formed by stacking layers of materials applicable to the insulating layer 447. The insulating layer 447 may be formed by combining a layer of a material having a light-shielding property with the above insulating material. It is also possible to use a laminate with a layer of material applicable to the edge layer 447. By forming the insulating layer 447 using a material layer, the oxide semiconductor layer 403d is prevented from being exposed to light. The incidence can be suppressed.

[0163] Note that, among the transistors shown in FIGS. 5A to 5C, the transistor shown in FIG. As with transistors, an insulating layer may be provided between the substrate and the conductive layer that functions as the gate electrode. stomach.

[0164] Each of the conductive layers 401a to 401d functions as a gate electrode of a transistor. The conductive layers 401a to 401d can be formed using, for example, molybdenum, titanium, Chromium, Tantalum, Tungsten, Aluminum, Copper, Neodymium, or Scandium A layer of a metal material such as these or an alloy material containing these as a main component can be used. The conductive layer 401a to 401d are formed by stacking layers of materials applicable to the formation of the conductive layers 401a to 401d. The conductive layers 401a to 401d can also be formed.

[0165] Each of the insulating layers 402a to 402d serves as a gate insulating layer of a transistor. The insulating layers 402a to 402d can be formed using, for example, a silicon oxide layer, a nitride layer, or the like. silicon oxide layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer an aluminum layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer; In addition, a material applicable to the insulating layers 402a to 402d can be used. The insulating layers 402a to 402d can also be formed by stacking layers. The layers of material applicable to the insulating layer 402a to the insulating layer 402d can be formed by, for example, plasma CVD or sputtering. For example, a silicon nitride layer is formed by the plasma CVD method. A silicon oxide layer is formed on the silicon nitride layer by plasma CVD. The insulating layers 402a to 402d can be formed by this.

[0166] The oxide semiconductor layers 403a to 403d are transistor channels. The oxide semiconductor layers 403a to 403d function as a panel-forming layer. Examples of oxide semiconductors that can be used include quaternary metal oxides, ternary metal oxides, and Binary metal oxides and the like can be used. Examples of quaternary metal oxides include In- Sn-Ga-Zn-O based metal oxides can be used. is, for example, an In-Ga-Zn-O based metal oxide, an In-Sn-Zn-O based metal oxide, an I n-Al-Zn-O metal oxide, Sn-Ga-Zn-O metal oxide, Al-Ga-Z nO-based metal oxides or Sn-Al-Zn-O-based metal oxides can be used. Examples of binary metal oxides include In-Zn-O based metal oxides and Sn-Zn-O based metal oxides. metal oxides, Al-Zn-O metal oxides, Zn-Mg-O metal oxides, Sn-Mg-O In-based metal oxides, In-Mg-O-based metal oxides, In-Ga-O-based metal oxides, or In- Sn—O-based metal oxides can be used. In-O based metal oxide, Sn-O based metal oxide, or Zn-O based metal oxide is used In addition, the oxide semiconductor may be a metal oxide that can be used as the oxide semiconductor. The oxide may also be an oxide containing SiO2.

[0167] When an In-Zn-O based metal oxide is used, for example, In:Zn=50:1 to In:Z n=1:2 (converted to a molar ratio of In2O3:ZnO=25:1 or In2O3:Zn In:Zn=1:4), preferably In:Zn=20:1 to In:Zn=1:1 (in terms of molar ratio) In2O3:ZnO=10:1 to In2O3:ZnO=1:2), more preferably Or In:Zn=15:1 or In:Zn=1.5:1 (converted to molar ratio In2 Oxide targets with a composition ratio of In2O3:ZnO=15:2 to In2O3:ZnO=3:4 A semiconductor layer of In-Zn-O based metal oxide can be formed using the above method. For example, The target used for forming the In-Zn-O based oxide semiconductor is a material with an atomic ratio of In:Zn:O When the ratio is H:S:Z, Z>1.5H+S. By increasing the amount of In, The mobility of the transistor can be improved.

[0168] In addition, as an oxide semiconductor, InMO3(ZnO) m (m is a number greater than 0) Here, M is selected from Ga, Al, Mn, and Co. It represents one or more metal elements. For example, M can be Ga, Ga and Al, or Ga and Mn. , or Ga and Co, etc.

[0169] The conductive layers 405a to 405d and the conductive layers 406a to 406d are The conductive layer functions as a source electrode or a drain electrode of a transistor. The conductive layers 405a to 405d and the conductive layers 406a to 406d may be, for example, For example, aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten Any metal material or alloy material containing these metal materials as the main component can be used. In addition, the conductive layers 405a to 405d and the conductive layers 406a to 406d The conductive layers 405a to 405d and the conductive layer 406 are formed by stacking layers of applicable materials. Each of the conductive layers 406a to 406d can be formed.

[0170] For example, a metal layer of aluminum or copper and a metal layer of titanium, molybdenum, or tungsten, etc. The conductive layers 405a to 405d and the conductive layers 406a to 406d are stacked with the high-melting-point metal layer. The conductive layer 406d can be formed. In addition, aluminum can be formed between the plurality of high melting point metal layers. Alternatively, the conductive layers 405a to 405d and the conductive layer 405e may be stacked on a copper metal layer. The conductive layers 406a to 406d can also be formed. The aluminum layer is doped with elements (Si, Nd, Sc, etc.) that prevent oxidation. The conductive layers 405a to 405d and the conductive layers 406a to 406d are formed. This can improve the heat resistance.

[0171] In addition, the conductive layers 405a to 405d and the conductive layers 406a to 406d Alternatively, a layer containing a conductive metal oxide may be used. For example, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), or indium oxide Indium-zinc oxide alloy (In2O3-ZnO), or silicon oxide in these metal oxides can be used.

[0172] Further, the conductive layers 405a to 405d and the conductive layers 406a to 406d are formed. Other wiring may be formed using the material used for the above.

[0173] The insulating layer 427 is a layer for protecting a channel formation layer of a transistor (also called a channel protection layer). ) and the insulating layer 427 is made of a material applicable to the insulating layer 447, for example. Alternatively, the insulating layer 427 may be formed by stacking layers of materials applicable to the insulating layer 427. 427 can also be configured.

[0174] The oxide insulating layer 407a and the oxide insulating layer 407c can be formed using an oxide insulating layer. For example, a silicon oxide layer can be used. The oxide insulating layer 407a and the oxide insulating layer 407c are stacked by stacking layers of materials applicable to the oxide insulating layer 407a and the oxide insulating layer 407c. A compound insulating layer 407c can also be formed.

[0175] The protective insulating layers 409a to 409c can be, for example, inorganic insulating layers. For example, a silicon nitride layer, an aluminum nitride layer, a silicon oxynitride layer, or an oxynitride layer can be used. An aluminum layer or the like can be used. The protective insulating layers 409a to 409c are formed by stacking layers of materials applicable to the insulating layer 409a. It can also be configured.

[0176] Further, as an example of a method for manufacturing a transistor of this embodiment, a transistor shown in FIG. 6(A) to 6(C), 7(A) and 7(B) are used to illustrate an example of a method for manufacturing a transistor. 6(A) to 6(C) and 7(A) and 7(B) are the same as those in FIG. 1A is a schematic cross-sectional view illustrating an example of a method for manufacturing the transistor shown in FIG.

[0177] First, a substrate 400a is prepared, and a first conductive film is formed on the substrate 400a.

[0178] The first conductive film may be made of, for example, molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, or scandium, or A film of an alloy material containing the following as a main component can be used. The first conductive film can also be made up of a laminate of material films.

[0179] Next, a first resist mask is formed on the first conductive film by a first photolithography process. The first conductive film is selectively etched using the first resist mask. A conductive layer 401a is formed, and the first resist mask is removed.

[0180] In this embodiment mode, the resist mask may be formed by an ink-jet method. When a resist mask is formed by the inkjet method, a photomask is not used, so the manufacturing process is This reduces manufacturing costs.

[0181] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, Etching may be performed using a resist mask formed from a gradation mask. A multi-tone mask is an exposure mask that transmits light with multiple intensities. The resist mask thus formed has a shape with multiple film thicknesses, and by etching, The shape can be changed, allowing for multiple etching processes to create different patterns. Therefore, at least two or more different types of masks can be produced using one multi-tone mask. Therefore, the number of exposure masks can be reduced. This simplifies the manufacturing process by eliminating the need for a photolithography process. It can be abbreviated.

[0182] Next, an insulating layer 402a is formed on the conductive layer 401a.

[0183] For example, the insulating layer 402a is formed by depositing an insulating film using a high density plasma CVD method. For example, high density microwaves (e.g., frequencies of 2.45 GHz) can be used. The plasma CVD method is capable of depositing dense, high-quality insulating films with high dielectric strength. It is preferable to form a high-quality insulating layer by depositing an insulating film using a high-density plasma CVD method. This reduces the interface state between the gate insulating layer and the channel forming layer of the transistor, This can improve the surface characteristics.

[0184] Alternatively, the insulating layer 402a may be formed by other methods such as sputtering or plasma CVD. Alternatively, heat treatment may be performed after the insulating layer 402a is formed. The heat treatment improves the quality of the insulating layer 402a and the interface characteristics with the oxide semiconductor. This can be done.

[0185] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm to 30 nm, is deposited on the insulating layer 402a. The oxide semiconductor film 530 is formed to a thickness of 1000 nm or less by a sputtering method. A semiconductor film 530 can be formed.

[0186] Note that before the oxide semiconductor film 530 is formed, argon gas is introduced to generate plasma. The powdery substances (particles, It is preferable to remove the dust. Inverse sputtering, a voltage is applied to the target side. Without applying the plasma, a voltage was applied to the substrate side using an RF power supply in an argon atmosphere, and plasma was generated near the substrate. This is a method of modifying the surface by forming a mask. Note that nitrogen or helium atmosphere can be used instead of argon atmosphere. , oxygen, etc. may also be used.

[0187] For example, an oxide semiconductor film 403a can be formed using an oxide semiconductor material that can be used for the oxide semiconductor layer 403a. In this embodiment, as an example, an In—Ga—Zn—O system The oxide semiconductor film 530 is formed by a sputtering method using an oxide target. The cross-sectional view at this stage corresponds to Figure 6(A). In the atmosphere, oxygen atmosphere, or a mixture of rare gas and oxygen, the sputtering method The oxide semiconductor film 530 can also be formed.

[0188] Examples of targets for forming the oxide semiconductor film 530 by a sputtering method include: For example, an acid with a composition ratio of In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] The target is not limited to the above targets, and may be, for example, For example, oxides with a composition ratio of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] A target may be used. In addition, the total volume of the oxide target to be produced may be The ratio of the volume of the body excluding the space occupied by voids (also called the filling rate) is 9 The filling rate is 0% or more and 100% or less, preferably 95% or more and 99.9% or less. An oxide semiconductor film formed using an oxide target becomes a dense film.

[0189] Note that a sputtering gas used in forming the oxide semiconductor film 530 is, for example, It is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. I wish.

[0190] Before the oxide semiconductor film 530 is formed, a conductive layer is formed in a preheating chamber of a sputtering apparatus. A substrate 400a on which a conductive layer 401a and an insulating layer 402a are formed, or The substrate 400a is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 400a. By the preheating, the insulating layer 402a and the oxide semiconductor film 53 It is possible to prevent hydrogen, hydroxyl groups, and moisture from entering the preheating chamber. As the exhaust means, it is preferable to use, for example, a cryopump. The heat treatment can be omitted. The substrate 400a on which the conductive layer 406a and the conductive layer 5a have been formed may also be subjected to the preheating treatment. stomach.

[0191] In addition, when the oxide semiconductor film 530 is formed by a sputtering method, the temperature is kept low. The substrate 400a is held in the film-forming chamber, and the substrate temperature is set to 100° C. or more and 600° C. or less, preferably The temperature is preferably 200° C. or higher and 400° C. or lower. The concentration of impurities contained in the oxide semiconductor film 530 can be reduced. Damage to the oxide semiconductor film 530 caused by heating is reduced. While the target is being heated, a sputtering gas from which hydrogen and moisture have been removed is introduced. An oxide semiconductor film 530 is formed over the insulating layer 402a.

[0192] In this embodiment, residual moisture in the film formation chamber during sputtering is removed. As a means, for example, an adsorption type vacuum pump can be used. Pumps include, for example, cryopumps, ion pumps, or titanium sublimation pumps. For example, by using a cryopump, hydrogen atoms, and compounds containing one or more of carbon atoms, etc., can be exhausted in the film formation chamber. The concentration of impurities contained in the formed film can be reduced. In this case, a turbo pump is used as a means of removing residual moisture in the film formation chamber during sputtering. A cold trap may also be used.

[0193] An example of the deposition conditions for the oxide semiconductor film 530 using a sputtering apparatus is as follows: The distance between the target and the target was 100 mm, the pressure was 0.6 Pa, the DC power supply was 0.5 kW, and the acid The conditions applied were a nitrogen atmosphere (oxygen flow rate 100%). When used, the amount of powdery material generated during film formation can be reduced, and the film thickness distribution becomes uniform.

[0194] Next, a second resist is formed on the oxide semiconductor film 530 by a second photolithography process. A mask is formed, and the oxide semiconductor film 530 is selectively etched using a second resist mask. By performing etching, the oxide semiconductor film 530 is processed into an island-shaped oxide semiconductor layer, and a second The resist mask is removed.

[0195] Note that when contact holes are formed in the insulating layer 402a, the oxide semiconductor film 530 is formed into an island shape. The contact holes can also be formed when processing the oxide semiconductor layer.

[0196] For example, dry etching, wet etching, or dry etching and wet etching. The oxide semiconductor film 530 can be etched using both wet etching and wet etching. The etching solution used for etching is, for example, a solution made by mixing phosphoric acid, acetic acid, and nitric acid. In addition, ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used as an etching solution. Good too.

[0197] Next, the oxide semiconductor layer is subjected to first heat treatment. The temperature of the first heat treatment is 400° C. or higher. The temperature is set to 750°C or lower, or 400°C or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, and the oxide semiconductor layer was heated at 450°C in a nitrogen atmosphere. After the heat treatment for 1 hour, water and hydrogen were re-absorbed into the oxide semiconductor layer without exposure to the air. The contamination is prevented, and an oxide semiconductor layer 403a is obtained (see FIG. 6B).

[0198] The heat treatment device is not limited to an electric furnace, and may be a device that uses heat conduction or heat from a heating element such as a resistance heating element. The apparatus may include a device for heating the object to be treated by radiation. GRTA (Gas Rapid Thermal Anneal) device or LRTA (L Rapid Thermal Anneal (RTA) equipment The LRTA device can be used with, for example, halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, Radiation of light (electromagnetic waves) emitted from lamps such as high-pressure sodium lamps or high-pressure mercury lamps The GRTA device uses high-temperature gas to heat the object to be treated. This is a device for performing heat treatment. The high-temperature gas is, for example, a rare gas such as argon or nitrogen. An inert gas that does not react with the object to be treated by heat treatment can be used.

[0199] For example, in the first heat treatment, the substrate is transferred into an inert gas heated to 650°C to 700°C. After heating for a few minutes, the substrate is removed from the heated inert gas. GRTA may be performed.

[0200] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. The purity of rare gases such as helium, neon, or argon is measured at 6N (99.9999%). ) or more, preferably 7N (99.99999%) or more, that is, the impurity concentration is 1 ppm or less. It is preferable to keep the concentration below 0.1 ppm.

[0201] After the oxide semiconductor layer is heated by the first heat treatment, the oxide semiconductor layer is heated while the heating temperature is maintained or In the process of lowering the temperature from the heating temperature, high-purity oxygen gas was added to the same furnace as that used for the first heat treatment. High-purity N2O gas or ultra-dry air (dew point below -40°C, preferably below -60°C) At this time, oxygen gas or N2O gas may be introduced into the atmosphere containing water, hydrogen, etc. It is preferable that the purity of the oxygen gas or N2O gas introduced into the heat treatment device is is 6N or more, preferably 7N or more, that is, the impurity concentration in the oxygen gas or N2O gas It is preferable to set the concentration of oxygen gas or N2 to 1 ppm or less, preferably 0.1 ppm or less. The action of O gas simultaneously reduces impurities through the dehydration or dehydrogenation process. By supplying a small amount of oxygen, the oxide semiconductor layer 403a is highly purified. .

[0202] In addition, the oxide semiconductor film 530 before being processed into the island-shaped oxide semiconductor layer is subjected to first heat treatment. In this case, the substrate is taken out of the heating device after the first heat treatment, and the island-like The oxide semiconductor layer is processed into an oxide semiconductor layer.

[0203] In addition to the above, if the oxide semiconductor layer is formed, a conductive film may be introduced onto the oxide semiconductor layer 403a. After the conductive layer 405a and the conductive layer 406a are formed, or after the conductive layer 405a and the conductive layer 406a are formed, The first heat treatment may be performed after the oxide insulating layer 407a is formed over the insulating film 407a.

[0204] In addition, when a contact hole is formed in the insulating layer 402a, the contact hole is formed before the first heat treatment. Contact holes may be formed.

[0205] In addition, the oxide semiconductor film is formed in two separate steps and heat-treated in two separate steps. Regardless of the material of the component, such as oxide, nitride, or metal, the film thickness is thick and the crystalline region (single crystal region) The oxide was grown using a film having a crystal region with a c-axis orientation perpendicular to the film surface. For example, a first oxide semiconductor layer having a thickness of 3 nm to 15 nm may be formed. A thin film is formed, and then, as a first heat treatment, the thin film is heated in an atmosphere of nitrogen, oxygen, a rare gas, or dry air. Heat treatment is carried out in air at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. a first oxide semiconductor film having a crystalline region (including a plate-like crystal) in a region including a surface thereof; Then, a second oxide semiconductor film that is thicker than the first oxide semiconductor film is formed. The second heat treatment is performed at a temperature of 450°C to 850°C, preferably 600°C to 700°C. The following heat treatment is performed to grow the first oxide semiconductor film using the first oxide semiconductor film as a seed for crystal growth. Crystal growth is performed upward from the oxide semiconductor film to the second oxide semiconductor film, and the second oxide semiconductor film is formed. As a result, an oxide semiconductor film having a thick crystalline region is used. The oxide semiconductor layer 403a can be formed using this method.

[0206] Next, a second conductive film is formed over the insulating layer 402a and the oxide semiconductor layer 403a.

[0207] The second conductive film may be made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. Metallic materials such as tungsten or tungsten, or alloy materials whose main components are these metallic materials In addition, a laminated film of films applicable to the second conductive film can be used. A conductive film may be formed.

[0208] Next, a third resist mask is formed on the second conductive film by a third photolithography process. Then, the conductive layer 405a and the conductive layer 405b are selectively etched using a third resist mask. After the conductive layer 406a is formed, the third resist mask is removed (see FIG. 6C).

[0209] Note that when the conductive layers 405a and 406a are formed, the second conductive film is used to form other wiring layers. Lines can also be formed.

[0210] In addition, ultraviolet light, KrF laser light, or ArF laser light is used as the exposure light when forming the third resist mask. The conductive layer 405a adjacent to the oxide semiconductor layer 403a is preferably formed by using the phototransistor. The gap width between the bottom end of the conductive layer 406a and the bottom end of the conductive layer 406b determines the channel width of the transistor to be formed later. The channel length L is determined. Note that when forming the third resist mask, the channel length L=25n When exposing to light of less than 100 nm, use extreme ultraviolet light (Ext It is recommended to use ultraviolet light. Therefore, the channel length L of the transistor to be formed later is It is also possible to set the thickness of the film to 10 nm or more and 1000 nm or less. By using transistors, the operating speed of the circuit can be increased, and further, The off-state current of the transistor is extremely small, which also reduces power consumption.

[0211] Note that when the second conductive film is etched, the oxide semiconductor layer 403a In order to suppress the separation of the Only the second conductive film is etched, and the oxide semiconductor layer 403a is not etched at all. It is difficult to obtain the condition that the oxide semiconductor is not broken during etching of the second conductive film. The layer 403a is only partially etched, and the oxide semiconductor layer 403 It can also be a.

[0212] In this embodiment, a titanium film is used as an example of the second conductive film, and the oxide semiconductor layer 403a As an example, an In-Ga-Zn-O oxide semiconductor is used, so Ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide) is used.

[0213] Next, an oxide insulating film was formed over the oxide semiconductor layer 403a, the conductive layer 405a, and the conductive layer 406a. At this time, the oxide insulating layer 407a is formed on the oxide semiconductor layer 403a. Touching part of the surface.

[0214] The oxide insulating layer 407a has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The oxide insulating layer 407a is formed by an appropriate method that prevents impurities such as water or hydrogen from being mixed in. When hydrogen is mixed into the oxide insulating layer 407a, the hydrogen penetrates into the oxide semiconductor layer. The back surface of the oxide semiconductor layer is formed by introducing hydrogen into the oxide semiconductor layer or extracting oxygen from the oxide semiconductor layer by the hydrogen. The channel becomes low resistance (N-type), and a parasitic channel may be formed. The oxide insulating layer 407a is formed so as to contain as little hydrogen as possible. It is preferable to use a method that does not use hydrogen as the manufacturing method.

[0215] In this embodiment, as an example of the oxide insulating layer 407a, a thin film having a thickness of 1000 nm is formed by a sputtering method. A 200 nm silicon oxide film is formed. The substrate temperature during film formation is between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. as an example. The film formation by the coating method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. The process can be carried out in a mixed atmosphere of nitrogen and oxygen.

[0216] The oxide insulating layer 407a may be formed using a target such as silicon oxide. For example, a silicon target or a silicon target can be used. Using a nozzle, a silicon oxide film is formed by sputtering in an atmosphere containing oxygen. It is possible.

[0217] The sputtering gas used in forming the oxide insulating layer 407a is, for example, hydrogen, It is preferable to use a high-purity gas from which impurities such as water, hydroxyl groups, or hydrides have been removed. .

[0218] Before forming the oxide insulating layer 407a, a gas such as N 2 O, N 2 , or Ar was used. The plasma treatment is performed to remove adsorbed water and the like attached to the exposed surface of the oxide semiconductor layer 403a. When the plasma treatment is performed, the oxide semiconductor layer may be removed without being exposed to the air. An oxide insulating layer 407a is preferably formed in contact with part of the top surface of 403a.

[0219] Further, a second heat treatment (preferably 20 It is also possible to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. As the second heat treatment, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. After the heat treatment, part of the top surface of the oxide semiconductor layer 403a is in contact with the oxide insulating layer 407a. It is heated in this state.

[0220] Through the above process, hydrogen, water, hydroxyl groups, or hydrides (also called hydrogen compounds) impurities such as fluorine-containing oxide (F2) and fluorine-containing oxide (H2O) are intentionally removed from the oxide semiconductor layer and oxygen is supplied to the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be highly purified.

[0221] Through the above steps, a transistor is manufactured (see FIG. 7A).

[0222] In addition, when a silicon oxide layer containing many defects is used as the oxide insulating layer 407a, The heat treatment after the formation of the oxide semiconductor layer reduces hydrogen, moisture, and hydroxide contained in the oxide semiconductor layer 403a. Impurities such as silicon dioxide or hydrides are diffused into the oxide insulating layer 407a, and the oxide semiconductor layer 40 This has the effect of further reducing the impurities contained in 3a.

[0223] A protective insulating layer 409a may be further formed over the oxide insulating layer 407a. The silicon nitride film is formed using the sputtering method. The RF sputtering method is suitable for mass production. Therefore, this method is preferable as a deposition method for the protective insulating layer 409a. A silicon nitride film is formed on the insulating layer 409a to form a protective insulating layer 409a (see FIG. 7(B)). see).

[0224] In this embodiment, as shown in FIG. 7(A), the oxide insulating layer 407a is formed on the substrate 4. 00a is heated to a temperature of 100℃ to 400℃, and a high-purity nitrogen gas containing hydrogen and moisture is removed. A sputtering gas containing silicon nitride was introduced, and a silicon semiconductor target was used to deposit a silicon nitride film. In this case, the oxide insulating layer 40 As with 7a, it is preferable to form the protective insulating layer 409a while removing the remaining moisture in the film forming chamber. Desirable.

[0225] After the protective insulating layer 409a is formed, the protective insulating layer 409a is further heated in the atmosphere at 100° C. or higher and 200° C. or lower for 1 hour or longer and 3 hours or longer. Heat treatment may be performed for 0 hours or less. In this heat treatment, a constant heating temperature is maintained. It may be heated, or the temperature may be increased from room temperature to a heating temperature of 100°C or more and 200°C or less. The temperature may be lowered from 100°C to room temperature several times. 1 is an example of a method for manufacturing a transistor.

[0226] Note that although an example of a method for manufacturing the transistor illustrated in FIG. 5A is shown, the method is not limited to this. For example, in each of the components shown in FIGS. 5(B) to 5(D), the names of the components shown in FIG. 5(A) may be the same as those of the components shown in FIG. The components are the same as those shown in FIG. 5(A) and at least some of the functions are the same as those shown in FIG. If so, the description of the example of the manufacturing method of the transistor in FIG. 5A can be used as appropriate. Cut.

[0227] As described above, the transistor of this embodiment has a high-purity silicon dioxide layer as a layer in which a channel is formed. The oxide semiconductor layer is an oxide semiconductor layer that has become I-type or substantially I-type by oxidation. By purifying the oxide semiconductor layer, the carrier concentration of the oxide semiconductor layer can be increased to 1×10 1 4 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 This makes it possible to suppress changes in characteristics due to temperature changes. By using the above structure, the off-current per 1 μm of channel width is reduced to 10 aA (1 × 10 -17 A) or less, and further, the off-current per 1 μm of channel width must be 1 aA (1 × 10 -18 A) or less, and further, the off-current per 1 μm of channel width is 10 zA (1 × 10 -20 A) or less, and further, the off-current per 1 μm of channel width is set to 1 zA (1 × 10 -21 A) or less, and further, the off-current per 1 μm of channel width is set to 100 yA (1 × 10 -22 A The lower the off-state current of the transistor, the better. The lower limit of the off-state current of the transistor of this embodiment is about 10 -30 A / μm can be.

[0228] Furthermore, the transistor of this embodiment was evaluated by measuring the leakage current using a characteristic evaluation circuit. An example of calculating the value of the off-state current will be described below.

[0229] First, the configuration of the characteristic evaluation circuit will be described with reference to FIG. 8. FIG. 8 shows the characteristic evaluation circuit FIG.

[0230] The characteristic evaluation circuit shown in Fig. 8 includes a plurality of measurement systems 801. The plurality of measurement systems 801 are In this example, eight measurement systems 801 are connected in parallel. It is completed.

[0231] The measurement system 801 includes a transistor 811, a transistor 812, a capacitance element 813, and a transistor 814. The transistor 814 and the transistor 815 are included.

[0232] A voltage V1 is input to one of the source and drain of the transistor 811. A voltage Vext_a is input to the gate of the transistor 811. The transistor 811 is a charge injection This is a necessary transistor.

[0233] One of the source and drain of the transistor 812 is connected to the source and drain of the transistor 811. The other of the source and drain of the transistor 812 is connected to a voltage V 2 is input to the gate of the transistor 812, and the voltage Vext_b is input to the gate of the transistor 813. The transistor 812 is a transistor for evaluating the leakage current. The leakage current includes the off-state current of the transistor.

[0234] A first electrode of the capacitor 813 is connected to the other of the source and the drain of the transistor 811. A voltage V2 is input to the second electrode of the capacitor 813. 0V is input.

[0235] A voltage V3 is input to one of the source and drain of the transistor 814. The gate of the transistor 814 is connected to the other of the source and drain of the transistor 811. The gate of the transistor 814 and the other of the source and drain of the transistor 811 One of the source and the drain of the transistor 812 and the first electrode of the capacitor 813 The connection point is also called node A.

[0236] One of the source and drain of the transistor 815 is connected to the source and drain of the transistor 814. The other of the source and drain of the transistor 815 is connected to a voltage V 4 is input to the gate of the transistor 815, and the voltage Vext_c is input to the gate of the transistor 816. Here, 0.5V is input as the voltage Vext_c.

[0237] Furthermore, the measurement system 801 detects the other of the source and drain of the transistor 814 and the The voltage at the connection point with one of the source and drain of the transistor 815 is output as the output voltage Vout. To exert effort.

[0238] Here, as an example of the transistor 811, a transistor including an oxide semiconductor layer and having a channel length L=1 The transistors used are 0 μm in thickness and 10 μm in channel width W. An example of the transistor 815 is a transistor including an oxide semiconductor layer, a channel length L=3 μm, and a A transistor with a channel width W of 100 μm is used. The semiconductor device includes an oxide semiconductor layer, and a source electrode and a drain electrode are in contact with the top of the oxide semiconductor layer. , the source electrode and the drain electrode do not overlap with the gate electrode, and the width is 1 μm A bottom gate transistor with an offset region of m is used. By providing the transistor 812, the parasitic capacitance can be reduced. For this purpose, transistors with six different channel lengths L and channel widths W are used (see Table 1). ).

[0239] [Table 1]

[0240] As shown in FIG. 8, a transistor for charge injection and a transistor for leakage current evaluation are By providing them separately, the transistor for leak current evaluation is always turned off during charge injection. If a transistor for charge injection is not provided, the charge injection The transistor for leak current evaluation must be turned on once, but it is necessary to turn it off from the on state. For devices that require time to reach a steady state, measurement takes time. .

[0241] In addition, a transistor for charge injection and a transistor for leak current evaluation are provided separately. This allows each transistor to be sized appropriately. The channel width W of the transistor for current evaluation is set to be smaller than the channel width W of the transistor for charge injection. By making it larger than the leakage current evaluation transistor, the leakage current of the characteristic evaluation circuit other than the leakage current evaluation transistor can be measured. As a result, the current component can be made relatively small. At the same time, the leakage current can be measured with high accuracy. Since it is not necessary to turn on the evaluation transistor once, the charge in the channel formation region There is no influence of voltage fluctuations at node A due to the current flowing into node A.

[0242] On the other hand, the channel width W of the charge injection transistor is By making it smaller than the channel width W, the leakage current of the charge injection transistor is relatively In addition, when the charge is injected, part of the charge in the channel forming region is transferred to the The effect of voltage fluctuations at node A due to current flowing into node A is also small.

[0243] In addition, as shown in Figure 8, by using a structure in which multiple measurement systems are connected in parallel, more accurate measurement can be achieved. The leakage current of the characteristic evaluation circuit can be accurately calculated.

[0244] Next, the off-state current of an example of the transistor of this embodiment was measured using a characteristic evaluation circuit shown in FIG. The method for calculating the value of is explained below.

[0245] First, a method for measuring the leakage current of the characteristic evaluation circuit shown in FIG. 8 will be described with reference to FIG. FIG. 9 is a timing diagram for explaining a leakage current measurement method using the characteristic evaluation circuit shown in FIG. It is a chart.

[0246] The leakage current measurement method using the characteristic evaluation circuit shown in Figure 8 is divided into a write period and a hold period. The operation during each period is explained below.

[0247] First, in the write period, the transistor 812 is turned off as the voltage Vext_b. Input a voltage VL (-3V) so that the voltage V1 is the write voltage Vw After inputting the voltage Vext_a, the transistor 811 is turned on for a certain period of time. This causes a charge to accumulate at node A, and the voltage VH (5V) is The voltage at A becomes equal to the write voltage Vw. A voltage VL is input so that the transistor 811 is turned off. , input voltage VSS (0V).

[0248] Then, during the retention period, the voltage at node A changes due to the change in the charge held at node A. The amount of change in the voltage is measured. The current flowing between the node A and the drain electrode can be calculated. and the amount of change in the voltage at node A can be measured.

[0249] At this time, the charge accumulation at node A and the change in the voltage at node A are measured (accumulation and measurement operations). First, the first accumulation and measurement operation is repeated 15 times. In the accumulation and measurement operation, a voltage of 5 V is input as the write voltage Vw during the write period, The retention period is one hour. Then, the second accumulation and measurement operation is repeated twice. In the accumulation and measurement operation of 2, a voltage of 3.5 V was input as the write voltage Vw during the write period. The data is input and held for 50 hours during the holding period. Next, the third accumulation and measurement operation is performed once. In the accumulation and measurement operation of 3, a voltage of 4.5 V was input as the write voltage Vw during the write period. The data is input and held for 10 hours. By repeating the accumulation and measurement operations, It can be confirmed that the measured current value is a value in a steady state. and the current I flowing through node A A Of these, the transient current (which decreases over time after measurement begins) As a result, leakage current can be measured with higher accuracy. It is possible.

[0250] In general, the voltage at node A, V A is expressed as a function of the output voltage Vout as shown in equation (1). do.

[0251]

number

[0252] Also, the charge Q at node A A is the voltage at node A, V A , capacitance C connected to node A A , fixed Using a constant, it is expressed as in equation (2). Capacity C A is the sum of the capacitance of the capacitor 813 and the capacitance components other than the capacitor 813.

[0253]

number

[0254] Current I at node A A is the charge flowing into (or out of) node A. Since it is a time derivative, the current I at node A A is expressed as in equation (3).

[0255]

number

[0256] Here, as an example, Δt is set to approximately 54,000 seconds. Capacitance C connected to A and the leakage current I at node A from the output voltage Vout A Therefore, the leakage current of the characteristic evaluation circuit can be calculated.

[0257] Next, the output voltage measurement results using the above characteristic evaluation circuit and the The calculated leakage current value of the characteristic evaluation circuit is shown.

[0258] FIG. 10 shows, as an example, the above measurements under conditions 4, 5, and 6 (first accumulation and The relationship between the elapsed time Time and the output voltage Vout is shown in FIG. The elapsed time Time for the measurement and the current I calculated by the measurement A This shows the relationship between The output voltage Vout fluctuates from the start of measurement, and it takes more than 10 hours to reach a steady state. It turns out that it is necessary.

[0259] FIG. 12 shows the voltage at node A under conditions 1 to 6 estimated by the above measurements. The relationship between the leakage current and the voltage at node A is shown in Figure 12. At 0V, the leakage current is 28 yA / μm. Since the off-state current is also included, the off-state current of the transistor 812 is also considered to be 28 yA / μm or less. It is possible.

[0260] 13 to 15 show the results of the above measurements at 85°C, 125°C, and 150°C. The relationship between the voltage at node A and the leakage current under conditions 1 to 6 is shown in FIG. As shown in FIG. 15, even at 150° C., the leakage current was 100 zA / μm It can be seen that the following is true.

[0261] As described above, the semiconductor device having a function as a channel formation layer and including a highly purified oxide semiconductor layer In the characteristic evaluation circuit using a transistor containing It can be seen that the off-state current of the transistor is sufficiently small. It can be seen that the current is sufficiently low even when the temperature is increased.

[0262] (Embodiment 5) In this embodiment, a structural example of a unit pixel in the liquid crystal display device shown in the above embodiment will be described. I will explain.

[0263] The unit pixel in this embodiment is a pixel provided with a semiconductor element such as a transistor. The first substrate (also called an active matrix substrate) and the second substrate (also called an opposing substrate) and a liquid crystal layer provided between the active matrix substrate and the counter substrate.

[0264] First, an example of the structure of an active matrix substrate in a unit pixel of this embodiment is shown in FIG. 16 is a diagram showing an active matrix in a unit pixel of this embodiment. 16A is a schematic diagram illustrating an example of the structure of a substrate, and FIG. 16B is a schematic plan view. 6(B) is a schematic cross-sectional view taken along line AB in FIG. 16(A). As an example of a transistor, the structure described with reference to FIG. The case where a transistor of is used is shown.

[0265] The active matrix substrate shown in FIGS. 16(A) and 16(B) comprises a substrate 501 and a conductive layer 511, conductive layer 512, insulating layer 521, semiconductor layer 541, conductive layer 551, and conductive The conductive layer 552, the conductive layer 553, the oxide insulating layer 561, the protective insulating layer 571, and the color film The semiconductor device includes a filter layer 581 , a planarizing insulating layer 601 , and a conductive layer 611 .

[0266] The substrate 501 corresponds to the substrate 400a in FIG.

[0267] The conductive layer 511 and the conductive layer 512 are provided on one surface of the substrate 501. The conductive layer 511 is The select signal SEL is input to the select signal line. The conductive layer 512 corresponds to the first electrode of the capacitor. Has.

[0268] The insulating layer 521 is provided on one surface of the substrate 501 via the conductive layers 511 and 512. The insulating layer 521 corresponds to the insulating layer 402a in FIG. 5(A) and is a dielectric layer of the capacitance element. It has bodily functions.

[0269] The semiconductor layer 541 overlaps with the conductive layer 511 and is separated from the substrate 511 and the insulating layer 521 with the conductive layer 511 and the insulating layer 521 interposed therebetween. The semiconductor layer 541 is provided on one surface of the oxide semiconductor layer 4 in FIG. Equivalent to 03a.

[0270] The conductive layer 551 is electrically connected to the semiconductor layer 541 and receives the pixel data signal PXD. 5A. do.

[0271] The conductive layer 552 is electrically connected to the semiconductor layer 541. The conductive layer 552 is also electrically connected to the insulating layer The conductive layer 552 overlaps with the conductive layer 512 with the conductive layer 521 interposed therebetween. 06a and functions as the second electrode of the capacitor.

[0272] The conductive layer 553 is electrically connected to the insulating layer 521 through a contact hole 531 . The conductive layer 553 functions as a wiring to which a voltage is input. The contact hole 531 is formed by, for example, forming the insulating layer 521 and then forming a conductive layer. The insulating layer 512 and the insulating layer 521 are formed on one surface of the substrate 501 by a photolithography process. A resist mask is formed, and the insulating layer 521 is selectively etched. Note that the conductive layer 553 is not necessarily provided, and the conductive layer 512 may function as a wiring. It can also be done.

[0273] The oxide insulating layer 561 is in contact with the semiconductor layer 541, and the conductive layer 511, the conductive layer 512, and the insulating layer 521, the semiconductor layer 541, and the conductive layers 551 to 553. The oxide insulating layer 561 is formed on a flat surface. Equivalent.

[0274] The protective insulating layer 571 is laminated on the oxide insulating layer 561. The protective insulating layer 571 is ) corresponds to the protective insulating layer 409a.

[0275] The color filter layer 581 is laminated on the protective insulating layer 571. The color filter layer 581 is When a white unit pixel is provided in a pixel, the white The color filter layer 581 is not provided in the unit pixel.

[0276] The planarization insulating layer 601 is laminated on the protective insulating layer 571 via the color filter layer 581. .

[0277] The conductive layer 611 is laminated on the planarization insulating layer 601, and the planarization insulating layer 601, the color filter The contact hole 581 is formed through the protective insulating layer 571 and the oxide insulating layer 561. The conductive layer 611 is electrically connected to the conductive layer 552 through the contact hole 591. It functions as a pixel electrode.

[0278] Furthermore, an example of the structure of the unit pixel of this embodiment will be described with reference to FIG. 2A and 2B are schematic cross-sectional views showing an example of the structure of a unit pixel according to the present embodiment.

[0279] The unit pixel shown in FIG. 17 is an active matrix substrate shown in FIGS. 16(A) and 16(B). In addition to the plate, it includes a substrate 621 , a conductive layer 631 , and a liquid crystal layer 641 .

[0280] The conductive layer 631 is provided on one surface of the substrate 621. The conductive layer 631 serves as a common electrode. The color filter layer 581 has a function of insulating the conductive layer 511 and the conductive layer 512. the layer 521, the semiconductor layer 541, the conductive layers 551 to 553, the oxide insulating layer 561, and The substrate 621 and the conductive layer 631 are not provided on one surface of the substrate 501 via the protective insulating layer 571. The conductive layer 631 does not necessarily have to be provided on one surface of the substrate 621. For example, the conductive layer 511 and the conductive layer 512, the insulating layer 521, the semiconductor layer 541, the conductive layer 5 51 to the conductive layer 553, the oxide insulating layer 561, the protective insulating layer 571, and the planarizing insulating layer 6 Alternatively, the light emitting element 501 may be provided on one surface of the substrate 501 via the optical fiber 501 .

[0281] The liquid crystal layer 641 is provided between the conductive layer 611 and the conductive layer 631. It functions as a liquid crystal containing crystal molecules.

[0282] The substrate 501 and the substrate 621 are substrates applicable to the substrate 400a in FIG. 5(A). can be used.

[0283] The conductive layer 511 and the conductive layer 512 can be applied to the conductive layer 401a in FIG. In addition, layers of materials applicable to the conductive layer 401a can be stacked. The conductive layers 511 and 512 may be formed by the above-mentioned method.

[0284] The insulating layer 521 is made of a material that can be used for the insulating layer 402a in FIG. In addition, the insulating layer 521 can be formed by stacking layers of materials that can be used for the insulating layer 402a. It may be configured.

[0285] The semiconductor layer 541 is formed of a material applicable to the oxide semiconductor layer 403a shown in FIG. The semiconductor layer 541 can be formed of a layer of Group 14 of the periodic table. A semiconductor layer using a semiconductor (such as silicon) may also be used.

[0286] The conductive layers 551 to 553 may be the conductive layer 405a or the conductive layer A layer of a material applicable to the conductive layer 406a can be used. The conductive layers 551 and 553 may be formed by stacking layers of materials applicable to 406a. stomach.

[0287] The oxide insulating layer 561 can be formed using a material that can be used for the oxide insulating layer 407a in FIG. Alternatively, a layer applicable to the oxide insulating layer 407a may be stacked to form an oxide insulating layer. A compound insulating layer 561 may be formed.

[0288] The protective insulating layer 571 is made of a material applicable to the protective insulating layer 409a in FIG. In addition, a protective insulating layer can be formed by stacking layers applicable to the protective insulating layer 409a. Layer 571 may be configured.

[0289] The color filter layer 581 may be, for example, a layer containing a dye or a pigment. For example, when a dye is included, the dye may be printed using a photolithography method, a printing method, or an inkjet method. When the ink is formed and contains a pigment, it may be formed by a photolithography method, a printing method, an electrodeposition method, an electrophotography method, or the like. In this example, the colored layer is formed by the inkjet method. By using the PET method, it is possible to manufacture at room temperature, in a low vacuum, or on a large substrate. In addition, since it is possible to manufacture without using a resist mask, This reduces costs and the number of manufacturing processes. Furthermore, since the film is applied only to the necessary areas, it is not necessary to apply it to the entire surface. Compared to the method of etching after film formation, this method wastes less material and reduces manufacturing costs. It is possible.

[0290] The planarization insulating layer 601 may be made of an organic material such as polyimide, acrylic, or benzocyclobutene. A layer of a material can be used. Also, a low-k material can be used as the planarization insulating layer. A layer of a material applicable to the planarization insulating layer can also be used. The planarization insulating layer 601 can also be formed by lamination.

[0291] The conductive layer 611 and the conductive layer 631 can be formed using, for example, a light-transmitting conductive material layer. Examples of the conductive material having light transmission include indium tin oxide and indium oxide. A metal oxide (also known as IZO: indium zinc oxide) made by mixing zinc oxide with cellulose Conductive materials made by mixing indium oxide with silicon oxide (SiO2), organic indium, Organotin, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, or indium tin oxide with titanium oxide Oxides and the like can be used.

[0292] The conductive layer 611 and the conductive layer 631 contain a conductive polymer. The conductive layer formed using the conductive composition can be The sheet resistance is 10,000 Ω / □ or less, and the light transmittance at a wavelength of 550 nm is 70% or more. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω· It is preferable that the thickness is less than 1 cm.

[0293] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples of the conjugated conductive polymer include polyaniline or its derivatives, and polypyrrole. or derivatives thereof, polythiophene or derivatives thereof, or aniline, pyrrole and Examples include copolymers of two or more types of thiophene or derivatives thereof.

[0294] The liquid crystal layer 641 may be, for example, a TN liquid crystal, an OCB liquid crystal, an STN liquid crystal, a VA liquid crystal, or an ECB type. Use of a layer containing liquid crystal, GH liquid crystal, polymer dispersed liquid crystal, discotic liquid crystal, or the like can be done.

[0295] As described with reference to FIGS. 16 and 17, an example of a unit pixel of this embodiment is a transistor. an active matrix substrate including a pixel electrode and a counter substrate; and a liquid crystal layer having liquid crystal between the substrate and the counter substrate. By doing so, it is possible to form a unit pixel of the liquid crystal display device according to the above embodiment. do.

[0296] (Embodiment 6) In this embodiment, one of the backlight units of the liquid crystal display device in the first embodiment is An example will be described.

[0297] An example of the configuration of the backlight unit in this embodiment will be described with reference to FIG. Fig. 18 is a schematic diagram showing an example of the configuration of a backlight unit according to this embodiment.

[0298] FIG. 18(A) is a schematic diagram showing a configuration example of a direct type backlight unit. The backlight unit shown in FIG. 7 includes a reflector 701a, a cold cathode fluorescent lamp 702a, and a diffusion plate 70 3a and a prism sheet 704a.

[0299] The cold cathode fluorescent lamp 702a is provided on one surface of the reflector 701a. As shown in FIG. 18(A), the cold cathode fluorescent lamps 702a are sandwiched between the cold cathode fluorescent lamps 702a. It may be provided.

[0300] The diffusion plate 703a is provided on one plane of the reflector 701a via the cold cathode fluorescent lamps 702a.

[0301] The prism sheet 704a reflects the light from the reflector 701 through the cold cathode fluorescent lamps 702a and the diffuser 703a. It is provided on one plane of a.

[0302] The backlight unit shown in FIG. 18(A) includes a diffusion plate 703a and a prism sheet 704. Light from the cold cathode fluorescent lamp 702a is emitted through a.

[0303] FIG. 18(B) is a schematic diagram showing an example of the configuration of a sidelight type backlight unit. The backlight unit shown in FIG. 18(B) includes a reflector 701b and cold cathode fluorescent lamps 702b. , the diffusion plate 703b, the prism sheet 704b, the scattering pattern 708, and the light guide plate 70 9 and a lamp reflector 710.

[0304] The cold cathode fluorescent lamps 702b are provided on a first side surface of the light guide plate 709. The thickness gradually decreases from the first side to the second side opposite the first side. It is preferable.

[0305] The diffusion plate 703 b is provided on a first plane of the light guide plate 709 .

[0306] The prism sheet 704b is provided on the first plane of the light guide plate 709 via the diffusion plate 703b. can be.

[0307] The scattering pattern 708 is provided on a second plane opposite to the first plane of the light guide plate 709 . As shown in FIG. 18B, a plurality of scattering patterns 708 may be provided.

[0308] The reflector 701b is provided on the second plane of the light guide plate 709 via the scattering pattern 708. .

[0309] The lamp reflector 710 is provided to collect the light from the cold cathode fluorescent lamp 702b. By using the reflector 710, the incidence efficiency of the light from the cold cathode tube 702b onto the light guide plate 709 is can be improved.

[0310] The backlight unit shown in FIG. 18(B) guides light from the cold cathode fluorescent lamp 702b onto the light guide plate 709. The light is totally reflected by the diffuser 703 and scattered by the scattering pattern 708. The light is emitted through the prism sheet 704b and the prism sheet 704b.

[0311] The diffusion plates 703a and 703b have the function of scattering incident light. By providing the diffusion plate 703a and the diffusion plate 703b, the light emitted from the backlight unit In addition, the luminance of the light can be made uniform by using the diffuser plate 703a and the diffuser plate 703b in a plurality of positions. It can also be set up.

[0312] Furthermore, the prism sheets 704a and 704b do not necessarily have to be provided. However, by providing the prism sheets 704a and 704b, The luminance of the light emitted from the light unit can be improved. The prism sheet 704a and the prism sheet 704b are formed by processing resin by etching or the like. The backlight unit of this embodiment is formed by a plurality of prism sheets 7. Alternatively, the optical element 704 may be configured to include a plurality of prism sheets 704a and a plurality of prism sheets 704b.

[0313] As described with reference to FIG. 18, an example of the backlight unit of this embodiment is a light source. By using the above configuration, light with high luminous efficiency can be emitted to the pixels. It can be injected into

[0314] Furthermore, light emitted from the backlight unit of the present embodiment is incident on the pixels, and the pixels are turned on by the backlight unit. By transmitting light from the light unit at a set transmittance, the display is It can be done.

[0315] (Embodiment 7) In this embodiment, an electronic device including the liquid crystal display device according to the above embodiment will be described. do.

[0316] Configuration examples of the electronic device of this embodiment are shown in FIGS. 19(A), 19(B), and 19(C). 19(A) to 19(F) will be used to explain the above. FIG. 19F is a diagram showing an example of the configuration of an electronic device according to this embodiment.

[0317] The electronic device shown in FIG. 19(A) is a portable information communication terminal. The information communication terminal includes at least a display unit 1001. The liquid crystal display device of the above embodiment is ,Since the display time for writing one pixel data is long, the interval between writing operations is long. Therefore, when the liquid crystal display device described in the above embodiment is used for the display portion 1001, Therefore, even when viewing an image on the display unit 1001 for a long time, It can reduce eye strain.

[0318] The electronic device shown in FIG. 19(B) is, for example, an information terminal including a car navigation system. The information guide terminal shown in FIG. 19(B) has at least a display unit 1101, and further has a display unit 1102 shown in FIG. The information guide terminal shown in B) is configured to have an operation button 1102 and an external input terminal 1103. The temperature inside a car fluctuates greatly with the outside air temperature, and if the temperature exceeds 50°C, However, the liquid crystal display device shown in the above embodiment is not affected by the change in characteristics due to temperature. Therefore, by using the liquid crystal display device of the above embodiment for the display portion 1101, It is possible to use the information terminal in an environment where the temperature fluctuates greatly, such as inside a car. This can be done.

[0319] The electronic device shown in Figure 19(C) is a notebook personal computer. The notebook personal computer shown in FIG. 1 includes a housing 1201, a display unit 1202, and a speaker. A connector 1203, an LED lamp 1204, a pointing device 1205, and a connection terminal 1206 and a keyboard 1207. Since the display time for writing pixel data is long, it is necessary to lengthen the interval between writing operations. Therefore, the liquid crystal display device described in the above embodiment can be used for the display portion 1202. As a result, even when viewing images on the display unit 1202 for a long period of time, eye strain is reduced. This can reduce labor.

[0320] The electronic device shown in Figure 19(D) is a portable gaming machine. 1301, a display unit 1302, a speaker 1303, a connection terminal 1304, LED lamp 1305, microphone 1306, recording medium reading unit 1307, and operation The liquid crystal display device of the above embodiment includes: Since the display time for writing pixel data once is long, the interval between writing operations is lengthened. Therefore, the liquid crystal display device described in the above embodiment can be used in the display portion 1301 or the display By using the display unit 1302, for example, the display unit 1301 or the display unit 1302 can be used for a long time. Even when viewing an intermediate image, eye strain can be reduced.

[0321] The electronic device shown in FIG. 19(E) is an electronic book. The electronic book shown in FIG. 19(E) is At least a housing 1401, a housing 1403, a display unit 1405, a display unit 1407, and a shaft portion 1408 are included. 411 and is equipped.

[0322] The housing 1401 and the housing 1403 are connected by a shaft 1411, and the electric The child book can be opened and closed around the axis 1411. The display unit 1405 can be mounted on the housing 1401. The display unit 1407 is incorporated into the housing 1403. The display unit 1407 may be configured to display different images. The display unit 1405 and the display unit 140 may be configured to display a series of images. 7 to display different images, for example, the right display section (in FIG. 19(E) The text image is displayed on the left display (display unit 1405 in FIG. 19(E)). 7) Videos can be displayed.

[0323] 19E, the electronic book reader is provided with an operation unit or the like in the housing 1401 or the housing 1403. For example, the electronic book configuration shown in FIG. 19(E) may be configured as a power button 1421 and an operation button. It may also be configured to include a key 1423 and a speaker 1425. (See FIG. 19(E)) The electronic book shown in FIG. 14 can be used to send and receive images of multiple pages by using the operation keys 1423. In addition, the display portion 1405 and the display portion 140 shown in FIG. 7, or a keyboard or a pointing device on the display unit 1405 or the display unit 1407. 19(E) and the housing 1401 of the electronic book may be provided. The back or side of the 1403 has external connection terminals (earphone terminal, USB terminal, or AC adapter). terminals that can be connected to various cables such as a printer or USB cable), a recording medium insertion section, etc. Furthermore, the electronic book shown in FIG. 19(E) may be provided with a function as an electronic dictionary. That's fine.

[0324] The liquid crystal display device of the above embodiment may be configured as a display portion 1405 and a display portion 1407, or a display The liquid crystal display device 1405 or the display device 1407 may be mounted on the liquid crystal display device 1405 or the display device 1407. The display time for writing one pixel data is long, so the interval between writing operations is Therefore, the liquid crystal display device shown in the above embodiment can be used in the display unit 140. 5 and display unit 1407, or display unit 1405 or display unit 1407 For example, when viewing an image for a long time on the display unit 1405 or the display unit 1407, This can also reduce eye strain.

[0325] The electronic book shown in FIG. 19(E) may be configured to be capable of transmitting and receiving data via wireless communication. This allows users to purchase and download desired book data from the e-book server. It is possible to add functionality.

[0326] The electronic device shown in FIG. 19(F) is a display. The device includes a housing 1501, a display unit 1502, a speaker 1503, and an LED lamp 1504. , operation button 1505, connection terminal 1506, sensor 1507, microphone 15 The liquid crystal display device of the above embodiment includes a pixel display unit 1508 and a support base 1509. The display time for writing data is long, allowing for a longer interval between write operations. Therefore, by using the liquid crystal display device described in the above embodiment mode for the display portion 1502, For example, even when viewing images on the display unit 1502 for a long period of time, eye strain is reduced. It is possible.

[0327] The electronic device shown in Figure 20 is a television set. The device includes a housing 1601 and a display unit 1603. The display unit 1603 is built into the housing 1601. The television device shown in FIG. 20 displays images on a display unit 1603. The television device shown in FIG. 20 can be mounted on a stand 1605 as an example. The liquid crystal display device of the above embodiment is configured such that the housing 1601 is supported by the Since the display time for writing pixel data is long, the interval between writing operations must be increased. Therefore, the liquid crystal display device described in the above embodiment can be used for the display portion 1603. Therefore, even when viewing an image on the display unit 1603 for a long time, eye strain is reduced. can be suppressed.

[0328] As shown in FIG. 20, the operation switches provided on the housing 1601 and the separate remote controller The television device shown in Figure 20 can be operated using the operating device 1610. The operation keys 1609 provided on the operation unit 1610 are used to operate the television device shown in FIG. It is possible to operate the channel and volume, and to operate the image displayed on the display unit 1603. In addition, the display unit 1610 can display information output from the remote control unit 1610. 07 may be provided on the remote control unit 1610.

[0329] The television device shown in FIG. 20 is configured to include a receiver, a modem, etc. By installing a TV receiver, you can receive general TV broadcasts. By connecting the television device to a wired or wireless communication network, One-way (sender to receiver) or two-way (between sender and receiver, or between receivers) It is also possible to carry out information communication.

[0330] The electronic device of the present embodiment also includes a solar cell and a power supply that supplies a voltage output from the solar cell. A DC power supply that converts the voltage charged in the power storage device into the voltage required for each circuit. The power supply circuit may be configured to include a conversion circuit. Since no power source is required, the above electronic devices can be used for long periods of time even in places where there is no external power source. This can improve convenience.

[0331] Furthermore, the electronic device of the present embodiment may have a touch panel function added to the display unit. The touch panel function can be realized by, for example, installing a touch panel unit on the display or by adding a photodetection circuit to the pixel. It can be added by providing

[0332] As described with reference to FIGS. 19 and 20, the liquid crystal display device according to the above embodiment is By incorporating the display device in the device, it is possible to provide an electronic device with low power consumption. [Explanation of symbols]

[0333] 101w display control circuit 101x Selection signal output circuit 101y pixel data signal output circuit 102 Backlight unit 103 pixels 103p unit pixel 104 Pixel section 131 Transistor 132 Liquid crystal element 133 Capacitor 201 Memory circuit 201 Frame Memory 202 Comparison circuit 203 Output selection circuit 300 sequential circuits 301a transistor 301b transistor 301c transistor 301d transistor 301e transistor 301f transistor 301g transistor 301h Transistor 301i transistor 301j transistor 301k transistor 311 period 312 period 313 period 400a board 400b board 400c board 400d board 401a Conductive layer 401b Conductive layer 401c conductive layer 401d Conductive layer 402a Insulating layer 402b Insulating layer 402c Insulation layer 402d Insulation layer 403a Oxide semiconductor layer 403b Oxide semiconductor layer 403c Oxide semiconductor layer 403d Oxide semiconductor layer 405a Conductive layer 405b Conductive layer 405c conductive layer 405d conductive layer 406a conductive layer 406b Conductive layer 406c conductive layer 406d Conductive layer 407a Oxide insulating layer 407c oxide insulating layer 409a Protective insulating layer 409b Protective insulating layer 409c Protective insulating layer 427 Insulating Layer 447 Insulating Layer 501 PCB 511 Conductive layer 512 Conductive layer 521 Insulating layer 530 Oxide semiconductor film 531 Contact Hole 541 Semiconductor layer 551 Conductive layer 552 Conductive layer 553 Conductive layer 561 Oxide insulating layer 571 Protective Insulation Layer 581 Color filter layer 591 Contact Hole 601 Planarization insulating layer 611 Conductive layer 621 Substrate 631 Conductive Layer 641 Liquid crystal layer 701a Reflector 701b Reflector 702a cold cathode tube 702b cold cathode tube 703a Diffuser 703b Diffuser 704a Prism Sheet 704b Prism sheet 708 Scattering Pattern 709 Light guide plate 710 Lamp Reflector 801 Measurement System 811 Transistor 812 transistors 813 Capacitor element 814 transistors 815 Transistor 1001 Display section 1101 Display section 1102 Operation button 1103 External input terminal 1201 Case 1202 Display section 1203 Speaker 1204 LED lamp 1205 Pointing Device 1206 Connection terminal 1207 Keyboard 1301 Display section 1302 Display section 1303 Speaker 1304 Connection terminal 1305 LED lamp 1306 Microphone 1307 Recording medium reading unit 1308 Operation button 1309 Sensor 1401 Case 1403 Case 1405 Display section 1407 Display section 1411 Shaft 1421 Power button 1423 Operation Key 1425 Speaker 1501 Case 1502 Display section 1503 Speaker 1504 LED lamp 1505 Operation button 1506 Connection terminal 1507 Sensor 1508 Microphone 1509 Support stand 1601 Case 1603 Display section 1605 Stand 1607 Display section 1609 Operation Key 1610 Remote control device

Claims

[Claim 1] A pixel unit and a selection signal output circuit, a function of stopping the output of a selection signal from the selection signal output circuit while maintaining a state in which an image is displayed in the pixel portion; the pixel portion includes a first transistor and a pixel electrode that is always electrically connected to one of a source and a drain of the first transistor; the selection signal output circuit has a second transistor; a pulse of one of a plurality of clock signals is input to one of the source and drain of the second transistor; the other of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; the first transistor includes a first oxide semiconductor layer having a c-axis oriented crystal region; the second transistor includes a second oxide semiconductor layer having a c-axis oriented crystal region; The output of the selection signal from the selection signal output circuit is stopped by: a first operation in which input of pulses of the plurality of clock signals to the selection signal output circuit is stopped in sequence; a second operation in which the input of a power supply voltage to the selection signal output circuit is stopped after the first operation; A liquid crystal display device that undergoes this.

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