Semiconductor device

Abstract

To provide a semiconductor device that achieves better operation.SOLUTION: A semiconductor device comprises a first transistor and a second transistor electrically connected to a gate of the first transistor. The first transistor has a first terminal electrically connected to a first wire, a second terminal electrically connected to a second wire, and a gate electrically connected to a first terminal or a second terminal of the second transistor. Each of the first and second transistors has an oxide semiconductor in at least a channel region, and has a small off current.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device. For example, a liquid crystal display device is exemplified, and other devices include a gate signal The display device in which pixels are selected by the signal lines and the source signal lines and an image is displayed is classified into two types of display devices. Also, semiconductor devices such as driver circuits used in display devices, display devices, Electronic devices using this technology are also included as one of the technical fields. [Background technology]

[0002] A gate made of amorphous silicon transistors (also called a-Si TFTs) Development of such a driver circuit is underway (for example, Patent Documents 1 and 2). The gate driver is a transistor ( A pull-up transistor has a source and a drain. One of the inputs is connected to a clock signal line, and the other of the source and drain is connected to a gate signal line. The potential of the gate of the pull-up transistor is connected to the clock by capacitive coupling. A driving method is used in which the potential of the signal is increased to a value higher than the H level. To achieve this, the gate of the pull-up transistor must be left floating. All transistors connected to the gate of the pull-up transistor must be in the off state. be. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-207413 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-009393 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, all transistors connected to the gate of the pull-up transistor Even when the transistor is in the off state, the off current of the transistor The charge held by the gate of the transistor was lost over time. It has been difficult to lower the driving frequency of semiconductor devices such as circuits. As a result, the range of drive frequencies that can be operated is narrowed. There was a limit to how much power could be improved.

[0005] In view of the above problem, one aspect of the present invention is to provide a method for controlling a timing at which a predetermined voltage is output to a subsequent circuit. In a semiconductor device having a transistor (pull-up transistor) that controls Another object of the present invention is to realize a device that operates better. A transistor (pull-up transistor) that controls the timing of outputting a predetermined voltage to the circuit In a semiconductor device having a transistor, one of the objectives is to improve the driving capability of the semiconductor device. Let's say. [Means for solving the problem]

[0006] One embodiment of the present invention is a semiconductor device including a first transistor and a gate electrode electrically connected to the gate of the first transistor. a first terminal of the first transistor connected to a first wiring; the second terminal of the first transistor is electrically connected to the second wiring, and the second terminal of the first transistor is electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first terminal or the second terminal of the second transistor. The first and second electrodes are connected to each other to form a semiconductor device. The transistor has an oxide semiconductor at least in a channel region and has a low off-state current. Alternatively, in the above, at least the second transistor The semiconductor device has an oxide semiconductor at least in the channel region and has a small off-state current. Specifically, the temperature at room temperature (here, 20°C) converted per 1 μm of channel width is The off-state current in the above case is 1 aA / μm or less. In this case, one or more second transistors can be provided. When there are a plurality of transistors, all of the transistors have an oxide semiconductor at least in the channel region. It is preferable to use a transistor having a small off-state current. The line can be electrically connected to a subsequent circuit. A transistor is a transistor that controls the timing of outputting a predetermined voltage to the subsequent circuit. It can function as a pull-up transistor.

[0007] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor electrically connected to a first wiring; The second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the second wiring, and the second terminal of the second transistor is The gate of the second transistor is electrically connected to the gate of the first transistor. The first terminal of the third transistor is electrically connected to the third wiring. The second terminal of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the third wiring. In the above, the first to third transistors are configured as follows: The transistor has at least a channel region formed of an oxide semiconductor. The off-state current of the first to third transistors can be 1 aA / μm or less. Alternatively, in the above, at least the second transistor The first to third transistors have at least a channel region formed of an oxide semiconductor. can be used, and the off-state current of at least the second transistor to the third transistor can be The light intensity can be 1 aA / μm or less.

[0008] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor electrically connected to a first wiring; The second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring, and the second terminal of the second transistor is The first terminal of the third transistor is electrically connected to the second wiring, and the first terminal of the third transistor is electrically connected to the fourth wiring. the second terminal of the third transistor is electrically connected to the gate of the first transistor; The gate of the third transistor is electrically connected to the fourth wiring. In the above, the first transistor to the third transistor are configured by the above. The transistor of 3 uses one in which at least the channel region is formed of an oxide semiconductor. The off-state current of the first to third transistors can be 1 aA / μm The following can be used: Or, in the above, at least the third transistor The capacitor may have at least a channel region formed of an oxide semiconductor. At least the third transistor may have an off-state current of 1 aA / μm or less. Cut.

[0009] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor and a fourth transistor, the first terminal of the first transistor being connected to a first wiring; and a second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring. The second terminal of the third transistor is electrically connected to the second wiring, and the first terminal of the third transistor is electrically connected to the second wiring. The second terminal of the third transistor is electrically connected to the third wiring, and the second terminal of the third transistor is electrically connected to the first wiring. The gate of the third transistor is electrically connected to the gate of the second transistor. The first terminal of the fourth transistor is electrically connected to the gate of the fourth wiring. The second terminal of the fourth transistor is electrically connected to the gate of the first transistor. The gate of the fourth transistor is electrically connected to the fourth wiring. In the above, the first transistor to the second transistor are formed by the above-mentioned steps. The fourth transistor has at least a channel region formed of an oxide semiconductor. The off-state current of the first to fourth transistors can be 1 aA. / μm or less. Alternatively, in the above, at least the second transistor At least a channel region of each of the first to fourth transistors is formed using an oxide semiconductor. At least the second to fourth transistors The off-state current of the transistor can be 1 aA / μm or less.

[0010] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor and a fourth transistor, the first terminal of the first transistor being connected to a first wiring; and a second terminal of the first transistor is electrically connected to the second wiring. The first terminal of the second transistor is electrically connected to the third wiring. The second terminal of the third transistor is electrically connected to the second wiring, and the first terminal of the third transistor is electrically connected to the second wiring. The second terminal of the third transistor is electrically connected to the fourth wiring, and the second terminal of the third transistor is electrically connected to the fourth wiring. The gate of the third transistor is electrically connected to the fourth wiring. a first terminal of the fourth transistor is electrically connected to the third wiring; and a second terminal of the fourth transistor electrically connected to the gate of the first transistor; The gate of the fourth transistor is electrically connected to the fifth wiring. In the above, the first to fourth transistors The capacitor may have at least a channel region formed of an oxide semiconductor. The first to fourth transistors each have an off-state current of 1 aA / μm or less. Alternatively, in the above, at least the second to fourth transistors The transistor has at least a channel region formed of an oxide semiconductor. At least the off-state current of the second to fourth transistors can be 1 aA / μm or less can be used.

[0011] Another embodiment of the present invention is a display device having a gate driver circuit, The semiconductor device is used as a circuit.

[0012] In this specification, when it is explicitly stated that X and Y are connected, X This includes the case where X and Y are electrically connected. For example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) X and Y An example of an electrical connection between X and Y is Elements (e.g., switches, transistors, capacitors, inductors, resistors, diodes) There is a configuration in which one or more of these are connected between X and Y. [Effects of the Invention]

[0013] One aspect of the present invention is a transistor ( In a semiconductor device having a pull-up transistor, This allows the charge stored in the gate to be maintained for a long period of time. In addition, the range of drive frequencies at which the semiconductor device can operate can be reduced. This allows for better operation of the semiconductor device. Alternatively, the driving capability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 illustrates a circuit configuration according to Embodiment 1. [Figure 2] 1A and 1B are a timing chart for explaining the operation of the circuit according to Embodiment 1 and a schematic diagram for explaining the operation of the circuit according to Embodiment 1. [Figure 3] 3A to 3C are schematic diagrams for explaining the operation of the circuit according to the first embodiment. [Figure 4] FIG. 1 illustrates a circuit configuration according to Embodiment 1. [Figure 5] 4 is a timing chart for explaining the operation of the circuit according to the first embodiment. [Figure 6] FIG. 1 illustrates a circuit configuration according to Embodiment 1. [Figure 7] 1A and 1B are diagrams illustrating a configuration of a circuit according to Embodiment 1 and a schematic diagram illustrating an operation of the circuit according to Embodiment 1. [Figure 8] FIG. 10 illustrates a configuration of a shift register circuit according to a second embodiment. [Figure 9] 10 is a timing chart for explaining the operation of the shift register circuit according to the second embodiment. [Figure 10] FIG. 10 illustrates a configuration of a shift register circuit according to a second embodiment. [Figure 11] 10A to 10C are examples of diagrams illustrating a manufacturing process of a transistor according to Embodiment 3. [Figure 12] 10A and 10B illustrate a structure of a display device according to Embodiment 4. [Figure 13] 1 is a diagram illustrating an example of an embodiment of a device embodying the technical idea of ​​the present invention; [Figure 14] 1 is a diagram illustrating an example of an embodiment of a device embodying the technical idea of ​​the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications can be made to the design and details of the present embodiment. It should not be construed as being limited to the contents of the description below. A part or a part having a similar function is indicated by a common reference numeral in different drawings, and the same part is Detailed descriptions of parts having similar functions will be omitted. Layer thicknesses or areas may be exaggerated for clarity. is not limited to this scale.

[0016] (Embodiment 1) In this embodiment, a circuit related to a display device which is one embodiment of the present invention will be described.

[0017] FIG. 1A shows a transistor 101, a transistor 102, a transistor 103, and a transistor 1 shows an example of a circuit configuration including a resistor 104, a transistor 105, and a circuit 200. The transistors that make up the circuit shown in A) are N-channel type. A transistor is turned on when the voltage difference between its gate and source is greater than the threshold voltage. It is a transistor.

[0018] Note that the semiconductor layer of the transistor included in the circuit shown in FIG. 1A has a sufficient hydrogen concentration. Intrinsic (i-type) or substantially intrinsic, with a sufficiently low carrier concentration. The oxide semiconductor of the transistor can be made i-type. The S value can be improved, and the off-state current of the transistor can be reduced. The breakdown voltage of the transistor can be improved. The temperature characteristics of the transistor can be improved. It is possible.

[0019] Note that the above oxide semiconductor is used for the semiconductor layers of some transistors, and As the semiconductor layer of the transistor, a semiconductor other than the above oxide semiconductor (for example, silicon (amorphous silicon) Silicon, microcrystalline silicon or polycrystalline silicon, organic semiconductors, etc. can be used. However, at least the source or the drain is electrically connected to the gate of the transistor 101. The above oxide semiconductor is used for a semiconductor layer of the transistor.

[0020] Next, the connection relationship of the circuit shown in FIG. The terminal (one of the source and the drain) of the transistor 101 is connected to the wiring 111. The second terminal (the other of the source and the drain) of the transistor 10 is connected to a wiring 112. A first terminal of the transistor 2 is connected to the wiring 113, and a second terminal of the transistor 102 is connected to the wiring 114. 12, and the gate of transistor 102 is connected to circuit 200. A first terminal of the transistor 103 is connected to a wiring 112, and a second terminal of the transistor 103 is connected to a The gate of the transistor 103 is connected to the wiring 111. The first terminal of the transistor 104 is connected to the wiring 114. The second terminal of the transistor 104 is connected to the gate of the transistor 101 and the second terminal of the transistor 104 is connected to the gate of the transistor 104. The first terminal of the transistor 105 is connected to a wiring 113. The second terminal of the transistor 105 is connected to the gate of the transistor 101. The gate of the transistor 105 is connected to the wiring 115. The gate, the second terminal of the transistor 103, the second terminal of the transistor 104, and the transistor The connection point between the second terminal of the transistor 105 and the gate of the transistor 102 is designated as node 11. The connection point between the circuit 200 and the input terminal 11 is indicated as node 12.

[0021] Note that a circuit related to a display device which is one embodiment of the present invention is not limited to the configuration shown in FIG. For example, as shown in FIG. 1B, the gate of the transistor 103 is It is possible to connect the gate of 102 to the gate of 103. As another example, as shown in FIG. The first terminal of the transistor 103 is connected to the wiring 113. The gate of the transistor 102 can be connected to the gate of the transistor 102. As shown in (D), the second terminal of the transistor 105 is connected to the wiring 112. As another example, as shown in FIG. 1(E), the first terminal of the transistor 104 The terminal can be connected to a wiring 116. As another example, as shown in FIG. In addition, the gate of the transistor 104 can be connected to the wiring 116. It is possible to combine at least two or more of the configurations shown in Figures 1(B) to 1(F). For example, by combining FIG. 1C and FIG. 1E, the first transistor 103 The first terminal of the transistor 104 is connected to a wiring 113, and the second terminal of the transistor 104 is connected to a wiring 116. It is possible to connect with.

[0022] The circuit 200 may be connected to any wiring or any node depending on its configuration. For example, the circuit 200 includes a wiring 111, a wiring 112, a wiring 113, a wiring 114, a wiring 115, a wiring 116, a wiring 117, a wiring 118, a wiring 119, a wiring 120, a wiring 121, a wiring 122, a wiring 123, a wiring 124, a wiring 125, a wiring 126, a wiring 12 4 and Node 11.

[0023] A clock signal is input to the wiring 111. A clock signal is output from the circuit of this embodiment mode to the wiring 112. A voltage V2 is supplied to the wire 113. A star is supplied to the wire 114. A reset pulse is input to the wiring 115. A reset signal is input to the wiring 11. 1. For convenience, the H-level potential of the signals input to the wiring 112, the wiring 114, and the wiring 115 is The potential V1 is set to the potential V2 of the signal input to the wiring 111, the wiring 112, the wiring 114, and the wiring 115. For convenience, the L level potential is referred to as potential V2.

[0024] The wiring 111 transmits signals such as clock signals from an external circuit such as a controller to the circuit of this embodiment. Wiring for transmitting signals, which functions as a signal line or clock signal line. A line 112 transmits the output signal of the circuit of this embodiment to a circuit such as a pixel circuit or a demultiplexer. The wiring 113 is a wiring for transmitting electric charges and functions as a signal line or a gate signal line. supplies a power supply voltage such as voltage V2 from an external circuit such as a power supply circuit to the circuit of this embodiment. The wiring 114 functions as a power supply line, a negative power supply line, or a ground line. The timing controller is a timing signal that is input to the circuit of this embodiment from an external circuit such as a timing controller or another circuit. The wiring 115 is a wiring for transmitting a target signal and functions as a signal line. A reset signal is sent to the circuit of this embodiment from an external circuit such as a timing controller or another circuit. It is a wiring for transmitting signals and functions as a signal line.

[0025] The transistor 101 functions as a switch that controls the conduction state between the wiring 111 and the wiring 112. The transistor 101 has the following function: The transistor 10 has a function of controlling the timing at which the potential of the node 11 is increased. 2 has a function as a switch that controls the conduction state between the wiring 113 and the wiring 112. The transistor 103 is a switch that controls the conduction state between the node 11 and the wiring 112. The transistor 104 functions as a conduction The transistor 104 functions as a switch that controls the state of the input terminal is connected to the wiring 114, and the output terminal is connected to the node 11. The transistor 105 controls conduction between the wiring 113 and the node 11. It functions as a switch.

[0026] Next, an example of the operation of the circuits shown in FIGS. 1A to 1F will be explained with reference to the timing diagram shown in FIG. With reference to the diagram and the schematic diagrams shown in FIGS. 2(B) to 2(E) and 3(A) to 3(C), Here, the circuit shown in FIG. 1A will be used as an example.

[0027] FIG. 2A shows a timing chart of potentials of the wiring 111, the wiring 114, the wiring 115, and the wiring 112. The potentials of the nodes 11 and 12 are also shown. The timing chart has periods A, B, C, D, and E. The timing chart shown in FIG. 1 includes a period in which period A, period B, and period C are arranged in this order, and a period The period D and the period E are alternately arranged.

[0028] First, the period A will be described with reference to FIGS. 2(A), 2(B), and 2(C). At A, the potential of the wiring 111 (shown as potential V111) becomes V2 (L-level potential). As a result, the transistor 103 is turned off, and the wiring 112 and the node 11 are The potential of the wiring 114 (denoted as potential V114) is V1 (H level potential). As a result, the transistor 104 is turned on, and the wiring 114 and the node 1 The potential of the wiring 115 (shown as potential V115) becomes V2. As a result, the transistor 105 is turned off, and therefore, the wiring 113 and the node 11 are not electrically connected. Therefore, the potential of the wiring 114 is supplied to the node 11, and therefore the potential of the node 1 The potential of node 11 (denoted as potential V11) begins to rise. Eventually, the potential of node 11 becomes V2+V th101 (Vth101 is the threshold voltage of the transistor 101). Since the transistor 101 is turned on, the wiring 112 and the wiring 111 are electrically connected. The potential of node 12 (denoted as potential V12) is set to V2 or at least V2 +Vth102 (Vth102 is the threshold voltage of the transistor 102). Therefore, the transistor 102 is turned off, and therefore the wiring 113 and the wiring 112 are not electrically connected. Therefore, the potential of the wiring 111 is supplied to the wiring 112. The potential (denoted as potential V112) becomes V2 (see FIG. 2B).

[0029] After that, the potential of the node 11 further increases. Eventually, the potential of the node 11 becomes equal to V1-V The voltage Vth104 rises to the threshold voltage of the transistor 104. Since the transistor 104 is turned off, the wiring 114 and the node 11 are not electrically connected. Therefore, the node 11 is in a floating state, and the potential of the node 11 is V1-Vth1. 04 (see Figure 2(C)).

[0030] The period B will be described with reference to FIG. 2(A) and FIG. 2(D). In the period B, the node 12 The potential of Vth102 remains below V2 or V2+Vth102 due to the circuit 200. Therefore, the transistor 102 remains off, and the wiring 113 and the wiring 112 are not electrically connected. The potential of the wiring 111 becomes V1. Then, the transistor 101 is turned on. Since the transistor 103 remains in the on state, the potential of the wiring 112 increases. Therefore, the wiring 112 and the node 11 are in a conductive state. The potential rises to V1-Vth103 (Vth103 is the threshold voltage of the transistor 103). By the way, the transistor 103 is turned off. Therefore, the wiring 112 and the node 11 The potential of the wiring 114 becomes V2. Since the node 11 remains in the off state, the wiring 114 and the node 11 remain in a non-conductive state. The potential of the line 115 remains at V2, which keeps the transistor 105 in an off state. Therefore, the wiring 113 and the node 11 remain in a non-conductive state. At this time, the potential of the wiring 112 continues to rise. The potential of the node 11 is increased by the parasitic capacitance between the gate and the second terminal of the transistor 101. It can rise to V1+Vth101+Va (Va is a positive number). This is a strapping operation. Thus, the potential of the wiring 112 rises to a value equal to the potential V1. This can be done (see Figure 2(D)).

[0031] The period C will be described with reference to Figs. 2(A), 2(E), and 3(A). The potential of the wiring 111 becomes V2. As a result, the transistor 103 remains off. Therefore, the wiring 112 and the node 11 remain in a non-conductive state. The potential of the wiring 114 is V As a result, the transistor 104 remains in the off state, and the wiring 1 The potential of the wiring 115 becomes V1. As a result, the transistor 105 is turned on, and electrical continuity between the wiring 113 and the node 11 is established. Therefore, the potential of the wiring 113 is supplied to the node 11. Since the potential of the node 11 is V2, the potential of the node 11 becomes V2. Since the node 12 is in an OFF state, the wiring 111 and the wiring 112 are not electrically connected to each other. , circuit 200, remains less than V2+Vth102. This allows transistor Since the transistor 102 remains in the off state, the wiring 113 and the wiring 112 remain in a non-conductive state. However, the potential of the wiring 111 becomes V2 at the timing when the transistor This is often earlier than the timing when the transistor 101 turns off. Before the power supply 101 is turned off, the potential of the wiring 111 is supplied to the wiring 112. The potential of 12 becomes V2 (see FIG. 3(A)).

[0032] The period D will be described with reference to FIGS. 2A and 3B. In the period D, the wiring 111 The potential of the wiring 11 becomes V1. 2 and the node 11 are electrically connected to each other. The potential of the wiring 114 remains at V2. Since the transistor 104 remains off, the wiring 114 and the node 11 are not electrically connected. The potential of the wiring 115 becomes V2. This causes the wiring 113 and the node 1 The potential of the node 12 is set to V2+Vth102 by the circuit 200. As a result, the transistor 102 is turned on, and the wiring 113 and Continuity is established with the wiring 112. Therefore, the potential of the wiring 113 is supplied to the node 11. Therefore, the potential of the node 11 becomes V2. As a result, the transistor 101 is turned off. Therefore, the wiring 111 and the wiring 112 are in a non-conductive state. Since the potential of the wiring 112 is V3, the potential of the wiring 112 becomes V2 (see FIG. 3B).

[0033] The period E will be described with reference to FIGS. 2A and 3C. In the period E, the wiring 111 As a result, the potential of the transistor 103 is turned off, and the potential of the wiring 11 2 and the node 11 are in a non-conductive state. The potential of the wiring 114 remains at V2. Therefore, the transistor 104 remains off, and the wiring 114 and the node 11 are not electrically connected. The potential of the wiring 115 remains at V2. The potential of node 12 is set to V2 or V2 by the circuit 200. +Vth102. This turns off the transistor 102, The line 113 and the wiring 112 are in a non-conductive state. Therefore, the node 11 is in a floating state. Therefore, the potential of the node 11 remains at V2. This causes the transistor 101 to be in an off state. Therefore, the wiring 111 and the wiring 112 remain in a non-conductive state. Since the potential of the wiring 112 is in a floating state, the potential of the wiring 112 remains at V2 (see FIG. 3C).

[0034] In the semiconductor device illustrated in FIG. 1C, the potential of the node 12 is V2+ It is preferable that the value exceeds Vth102 and exceeds V2+Vth103. As a result, the transistor 103 is turned on, and electrical continuity between the wiring 113 and the node 11 is established. Therefore, the potential of the wiring 113 is supplied to the node 11. The potential of node 11 is supplied to node 11 through one transistor. can be stabilized.

[0035] Note that in the circuit illustrated in FIG. 1D, the transistor 105 is turned on during the period C. When this occurs, the wiring 113 and the wiring 112 are brought into electrical continuity. This shortens the fall time of the potential of the wiring 112. can be done.

[0036] Note that in the circuit illustrated in FIG. 1E, the potential of the wiring 116 is set to V1 in the period A. In the periods B to E, the potential of the wiring 116 can be V1 or V2. Therefore, the wiring 116 can be supplied with a voltage V1. Alternatively, the wiring 116 may have a phase difference from the clock signal input to the wiring 111. A clock signal input to the wiring 111 or an inverted signal of the clock signal input to the wiring 112 is input. In the semiconductor device illustrated in FIG. 1F, the potential of the wiring 116 is In periods C to E, the potential of the wiring 11 is V1. The potential of the capacitor 6 can be V1 or V2. The line 116 is connected to a clock signal whose phase is shifted from that of the clock signal input to the wiring 111, or Alternatively, an inverted signal of the clock signal input to the wiring 111 can be input. .

[0037] As described above, the above circuit uses the bootstrap operation to The potential can be set to be equal to the potential of the wiring 111.

[0038] In the conventional technology, the S value of the transistor is high. The time it takes for the transistor 104 to turn off after the potential of the transistor 104 reaches V1 is longer. Or, since it is necessary to lengthen period A, it is difficult to increase the driving frequency. Alternatively, the rise time of the potential of the wiring 112 is increased (the rise time of the output signal is increased). (The rise time was longer.) Or, the load that can be connected to the wiring 112 is smaller. Alternatively, the channel width of the transistor 101 is increased. The area was getting bigger.

[0039] In contrast, in this embodiment, the S value of the transistor is low. For example, since the S value of the transistor 104 is low, the wiring 114 The time from when the potential of the transistor 104 reaches V1 until the transistor 104 is turned on is shortened. Therefore, the duration of period A can be shortened. As another example, the low S value of the transistor 101 can improve This can shorten the rise time of the potential of the wiring 112. Even if a large load is connected, the load can be driven. Since the channel width can be reduced, the layout area can be reduced.

[0040] In the conventional technology, the off-state current of the transistor is large. The amount of charge lost from node 11 was large over time. Or, the potential of node 11 Alternatively, the potential of the node 11 is lowered to a value at which the transistor 101 is turned on or higher. The time that the drive frequency can be maintained is shortened, or it is difficult to lower the drive frequency. Or, the range of drive frequencies that can be operated is narrowed.

[0041] In contrast, in this embodiment, the off-state current of the transistor is small. For example, the transistor 103, the transistor 104, and the transistor The small off-current of the transistor 105 reduces the amount of charge lost from the node 11. Therefore, the potential drop of the node 11 can be suppressed. The time during which the potential of the node 11 can be maintained at or above the value at which the transistor 101 is turned on is determined. This allows the drive frequency to be lowered, This allows for a wider range of drive frequencies that can be used.

[0042] The circuits shown in FIGS. 1A to 1F may also be provided with other elements such as transistors. An example of this will be described below.

[0043] FIG. 4A shows an example in which a transistor 121 is provided in the circuit shown in FIG. The circuits illustrated in FIGS. 1B to 1F can be provided with a transistor 121. A first terminal of the transistor 121 is connected to the wiring 113, and a second terminal of the transistor 121 is connected to the wiring 113. The terminal is connected to the wiring 112, and the gate of the transistor 121 is connected to the wiring 116. A clock signal is preferably input to the wiring 116. When the transistor 121 is turned on, the potential of the wiring 113 is changed to the potential of the wiring 112. Therefore, noise in the wiring 112 can be reduced.

[0044] FIG. 4B shows an example in which a transistor 122 is provided in the circuit shown in FIG. 1A. In the circuits shown in FIGS. 1B to 1F and 4A, a transistor 122 is provided. A first terminal of the transistor 122 is connected to the wiring 113. The second terminal of the transistor 122 is connected to the wiring 112, and the gate of the transistor 122 is connected to the wiring 112. 15. As a result, the transistor 122 is turned on during the period C. This allows the potential of the wiring 113 to be supplied to the wiring 112. The fall time of the potential of 12 can be shortened.

[0045] FIG. 4C shows an example in which a transistor 123 is provided in the circuit shown in FIG. In the circuits shown in FIGS. 1B to 1F and 4A to 4B, the transistor 12 A first terminal of the transistor 123 is connected to the wiring 114. The second terminal of the transistor 123 is connected to the node 11. The gate is connected to the wiring 116. Thus, even in the period E, the potential of the wiring 114 is This allows the voltage to be supplied to node 11. This reduces noise at node 11. Cut.

[0046] FIG. 4D shows an example in which a transistor 124 is provided in the circuit shown in FIG. In the circuits shown in FIGS. 1B to 1F and 4A to 4C, the transistor 12 A first terminal of the transistor 124 is connected to the wiring 111. The second terminal of the transistor 124 is connected to the wiring 117. The gate is connected to the node 11. Thus, the potential of the wiring 117 is connected to the potential of the wiring 112. In this case, the wiring 112 and the wiring 117 can be changed at the same timing as the position. It is advisable to connect one end of the resistor to a load and the other end to another circuit. The other circuit can be driven without being affected by fluctuations in the output voltage.

[0047] FIG. 4E shows a circuit in which a transistor 124 and a transistor 125 are added to the circuit shown in FIG. Similarly, in the circuits shown in FIGS. 1(B) to 1(F) and 4(A) to 4(C), In this case, a transistor 124 and a transistor 125 may be provided. A first terminal of the transistor 125 is connected to the wiring 113, and a second terminal of the transistor 125 is connected to the wiring 114. The gate of transistor 125 is connected to line 117 and the gate of transistor 125 is connected to node 12. Therefore, the potential of the wiring 117 can be maintained at V2. can be reduced.

[0048] FIG. 4F shows an example in which a capacitor 126 is provided in the circuit shown in FIG. 1A. In the circuits shown in (B) to (F) and (A) to (E) of FIG. 4, a capacitor 126 is provided. The capacitor 126 is connected between the gate and the second terminal of the transistor 101. It is set up in between.

[0049] Note that the circuits shown in FIGS. 1A to 1F include transistors 121 to 125 and capacitors. It is possible to provide more than one element in element 126.

[0050] The circuit of this embodiment mode includes not only the timing chart shown in FIG. 2A but also various other circuits. A timing chart such as the one shown in FIG. The potential of the gate 12 is V2+Vth10 during at least the period B among the periods A to E. Therefore, in the period A and the periods C to E, the potential of the node 12 is , it can be less than V2+Vth102, or it can be greater than V2+Vth102. However, in either period D or period E (particularly in period D), node 1 The potential of period D is preferably a value exceeding V2+Vth102. During the other period between E and E (particularly during the period E), the potential of the node 12 is less than V2+Vth102. This makes it possible to shorten the time during which the transistor 102 is in an on state. Therefore, the shift in the threshold voltage of the transistor 102 can be suppressed. In the circuit shown in FIG. 1(C), in the period A, the potential of the node 12 exceeds V2+Vth102. When the potential of the node 11 becomes higher than the threshold voltage, the transistor 103 is turned on, and the potential of the node 11 decreases. Therefore, during the period A, the potential of the node 12 is less than V2+Vth102. As another example, as shown in FIG. 5A, a signal input to the wiring 111 is preferably As a result, in the period C, the potential of the wiring 111 is V2 Therefore, the timing when the potential of the wiring 115 becomes V1 can be delayed compared to the timing when the potential of the wiring 115 becomes V2. Therefore, the fall time of the potential of the wiring 112 can be shortened. As shown in FIG. 5B, the signal input to the wiring 111 is a multiphase clock signal. This makes it possible to reduce power consumption. 10 shows a timing chart in the case where four-phase clock signals are input to the wiring 111.

[0051] For example, the W / L (W: channel width, L: channel length) ratio of the transistor 101 is Transistor 102, transistor 103, transistor 104, transistor 105, A transistor 121, a transistor 122, a transistor 123, a transistor 124, and a transistor 125. It is preferable that the W / L ratio is larger than that of all the transistors 125. The rise time and fall time can be shortened. The W / L ratio of the transistor 104 is preferably at least 2 times but less than 20 times the W / L ratio of the transistor 104. More preferably, it is 3 times or more and less than 15 times. Even more preferably, it is 5 times or more and less than 15 times. As another example, the W / L ratio of transistor 105 is less than twice that of transistor 104. Therefore, in the period C, the transistor 101 is turned on. Since the timing of the transition to the OFF state can be delayed, the timing of the potential fall of the wiring 112 can be delayed. Specifically, the W / L ratio of the transistor 105 can be It is preferable that the W / L ratio of the heater 104 is 0.3 times or more and less than 1 time. More preferably, It is preferably 0.4 times or more and 0.9 times or less. More preferably, it is 0.5 times or more and As another example, the W / L ratio of the transistor 103 is preferably 0.8 times or less. It is preferable that the W / L ratio is smaller than that of the transistor 104. This can prevent the potential of the transistor 11 from decreasing too much. The W / L ratio of 03 must be 0.1 times or more and less than 1 times the W / L ratio of transistor 104. It is more preferably 0.3 times or more and 0.9 times or less. It is greater than 0.4 times and less than 0.7 times.

[0052] For example, the W / L ratio of transistor 122 is greater than the W / L ratio of transistor 102. This can shorten the fall time of the potential of the wiring 112. In practice, the W / L ratio of transistor 122 is more than twice the W / L ratio of transistor 102. It is preferably less than 20 times, and more preferably 3 times or more and 15 times or less. Preferably, the W / The L ratio is preferably smaller than the W / L ratio of the transistor 101. This is because the load connected to the wiring 112 is often smaller than the load connected to the wiring 112. For example, the W / L ratio of transistor 125 is less than the W / L ratio of transistor 102. This is because the load connected to the wiring 117 is smaller than the load connected to the wiring 112. Because they are often small.

[0053] For example, the amplitude voltage of node 12 is the amplitude voltage of node 11, wiring 111, wiring 112, wiring 114, It is preferable that the amplitude voltage of at least one of the wiring 115, the wiring 116, and the wiring 117 is less than that of the wiring 116. This is desirable. This makes it possible to reduce power consumption. The width voltage is preferably 0.3 times or more and less than 1 time the amplitude voltage of the wiring 111. Preferably, it is 0.5 times or more and less than 1 time. More preferably, it is 0.6 times or more and less than 0.9 times. As another example, the amplitude voltage of the node 11 is equal to or less than twice the amplitude of the node 12, the wiring 111, and the wiring 112. 112, wiring 114, wiring 115, wiring 116, and wiring 117. This preferably exceeds the voltage between the gate and source of the transistor 101. Since the potential difference between the wirings 112 and 113 can be increased, the rise time and fall time of the potential of the wiring 112 can be reduced. Specifically, the amplitude voltage of the node 11 is It is preferable that the amplitude voltage is more than 1 time and 2 times or less. More preferably, it is 1.2 times or more. The ratio is preferably from 1.4 to 1.6 times.

[0054] For example, while the transistor 102 is in an off state, the potential of the wiring 111 is at an H level. It is preferable that the time is longer than the time required for the heating.

[0055] Furthermore, the technology using amorphous silicon had low transistor mobility. In addition, the transistor 101 drives a large load (for example, a gate signal line). It was necessary to increase the channel width of the transistor 101. The channel width was larger than the wiring width of the wiring 111. In contrast, in the circuit of this embodiment, The mobility of the transistors that make up the Therefore, the channel width of the transistor 101 can be reduced.

[0056] Therefore, the channel width of the transistor 101 is equal to the width of at least a part of the wiring 111. In particular, the channel width of the transistor 101 is preferably at least It is preferable that the width is 0.3 times or more and less than 1 time of the width of the wiring. More preferably, it is 0.4 times or more. More preferably, it is 0.5 to 0.8 times.

[0057] Next, a specific example of the circuit 200 will be described. FIG. 7A shows a circuit including a capacitor 201 and a transistor. 2 shows a configuration example of a circuit 200 having a capacitor 201 and a capacitor 202. One electrode of the capacitor 201 is connected to a wiring The other electrode of the capacitor 201 is connected to the node 111, and the other electrode of the capacitor 201 is connected to the node 12. A first terminal of the transistor 202 is connected to the wiring 113, and a second terminal of the transistor 202 is connected to the wiring 113. The gate of transistor 201 is connected to node 12, and the gate of transistor 202 is connected to node 11. The gate of the transistor 202 can be connected to the wiring 112 or the wiring 114. is.

[0058] Next, an example of the operation of the circuit 200 will be described with reference to FIGS.

[0059] During periods A and B, the potential of node 11 is set to a high potential (for example, V2+Vth202 (Vth 202 can have a value that exceeds the threshold voltage of transistor 202. For example, The potential of the node 11 has a value of V1-Vth104 during the period A, and V1+Vt during the period B. This causes transistor 202 to be in an on state, so that The wiring 113 and the node 12 are brought into electrical continuity. 2. Since the potential of the wiring 113 is V2, the potential of the node 12 becomes V2 (see FIG. 7). (See (B)).

[0060] In the period C, the potential of the wiring 111 is V2. At this time, the transistor 202 is in the on state. Therefore, the wiring 113 and the node 12 remain in a conductive state. The potential of 113 remains supplied to node 12, so the potential of node 12 remains at V2. At this time, the capacitor 201 holds the difference between the potential of the wiring 111 and the potential of the node 12. After that, the potential of node 11 becomes V2, which turns on transistor 202. Therefore, the wiring 113 and the node 12 are not electrically connected to each other. However, the potential of the node 12 is maintained at V2 by the capacitor 201. (See FIG. 7(C)).

[0061] During period D, the potential of node 11 remains at V2. This causes transistor 202 to Since the transistor remains in the off state, the wiring 113 and the node 12 remain in a non-conductive state. At this time, the potential of the wiring 111 becomes V1. As a result, the potential of the node 12 becomes V2. During period E, the potential of node 11 rises due to the capacitive coupling of V2 As a result, the transistor 202 remains in the off state, and the wiring 11 3 and the node 12 remain in a non-conductive state. At this time, the potential of the wiring 111 becomes V2. As a result, the potential of the node 12 decreases due to the capacitive coupling of the capacitor 201 (FIG. 7( See E).

[0062] As described above, a circuit capable of controlling the potential of the node 12 can be constructed using a small number of elements. It can be achieved.

[0063] As shown in FIG. 7F, the first terminal is connected to the wiring 113 in FIG. a transistor having a second terminal connected to the node 12 and a gate connected to the wiring 114; The transistor 203 is turned on in the period A. Therefore, the wiring 113 is in an OFF state during the period B to the period E. Since the potential is supplied to the node 12, the fall time of the potential of the node 12 in the period A is In addition, if the gate of the transistor 203 is connected to the wiring 115, The transistor 203 is turned on during period C, and is turned on during periods A, B, D, and E. In period E, the potential of the wiring 113 is turned off. Therefore, the voltage required for operation of the capacitor element 201 can be reliably maintained. Alternatively, in the period C, the time for which the capacitor 201 holds the voltage may be extended. Therefore, the capacitance value of the capacitor 201 can be increased. If the capacitance value is large, the potential of the node 12 during the period D can be made high.

[0064] In this embodiment, for example, the off-state current of the transistor 202 is small, so that the capacitance element Therefore, the amount of charge lost from the node 201 can be reduced. The potential on the L side of the node 12 can be prevented from increasing. This allows you to extend the time from the start time of period A to the start time of the next period A. In other words, the driving frequency can be lowered. The range of drive frequencies that can be achieved can be widened.

[0065] The circuit described in this embodiment includes the following configuration as one embodiment of the present invention. A semiconductor device having a resistor 101, a transistor 103 and a transistor 104 (FIG. 6( A)). The transistor 101, the transistor 102 and the transistor 104 are included. Semiconductor device (see FIG. 6B). A semiconductor device including a capacitor 103 and a transistor 104 (see FIGS. 6C and 6D). The transistor 101, the transistor 102, the transistor 104, and the transistor 105 are included. A semiconductor device (see FIG. 6E) includes a transistor 101, a transistor 102, and a transistor A semiconductor device having a resistor 103, a transistor 104, and a transistor 105 (FIG. 6(F) )reference).

[0066] (Embodiment 2) In this embodiment, a shift register circuit according to a display device of one embodiment of the present invention will be described. The shift register circuit of this embodiment includes the circuit described in the first embodiment. The shift register circuit of this embodiment can be used in conjunction with a gate driver circuit and / or Alternatively, it can be used in a driver circuit of a display device such as a source driver circuit.

[0067] FIG. 8 shows a shift register having N circuits 301 (referred to as circuits 301_1 to 301_N). 3 is a configuration example of a master circuit. The circuit in Embodiment 1 can be used as the circuit 301. 8 shows an example in which the circuit shown in FIG. 1A is used as the circuit 301.

[0068] The connection relationship of the shift register circuit shown in FIG. 8 will be described. The connection relationship of the circuit 301_i is explained using an example of the connection relationship of the wiring 311 _i, wiring 311_i−1, wiring 311_i+1, one of wiring 312 and wiring 313, and and a wiring 314. Specifically, in the circuit 301_i, the wiring 112 is connected to the wiring 314. 11_i, the wiring 114 is connected to the wiring 311_i-1, and the wiring 115 is connected to the wiring 311_i+ 1, the wiring 111 is connected to one of the wiring 312 and the wiring 313, and the wiring 113 is The wiring 111 is connected to the wiring 312. When the wiring 111 is connected to the circuit 301_i+1 and the circuit 301_i−1, the wiring 111 is connected to the circuit 301_i+1 and the circuit 301_i−1. In the circuit 301_1, the wiring 114 is preferably connected to the wiring 315. However, this is different from the circuit 301_i. Also, in the circuit 301_N, the wiring 115 is a dummy The output terminal of the circuit (not shown), the wiring (not shown) to which the reset signal is input, or the wiring 3 15, etc. is connected to the circuit 301_i.

[0069] Next, regarding the operation of the shift register circuit shown in FIG. 8, the timing chart shown in FIG. 9 will be described. Please refer to the following for explanation.

[0070] The operation of the circuit 301_i will be described as an example. First, the potential of the wiring 311_i-1 (potential V3 11_i-1) becomes V1. Then, the circuit 301_i performs the operation in the period A as follows: Then, the potential of the wiring 311_i (denoted as potential V311_i) becomes V2. The potential of the wiring 12 (denoted as potential V312) and the potential of the wiring 313 (denoted as potential V313) are inverted. Then, the circuit 301_i operates in the period B, and the potential of the wiring 311_i is Then, the potential of the wiring 312 and the potential of the wiring 313 are inverted, and the potential of the wiring 311_i The potential of +1 (denoted as potential V311_i+1) becomes V1. Then, the circuit 301_i The operation in the period C is performed, and the potential of the wiring 311_i becomes V2. i is the operation in the period D and the period E until the potential of the wiring 311_i-1 becomes V1 again. The operations in steps 1 and 2 are repeated in order, and the potential of the wiring 311_i remains at V2. When the potential of the wiring 315 (denoted as a potential V315) becomes V1, the circuit 301_1 The circuit 301_i differs from the circuit 301_i in that it performs the operation in the above.

[0071] As described above, the potential of the wiring 311_1 (denoted as potential V311_1) is changed to the potential of the wiring 311_N. The potential (denoted as potential V311_N) can in turn be set to V1.

[0072] An output signal of the shift register circuit is supplied to the wiring 311. A clock signal is supplied to the wiring 312. The wiring 313 receives a clock signal that is out of phase with the clock signal input to the wiring 312. A different clock signal or an inverted signal of the clock signal input to the wiring 312 is input. A voltage V2 is supplied to the wiring 314. A start signal is input to the wiring 315. .

[0073] The wiring 311 transmits the output signal of the shift register circuit to a pixel circuit or a circuit such as a demultiplexer. The wiring 31 is a wiring for transmitting the signal and functions as a signal line or a gate signal line. 2 and wiring 313 are connected from an external circuit such as a controller to the shift register circuit of this embodiment. It is a wiring for transmitting signals such as clock signals, and is used as a signal line or clock signal line. The wiring 314 is a wiring for connecting an external circuit such as a power supply circuit to the shift register of this embodiment. This is the wiring for supplying a power supply voltage such as voltage V2 to the inverter circuit. It is also called a power supply line, a negative power supply line, or The wiring 315 functions as a ground line. This is a wiring for transmitting a start signal to the shift register circuit in the form of It has all the functions.

[0074] By providing a transistor in the shift register circuit shown in FIG. 8, the scanning direction can be switched. That is, the power supply from the wiring 311_1 to the wiring 311_N can be and driving the potentials of the wiring 311_N to the wiring 311_1 to V1 in order. Figure 10 shows the switch for switching the scanning direction. 10 shows an example of a shift register circuit including circuits 301_i-1 to 301_i-2. 10. The shift register circuit shown in FIG. , N transistors 302 (referred to as transistors 302_1 to 302_N), N Transistors 303 (referred to as transistors 303_1 to 303_N), N transistors 304 (denoted as transistors 304_1 to 304_N) and N transistors 304_1 to 304_N. 05 (referred to as transistors 305_1 to 305_N). For example, A first terminal of the transistor 302_i is connected to the wiring 311_i-1. The second terminal is connected to the wiring 114 of the circuit 301_i and is connected to the gate of the transistor 302_i. The first terminal of the transistor 303_i is connected to the wiring 311_ i-1, and the second terminal of the transistor 303_i is connected to the wiring 11 of the circuit 301_i. 5, and the gate of the transistor 303_i is connected to the wiring 316. The first terminal of the transistor 304_i is connected to the wiring 311_i+1. The second terminal of the transistor 304_i is connected to the wiring 114 of the circuit 301_i. The gate of the transistor 305_i is connected to a wiring 316. The first terminal of the transistor 305_i is connected to a wiring 31 1_i+1, and the second terminal of the transistor 305_i is connected to the wiring The gate of the transistor 305_i is connected to the wiring 315.

[0075] An example of the operation of the shift register circuit shown in Fig. 10 will be described. In the case of driving the potentials of the lines 311_N to V1 in order, an H signal is input to the line 315, and It is advisable to input an L signal to the line 316. This causes the transistor 302_i to be turned on. As a result, the transistor 303_i is turned off and the transistor 304_i is turned off. As a result, the transistor 305_i is turned on. The signal transmitted is transmitted to the wiring 114 of the circuit 301_i+1 and the wiring 115 of the circuit 301_i-1. On the other hand, the potentials of the wirings 311_N to 311_1 are sequentially set to V1. In the case of operation, it is preferable to input an L signal to the wiring 315 and an H signal to the wiring 316. Therefore, the transistor 302_i is turned off and the transistor 303_i is turned on. As a result, the transistor 304_i is turned on and the transistor 305_i is turned off. As a result, the signal output from the wiring 311_i is transmitted to the wiring 11 of the circuit 301_i+1. 5 and the wiring 114 of the circuit 301_i-1.

[0076] The amplitude voltage of a signal input to one or both of the wiring 315 and the wiring 316 is N. The amplitude voltage of a signal input to at least one of the wiring 311, the wiring 312, and the wiring 313 is It is preferable that the thickness is larger than the thickness of the slab.

[0077] (Embodiment 3) In this embodiment, an example of a transistor included in the circuit described in Embodiment 1 or 2 is Specifically, at least the channel region is formed of an oxide semiconductor. An example of a structure and a manufacturing process of a transistor will be described.

[0078] As oxide semiconductors, there are four-component metal oxides, such as In-Sn-Ga-Zn-O oxide semiconductors. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, and In-Sn-Zn -O-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based oxide semiconductors oxide semiconductor, Al-Ga-Zn-O based oxide semiconductor, or Sn-Al-Zn-O based oxide In-Zn-O-based oxide semiconductors, which are binary metal oxides, and Sn-Zn- O-based oxide semiconductors, Al-Zn-O-based oxide semiconductors, Zn-Mg-O-based oxide semiconductors, S n-Mg-O based oxide semiconductors, In-Mg-O based oxide semiconductors, In-O based oxide semiconductors , an oxide semiconductor such as a Sn-O-based oxide semiconductor or a Zn-O-based oxide semiconductor is used. Alternatively, the oxide semiconductor may be one obtained by adding SiO2 to the above oxide semiconductor.

[0079] In addition, the oxide semiconductor is InMO3(ZnO) m (m>0 and m is not a natural number) The following materials can be used, where M is selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, Ga and Co. InMO3(ZnO) m (m>0 and m is natural Among oxide semiconductors with a structure expressed by the formula (not a number), oxide semiconductors with a structure containing Ga as M are The conductor is called the above-mentioned In-Ga-Zn-O oxide semiconductor, and its thin film is called In-Ga-Zn In this specification, the term "In-Ga-Zn-O" is used. The oxide semiconductor material used is InGaO3(ZnO) m (m>0 and m is not a natural number) The fact that m is not a natural number can be confirmed using ICP-MS analysis or RBS analysis. can be done.

[0080] FIG. 1 shows one embodiment of a method for manufacturing a transistor in which a channel region is formed using an oxide semiconductor. 11 for further explanation.

[0081] 11A to 11D are diagrams illustrating an example of a cross-sectional structure of a transistor. The transistor 410 shown in FIGS. 1) to 1) has a bottom gate structure called a channel etch type. It is one of the structures.

[0082] Although single-gate transistors are shown in FIGS. 11A to 11D, Depending on the type of transistor, a multi-gate structure transistor having multiple channel regions can be used. do.

[0083] 11A to 11D, a process for fabricating a transistor 410 on a substrate 400 will be described. Explain the process.

[0084] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 411 is formed by the process.

[0085] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary for the material to have heat resistance sufficient to withstand subsequent heat treatment. Glass substrates such as sodium borosilicate glass and aluminoborosilicate glass can be used. In addition, if the temperature of the subsequent heat treatment is high, a glass substrate with a distortion point of 730°C or higher can be used. It is good to use.

[0086] An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 411. It has a function of preventing the diffusion of impurity elements from the substrate 400, and is a silicon nitride film, a silicon oxide film, etc. The insulating film is made of one or more films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It can be formed in a laminated structure.

[0087] The material of the gate electrode layer 411 is selected from the group consisting of molybdenum, titanium, chromium, tantalum, and tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The insulating film 10 can be formed as a single layer or a stacked layer using an alloy material.

[0088] Next, the gate insulating layer 402 is formed over the gate electrode layer 411 .

[0089] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer The gate insulating layer can be formed as a single layer or a stacked layer. High-k materials such as fluorine (HfOx) and tantalum oxide (TaOx) can also be used. The thickness of the gate insulating layer 402 is set to 100 nm or more and 500 nm or less. For example, the first gate insulating layer has a thickness of 50 nm or more and 200 nm or less, and the second gate insulating layer has a thickness of 100 nm or more and 200 nm or less. A second gate insulating layer having a thickness of 5 nm to 300 nm is laminated on the insulating layer.

[0090] In this embodiment, the gate insulating layer 402 is formed by plasma CVD to a thickness of 100 nm or more. A bottom silicon oxynitride layer is formed.

[0091] In addition, a silicon oxynitride film is formed as the gate insulating layer 402 using a high density plasma device. Here, the high density plasma device may be used. 11 / cm 3 Plasma density above For example, a microwave power of 3kW to 6kW can be applied to the The insulating film is formed by generating plasma. The insulating film obtained by the high density plasma device is It is possible to form a film of a consistent thickness, which makes it excellent for covering steps. The insulating film obtained by this method can be precisely controlled in thickness.

[0092] The insulating film obtained by the high-density plasma device is different from that obtained by the conventional parallel plate PCVD device. The etching rates are significantly different from those of the insulating films used in the previous study, and the etching rates were compared using the same etchant. In this case, the insulating film obtained by the parallel plate type PCVD equipment is 10% or more or 20% or more The insulating film obtained by the high-density plasma device can be said to be a dense film.

[0093] Note that the oxide semiconductor (highly purified oxide) to be made i-type or substantially i-type in a later step Since semiconductors are extremely sensitive to interface states and interface charges, the interface with the gate insulating layer Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor must be highly Therefore, high density plasma CVD using microwaves (2.45GHz) is This is preferable because it allows the formation of a dense, high-quality insulating film with high dielectric strength. The close contact between the semiconductor and the high-quality gate insulating layer reduces interface states and improves interface characteristics. It goes without saying that the film quality as a gate insulating layer is good. It is important to reduce the interface state density with the oxide semiconductor and form a good interface. is.

[0094] Next, an oxide semiconductor film 43 having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 402. The oxide semiconductor film 430 is formed of an In—Ga—Zn—O system or an In—Zn—O system. In this embodiment, the oxide semiconductor film 430 is an In- A film is formed by sputtering using a Ga-Zn-O based oxide semiconductor target. 11A. The oxide semiconductor film 430 is formed by oxidizing a rare gas (typically, In an atmosphere of noble gas (typically argon), oxygen, or a mixture of noble gas (typically argon) and oxygen, It can be formed by sputtering in a mixed atmosphere.

[0095] Here, a metal oxide target containing In, Ga, and Zn (In2O3:Ga2O3 ZnO = 1:1:1 [molar ratio]) and the distance between the substrate and the target was set at 10 0 mm, pressure 0.2 Pa, direct current (DC) power supply 0.5 kW, argon and oxygen (argon: The film is formed in an atmosphere of oxygen = 30sccm:20sccm (oxygen flow rate ratio 40%). By using a pulsed direct current (DC) power supply, the amount of powdery material generated during film formation can be reduced, and the film thickness distribution can be improved. The thickness of the In-Ga-Zn-O film is preferably 5 nm or more and 200 nm or less. In this embodiment, an oxide semiconductor film is formed using an In—Ga—Zn—O-based metal oxide film. A 20 nm thick In-Ga-Zn-O film was formed by sputtering using an In-Ga-Zn-O target. Next, the oxide semiconductor film 430 is formed into island-shaped oxide films by a second photolithography process. The resulting semiconductor layer is then processed into a compound semiconductor layer.

[0096] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and the oxide semiconductor The layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to the air. Therefore, water and hydrogen are prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 431 is obtained. See Figure 11(B)).

[0097] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0098] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA can be used to heat the food at high temperatures in a short time. become.

[0099] The atmosphere of the first heat treatment may be nitrogen, helium, neon, argon, or the like. It is preferable that the rare gas and dry air do not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the device should be 6N (99 0.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0100] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 430 can also be subjected to the first heat treatment. The substrate is removed from the device and subjected to a second photolithography process.

[0101] In addition, when an opening is formed in the gate insulating layer 402, the process is performed in the oxide semiconductor film 430. This may be carried out before or after the dehydration or dehydrogenation treatment.

[0102] Note that the etching of the oxide semiconductor film 430 here is not limited to wet etching. Dry etching may also be used.

[0103] The etching gas used for dry etching of the oxide semiconductor film 430 is a chlorine-containing gas. Gases such as chlorine (Cl2), boron chloride (BCl3), etc. are preferred.

[0104] The etching solution for the oxide semiconductor film 430 used in the wet etching is a mixture of phosphoric acid and acetic acid. and nitric acid solution, ammonia hydrogen peroxide solution (31% by weight hydrogen peroxide solution: 28% by weight ammonia Water: water = 5:2:2) can also be used. may also be used.

[0105] Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by sputtering or vacuum deposition. Aluminum (Al), Chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti) , molybdenum (Mo), tungsten (W), neodymium (Nd), scandium (Sc) an element selected from the above, an alloy containing the above elements as a component, or a composite of the above elements Also, a nitride film of the above elements may be used. ), magnesium (Mg), zirconium (Zr), beryllium (Be), yttrium The metal conductive film may be made of one or more materials selected from (Y). The film may have a single layer structure or a laminated structure of two or more layers. a single-layer structure of titanium film, a two-layer structure of titanium film on aluminum film, and a titanium film on aluminum film. Examples include a three-layer structure in which a titanium film is laminated on an aluminum film and then a titanium film is laminated on an aluminum film. can be.

[0106] When heat treatment is performed after forming the metal conductive film, the metal conductive film must have heat resistance to withstand this heat treatment. It is preferable to make it

[0107] A resist mask is formed on the metal conductive film by a third photolithography process. After etching to form the source electrode layer 415a and the drain electrode layer 415b, The photomask is removed (see FIG. 11(C)).

[0108] In this embodiment, a titanium film is used as the metal conductive film, and an In film is used for the oxide semiconductor layer 431. -Ga-Zn-O oxide was used, and ammonia hydrogen peroxide (ammonia) was used as an etchant. A mixture of water and hydrogen peroxide is used.

[0109] Note that in the third photolithography step, only a part of the oxide semiconductor layer 431 is etched. In some cases, the oxide semiconductor layer is etched to have a groove (depression).

[0110] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, The resist mask is formed by a multi-tone mask, which is an exposure mask that allows the incident light to have multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and ashing can further deform the shape. Therefore, it can be used in multiple etching processes to process different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0111] Then, gases such as nitrous oxide (N2O), nitrogen (N2), or argon (Ar) are used. The surface of the oxide semiconductor layer exposed by this plasma treatment is In addition, a plasma treatment is performed using a mixture of oxygen and argon gas. The theory may also be carried out.

[0112] After the plasma treatment, a film that is in contact with part of the oxide semiconductor layer 431 is formed without being exposed to the air. An oxide insulating layer 416 serving as a protective insulating film is formed.

[0113] The oxide insulating layer 416 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The layer 416 can be formed by using an appropriate method that prevents impurities such as water and hydrogen from being mixed into the layer 416. When hydrogen is contained in the oxide insulating layer 416, the hydrogen penetrates into the oxide semiconductor layer and is oxidized. The back channel of the compound semiconductor layer 431 becomes low resistance (N-type), and a parasitic channel is formed. Therefore, the oxide insulating layer 416 is formed so as to contain as little hydrogen as possible. It is important that hydrogen is not used in the membrane process.

[0114] In this embodiment, a 200-nm-thick silicon oxide film is sputtered as the oxide insulating layer 416. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas (typically In an atmosphere of noble gas (typically argon), oxygen, or a mixture of noble gas (typically argon) and oxygen, The target may be a silicon oxide target or For example, a silicon target can be used to The silicon oxide film can be formed by sputtering in a hydrogen or nitrogen atmosphere.

[0115] Then, a second heating step is performed under an inert gas atmosphere, a dry air atmosphere, or an oxygen gas atmosphere. (preferably 200°C or higher and 400°C or lower, for example 250°C or higher and 350°C or lower) For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. When the heat treatment is performed, part of the oxide semiconductor layer (channel region) is in contact with the oxide insulating layer 416. As a result, oxygen is supplied to a part (channel region) of the oxide semiconductor layer.

[0116] By undergoing the above steps, the oxide semiconductor layer is subjected to dehydration or dehydrogenation. After the heat treatment, a part of the oxide semiconductor layer (channel region) is selectively made into an oxygen-excess state. Through the above steps, the transistor 410 is formed.

[0117] Furthermore, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The temperature increase and decrease from the heating temperature to room temperature may be repeated several times.

[0118] A protective insulating layer may be further formed over the oxide insulating layer 416. For example, a protective insulating layer may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. This is a preferred method. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films and nitride films are used. An aluminum film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In the first embodiment, a protective insulating layer 403 is formed using a silicon nitride film as a protective insulating layer (FIG. 11(D)). reference).

[0119] In this embodiment, the oxide semiconductor layer of the transistor 410 contains hydrogen as an n-type impurity. The oxide semiconductor is removed and highly purified to minimize the amount of impurities other than the main components of the oxide semiconductor. It is purified to become genuine (type i) or substantially genuine. That is, instead of adding impurities to make it i-type, impurities such as hydrogen and water were removed as much as possible. It is characterized by being a highly purified i-type (intrinsic semiconductor) or close to it. By doing so, the Fermi level (Ef) is raised to the same level as the intrinsic Fermi level (Ei). It is possible.

[0120] The band gap (Eg) of the oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4. The titanium (Ti) that constitutes the source electrode layer and the drain electrode layer is said to be 3 eV. The work function of the oxide semiconductor is approximately equal to the electron affinity (χ). At the interface between the semiconductor and the electrons, no Schottky barrier is formed.

[0121] For example, if the channel width W of a transistor is 1×10 4 The device has a channel length of 3 μm and a width of 1 μm. However, at room temperature, the off-state current is -13 A or less, and the S value is 0.1V / deca de (gate insulating layer thickness 100 nm).

[0122] In this way, it is possible to purify the oxide semiconductor to the extent possible so that it does not contain impurities other than the main component. This allows the transistor 410 to operate well.

[0123] The oxide semiconductor described above is designed to prevent fluctuations in electrical characteristics by preventing hydrogen, moisture, Impurities such as hydroxyl groups or hydrides (also called hydrogen compounds) are intentionally excluded, and Oxygen, the main component of oxide semiconductors, is also reduced during the removal process. Since the oxide semiconductor is supplied with SiO 2 , it is a highly purified and electrically i-type (intrinsic) oxide semiconductor.

[0124] Therefore, the less hydrogen there is in the oxide semiconductor, the better. There are very few carriers in semiconductors (close to zero), with a carrier density of 1×10 12 / c m 3 Less than 1 x 10 11 / cm 3 That is, the carrier of the oxide semiconductor layer is less than The carrier density is set to be as close to zero as possible. The reverse bias characteristics of the transistor can reduce the off-state current. The smaller the value, the better. A transistor has a current value of 1 μm per 1 μm of channel width (w). 00 aA / μm or less, preferably 10 zA (zeptoamperes) or less, and more preferably 1 z Furthermore, since there is no pn junction and no hot carrier degradation, The electrical characteristics of the transistor are not affected.

[0125] In this way, the hydrogen contained in the oxide semiconductor layer was thoroughly removed, resulting in a highly purified oxide semiconductor. A transistor using an oxide semiconductor for a channel region has an extremely small off-state current. In other words, when the transistor is off, the oxide semiconductor layer can be regarded as an insulator. On the other hand, the oxide semiconductor layer can be used to control the conduction state of a transistor. In this case, a higher current supply capacity than that of a semiconductor layer formed from amorphous silicon is expected. can be done.

[0126] In addition, thin film transistors having low-temperature polysilicon are manufactured using oxide semiconductors. The off-state current is estimated to be about 10,000 times larger than that of the transistors used. Therefore, in the transistor having an oxide semiconductor, low-temperature polysilicon When the storage capacitance is the same (about 0.1 pF) as that of a thin film transistor having a The pressure retention period can be extended by approximately 10,000 times. When performing at 60 frames per second, the retention period for one signal write is increased by 10,000 times to 160 Even with a small number of image signal writes, the static image on the display can be displayed in approximately 10 seconds. Still images can be displayed.

[0127] (Fourth embodiment) In this embodiment, an example of a display device according to one embodiment of the present invention will be described.

[0128] FIG. 12A illustrates an example of a display device in which the shift register circuit of Embodiment 2 is used. The display device shown in FIG. 12A includes a timing controller 5360 and a source driver circuit. a gate driver circuit 5363_1 and a gate driver circuit 5363_2. The pixel portion 5364 includes a driver circuit 5361 for driving a source driver. A plurality of source signal lines 5371 are arranged extending from the driver circuit 5362, and the gate driver A plurality of gate signal lines 5372 are connected to the circuit 5363_1 and the gate driver circuit 5363_2. A plurality of source signal lines 5371 and a plurality of gate signal lines 5372 are arranged in an extended manner. In each of the intersecting regions, pixels 5367 are arranged in a matrix.

[0129] The display device may include a lighting device and its control circuit. 5367 may have a liquid crystal element.

[0130] Note that one of the gate driver circuit 5363_1 and the gate driver circuit 5363_2 is omitted. It can be omitted.

[0131] The timing controller 5360 supplies a control signal to the drive circuit 5361. , a circuit having a function of controlling the operation of the driver circuit 5361. For example, The controller 5360 supplies a start signal SSP, a clock signal control signals such as signal SCK, inverted clock signal SCKB, video signal DATA, and latch signal LAT The timing controller 5360 also supplies a gate driver circuit 5363 _1 and the gate driver circuit 5363_2 are supplied with a start signal GSP and a clock signal GCK , and supplies control signals such as the clock signal GCKB.

[0132] The source driver circuit 5362 outputs video signals to a plurality of source signal lines 5371. The image display circuit is a circuit having a function of displaying an image, and can be called a driver circuit or a signal line driver circuit. The image signal is input to the pixel 5367, and the display element that constitutes the pixel 5367 responds to the image signal. The resulting gradation is the same.

[0133] The gate driver circuit 5363_1 and the gate driver circuit 5363_2 drive the pixels 5 367 in sequence, and is called a driver circuit or a scanning line driver circuit. The timing for selecting the pixel 5367 is controlled by the gate driver circuit 5363. _1 and the gate driver circuit 5363_2 output a gate signal to the gate signal line 5372. This is done by:

[0134] In the display device shown in FIG. 12A, the gate driver circuit 5363_1 and the gate The driver circuit 5363_2 can be formed on the same substrate as the pixel portion 5364. FIG. 12B shows a gate driver An example in which a circuit 5363_1 and a gate driver circuit 5363_2 are formed is shown. The substrate 5380 and an external circuit are connected via a terminal 5381 .

[0135] In the display device shown in FIG. 12A, a part of the source driver circuit 5362 (for example, For example, switches, multiplexers, shift register circuits, decoder circuits, inverter circuits, The pixel portion 5364 is formed on the same substrate as the pixel portion 5364. FIG. 12C shows a substrate (referred to as a substrate 5380) that is the same as the pixel portion 5364. 5363_1 and 5363_2 and a source driver circuit A part of the source driver circuit 5362 (shown as 5362a) is formed. Another portion (designated 5362b) is formed on a substrate different from substrate 5380. show.

[0136] The shift register described in the second embodiment is used as a driving circuit or part of a driving circuit of a display device. In particular, the driver circuit of the display device may be the same as that described in the third embodiment. By configuring the driving circuit using a transistor, the driving capability can be improved. Therefore, the display device can be made larger. Alternatively, the resolution of the display device can be improved. Alternatively, the layout area of ​​the drive circuit can be reduced, so that the display This allows the frame of the display device to be made smaller.

[0137] (Embodiment 5) In this embodiment, an example of an electronic device will be described.

[0138] 13(A) to 13(H) and 14(A) to 14(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED Lamp 5004, operation keys 5005 (including a power switch or an operation switch), connection terminal Child 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (has the function of measuring flow rate, humidity, gradient, vibration, smell or infrared rays), microphone 5008, etc.

[0139] FIG. 13(A) shows a mobile computer, which includes, in addition to the above components, a switch 5009, It may have an infrared port 5010, etc. FIG. 13(B) shows a portable device equipped with a recording medium. A type of image reproducing device (for example, a DVD reproducing device), which, in addition to the above, also has a second display 13C shows a GOG In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. FIG. 13(D) shows a portable game machine. In addition to the above, it can have a recording medium reading unit 5011, etc. In addition to the components described above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 13(F) shows a portable gaming machine, which, in addition to the above, has a second display unit 13G shows a television receiver. In addition to the components described above, the image processing unit may also include a tuner, an image processor, etc. 13(H) is a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 14A is a display, and the above-mentioned In addition to the above, it may have a support stand 5018, etc. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 14(C) is a computer, In addition, there are a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 14(D) shows a mobile phone, which can have the above-mentioned Antennas for One-Seg (one-segment partial reception service for mobile phones and mobile terminals) tuners, etc.

[0140] The electronic devices shown in FIGS. 13(A) to 13(H) and 14(A) to 14(D) are various For example, various information (still images, videos, text images, etc.) Function to display on the display, touch panel function, calendar, date or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, The function of transmitting or receiving various data using the program or The data can be read out and displayed on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another is used A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a three-dimensional image. In electronic devices with an image receiving unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to save the captured image to a recording medium (external or camera). It can have functions such as saving the captured image to a built-in memory, displaying the captured image on the display, etc. Note that the electronic devices shown in FIGS. 13(A) to 13(H) and 14(A) to 14(D) The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0141] FIG. 14(E) shows an example in which a display device is integrated with a building. The device includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 50 25, etc. The display device is wall-mounted and integrated into the building, requiring a large installation space. It can be installed without the need for

[0142] FIG. 14(F) shows another example in which a display device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027, and bathers can see the The display panel 5026 becomes viewable.

[0143] In this embodiment, a wall and a unit bath are used as examples of buildings. The manner in which the display device is installed is not limited to this, and the display device can be installed in various buildings.

[0144] Next, an example in which the display device is provided integrally with a moving object will be described.

[0145] FIG. 14(G) is a diagram showing an example in which the display device is installed in an automobile. 028 is attached to the body 5029 of the automobile, and is The information input can be displayed on demand. It may be possible.

[0146] FIG. 14(H) is a diagram showing an example in which a display device is provided integrally with a passenger airplane. FIG. 14(H) shows a passenger airplane in which a display panel 5031 is installed on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 503. 0 and is attached to the hinge portion 5032, and the extension and contraction of the hinge portion 5032 This allows passengers to view the display panel 5031. The display panel 5031 is operated by the passenger. This allows the device to display information.

[0147] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorails, etc.), It can be installed on a variety of things, including buildings, railways, ships, etc.

[0148] The electronic device described in this embodiment mode preferably includes the shift register circuit of Embodiment 2. In particular, the shift register of the second embodiment is preferably used as a circuit for driving a display unit of an electronic device. It is preferable to mount a shift register circuit in the electronic device. By incorporating it as a circuit to drive the display unit, the area of ​​the drive circuit can be reduced. This allows the display unit to be enlarged, and the resolution of the display unit to be improved. . [Explanation of symbols]

[0149] 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 121 Transistor 122 transistors 123 Transistor 124 transistors 125 transistors 126 Capacitor element 200 circuits 201 Capacitor element 202 Transistor 203 Transistor 301 Circuit 302 Transistor 303 Transistor 304 Transistor 305 Transistor 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 400 boards 402 Gate insulating layer 403 Protective Insulation Layer 410 Transistor 411 Gate electrode layer 415a Source electrode layer 415b Drain electrode layer 416 Oxide insulating layer 430 Oxide semiconductor film 431 Oxide semiconductor layer 5000 cabinets 5001 Display section 5002 2nd display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5360 Timing Controller 5361 Circuit 5362 Circuit 5362a circuit 5362b circuit 5363_1 Circuit 5363_2 Circuit 5364 Pixel section 5367 pixels 5371 Source signal line 5372 Gate signal line 5380 PCB 5381 Terminal

Claims

1. The semiconductor device includes first to ninth transistors and first to seventh wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of the source and the drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the first wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; one of the source and the drain of the eighth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the second wiring; a gate of the eighth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the ninth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the ninth transistor is always electrically connected to the third wiring; a gate of the ninth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled in accordance with a potential of a gate of the third transistor; the seventh transistor is controlled to be in an on state or an off state in accordance with a potential of a gate of the seventh transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a gate signal line, the seventh wiring has a function of outputting a first signal; Semiconductor device.

2. The semiconductor device includes first to ninth transistors and first to seventh wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of the source and the drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the first wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; one of the source and the drain of the eighth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the second wiring; a gate of the eighth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the ninth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the ninth transistor is always electrically connected to the third wiring; a gate of the ninth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled in accordance with a potential of a gate of the third transistor; the seventh transistor is controlled to be in an on state or an off state in accordance with a potential of a gate of the seventh transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a gate signal line, A clock signal is input to the second wiring, a power supply voltage is input to the third wiring, the seventh wiring has a function of outputting a first signal; Semiconductor device.

3. The semiconductor device includes first to ninth transistors and first to seventh wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of the source and the drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the first wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; one of the source and the drain of the eighth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the second wiring; a gate of the eighth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the ninth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the ninth transistor is always electrically connected to the third wiring; a gate of the ninth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled in accordance with a potential of a gate of the third transistor; the seventh transistor is controlled to be in an on state or an off state in accordance with a potential of a gate of the seventh transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a gate signal line, the seventh wiring has a function of outputting a first signal, the third transistor has a smaller ratio of channel width to channel length than the fourth transistor; the eighth transistor has a smaller ratio of channel width to channel length than the first transistor; the ninth transistor has a smaller ratio of channel width to channel length than the second transistor; Semiconductor device.

4. The semiconductor device includes first to ninth transistors and first to seventh wirings, one of the source and the drain of the first transistor is always electrically connected to the first wiring; the other of the source and the drain of the first transistor is always electrically connected to the second wiring; one of the source and the drain of the second transistor is always electrically connected to the first wiring; the other of the source and the drain of the second transistor is always electrically connected to the third wiring; one of the source and the drain of the third transistor is always electrically connected to the first wiring; the other of the source and the drain of the third transistor is always electrically connected to the gate of the sixth transistor; one of the source and the drain of the fourth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fourth transistor is always electrically connected to the fourth wiring; the gate of the fourth transistor is always electrically connected to the fifth wiring; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the third wiring; the gate of the fifth transistor is always electrically connected to the sixth wiring; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is always electrically connected to the third wiring; one of the source and the drain of the seventh transistor is always electrically connected to the first wiring; the other of the source and the drain of the seventh transistor is always electrically connected to the third wiring; one of the source and the drain of the eighth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the eighth transistor is always electrically connected to the second wiring; a gate of the eighth transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the ninth transistor is always electrically connected to the seventh wiring; the other of the source and the drain of the ninth transistor is always electrically connected to the third wiring; a gate of the ninth transistor is always electrically connected to a gate of the second transistor; an on state or an off state of the third transistor is controlled in accordance with a potential of a gate of the third transistor; the seventh transistor is controlled to be in an on state or an off state in accordance with a potential of a gate of the seventh transistor; when the fourth wiring is electrically connected to the gate of the first transistor through at least a channel region of the fourth transistor, a potential of the fourth wiring is applied to the gate of the first transistor; the first wiring has a function as a gate signal line, A clock signal is input to the second wiring, a power supply voltage is input to the third wiring, the seventh wiring has a function of outputting a first signal, the third transistor has a smaller ratio of channel width to channel length than the fourth transistor; the eighth transistor has a smaller ratio of channel width to channel length than the first transistor; the ninth transistor has a smaller ratio of channel width to channel length than the second transistor; Semiconductor device.

5. In any one of claims 1 to 4, the first to ninth transistors have the same channel type; Semiconductor device.

Images