Semiconductor device and electronic appliance

Abstract

To provide a display device capable of increasing the image quality with low consumption power.SOLUTION: A storage node is provided in each pixel, and a first signal can be kept in the storage node. A second signal is added to the first signal by capacitive coupling, and a display element is operated in accordance with a generated third signal. Therefore, a high voltage can be supplied to the display element regardless of an output voltage of a driver that supplies data. Even the display element that requires a relatively high voltage for the operation can operate with low consumption power.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors have been attracting attention. Examples of oxide semiconductors include: Not only oxides of single metals such as indium oxide and zinc oxide, but also oxides of multi-component metals Among the multi-component metal oxides, In-Ga-Zn oxide (hereinafter referred to as IG There is a lot of research being done on the ZO (also called ZO).

[0005] Research on IGZO has revealed that CAA, which is neither single-crystal nor amorphous, is an oxide semiconductor. C (c-axis aligned crystalline) structure and nc (nan A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, a transistor is formed using an oxide semiconductor having a CAAC structure. Furthermore, a technique for fabricating a transistor with a CAAC structure and an nc structure has been disclosed. Even oxide semiconductors with low crystallinity have minute crystals, as reported in Non-Patent Document 4 and Non-Patent Document 5. This is shown in reference 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non-specific 6), and LSIs and displays utilizing this property have been reported (Non-Patent Document 6). See patent document 7 and non-patent document 8).

[0007] In addition, a memory device having a structure in which a transistor with extremely low off-state current is used as a memory cell is disclosed in a patent document. This is disclosed in reference 1. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119674 [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-patent document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-patent document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-patent document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0010] Display devices are becoming increasingly high-resolution, with 8K4K (pixel count: 7680 x 4320) resolution or Hardware that can display at higher resolutions is being developed. The introduction of HDR (High Dynamic Range) display technology, which improves image quality through adjustments, is also progressing. There is.

[0011] To display the image properly on a display device, the image data must be adjusted to the resolution of the display device. For example, if the resolution of the display device is 8K4K and the image data is 4K2K (number of pixels: 3 If the resolution is 840 x 2160, the data size must be converted to 4 times the original size to display in full screen. Conversely, if the resolution of the display device is 4K2K and the image data is for 8K4K, In some cases, the number of data items must be converted to 1 / 4.

[0012] In addition, dedicated circuits are required to generate image data and convert the amount of data used for HDR processing. However, there is also the problem of increasing power consumption. It is preferable that the input signal can be input to the pixels.

[0013] Therefore, one aspect of the present invention is to provide a display device that can improve image quality. One of the purposes is to provide a display device that can display image data appropriately without converting it. One of the purposes is to provide a display device capable of HDR display. One of the purposes is to provide a display device that can perform up-conversion. Another object of the present invention is to provide a display device that can increase the brightness of a displayed image. One of the purposes is to provide a display device that can display two images superimposed on each other. One of the purposes is to provide

[0014] Another object is to provide a display device with low power consumption. One of the purposes is to provide a new display device. Another object of the present invention is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

[0015] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0016] One aspect of the present invention relates to a display device capable of improving image quality. The present invention relates to a display device that can perform the above.

[0017] One embodiment of the present invention is a display device including a pixel provided with a light-emitting element, wherein the light-emitting element A tandem structure in which two or more light-emitting layers are connected in series, and the pixel stores a first signal. The pixel has a function of adding the first signal to the second signal to generate a third signal. The light-emitting element is a display device having a function of emitting light based on the third signal.

[0018] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a pixel provided with a first capacitance element and a circuit block; a first wiring; and a second wiring. , wherein one of the source and drain of the first transistor is The first transistor is electrically connected to one of the source and drain of the second transistor. one of the source and drain of the capacitor is electrically connected to one electrode of the first capacitor element, The other electrode of the first capacitor is electrically connected to one of the source and drain of the third transistor. The third transistor is electrically connected to the circuit block. The other of the source and the drain of the first transistor is electrically connected to the first wiring. The other of the source and the drain of the third transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the second wiring. The gate of the third transistor is electrically connected to the second wiring, and the circuit block is The display device has a light emitting element having a tandem structure in which the light emitting layers are connected in series.

[0019] The light emitting element preferably emits white light. the first pixel has a colored layer of R (red), and the second pixel has a colored layer of G (green), The third pixel has a B (blue) colored layer, and in the first to third pixels, light from the light emitting element is In the fourth pixel, the light from the light emitting element is transmitted to the outside through the colored layer. may be injected into

[0020] The circuit block further includes a fourth transistor, a fifth transistor, and a second capacitive element. and one electrode of the light-emitting element is connected to one of the source and drain electrodes of the fifth transistor. The other of the source and drain of the fifth transistor is electrically connected to the second capacitor. One electrode of the second capacitance element is electrically connected to one electrode of the fourth transistor. a gate of a fourth transistor electrically connected to one of the source and drain of the fourth transistor; is electrically connected to the other electrode of the second capacitor element, and the other electrode of the second capacitor element is The second electrode can be electrically connected to one electrode of the first capacitor.

[0021] In the above configuration, the other of the source and the drain of the fourth transistor is connected to the second transistor. The source or drain of the transistor can be electrically connected to the other of the source or drain of the transistor.

[0022] The third transistor has a metal oxide in a channel formation region, and the metal oxide contains In and Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) , preferably having [Effects of the Invention]

[0023] To provide a display device capable of improving image quality by using one embodiment of the present invention. Alternatively, a display device that can display image data appropriately without converting the image data can be provided. Alternatively, a display device capable of HDR display can be provided. Alternatively, a display device capable of up-conversion can be provided. It is possible to provide a display device that can enhance the brightness of an image. It is possible to provide a display device that can display images in an overlapping manner.

[0024] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. Furthermore, a method for driving the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided. It can be provided. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 2] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 3] 5A to 5C are diagrams illustrating image data correction and image synthesis. [Figure 4] FIG. 2 is a diagram illustrating a circuit block. [Figure 5] FIG. 2 is a diagram illustrating a circuit block. [Figure 6] FIG. 2 is a diagram illustrating a circuit block. [Figure 7] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 8] FIG. 2 is a diagram illustrating a pixel array. [Figure 9] 4 is a timing chart illustrating the operation of the pixel array. [Figure 10] FIG. 1 is a block diagram illustrating a display device. [Figure 11] FIG. 1 is a diagram illustrating an example of the configuration of a neural network. [Figure 12] FIG. 2 is a diagram illustrating the configuration of a pixel array used in a simulation. [Figure 13] FIG. 10 is a diagram illustrating the results of a simulation. [Figure 14] FIG. 10 is a diagram illustrating the results of a simulation. [Figure 15] FIG. 10 is a diagram illustrating the results of a simulation. [Figure 16] FIG. 2 is a diagram illustrating the configuration of a pixel. [Figure 17] 1A and 1B are diagrams illustrating a display device. [Figure 18] FIG. 2 is a diagram illustrating a touch panel. [Figure 19] 1A and 1B are diagrams illustrating a display device. [Figure 20] 1A and 1B are diagrams illustrating a display device. [Figure 21] 1A and 1B are diagrams illustrating light-emitting elements. [Figure 22] 1A and 1B are diagrams illustrating a light-emitting layer and its operation. [Figure 23] 1A and 1B are diagrams illustrating an equivalent circuit and a voltage drop of a light-emitting element. [Figure 24] 1A and 1B are diagrams illustrating a transistor. [Figure 25] 1A and 1B are diagrams illustrating a transistor. [Figure 26] 1A and 1B are diagrams illustrating a transistor. [Figure 27] 1A and 1B are diagrams illustrating a transistor. [Figure 28] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0027] In addition, even if a circuit diagram shows a single element, there may be functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, a transistor that operates as a switch may be used. In some cases, multiple resistors may be connected in series or in parallel. In some cases, the sensor may be divided and placed in multiple positions.

[0028] In addition, when one conductor has multiple functions such as wiring, electrode, and terminal, In this specification, the same element may be referred to by multiple names. Even if the circuit diagram shows direct connections between elements, In some cases, the elements are connected via multiple conductors, and in this specification, Even configurations such as this are included in the category of direct connection.

[0029] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0030] One embodiment of the present invention is a display device having a function of correcting image data in each pixel. A storage node is provided in the first data storage unit, and the first data can be stored in the storage node. The first data is added to the second data by capacitive coupling and can be supplied to the display element. Alternatively, the first data can be written to the storage node by capacitive coupling after the second data is written to the storage node. It can also be added with

[0031] Therefore, the display device can display a corrected image. It is possible to up-convert the image or to convert part or all of the image on the display. The image can be corrected and displayed in HDR. By using the same image data as the data, the brightness of the displayed image can be significantly improved. Alternatively, by using different image data as the first data and the second data, Any image can be displayed superimposed on it.

[0032] Furthermore, by using one aspect of the present invention, two image data sets, one for high resolution and one for low resolution, can be obtained. To display properly without up-converting or down-converting When displaying at high resolution, the first transistor of each pixel is connected to each Individual data is supplied to each pixel. When displaying at low resolution, multiple pixels are electrically connected. The same data is supplied to the plurality of pixels via a second transistor.

[0033] Here, high resolution image data is, for example, 8K4K (pixel count: 7680 x 4320 ) In addition, low-resolution image data corresponds to, for example, 4K2K (Number of pixels: 3840 x 2160) The ratio of the number of valid data (corresponding to the number of valid pixels) between the image data and the low-resolution image data is 4: Assume that it is 1.

[0034] If the ratio of the number of data (number of pixels) is 4:1, it is not limited to the above example, and can be used for high-resolution images. The image data corresponds to 4K2K, and the image data for low resolution is FullHD (number of pixels It may also be data corresponding to a high resolution image (1920 x 1080). The data corresponds to 16K8K (pixel count: 15360 x 8640), and the image data is for low resolution. The image data may be data corresponding to 8K4K.

[0035] FIG. 1 illustrates a pixel 10 that can be used in a display device of one embodiment of the present invention. The pixel 10 includes a transistor 101, a transistor 102, a transistor 103, and a capacitor. The circuit block 110 includes a transistor, It may have a capacitive element, a display element, and the like, which will be described in detail later.

[0036] The source or drain of the transistor 101 is connected to the source or drain of the transistor 102. is electrically connected to one of the source and drain of the transistor 102. One of the electrodes is electrically connected to one of the electrodes of the capacitor 104. The electrode is electrically connected to one of the source and drain of the transistor 103. One of the source and drain of the transistor 103 is electrically connected to the circuit block 110. do.

[0037] Here, one of the source and drain of the transistor 103 and the other of the capacitor 104 The wiring to which the pole and the circuit block 110 are connected is referred to as a node NM. The element of the circuit block 110 that connects to the node NM can be floating. do.

[0038] The gate of the transistor 101 is electrically connected to the wiring 122. The gate of the transistor 101 and the gate of the transistor 103 are electrically connected to a wiring 121. The other of the source or drain of the transistor 101 and the other of the source or drain of the transistor 103 The other of the drains is electrically connected to a wiring 123. The other end of the drain is electrically connected to a wiring that can supply a specific potential "Vref". To be continued.

[0039] The wirings 121 and 122 function as signal lines for controlling the operation of the transistors. The wiring 123 can be used as a signal line for supplying the first data or the second data. The wiring that can supply "Vref" is, for example, For example, a power supply line electrically connected to the elements of the circuit block 110 can be used.

[0040] In order to perform the capacitive coupling operation described later, the pixel must be supplied with "Vref" and the first data ( For example, correction data) must be supplied during the same period. When supplying from a line, at least a signal line that supplies the first data and a line that supplies "Vref" or A signal line for supplying the second data (for example, image data) is required.

[0041] On the other hand, in the display device of one embodiment of the present invention, "Vref" is supplied from a power supply line or the like. By switching the timing, the first data supply or the second data supply can be This can be done from the signal line (wiring 123). In other words, it can be configured with a small number of wirings. can.

[0042] The node NM is a storage node, and when the transistor 103 is turned on, a The supplied data can be written to the node NM. By making the transistor 10 conductive, the data can be held at the node NM. By using a transistor with extremely low off-state current as 3, the potential of the node NM can be maintained for a long time. In the transistor, for example, a metal oxide is used as a channel forming region. The transistors used in the above (hereinafter referred to as OS transistors) can be used.

[0043] In addition to the transistor 103, other transistors constituting the pixel may be OS transistors. In addition, the transistor 103 may have Si in the channel formation region. Alternatively, an OS transistor may be used. It is also possible to use both a silicon transistor and a silicon transistor. , amorphous silicon transistors, crystalline silicon (typically low-temperature poly Examples include transistors using silicon (polysilicon, single crystal silicon).

[0044] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Because it exhibits high mobility, it is suitable for use in transistors that operate at high speed.

[0045] OS transistors have a large energy gap and therefore exhibit extremely low off-state current. In addition, OS transistors have the following drawbacks: impact ionization, avalanche breakdown, and short-channel It has features that are different from Si transistors, such as no effects, and is highly reliable with high voltage resistance. In addition, the non-uniformity of crystallinity, which is a problem with Si transistors, can be eliminated. OS transistors are also less susceptible to variations in electrical characteristics caused by this.

[0046] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The film can be made of a material such as a silicon dioxide film.

[0047] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0048] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or The oxide semiconductor is called a substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and It can be said that this is an oxide semiconductor with stable characteristics.

[0049] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0050] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase, causing the semiconductor layer to become n-type. The concentrations of phosphate and carbon (obtained by secondary ion mass spectrometry) were measured at 2 × 10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0051] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0052] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0053] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0054] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0055] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0056] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This section explains the structure of the .NET composite OS.

[0057] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0058] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0059] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1, or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0060] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0061] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0062] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0063] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0064] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0065] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0066] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0067] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0068] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction measurement, It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0069] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped area of ​​high brightness (phosphor) is formed. The electron diffraction pattern is Therefore, the crystal structure of CAC-OS does not have orientation in the planar direction and the cross-sectional direction. It is clear that the material has a nanocrystalline structure.

[0070] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0071] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0072] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0073] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0074] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) This can be done.

[0075] Furthermore, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0076] Correction data is added to the image data using the timing charts shown in Figures 2(A) and 2(B). In the following description, a high potential is referred to as "H" and Low potential is represented by "L". Correction data is represented by "Vp", image data is represented by "Vs", and specific voltage is represented by "Vp". The reference voltage is "Vref". "Vref" can be, for example, 0V, GND potential, or a specific The reference potential can be used. Note that "Vp" is an arbitrary first data, and "Vs" is an arbitrary It can also be said to be the second data.

[0077] First, the operation of writing the correction data "Vp" to the node NM will be described with reference to FIG. In addition, in the distribution, coupling or loss of potential, the circuit configuration and operation timing, etc. The detailed changes due to the capacitive coupling using the capacitive element are not taken into consideration. Although it depends on the capacitance ratio between the capacitive element and the load connected thereto, for the sake of clarity, The capacitance value of the circuit block 110 is assumed to be sufficiently small.

[0078] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When "Vp" is set, the transistor 102 is turned on, and the potential of one electrode of the capacitor 104 is This operation is a reset for the subsequent correction operation (capacitive coupling operation). It is an action.

[0079] Also, the transistor 103 is turned on, and the potential of the wiring 123 (the correction data “Vp ") is written.

[0080] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", the potential of the wiring 123 is set to "L", When the transistor 102 and the transistor 103 are set to "L", the transistor 102 and the transistor 103 are turned off, and the node The correction data "Vp" is stored in the NM. " is retained.

[0081] This is the write operation of the correction data "Vp". If no correction is to be performed, In the above operation, the same potential as "Vref" may be supplied as the correction data "Vp".

[0082] Next, referring to FIG. 2B, the correction operation of the image data “Vs” and the circuit block 110 The display operation of the display element included in the LCD panel will be described below.

[0083] The operations shown in FIGS. 2A and 2B can be performed consecutively within one horizontal period. The action in (A) is performed in the kth frame (k is a natural number), and the action in (B) in Figure 2 is performed in the k+1th frame. Alternatively, after the operation in FIG. 2(A), the operation in FIG. 2(B) may be performed multiple times. That's fine.

[0084] At time T11, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 123 is set to "H". When Vs is used, the transistor 101 becomes conductive and the capacitance of the capacitor 104 causes a The potential "Vs" of the wiring 123 is added to the potential of the node NM. If "Vp-Vref+Vs" and "Vref"=0, the potential of the node NM is Vp+Vs”.

[0085] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When the voltage Vp+ is set to "L", the transistor 103 is turned off and the potential of the node NM is set to "Vp+ Vs”.

[0086] Thereafter, the display element included in the circuit block 110 displays a display according to the potential of the node NM. Depending on the configuration of the circuit block, the display may start from time T1 or time T11. Sometimes it performs an action.

[0087] Here, the image data correction operation will be described with reference to FIG.

[0088] The diagram shown in FIG. 3(A) shows four pixels (P1 to P4) in the horizontal and vertical directions. Input image data (Vs1, Vs2, Vs3), input correction data (+Vp1, V p0, -Vp1) are the corrected image data to be generated. In a display element, when the potential of the image data is relatively high, the display is high brightness, and when it is low, the display is low brightness. This will be possible.

[0089] For example, in pixel P1, positive correction data "+Vp When "Vs1+Vp1" is applied, the image data becomes "Vs1+Vp1" and the brightness increases. 2 and P3, the correction data " When "Vp0" is applied, the image data becomes "Vs2+Vp0=Vs2" and the brightness does not change. At pixel P4, negative correction data "-V When "Vs3-Vp1" is applied, the image data becomes "Vs3-Vp1" and the brightness decreases.

[0090] In this combination of image data and correction data, R display, correction of display irregularities inherent to the display device, compensation of the threshold voltage of the transistors in the pixels It is possible to perform corrections etc.

[0091] In the up-conversion operation, for example, the same image data is supplied to all four pixels. For example, the number of pixels for 8K and 4K can be increased by It is suitable for one specific pixel of a display device having 4K2K pixels and for four specific pixels of a display device having 4K2K pixels. It is possible to input data used in the image and display it with improved resolution.

[0092] In a broad sense, it is a correction of image data, but it can also be used to display different images superimposed on each other. Figure 3(B) shows the image on the entire display, and from the left, the image data "Vs" is composed of a first image consisting of correction data "Vp"; a second image consisting of correction data "Vp"; is the synthesized image.

[0093] In such a combination of image data and correction data, different images can be synthesized and displayed. In addition, it is possible to improve the brightness of the entire displayed image. For example, it is possible to insert characters and AR (A This can be applied to displaying 3D images in a 3D environment, such as enhanced reality.

[0094] In addition, a high voltage can be supplied to the display element even when a general-purpose driver IC is used. For example, it is possible to drive a liquid crystal element that requires a high voltage for gradation control. The voltage supplied from the driver IC to drive general liquid crystal elements and light emitting elements is reduced by approximately 1 / 2, the power consumption of the display device can be reduced.

[0095] 4A to 4C are applicable to the circuit block 110 and include a light-emitting element as a display element. This is an example of a configuration that includes:

[0096] The structure shown in FIG. 4A includes a transistor 111, a capacitor 113, and a light-emitting element 114. One of the source and drain of the transistor 111 is connected to one of the light-emitting elements 114. One electrode of the light-emitting element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to a node NM. do.

[0097] The other of the source and the drain of the transistor 111 is electrically connected to a wiring 128. The other electrode of the light emitting element 114 is electrically connected to the wiring 129. For example, the wiring 128 can supply high potential power. In addition, the wiring 129 can supply a low potential power supply.

[0098] In the configuration shown in FIG. 4A, the potential of the node NM is higher than the threshold voltage of the transistor 111. When this occurs, a current flows through the light emitting element 114. Therefore, the weight (W) is applied to the node NM. The light emitting element 114 may start emitting light at the stage when the data is written, which may limit the use of the device. be.

[0099] Alternatively, as shown in FIG. 4B, one electrode of the light emitting element 114 is electrically connected to the wiring 128. The other electrode of the light emitting element 114 is connected to the other of the source or drain of the transistor 111. This configuration may be electrically connected to another circuit block 1 having a light emitting element 114. It can also be applied to 10.

[0100] FIG. 4C shows a configuration in which a transistor 112 is added to the configuration of FIG. 4A. One of the source or drain of transistor 112 is connected to the source or drain of transistor 111. The other of the source and the drain of the transistor 112 is electrically connected to The gate of the transistor 112 is electrically connected to one electrode of the light-emitting element 114. The wiring 130 is electrically connected to a signal line that controls the conduction of the transistor 112. It can function as a route.

[0101] In this configuration, the potential of the node NM is equal to or higher than the threshold voltage of the transistor 111. When the transistor 112 is conductive, a current flows through the light emitting element 114. Therefore, the weight ( The light emitting element 114 starts emitting light at an arbitrary timing after the addition of the data (W) and the data (D). This can be done.

[0102] FIG. 4D shows a configuration in which a transistor 115 is added to the configuration of FIG. 4C. One of the source or drain of transistor 115 is connected to the source or drain of transistor 111. The other of the source and drain of the transistor 115 is electrically connected to The gate of the transistor 115 is electrically connected to a wiring 132. The wiring 132 functions as a signal line that controls the conduction of the transistor 115. can have:

[0103] The wiring 131 can be electrically connected to a source of a specific potential such as a reference potential. A specific potential is applied to either the source or drain of transistor 111 from line 131. This also makes it possible to stabilize the writing of image data.

[0104] The wiring 131 can be connected to the circuit 120 and has a function as a monitor line. The circuit 120 can also be configured to control the specific potential source and the electrical characteristics of the transistor 111. The correction data generating unit may have one or more of the functions of acquiring the correction data and generating the correction data.

[0105] 5A to 5D are applicable to the circuit block 110 and include a liquid crystal element as a display element. This is an example of a configuration that includes:

[0106] The structure shown in FIG. 5A includes a capacitor 116 and a liquid crystal element 117. One electrode of the capacitor 7 is electrically connected to one electrode of the capacitor 116. One electrode of the transistor is electrically connected to a node NM.

[0107] The other electrode of the capacitor 116 is electrically connected to the wiring 133. One electrode is electrically connected to a wiring 134. The wirings 133 and 134 are used to supply power. For example, the wirings 133 and 134 may be connected to a reference potential such as GND or 0V or to an arbitrary potential. can be supplied.

[0108] As shown in FIG. 5B, the capacitor 116 may be omitted. In addition, an OS transistor can be used as the transistor connected to the node NM. Since the transistor has an extremely small leakage current, the capacitor 116 that functions as a storage capacitor Even if the OS transistor is omitted, the display can be maintained for a relatively long time. Regardless of the configuration, high-speed operation such as field sequential driving can shorten the display period. It is also effective to omit the capacitor element 116 when the aperture ratio is increased. Alternatively, the transmittance of the pixel can be improved.

[0109] In the configurations of FIGS. 5A and 5B, when the potential of the node NM is higher than the operating threshold of the liquid crystal element 117, When the weight is written to the node NM, the liquid crystal element 117 starts to operate. The display operation may start when the data is written, and the usage may be limited. In the case of a transmissive liquid crystal display device, the timing at which the addition of weight (W) and data (D) is completed is By combining this with other operations such as turning off the backlight until the Even if the object is not visible, it is possible to suppress its visibility.

[0110] FIG. 5C shows a configuration in which a transistor 118 is added to the configuration of FIG. 5A. One of the source and drain of the capacitor 118 is electrically connected to one electrode of the capacitor element 116. The other of the source and drain of the transistor 118 is electrically connected to the node NM. The gate of the transistor 118 is electrically connected to the wiring 127. 27 can function as a signal line for controlling the conduction of the transistor 118. .

[0111] In this configuration, when the transistor 118 is turned on, the potential of the node NM is applied to the liquid crystal element 117. Therefore, at any timing after the addition of weight (W) and data (D), The liquid crystal element can then start operating.

[0112] When the transistor 118 is off, the voltage supplied to the capacitor element 116 and the liquid crystal element 117 is Since the supplied potential is maintained, the capacitor element 116 and the It is preferable to reset the potential supplied to the liquid crystal element 117. For example, a reset potential is supplied to the wiring 123 (see FIG. 1) and the transistor 103 (see FIG. 1) and transistor 118 may be simultaneously turned on.

[0113] FIG. 5D shows a configuration in which a transistor 119 is added to the configuration of FIG. 5C. One of the source and drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source and the drain of the transistor 119 is electrically connected to a wiring 131. The gate of the transistor 119 is electrically connected to the wiring 132. The reference numeral 32 can function as a signal line for controlling the conduction of the transistor 119 .

[0114] The circuit 120 electrically connected to the wiring 131 is the same as that described above with reference to FIG. In addition, the potential supplied to the capacitor element 116 and the liquid crystal element 117 is reset. It may be possible.

[0115] 6A to 6C are specific examples of wiring for supplying "Vref" shown in FIG. 1 etc. As shown in FIG. 6(A), when a light-emitting element is used as a display element, Wiring 128 can be applied to wiring for supplying "Vref". "Vref" is Since it is preferable that the potential is 0V, GND, or low potential, the wiring 128 is at least one of these. The wiring 128 also has a function of supplying either one of the potentials. At the timing when the light emitting element 114 is turned on, "Vref" is supplied. Alternatively, as shown in FIG. 6B, a wiring for supplying a low potential may be used. 129 may be applied as wiring for supplying "Vref."

[0116] Also, as shown in FIG. 6(C), when a liquid crystal element is used as a display element, "Vref" The wiring 133 can be applied to the wiring for supplying the Regardless of the type of display element, a dedicated common wiring that supplies "Vref" may be provided.

[0117] In addition, although Figure 6 shows an example in which "Vref" is supplied from the power supply line, it can also be supplied from the scanning line. For example, as shown in FIG. 7(A), "Vref" can be supplied from the wiring 122. As shown in FIG. 2A, when the correction data is written (when the transistor 103 is conductive), ) is supplied with a potential corresponding to "L", so the potential is set to "Vref" It can be used as.

[0118] As shown in FIGS. 7B and 7C, the transistors 101, 102, and 103 are back-coupled. FIG. 7B shows a configuration in which the back gate is electrically connected to the front gate. This shows a configuration in which the transistors are electrically connected, which has the effect of increasing the on-state current. The gate is electrically connected to a wiring 134 that can supply a constant potential. The threshold voltage of the transistor can be controlled. The transistors included in the circuit block 110 shown in (A) to (C) and (A) to (C) of FIG. A back gate may also be provided in the resistor.

[0119] FIG. 8 shows a part (four pixels) of a pixel array having a pixel 11 to which the basic configuration of pixel 10 is applied. The pixel 11 includes a transistor 103, a capacitor 104, and a circuit block. In addition, the n and m in the parentheses attached to the symbols indicate a specific row, and the i indicates a specific column. (n, m, i are natural numbers).

[0120] The pixels 11 are arranged in a matrix, and the pixels 11 are arranged in the nth row and the ith column, the nth row and the (i+x)th column (x is natural number), and can be placed in the (n+1)th row, i-th column and the (n+1)th row, (i+x)th column. Note that FIG. 8 shows the arrangement when x=1.

[0121] The pixel array also includes a transistor 101 electrically connected to four pixels 11, a transistor Transistor 102a and transistor 102b are provided. 02b has the function of the transistor 102 in the pixel 10.

[0122] The transistor 101 is an element of each pixel 11 and is shared by four pixels. The transistor 102a is connected to the pixel 11[n,i] and the pixel 11[n,i+1]. The transistor 102b is an element shared by two pixels. 11[n+1,i] and the element of pixel 11[n+1,i+1], which are common to the two pixels. It can be said that the transistors 101, 102a, and 102b have They may be distributed over the pixel area.

[0123] In each pixel 11, one of the source and drain of the transistor 103 is connected to the capacitor element 1 One electrode of the capacitor 104 is electrically connected to one electrode of the capacitor 104. The other electrode of the capacitor 104 is electrically connected to the source electrode 110 of the transistor 101. The source or drain of the transistor 101 is electrically connected to the One of the drains is electrically connected to one of the source and drain of the transistor 102a. In addition, one of the source and drain of the transistor 101 is connected to the transistor 102. b is electrically connected to either the source or the drain of b.

[0124] In this pixel array, the number of wirings and the number of wirings are reduced compared to a configuration in which the pixels 10 are simply arranged in a matrix. It is possible to perform some of the same operations with a configuration that uses fewer transistors.

[0125] Furthermore, even if the resolution of the display device and the image data are different, the image data and the correction data can be By switching the input path of the data, it can be up-converted or down-converted. Appropriate display can be made without any problems.

[0126] Using the timing charts shown in (A1) and (A2) of FIG. 9, different timings are applied to the pixels 11. An example of the operation of writing data for a pixel count of 8K / 4K will be described. When inputting high-resolution image data (8K4K data), Although the explanation will be given for one pixel 11, the other pixels 11 also operate in the same manner. can be applied.

[0127] In the following explanation, high potential is referred to as "H", low potential as "L", and a specific voltage between high potential and low potential is referred to as "L". The potential is expressed as "M". Note that "M" is a reference potential such as 0V or GND. However, other potentials may be used. ", and the correction data for high resolution is "Vp1". Note that "Vp1" is an arbitrary first data The data "VsH" can also be said to be arbitrary second data.

[0128] First, the operation of writing image data "VsH" to the node NM will be described with reference to FIG. 9(A1). In this case, the distribution, coupling, or loss of potential is affected by the circuit configuration and operation timing. Detailed changes due to factors such as the above will not be taken into account.

[0129] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When "VsH" is set, the transistor 102 is turned on, and the potential of the other electrode of the capacitor 104 This operation is a reset for the subsequent correction operation (capacitive coupling operation). This is a fast operation.

[0130] In addition, the transistor 103 is turned on, and the potential of the wiring 123 (image data “Vs H”) is written.

[0131] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", the potential of the wiring 123 is set to "L", When "M" is selected, the transistors 102 and 103 are turned off. The image data "VsH" is held in the node NM. ef” is retained.

[0132] This is the write operation of the image data "VsH". Next, using FIG. 9(A2), , the correction operation of the image data “VsH” and the display on the display element of the circuit block 110 The operation will be explained.

[0133] The operations of (A1) and (A2) in FIG. 9 can be performed continuously within one horizontal period. The operation of FIG. 9(A1) is performed in the kth frame (k is a natural number), and the operation of FIG. 9(A2) is performed in the kth frame. It may be performed in the +1 frame. Alternatively, after the operation of FIG. 9(A1), the operation of FIG. 9(A2) may be performed. may be performed multiple times.

[0134] At time T11, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 123 is set to "H". is set to "Vp1", the transistor 101 is turned on, and the capacitance of the capacitance element 104 The potential "Vp1" of the wiring 123 is added to the potential of the node NM. The potential is "VsH-Vref+Vp1", and if "Vref"=0, then the The potential is "VsH+Vp1". If no correction is made, the above operation will be as follows: The same potential as "Vref" may be supplied as the correction data "Vp1."

[0135] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When "M" is selected, the transistor 101 is turned off, and the potential of the node NM is "VsH+ Vp1”.

[0136] Thereafter, the display element included in the circuit block 110 displays a display according to the potential of the node NM. Depending on the configuration of the circuit block, the display may start from time T1 or time T11. Sometimes it performs an action.

[0137] By performing correction using selected pixels in this way, HDR display and the like can be achieved. The correction data "Vp1" has the same value for all four pixels, but to achieve the visual effect of light and dark, Furthermore, when no correction is performed, the wiring 123 Alternatively, the potential of the wiring 122 may be set to "L" to maintain the transistor The starter 101 should not be conductive.

[0138] Next, using the timing charts shown in FIGS. 9(B1) and 9(B2), the four pixels 11 are simultaneously This operation is performed, for example, when the number of pixels corresponds to 8K4K. A display device that corresponds to the case where low-resolution image data (4K2K data) is input. .

[0139] First, the operation of writing the correction data "Vp2" to the node NM will be described with reference to FIG. 9(B1). In the following, the image data for low resolution is called "VsL" and the correction data for low resolution is called "Vp 2". Note that "Vp2" is any first data, and "VsL" is any second data. It is also possible to say this.

[0140] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When "Vp2" is set, the transistor 102 is turned on, and the potential of the other electrode of the capacitor 104 This operation is a reset for the subsequent correction operation (capacitive coupling operation). This is a fast operation.

[0141] Also, the transistor 103 is turned on, and the potential of the wiring 123 (the correction data “Vp 2") is written.

[0142] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", the potential of the wiring 123 is set to "L", When set to "M", the transistors 102 and 103 are turned off, and the node The image data "Vp2" is stored in the NM. ef” is retained.

[0143] This completes the write operation of the correction data "Vp2". If no correction is performed, In the above operation, the same potential as "Vref" should be supplied as the correction data "Vp2". stomach.

[0144] Next, referring to FIG. 9(B2), the correction operation of the image data “VsL” and the circuit block 1 The display operation of the display element 10 will be described.

[0145] The operations of (B1) and (B2) of FIG. 9 can be performed continuously within one horizontal period. 9(B1) is performed in the kth frame, and the operation of FIG. 9(B2) is performed in the k+1th frame. Alternatively, after the operation of FIG. 9(B1), the operation of FIG. 9(B2) may be performed multiple times. good.

[0146] At time T11, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "H", and the potential of the wiring 123 is set to "H". When VsL is set, the transistor 101 becomes conductive, and the capacitance of the capacitor 104 The potential "VsL" of the wiring 123 is added to the potential of the node NM. The potential is "Vp2-Vref+VsL", and if "Vref"=0, then the The potential becomes "Vp2+VsL."

[0147] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When "M" is selected, the transistor 101 is turned off, and the potential of the node NM is "Vp 2+VsL”.

[0148] Thereafter, the display element included in the circuit block 110 displays a display according to the potential of the node NM. Depending on the configuration of the circuit block, the display operation may start from time T11. There are also.

[0149] As the correction data "Vp2", different values ​​can be input to each pixel 11. Even if the image data "VsL" is the same, each pixel 11 can display different images. In other words, up-conversion is possible. Note that if no correction is performed, the same image will be generated using four pixels. is displayed.

[0150] By operating in this way, the original image data can be displayed on the display without being up-converted. The image can be input to the device and displayed appropriately. Correction can be made.

[0151] FIG. 10A is an example of a block diagram of a display device of one embodiment of the present invention. a pixel array 12 in which pixels 11 are arranged in a matrix, a row driver 13, and a column driver It has a driver 14, a circuit 15, and a selection circuit 16. In FIG. The transistor 102a and the transistor 102b are represented by one block, and the potential "Vref" is The connection with the wiring that supplies the power is omitted.

[0152] The row driver 13 is, for example, a combination of a shift register 20 and a buffer circuit 21. By controlling the conduction of the buffer circuit 21, the wiring 121 Alternatively, data can be output to the wiring 122.

[0153] The column driver 14 is, for example, a combination of a shift register 22 and a buffer circuit 23. By controlling the conduction of the buffer circuit 23, the wiring 12 3 can output data.

[0154] The circuit 15 has a function of generating correction data. It can also be considered an external device for

[0155] The row driver 13 controls the conduction of the transistor 101 and the transistors 102a and 102b. The column driver 14 can control the wiring 123 to transmit correction data or image data. Data can be supplied.

[0156] The circuit 15 receives image data for high resolution “VsH” (for example, 8K4K data) or low Image data with a resolution of "VsL" (for example, 4K2K data) is input. When "VsH" is input, correction data "Vp1" is generated and image data "VsL" is When input, correction data "Vp2" is generated.

[0157] The selection circuit 16 selects the correction data "Vp1" and "Vp2" generated by the circuit 15 as well as the external Correction data "Vp1", "Vp2" or image data "VsH", "VsL" generated by can be output to the column driver 14.

[0158] In the configuration shown in FIG. 11(A), for example, when a display operation without correction is performed at low resolution, each driver This allows the number of output stages of the driver to be halved, thereby reducing power consumption.

[0159] The circuit 15 may have a neural network. For example, a large number of images may be used as a training data. By using a deep neural network trained as data, highly accurate correction data can be obtained. Data can be generated.

[0160] As shown in Figure 11(A), the neural network NN consists of an input layer IL, an output layer OL, and a middle layer OL. It can be composed of an input layer IL, an output layer OL, and an intermediate layer H Each L has one or more neurons (units). It may be a single layer or two or more layers. The network can also be called a DNN (deep neural network), and Learning using neural networks can also be called deep learning.

[0161] Input data is input to each neuron in the input layer IL, and previous data is input to each neuron in the hidden layer HL. The output signal of the neurons in the layer OL or the subsequent layer is input, and each neuron in the output layer OL receives the signal of the neurons in the previous layer. The output signal of each neuron is input. Each neuron is connected to all the neurons in the previous and next layers. It may be connected to all neurons (fully connected) or to a portion of neurons.

[0162] Figure 11(B) shows an example of a neuron operation. Here, we consider a neuron N and a neuron B. The figure shows two neurons in the front layer that output signals to neuron N. Neuron N has a The output x1 of the neuron in the previous layer and the output x2 of the neuron in the previous layer are input. In Ron N, the multiplication result of output x1 and weight w1 (x1w1) and the multiplication result of output x2 and weight w2 After the sum of the calculation results (x2w2) x1w1+x2w2 is calculated, the bias b is applied as needed. are added to obtain the value a=x1w1+x2w2+b. The value a is then applied to the activation function h Thus, the neuron N outputs the output signal y=h(a).

[0163] In this way, the operation of a neuron involves adding the product of the output of the previous layer neuron and the weight. This multiplication and addition operation is called multiplication and addition (x1w1+x2w2 above). This may be done on software using a program, or on hardware. When the multiply-and-accumulate operation is performed by hardware, a multiply-and-accumulate circuit can be used. This product-sum operation circuit may be a digital circuit or an analog circuit. Good too.

[0164] The sum-of-products operation circuit may be configured using Si transistors or OS transistors. In particular, since the off-state current of an OS transistor is extremely small, it is possible to It is suitable as a transistor for composing an analog memory of a circuit. A product-sum circuit may be configured using both an OS transistor and an OS transistor.

[0165] The correction data can be generated not only by the circuit 15 but also by the circuit 120 described above ( (See Figure 10(B)). Also, a grayscale display is performed on the display unit, and the brightness of the display is adjusted. Correction data is generated based on the data read by the thermometer or the data read from the photograph of the display. Also, a sensor 24 that can detect the brightness of the display may be provided to detect the deterioration of the display element. A circuit 25 capable of generating correction data may be provided (see FIG. 10(C)).

[0166] Next, a configuration in which the circuit block shown in FIG. 4(A) is applied to the pixel array shown in FIG. 8 (see FIG. 12) will be described. The simulation results for the above (reference) are explained below. The parameters are as follows: The size is L / W=6μm / 6μm (transistor 111), L / W=4μm / 4μm (other other transistors), the capacitance of the capacitor 104 is 150 fF, the capacitance of the capacitor 113 is 5 0fF, the light emitting element 114 is an FN diode model, and the wiring 128 is an anode potential of +1 0V, +1V as "Vref", wire 129 is -5V as cathode potential, image data The minimum value of the correction data was +1V, and the maximum value was +8V. SPICE was used as the simulation software.

[0167] Figures 13(A) to 13(C) show the simulation results for verifying high resolution display (without correction). FIG. 13(A) is a timing chart used for the verification. By turning on the transistor 103 at times T1 and T2, the image The image data “Vs” (s[n]) is written. At this time, the wiring 128 is connected to the anode electrode 126. This will be ranked 1st.

[0168] FIG. 13(B) shows the image data “V S The current (I LED )of This is the result of the simulation. Figure 13(B) shows the simulation for one pixel. As a result, it was confirmed that any pixel (pix1 to pix4) can display gradation. It is being done.

[0169] FIG. 13C shows the potential "V" of the node NM relative to the image data "Vs". NM " Change The simulation results show that the potential of the node NM is V NM " is a picture It has been confirmed that it is proportional to the image data "Vs".

[0170] That is, it is possible to display the high resolution image data "Vs" supplied from the wiring 123. Confirmed.

[0171] 14(A) to 14(D) show the simulation results for verifying low-resolution display (without correction). Figure 14 (A) and (B) are timing charts used for the verification. The potential of the line 123 is set to the minimum value (+1V) at all times T1 to T4 in FIG. 14(A). At this time, the wiring 128 is set to the potential "V Since the potential is set to ref″ (+1 V), the differential potential held in the capacitor 104 is 0. That is, no correction is made.

[0172] After that, at times T1 and T2 shown in FIG. 14B, the transistor 101 is turned on. By this, the image data “Vs” (s[m]) is written from the wiring 123.

[0173] FIG. 14C shows the current (I LED )of The simulation results are shown in Fig. 14(C). Although this is a test result, it was confirmed that any pixel (pix1 to pix4) can display gradation. It has been done.

[0174] FIG. 14D shows the potential "V" of the node NM relative to the image data "Vs". NM " Change The simulation results show that the potential of the node NM is V NM " is a picture It has been confirmed that it is proportional to the image data "Vs".

[0175] That is, it is possible to display the low-resolution image data "Vs" supplied from the wiring 123. Confirmed.

[0176] 15(A) to 15(D) show the simulation results for verifying low-resolution display (with correction). Figure 15(A) and (B) are timing charts used for the verification. The desired correction data "Vp" is supplied to the line 123, and the time from T1 to T2 in FIG. The correction data “Vp” (p[n]) is written at time T3 to T4. At this time, the wiring 128 is set to the potential “Vre f” (+1V), the differential potential held in the capacitance element 104 is “Vp-1”. be.

[0177] After that, at times T1 and T2 shown in FIG. 15B, the transistor 101 is turned on. By this, the image data "Vs" is written from the wiring 123, and the correction data is added to the image data. At this time, the wiring 128 is set to an anode potential.

[0178] FIG. 15C shows the current (I LED )of This is the result of a simulation for each correction data. The correction data "Vp" is set to 1V to 8V. In either case, gradation can be displayed by writing V and combining it with image data "Vs". It has been confirmed that:

[0179] FIG. 15D shows the potential "V" of the node NM relative to the image data "Vs". NM " Change This is the result of simulating the correction data "Vp" for each correction data "Vp". In either case, 1V to 8V is written and combined with the image data "Vs". The potential of the node NM, “V NM It has been confirmed that there is a proportional trend.

[0180] That is, the correction data "Vp" and the low-resolution image data " It was confirmed that Vs" could be combined to produce an effective display.

[0181] FIG. 16 shows an example in which a pixel according to one embodiment of the present invention is applied to an EL display device capable of color display. This is an example. Generally, the pixels of a display device that can display color are R (red), G (green), and B (blue). ) and the sub-pixels emitting the respective colors. Three sub-pixels of each color, the pixel 10R, the sub-pixel 10G, and the sub-pixel 10B, constitute one pixel. These represent four pixels in the horizontal and vertical directions. a and transistor 102b are represented by one block.

[0182] As described above, in one embodiment of the present invention, the transistors 101 are arranged in a matrix. The four pixels (corresponding to four sub-pixels emitting the same color in this case) are given correction data "Vp1" or Image data "VsL" can be input. A potential is applied to two pixels (corresponding to two sub-pixels emitting the same color) arranged in the horizontal direction via "Vref" can be supplied.

[0183] In the stripe arrangement, it is preferable that the sub-pixels are arranged at equal intervals. When wiring or transistors are shared among elements, the spacing between each sub-pixel (elements with the same function) It may be difficult to keep the interval constant.

[0184] Therefore, the pixel electrodes connected to the subpixels 10R, 10G, and 10B are , electrodes 26R, 26G, and 26B, as shown in FIG. It is preferable to arrange the pixel electrodes 6B at equal intervals. Although it can be said that it is a separate element here for clarity of explanation, this configuration is This is effective for a transmission type EL display device or a reflection type liquid crystal display device.

[0185] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0186] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using a light-emitting element will be described. In this embodiment, the display described in the first embodiment is Description of the elements, operations and functions of the device will be omitted.

[0187] 17A to 17C show the structure of a display device to which one embodiment of the present invention can be applied. Figure.

[0188] In FIG. 17A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display portion 215 is attached to the sealant 4005 and the second substrate 4. Sealed by 006.

[0189] The display portion 215 can be provided with the pixel shown in FIG. 1 of Embodiment 1. The scanning line driving circuit described in corresponds to a row driver, and the signal line driving circuit corresponds to a column driver. .

[0190] In FIG. 17A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline The signal line driving circuit 231a and the signal line driving circuit 232a are formed of semiconductors. The scanning line driving circuit 221a has the function of the column driver shown in the first embodiment. The common line driver circuit 241a has the function of the row driver shown in the first embodiment. It has the function of supplying a specified potential to the wiring that supplies the power supply and Vref shown in the figure. do.

[0191] The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal Various signals and potentials are applied to the signal line driver circuit 232a via a flexible printed circuit (FPC). The power supply is supplied via a 4018 printed circuit.

[0192] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 included in the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. It is implemented in a different area from the area where it is installed.

[0193] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0194] FIG. 17B shows an integrated circuit included in the signal line driver circuit 231a and the signal line driver circuit 232a. The circuit 4042 is implemented by the COG method. The display unit 215 and the display unit 216 can be integrally formed on the same substrate to form a system-on-panel. Cut.

[0195] In FIG. 17B, the scanning line driving circuit 221a and the common line driving circuit 241a are connected to the display unit 2. 15. The driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts at the same time, the number of parts can be reduced, which increases productivity. can.

[0196] In FIG. 17B, the display portion 215 provided on the first substrate 4001 and the scanning line driver A sealant 4005 is provided to surround the common line driving circuit 221a and the common line driving circuit 241a. In addition, a display unit 215, a scanning line driving circuit 221a, and a common line driving circuit The second substrate 4006 is provided on the display unit 215, the scanning line driver 241a. The driving circuit 221a and the common line driving circuit 241a are mounted on the first substrate 4001 and the sealing material 40. The display element is sealed by the second substrate 4005 and the second substrate 4006 .

[0197] In addition, in FIG. 17B, the signal line driver circuit 231a and the signal line driver circuit 232a are separately 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or the scanning line driver circuit. A part of the driving circuit may be formed separately and mounted. The signal line driving circuit 231a and the signal line driving circuit 232a are formed on the same substrate as the display unit 215. That's fine.

[0198] The display device also includes a panel in which a display element is sealed, and a controller for the panel. This may also include a module in which an IC or the like including the above is mounted.

[0199] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistors in the peripheral driver circuits and the transistors in the pixel circuits of the display unit The structures of the transistors in the peripheral driver circuits may be the same or different. The transistors may all have the same structure, or may have two or more types of transistor structures. Similarly, the transistors in the pixel circuit may all have the same structure. The semiconductor device may have two or more types of transistor structures.

[0200] An input device 4200 can be provided on the second substrate 4006. A display device provided with an input device 4200 can function as a touch panel. .

[0201] There is no limitation on the detection elements (also referred to as sensor elements) included in the touch panel of one embodiment of the present invention. We offer a variety of sensors that can detect the proximity or contact of a finger, stylus, or other object. , can be applied as a sensing element.

[0202] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or the like.

[0203] In this embodiment, a touch panel having a capacitance type detection element will be described as an example. .

[0204] The capacitance type includes a surface capacitance type, a projected capacitance type, etc. The capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0205] The touch panel of one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A detector element is formed on one or both of a substrate supporting a display element and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes or the like are provided.

[0206] 18(A) and (B) show examples of touch panels. FIG. 18(A) shows a touch panel 4 18(B) is a perspective view of the input device 4200. For clarity, only representative components are shown.

[0207] The touch panel 4210 is made by bonding a display device and a sensing element that are separately manufactured. be.

[0208] The touch panel 4210 has an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0209] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. and electrically connects to each of the plurality of wirings 4238. 3b can be provided.

[0210] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In this case, in addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also available. may be applied.

[0211] 19(A) and 19(B) show the structure of the region indicated by the chain line N1-N2 in FIG. 17(B). The display device shown in FIG. 19(A) and FIG. 19(B) has an electrode 4015. The electrode 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. 19(A) and 19(B), the electrode 4015 is Wiring is formed in openings formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110. It is electrically connected to 4014.

[0212] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The same conductive layer is used.

[0213] The display portion 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are 19(A) and 19(B), the display unit 215 The included transistor 4010 and the transistor included in the scanning line driver circuit 221a 19(A) and 19(B), the transistor 4 010 and a bottom-gate transistor is shown as an example of a transistor 4011. However, it may be a top-gate transistor.

[0214] In FIG. 19(A) and FIG. 19(B), the transistor 4010 and the transistor 401 19(B), an insulating layer 4112 is provided on the insulating layer 4112. A partition wall 4510 is formed.

[0215] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The electrode 4017 is formed on the semiconductor substrate 401. The electrode 4017 functions as a back gate electrode. It is possible.

[0216] 19A and 19B includes a capacitor 4020. The display device shown in FIG. The capacitor 4020 has an electrode 4 formed in the same process as the gate electrode of the transistor 4010. 021 and electrodes formed in the same process as the source electrode and drain electrode. The electrodes overlap with each other with an insulating layer 4103 interposed therebetween.

[0217] Generally, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set to be able to hold charge for a predetermined period, taking into consideration factors such as leakage current of the capacitor. The capacitance of the capacitor may be set in consideration of the off-state current of the transistor.

[0218] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. (A) is an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal display device, a liquid crystal element 4013 is a display element. 31, and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between alignment films. The second electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as a The first electrode layer 4030 and the second electrode layer 4031 are disposed on the second substrate 4006 side. Overlapping through layer 4008.

[0219] As the liquid crystal element 4013, liquid crystal elements to which various modes are applied can be used. For example, VA (Vertical Alignment) mode, TN (Twisted Nematic (IPS) mode, In-Plane-Switching (IPS) mode, A SM(Axially Symmetric aligned Micro-cell) Mode, OCB (Optically Compensated Bend) Mode, F LC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, EC B(Electrically Controlled Birefringence) Use of LCD elements that use mode, VA-IPS mode, guest host mode, etc. can be done.

[0220] In addition, the liquid crystal display device shown in this embodiment may be a normally black liquid crystal display device, for example. A transmissive liquid crystal display device employing a vertical alignment (VA) mode may also be used. The code is MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc. can.

[0221] The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of liquid crystals is due to the electric field (horizontal electric field, vertical electric field or The liquid crystal used in the liquid crystal element is thermoelectric. ropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC) Dispersed Liquid Crystal, Ferroelectric Liquid Crystal, Antiferroelectric Liquid Crystal These liquid crystal materials can exhibit a cholesteric phase, a smectic phase, etc. depending on the conditions. These phases include nematic, cubic, chiral nematic, and isotropic phases.

[0222] In FIG. 19A, an example of a liquid crystal display device having a vertical electric field type liquid crystal element is shown. One embodiment of the present invention can be applied to a liquid crystal display device having a lateral electric field liquid crystal element. When the field method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, it changes from the cholesteric phase to the equilibrium phase. This is the phase that appears just before the transition to the rhombohedral phase. The blue phase appears only in a narrow temperature range. In order to improve the temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is mixed. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of The liquid crystal composition includes a liquid crystal that exhibits a blue phase and a chiral agent. In this case, alignment treatment is not required and the viewing angle dependency is small. Rubbing is no longer necessary, preventing electrostatic damage caused by rubbing. This makes it possible to reduce defects or damage to the liquid crystal display device during the manufacturing process.

[0223] The spacers 4035 are columnar spacers obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0224] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, an anti-reflection member, etc. may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. A backlight, a sidelight, or the like may be used. Micro LEDs or the like may be used as the light.

[0225] In the display device shown in FIG. 19A, the following is provided between the second substrate 4006 and the second electrode layer 4031: A light-shielding layer 4132, a colored layer 4131, and an insulating layer 4133 are provided.

[0226] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film made of an inorganic material such as a metal. For example, a laminated film of a film containing a material of a colored layer may be used as the light-shielding layer. A film containing a material used for a color layer that transmits light of a certain color and a material used for a color layer that transmits light of another color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0227] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. The light-shielding layer and the colored layer may be formed by, for example, an ink-jet method. It can be formed using:

[0228] In addition, the display device shown in FIGS. 19(A) and 19(B) has an insulating layer 4111 and an insulating layer 41 The insulating layer 4111 and the insulating layer 4104 are insulating layers that are difficult for impurity elements to penetrate. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, It is possible to prevent impurities from entering from the outside.

[0229] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. An EL element can be applied. An EL element is a device that has a light-emitting compound between a pair of electrodes. The EL element has a layer (also referred to as an "EL layer") containing a voltage lower than the threshold voltage of the EL element between a pair of electrodes. When a large potential difference is generated, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the luminescent The compound emits light.

[0230] EL elements are also classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0231] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer, and then the carriers (electrons and holes) recombine. By this, the light-emitting organic compound is excited and returns to the ground state. Due to this mechanism, such a light-emitting element is called a current-excited light-emitting element. It is called a child.

[0232] In addition to the light-emitting compound, the EL layer may contain a material having a high hole injection property and a material having a high hole transport property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The layer may contain a highly functional substance (a substance having high electron-transporting and hole-transporting properties).

[0233] The EL layer can be formed by a variety of methods, including vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0234] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. It is a localized emission that uses

[0235] Furthermore, a micro LED using a compound semiconductor may be used as the light emitting element. Here, an organic EL element will be used as the light emitting element for explanation.

[0236] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. The transistor and the light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. Top emission structure, which emits light from the top surface, and bottom emission structure, which emits light from the surface of the substrate. (bottom emission) structure and double-sided emission (dual emission) structure There are light emitting elements with a light-emitting structure, and any light emitting element with an emission structure can be applied.

[0237] FIG. 19(B) shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513 is an example of a display element. The light-emitting element 4513 is electrically connected to the transistor 4010. The electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031 are laminated together. The light emitting element 4513 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4513. The configuration of 13 can be changed as appropriate.

[0238] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is It is preferable to form the inclined surface with a curvature.

[0239] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers stacked. Either way is fine.

[0240] The light emitting element 4513 emits light in a variety of colors, including white, red, green, and blue, depending on the material that makes up the light emitting layer 4511. , cyan, magenta, or yellow, etc.

[0241] To achieve color display, a white light-emitting element 4513 is combined with a colored layer. There are two methods: one is to combine the two and the other is to provide a light emitting element 4513 with a different luminescent color for each pixel. The first method has higher productivity than the latter method. However, the latter method is less productive than the former method because it requires separate production. In addition to the latter method, it is possible to obtain an emission color with higher color purity than the former method. By adding a microcavity structure to the element 4513, color purity can be further improved. can be done.

[0242] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. By using the child dots in the light-emitting layer, they can also function as a light-emitting material.

[0243] The quantum dot materials include colloidal quantum dot materials, alloy quantum dot materials, and A shell-type quantum dot material, a core-type quantum dot material, etc. can be used. Materials containing elements from groups 12 and 16, 13 and 15, or 14 and 16 are used. Alternatively, cadmium, selenium, zinc, sulfur, phosphorus, indium, tellurium, lead Quantum dot materials containing elements such as gallium, arsenic, and aluminum may also be used.

[0244] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be formed of silicon nitride. silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (laminating film) with high airtightness and low outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. I wish.

[0245] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or Ethylene vinyl acetate (EVA) can also be used. may contain a desiccant.

[0246] The sealing material 4005 is made of glass materials such as glass frit, or ordinary materials such as two-component mixed resin. Resin materials such as heat-curable resin, photo-curable resin, and thermosetting resin can be used. The sealing material 4005 may also contain a desiccant.

[0247] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0248] In addition, by using a microcavity structure for the light-emitting element, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves the visibility of the displayed image.

[0249] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0250] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, may be used. This can be done.

[0251] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or its alloy, or metal nitride thereof. .

[0252] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or Its derivatives are also included.

[0253] FIG. 20 shows an example of a light-emitting display device that uses light-emitting elements and colored layers to perform color display. The coloring layer 4131 is provided so as to overlap with the light-emitting element in the pixel. For example, it can be made of materials that transmit light such as R (red), G (green), and B (blue), and emits light. A white light-emitting element can be used for the optical element 4513. In this case, the pixel corresponds to the colored layer 4131. A layer that transmits white light is provided as a layer, or a layer corresponding to the colored layer 4131 is not provided. The configuration will be as follows.

[0254] The light-emitting element 4513 preferably has a structure in which a light-emitting layer contains two or more kinds of light-emitting substances. To obtain white light, two or more luminescent materials must be used, each of which emits a complementary color. Just select.

[0255] The light-emitting layer contains light-emitting materials that emit light in R (red), G (green), B (blue), Y (yellow), O (orange), etc. It is preferable that the light-emitting element contains two or more luminescent materials. Alternatively, the light-emitting element contains two or more luminescent materials, and each luminescent material The emitted light preferably contains spectral components of two or more of the colors R, G and B.

[0256] Furthermore, the spectrum of light emitted from the light emitting element is in the visible light region (for example, 350 nm to 7 It is preferable to use a light emitting device having two or more peaks within the range of 50 nm. , the emission spectrum of the material with a peak in the yellow wavelength region is green and / or red Preferably, the material has spectral components in the wavelength region as well.

[0257] Specifically, as shown in the cross-sectional structure diagram of the light-emitting element 4513 in FIG. 21(A), 511 is a light-emitting layer 4610 having a light-emitting material that emits blue light, and a light-emitting layer 4611 having a light-emitting material that emits yellow light, which is the complementary color of blue. The light-emitting layer 4620 having a light-emitting material exhibiting the above property can be connected in series to form a two-layer tandem structure. Cut.

[0258] Alternatively, as shown in FIG. 21(B), a three-layer substrate may be used in which a light-emitting layer 4620 is sandwiched between light-emitting layers 4610. A tandem structure may also be used.

[0259] 21(C), the light-emitting layer 4620 is formed by the light-emitting layer 4630 and the light-emitting layer 46 The light-emitting layer 4630 and the light-emitting layer 4640 may have different emission colors. a layer having a light-emitting material that emits yellow light, a layer having a light-emitting material that emits red light, and a layer having a light-emitting material that emits green light. Any layer having a light-emitting material that emits light can be used.

[0260] In addition, the light-emitting layer 4620 is divided into a light-emitting layer 4630 and a light-emitting layer 4640 as shown in FIG. The light-emitting layer 4630, the light-emitting layer 4640, and the light-emitting layer 4650 may be formed. The light-emitting layer 4650 emits light of different colors, and the light-emitting layer 4650 has a layer containing a light-emitting material that emits yellow light, and the light-emitting layer 4650 has a layer containing a light-emitting material that emits red light. a layer having a light-emitting material that emits green light, or a layer having a light-emitting material that emits green light; It can be used.

[0261] The color gamut can be expanded by adding red and / or green emitting layers to the yellow emitting layer. 21(A) to 21(D), the display quality can be improved. For clarity, only the electrode layer and the light-emitting layer are shown as examples. a layer containing a substance with high hole transport properties (hole injection layer), a layer containing a substance with high hole transport properties (hole transport layer), a layer containing a material with high electron injection properties (electron injection layer); An intermediate electrode layer or the like may be provided to connect the layers.

[0262] FIG. 22(A) shows one of a plurality of light-emitting layers that can be used for the light-emitting layer 4511. 22(A) is a schematic diagram showing a cross section of a light-emitting layer. The host material 4711 is composed of a single organic compound. It may be possible to co-produce organic compounds 4711_1 and 4711_2. It may be composed of the st system.

[0263] In addition, a light-emitting organic material may be used as the guest material 4712. The materials include materials that can emit fluorescence (hereinafter referred to as fluorescent materials) and materials that can emit phosphorescence. In the following description, examples of the material include a material that can emit light (hereinafter also referred to as a phosphorescent material). In this example, a phosphorescent material is used as the guest material 4712. The phosphorescent material 4712 may be read as a phosphorescent material.

[0264] Generally, two types of organic compounds, such as organic compound 4711_1 and organic compound 4711_2, are used in the light-emitting layer. In the case of using a host material (co-host system), the electron transporting material and the hole transporting material are This structure is useful for hole injection between the hole transport layer and the light emitting layer. The barrier between the electron transport layer and the light-emitting layer is reduced, thereby reducing the driving voltage. This is a preferable configuration because it is possible to

[0265] Next, the light emitting mechanism of the light emitting layer shown in FIG. 22(A) will be described.

[0266] Organic compound 4711_1 and organic compound 4 contained in host material 4711 in the light-emitting layer 711_2 is an exciplex (exciplex, exciplex or exciple x) can be formed. Hereinafter, organic compound 4711_1 and organic compound The case where 4711_2 forms an exciplex will be described.

[0267] Organic compound 4711_1, organic compound 4711_2, and guest material 47 in the light-emitting layer The correlation of the energy levels with 12 is shown in FIG. 22(B). The symbols are as follows. In the following, the organic compound 4711_1 is used as an electron transporting The organic compound 4711_2 will be described as a hole transporting material. ·Host(4711_1): Organic compound 4711_1 (host material) ·Host(4711_2): Organic compound 4711_2 (host material) Guest (4712): Guest material 4712 (phosphorescent compound) ·S PH1 : S1 level of organic compound 4711_1 (host material) T PH1 :T1 level of organic compound 4711_1 (host material) ·S PH2 : S1 level of organic compound 4711_2 (host material) T PH2 :T1 level of organic compound 4711_2 (host material) ·S PG : S1 level of guest material 4712 (phosphorescent compound) T PG : T1 level of guest material 4712 (phosphorescent compound) ·S PE : S1 level of the exciplex T PE :T1 level of exciplex

[0268] The organic compound 4711_1 and the organic compound 4711_2 form an exciplex, and the S1 level (S PE ) and T1 level (T PE ) are adjacent energies (Figure 22( B) See Route E1).

[0269] Organic compound 4711_1 receives an electron, and organic compound 4711_2 receives a hole. Alternatively, when one of them is excited, the other quickly becomes excited. The excited energy level of the exciplex (S PE Also is T PE ) is a host material (organic compound 4711_1 and organic compound 4711_2) that forms an exciplex. 4711_2) S1 level (S PH1 and S PH2 ) lower, resulting in lower excitation This allows the formation of excited states in the host material 4711. The driving voltage of the light-emitting element can be reduced. The organic compound 4711_2 may receive an electron to form an exciplex.

[0270] And the (S PE ) and (T PE) and the energy of the guest material 4712 (phosphorescent compound) to the T1 level to obtain light emission (Figure 22(B) Route E2 , see E3).

[0271] In addition, the T1 level of the exciplex (T PE ) is the T1 level (T PG )twist By doing so, the singlet excitation energy and and triplet excitation energy to the S1 level (S PE ) and T1 level (T PE )mosquito The T1 level (T PG ) can transfer energy to

[0272] In addition, in order to efficiently transfer excitation energy from the exciplex to the guest material 4712, , the T1 level of the exciplex (T PE ) are each organic compound that forms an exciplex (organic compound 47 T1 levels (T PH1 and T PH2 ) It is preferable that the value is smaller than or equal to 1.0. This allows each organic compound (organic compound 4711_1 and and the triplet excitation energy of the exciplex is quenched by organic compounds (4711_2). This makes it difficult to transfer energy from the exciplex to the guest material 4712 efficiently.

[0273] The process of routes E2 and E3 shown above is based on ExTET (Exciplex-Trip It can be called ExTET (Express Energy Transfer). By using this, a light emitting element with good luminous efficiency, reduced driving voltage, and good reliability can be obtained. It is possible.

[0274] As mentioned above, a tandem structure with two or more light-emitting layers is effective for white light emission. The tandem structure reduces the current stress per element, thereby extending the element life. It can also be extended.

[0275] On the other hand, for example, the equivalent circuit of a three-layer tandem light emitting element incorporated into a pixel circuit is shown in Figure 23 ( As shown in A), three diodes are connected in series.

[0276] Figure 23(B) shows the IV characteristics that explain the voltage drop in the forward direction of a light-emitting element (diode). When the forward voltage of a certain light-emitting element (diode) is "Vf", the same light-emitting element When three light emitting elements (diodes) are connected in series, current begins to flow through the three light emitting elements (diodes). The voltage that can be applied is "3Vf" or higher.

[0277] A tandem structure, which can emit light from multiple layers, requires less current to emit the same amount of light as a single structure. High strength can be achieved, but high voltage is required.

[0278] Therefore, it is necessary to increase the voltage supplied to the light-emitting element. Low power consumption is achieved by adding the voltages output by the drivers in the circuit to generate a relatively high voltage. In addition, it is possible to eliminate the need for a high-voltage output driver, and a general-purpose driver can be used. Alternatively, a high-voltage output driver IC can be used. It is also possible to operate a display element.

[0279] In addition, transistors included in the driver circuits of display devices are easily damaged by static electricity, etc. It is preferable to provide a protection circuit. The protection circuit is preferably configured using a non-linear element. I wish.

[0280] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0281] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0282] The display device of one embodiment of the present invention includes a bottom-gate transistor and a top-gate transistor. The present invention can be fabricated using various types of transistors, such as a transistor having a MOSFET. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0283] [Bottom-gate transistor] FIG. 24(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 24(A1) is a cross-sectional view of the transistor 810 in the channel length direction. The transistor 810 is formed on the substrate 771. The electrode 746 is provided with an insulating layer 772 interposed therebetween. The semiconductor layer 742 is provided. The electrode 746 can function as a gate electrode. The insulating layer 726 is provided as a gate electrode. It can function as a gate insulating layer.

[0284] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. Electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the insulating layer 726. 744a can function as either a source or drain electrode. It can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0285] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor with good electrical characteristics can be realized.

[0286] The transistor 810 includes an electrode 744a, an electrode 744b, and an insulating layer 741. The insulating layer 729 is disposed on the insulating layer 728 .

[0287] When an oxide semiconductor is used for the semiconductor layer 742, at least one of the electrodes 744a and 744b At least in the area in contact with the semiconductor layer 742, oxygen is taken from a part of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material that can generate oxygen vacancies in the semiconductor layer 742. The carrier concentration in the resulting region increases, and the region becomes n-type. + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen vacancies are eliminated. Examples of materials that can be used include tungsten and titanium. do.

[0288] The source and drain regions are formed in the semiconductor layer 742, forming an electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0289] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, as an n-type semiconductor or a p-type semiconductor. It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0290] The insulating layer 729 has a function of preventing or reducing diffusion of impurities into the transistor from the outside. It is preferable to form the insulating layer 729 using a material having the above structure. You can also do this.

[0291] The transistor 811 shown in FIG. 24A2 has a back gate electrode over the insulating layer 729. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. The electrode 723 is an electrode It can be formed using the same materials and methods as 746.

[0292] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can be made to function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled. The voltage can be varied to any desired value.

[0293] Both the electrode 746 and the electrode 723 can function as gate electrodes. The insulating layer 726, the insulating layer 728, and the insulating layer 729 each serve as a gate insulating layer. The electrode 723 can function as a gate electrode. That's fine.

[0294] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as a "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0295] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, the electrode 74 6 and the electrode 723 are set to the same potential, the region where carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility also increases.

[0296] Therefore, the transistor 811 is a transistor having a large on-state current relative to its area. That is, the area occupied by the transistor 811 is set to According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0297] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity The back gate electrode has an electric field shielding function against the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0298] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This prevents light from entering the semiconductor layer from the side. This can prevent degradation of electrical characteristics such as a shift in the threshold voltage of the transistor. .

[0299] According to one embodiment of the present invention, a highly reliable transistor can be provided. A highly reliable semiconductor device can be realized.

[0300] FIG. 24(B1) shows a channel protection type transistor 82 having a different configuration from that shown in FIG. 24(A1). 8 is a cross-sectional view of the transistor 820 in the channel length direction. It has a similar structure, but differs in that an insulating layer 741 covers the edge of a semiconductor layer 742. In addition, an opening formed by selectively removing a part of the insulating layer 741 that overlaps the semiconductor layer 742 In this portion, the semiconductor layer 742 and the electrode 744a are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 42, The insulating layer 741 is electrically connected to the electrode 744b. The overlapping region can function as a channel protection layer.

[0301] The transistor 821 shown in FIG. 24B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0302] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when forming the electrode 744a and the electrode 744b, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0303] Also, the transistors 820 and 821 are the same as the transistors 810 and 821. The distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are smaller than the distance between the electrode 744a and the electrode 746 and the electrode 744b. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 is In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0304] Figure 24(C1) shows a channel-etched type, which is one of the bottom-gate type transistors. 1 is a cross-sectional view of a transistor 825 in the channel length direction. Electrodes 744a and 744b are formed without using 41. In addition, a part of the semiconductor layer 742 that is exposed during the formation of the electrode 744b may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be increased.

[0305] The transistor 826 shown in FIG. 24C2 has an insulating layer 729 over which a back gate electrode is formed. It differs from transistor 825 in that it has a functioning electrode 723 .

[0306] 25(A1) to (C2) show transistors 810, 811, 820, 821, 825, 826 are cross-sectional views in the channel width direction.

[0307] In the structures shown in FIGS. 25(B2) and (C2), the gate electrode and the back gate electrode are connected. The gate electrode and the back gate electrode have the same potential. The gate electrode is sandwiched between the gate electrode and the back gate electrode.

[0308] The length of each of the gate electrode and the back gate electrode in the channel width direction is 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is 726, 741, 728, and 729 are sandwiched between the gate electrode or the back gate electrode. It is a structure that

[0309] With this structure, the semiconductor layer 742 included in the transistor can be used as a gate electrode and a barrier layer. The gate electrode can be electrically surrounded by the electric field of the gate electrode.

[0310] Like the transistor 821 or the transistor 826, the gate electrode and the back gate The electric field of the electrode electrically surrounds the semiconductor layer 742 in which the channel formation region is to be formed. The device structure of the transistor is called the Surrounded channel (S-channel el) structure.

[0311] By using an S-channel structure, either one of the gate electrode and the back gate electrode By both, an electric field is effectively applied to the semiconductor layer 742 to induce a channel. This improves the current driving capability of the transistor and makes it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, it is possible to miniaturize transistors. In addition, the S-channel structure allows for mechanical Strength can be increased.

[0312] [Top-gate transistor] The transistor 842 illustrated in FIG. 26A1 is a top-gate transistor. The electrode 744a and the electrode 744b are formed on the insulating layer 728 and the insulating layer 729. The insulating film 742 is electrically connected to the semiconductor layer 742 in the opening.

[0313] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer 726 as a mask to introduce impurities into the semiconductor layer 742. It is possible to form an impurity region in a self-aligned manner. The sintered body 842 has an area where the insulating layer 726 extends beyond the edge of the electrode 746. The impurity concentration in the region of the layer 742 into which the impurity is introduced through the insulating layer 726 is The semiconductor layer 742 is connected to the electrode 746 and is smaller than the region where the impurity is introduced without the electrode 746. LDD (Lightly Doped Drain) regions are formed in the non-overlapping regions .

[0314] The transistor 843 shown in FIG. 26A2 has an electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. can function as a back gate electrode.

[0315] In addition, the transistor 844 shown in FIG. 26(B1) and the transistor shown in FIG. 26(B2) As in the case of the electrode 845, the insulating layer 726 in the area that does not overlap with the electrode 746 may be entirely removed. In addition, the transistor 846 shown in FIG. 26(C1) and the transistor shown in FIG. 26(C2) The insulating layer 726 may remain, as may the insulating layer 847.

[0316] The transistors 842 to 847 are also formed with the electrode 746. By introducing impurities into the semiconductor layer 742 using the mask, According to one aspect of the present invention, the impurity region can be formed in a self-aligned manner. Furthermore, according to one embodiment of the present invention, a high degree of integration can be achieved. Therefore, a semiconductor device with a high resistance can be realized.

[0317] Transistors 842, 843, 844, 845, and 846 are shown in FIGS. 847 are cross-sectional views in the channel width direction.

[0318] The transistors 843, 845, and 847 are respectively However, the present invention is not limited to this, and the transistor 84 may have an S-channel structure. 3. Transistor 845 and transistor 847 should not be of S-channel structure. That's fine.

[0319] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0320] (Fourth embodiment) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 28.

[0321] FIG. 28(A) shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed. The following display can be performed.

[0322] FIG. 28(B) shows a digital signage having a large display unit 922. The display device of one embodiment of the present invention is used for the display portion 922. , various images can be displayed.

[0323] FIG. 28C shows a mobile phone, which includes a housing 951, a display unit 952, an operation button 953, and an external The mobile phone has a connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The telephone has a touch sensor on the display 952. All operations such as the above can be performed by touching the display unit 952 with a finger or a stylus. The housing 951 and the display unit 952 are flexible and can be folded as shown in the figure. By using the display device of one embodiment of the present invention for the display portion 952, various It is possible to display a clear image.

[0324] FIG. 28D shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera, and the like. The display unit 912 has a touch panel function for inputting and outputting information. By using the display device of one embodiment of the present invention for the display portion 912, various images can be displayed. The following display can be performed.

[0325] FIG. 28(E) shows a television, which includes a housing 971, a display unit 973, operation keys 974, and a speaker 975. The display unit 973 has a touch sensor 975, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973. By using this, various images can be displayed.

[0326] FIG. 28(F) shows an information processing terminal, which includes a housing 901, a display unit 902, a display unit 903, a sensor The display unit 902 and the display unit 903 are each made up of a single display panel, and are flexible. The housing 901 is also flexible and can be folded as shown in the figure. It can also be used in a flat form like a tablet device. 4 can sense the shape of the housing 901, for example, when the housing 901 is bent, The display on the display unit 902 and the display unit 903 can be switched. By using the display device of one embodiment of the present invention for the display portion 903, various images can be displayed. can.

[0327] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible. [Explanation of symbols]

[0328] 10 pixels 10B subpixel 10G subpixel 10R subpixel 11 pixels 12 pixel array 13 Low Driver 14 Column Driver 15 circuits 16 Selection circuit 20 Shift Register 21 Buffer circuit 22 Shift Register 23 Buffer circuit 24 sensors 25 circuits 26B electrode 26G electrode 26R electrode 50fF capacitance value 101 Transistor 102 transistor 102a transistor 102b transistor 103 Transistor 104 Capacitive element 110 Circuit Block 111 Transistor 112 transistors 113 Capacitor element 114 Light-emitting element 115 transistors 116 Capacitor element 117 Liquid crystal element 118 transistors 119 Transistor 120 circuits 121 Wiring 122 Wiring 123 Wiring 127 Wiring 128 Wiring 129 Wiring 130 Wiring 131 Wiring 132 Wiring 133 Wiring 134 Wiring 215 Display section 221a Scanning line driving circuit 231a Signal line driver circuit 232a Signal line driver circuit 241a Common line driver circuit 723 Electrode 726 Insulation Layer 728 Insulation Layer 729 Insulation Layer 741 Insulation Layer 742 Semiconductor layer 744a electrode 744b electrode 746 Electrode 771 Circuit Board 772 Insulation Layer 810 Transistor 811 Transistor 820 transistors 821 Transistor 825 transistors 826 Transistor 842 transistors 843 Transistor 844 transistors 845 transistors 846 transistors 847 Transistor 901 Case 902 Display section 903 Display section 904 Sensors 911 chassis 912 Display section 913 Speaker 919 Camera 921 Pillar 922 Display section 951 Case 952 Display section 953 Operation Button 954 External connection port 955 Speaker 956 Mike 957 Camera 961 Case 962 Shutter button 963 Mike 965 Display section 966 Operation Key 967 Speaker 968 Zoom Lever 969 Lens 971 Case 973 Display section 974 Operation Key 975 Speaker 976 Communication connection terminal 977 Optical Sensor 4001 board 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4014 Wiring 4015 Electrode 4017 Electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Capacitor 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4041 Printed Circuit Board 4042 Integrated Circuits 4102 Insulation layer 4103 Insulation layer 4104 Insulation layer 4110 Insulation layer 4111 Insulation layer 4112 Insulation layer 4131 Colored layer 4132 Light blocking layer 4133 Insulation layer 4200 input device 4210 Touch Panel 4227 Electrode 4228 Electrode 4237 Wiring 4238 Wiring 4239 Wiring 4263 Circuit Board 4272b FPC 4273b IC 4510 Bulkhead 4511 Light-emitting layer 4513 Light-emitting element 4514 Filling material 4610 Light-emitting layer 4620 Light-emitting layer 4630 Light-emitting layer 4640 Light-emitting layer 4650 luminescent layer 4711 Host material 4711_1 Organic compounds 4711_2 Organic compounds 4712 Guest Materials

Claims

[Claim 1] A display device having pixels each provided with a light-emitting element, the light-emitting element has a tandem structure in which two or more light-emitting layers are connected in series, The pixel has a function of storing a first signal; the pixel has a function of generating a third signal by adding the first signal to a second signal; The light-emitting element is a display device having a function of emitting light based on the third signal.

Images