Display device

Abstract

To provide a thin film transistor which has excellent electrical characteristics and high reliability, and a display device using the thin film transistor as a switching element.SOLUTION: In a channel protected thin film transistor in which an oxide semiconductor is used for a channel formation region, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region composed of nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphous and microcrystals in which an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an N-type caused by re-entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented, and a contact resistance with source and drain electrodes can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and a display device and electronic equipment using the same. [Background technology]

[0002] In recent years, semiconductor thin films (thicknesses ranging from several nm to several hundred nm) formed on substrates with insulating surfaces have become popular. The technology of constructing thin film transistors (TFTs) using a thin film transistor (TFT) is attracting attention. Transistors are widely used in electronic devices such as ICs and electro-optical devices, especially in image display devices. Development of metal oxides as switching elements is being rushed. Indium oxide is a well-known material used in LCD displays and other displays. It is used as a necessary transparent electrode material.

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using metal oxides with such semiconducting properties as the channel formation region are already known. (Patent Document 1 and Patent Document 2).

[0004] Furthermore, TFTs using oxide semiconductors have high field-effect mobility. It is also possible to configure a driving circuit for a display device or the like using the above. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] When forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit are formed on the same substrate. In this case, the thin film transistor used in the pixel portion has excellent switching characteristics, e.g. For example, a large on-off ratio is required, and the thin film transistors used in the drive circuits have to have high operating speeds. In particular, the higher the resolution of the display device, the faster the display image Since the image writing time is shortened, the thin film transistors used in the driver circuit have a high operating speed. It is preferable to do so.

[0007] One embodiment of the present invention is a thin film transistor having favorable electrical characteristics and high reliability, and a method for manufacturing the thin film transistor. It is an object of the present invention to provide a display device using a transistor as a switching element. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment of the present invention includes a gate electrode layer over a substrate, a gate insulating film over the gate electrode layer, and a gate insulating film over the gate electrode layer. a gate insulating layer; an oxide semiconductor layer over the gate insulating layer; and an oxide insulating layer in contact with a part of the oxide semiconductor layer. and a source electrode layer and a drain electrode layer in contact with a part of the oxide semiconductor layer, In the semiconductor layer, the region between the source electrode layer and the oxide insulating layer and the region between the drain electrode layer and the oxide insulating layer are The region between the insulating layers includes a region overlapping with the source electrode layer, a region overlapping with the oxide insulating layer, and The insulating film has a thickness thinner than that of a region overlapping with the drain electrode layer.

[0009] The oxide semiconductor layer has a crystalline region in a surface portion thereof in contact with the oxide insulating layer. do.

[0010] In the above structure, a gate electrode layer, a source electrode layer, and a drain electrode layer included in the semiconductor device The layers are aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, A film mainly composed of a metal element selected from zinc and scandium, or an alloy film thereof The source electrode layer and the drain electrode layer are formed of a laminated film containing the above-mentioned elements. The layer is not limited to a single layer containing the above, and a laminate of two or more layers can be used.

[0011] In addition, indium oxide, indium oxide tin oxide alloy, indium oxide zinc oxide alloy, acid zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, etc. A light-transmitting oxide conductive layer is used for the source electrode layer, the drain electrode layer, and the gate electrode layer. This improves the light transmittance of the pixel portion, and also increases the aperture ratio.

[0012] In addition, the film containing the metal element as a main component constituting the source electrode layer and the drain electrode layer is oxidized. By forming the oxide conductive layer between each of the compound semiconductor layers, a high-performance semiconductor device with reduced contact resistance can be obtained. It is also possible to configure a semiconductor device capable of high-speed operation.

[0013] In the above structure, the semiconductor device includes an oxide semiconductor layer, and an oxide semiconductor layer is formed on the oxide semiconductor layer. The oxide insulating layer is in contact with a channel formation region of the oxide semiconductor layer. It acts as a protective layer.

[0014] In the above structure, the oxide insulating layer functioning as a channel protective layer of the semiconductor device is An inorganic insulating film formed by sputtering is used, typically a silicon oxide film or a silicon nitride oxide film. , an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0015] The oxide semiconductor layer is InMO3(ZnO) m (m>0 and m must be an integer. A thin film represented by (b) is formed, and the thin film is used as an oxide semiconductor layer. Here, M is a metal element selected from Ga, Fe, Ni, Mn, and Co. Or it can represent multiple metal elements. For example, M can be Ga, or Ga and Ni. Alternatively, the above metal elements other than Ga, such as Ga and Fe, may be contained. In semiconductors, in addition to the metal elements contained as M, Fe, Ni, etc. are also included as impurity elements. Other transition metal elements or oxides of the transition metals may be included. In the case of InMO3(ZnO) m (m>0 and m is not an integer) Among the oxide semiconductor layers, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O This is called an In-Ga-Zn-O oxide semiconductor, and its thin film is also called an In-Ga-Zn-O film.

[0016] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-O, I n-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga -Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al- Zn-O, In-O, Sn-O, or Zn-O metal oxides can be used. Furthermore, silicon oxide may be contained in the oxide semiconductor layer made of the metal oxide.

[0017] In addition, the oxide semiconductor layer is subjected to dehydration or dehydrogenation treatment at high temperature for a short time by RTA or the like. The surface of the oxide semiconductor layer is heated by a heating process such as RTA. It has a crystalline region made up of so-called nanocrystals with a size of 1 nm to 20 nm. The other parts are amorphous or a mixture of amorphous and microcrystalline with microcrystalline scattered in the amorphous regions. It becomes a mixture.

[0018] By using an oxide semiconductor layer having such a structure, it is possible to prevent re-penetration of moisture from the surface layer and oxidation. This prevents the deterioration of electrical characteristics due to the N-type structure caused by the desorption of electrons. The surface layer of the body layer is on the back channel side and has a crystalline region made up of nanocrystals. This can suppress the occurrence of parasitic channels.

[0019] In addition, when the oxide semiconductor layer is formed into an island shape after dehydration or dehydrogenation, crystals are formed on the side surfaces. The crystal region is not formed, and the crystal region is formed only in the surface layer excluding the side surface. The rate is small and does not interfere with the above effects.

[0020] In addition, a driver circuit portion and a pixel portion can be formed on the same substrate using a thin film transistor which is one embodiment of the present invention. Form it on a plate and create a display device using an EL element, a liquid crystal element, or an electrophoretic element. It is possible.

[0021] A display device according to one embodiment of the present invention includes a plurality of thin film transistors in a pixel portion. In the element area, the gate electrode of a thin film transistor and the source wiring of another thin film transistor Alternatively, the display device according to one embodiment of the present invention has a portion to which a drain wiring is connected. In the drive circuit of the device, the gate electrode of the thin film transistor and the The gate electrode has a portion for connecting a source wiring or a drain wiring.

[0022] In addition, thin film transistors are easily damaged by static electricity, so the gate line or source A protection circuit for protecting the thin film transistors in the pixel area can be provided on the same substrate as the line. The protection circuit is preferably configured using a nonlinear element using an oxide semiconductor layer. It's nice.

[0023] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate

[0024] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Effects of the Invention]

[0025] In a thin film transistor using an oxide semiconductor layer, a channel formation region of the oxide semiconductor layer By having a crystalline region on the surface of the region, it is possible to obtain excellent electrical characteristics and high reliability. A thin film transistor and a display device can be manufactured. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 3] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 4] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 5] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional process diagrams illustrating one embodiment of the present invention. [Figure 7] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 8] 1A and 1B are a circuit diagram and a timing chart of a signal line driver circuit; [Figure 9] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 10] 3A and 3B are a circuit diagram and a timing chart illustrating the operation of a shift register. [Figure 11] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 14] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 15] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 16] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 17] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 18] FIG. 1 is an external view showing an example of an electronic book. [Figure 19] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 20] FIG. 1 is an external view showing an example of a gaming machine. [Figure 21] FIG. 1 is an external view showing an example of a mobile phone. [Figure 22] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 23] 1A and 1B illustrate an example of a crystal structure of an oxide semiconductor. [Figure 24] A diagram explaining the overview of scientific computing. [Figure 25] A diagram explaining the overview of scientific computing. [Figure 26] A diagram explaining the results of scientific calculations. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to denote the same parts or parts having similar functions. A repeated explanation will be omitted.

[0028] (Embodiment 1) In this embodiment, a structure of a thin film transistor will be described with reference to FIG.

[0029] FIG. 1 shows a channel protective thin film transistor according to this embodiment.

[0030] The thin film transistor 470 shown in FIG. 1 includes a gate electrode layer 404 formed on a substrate 400 having an insulating surface. 21a, a gate insulating layer 402, an oxide semiconductor layer 423 including a channel formation region, a source electrode a pole layer 425a, a drain electrode layer 425b, and an oxide insulating layer acting as a channel protection layer. A layer 426a is provided.

[0031] The gate electrode layer 421a is made of aluminum, copper, molybdenum, titanium, chromium, tantalum, Metallic materials such as tungsten, neodymium, scandium, etc., or materials mainly composed of these metallic materials Single layer or multilayered structure using alloy materials containing these metal materials or nitrides containing these metal materials. Preferably, the electrode is made of a low resistance metal material such as aluminum or copper. Although it is effective, it is recommended to use it in combination with a high melting point metal material due to issues of heat resistance and corrosion. High melting point metal materials include molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. Dymium, scandium, etc. can be used.

[0032] In addition, in order to improve the aperture ratio of the pixel portion, an oxide film is formed on the gate electrode layer 421a. Indium oxide, indium tin oxide alloy, indium oxide zinc oxide alloy, zinc oxide, zinc oxide Light-transmitting materials such as lead aluminum, zinc aluminum oxynitride, or zinc gallium oxide An oxide conductive layer can also be used.

[0033] The gate insulating layer 402 is made of silicon oxide or silicon oxynitride formed by CVD or sputtering. Single layer films such as silicon nitride oxide, silicon nitride, aluminum oxide, and tantalum oxide Alternatively, a laminated film can be used.

[0034] The oxide semiconductor layer 423 is an In—Ga—Zn—O-based film containing In, Ga, and Zn. , InMO3(ZnO) m (m>0). M is gallium ( Selected from the group consisting of Ga, iron (Fe), nickel (Ni), manganese (Mn) and cobalt (Co). It indicates one or more metallic elements that are identified. For example, M can be Ga. In addition, the above metal elements other than Ga may be contained, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M in the oxide semiconductor, Some contain Fe, Ni or other transition metal elements, or oxides of these transition metals.

[0035] The oxide semiconductor layer 423 is formed by a sputtering method. The thickness is preferably 20 nm or more and 100 nm or less. The oxide semiconductor layer 423 is formed in the third region 4 between the source electrode layer 425a and the oxide insulating layer 426a. 24c and a fourth region 424d between the drain electrode layer 425b and the oxide insulating layer 426a. a first region 424a overlapping the source electrode layer 425a; a fifth region 424b overlapping the oxide insulating layer 426a; The thickness of the second region 424b is thinner than that of the region 424e and the second region 424b overlapping with the drain electrode layer 425b. It has.

[0036] The oxide semiconductor layer 423 is formed by a rapid thermal annealing (RTA) method or the like. Use materials that have been dehydrated or dehydrogenated at high temperatures for a short time. is a process in which high-temperature nitrogen or inert gas such as rare gas or light is used to heat the material to between 500℃ and 750℃ ( or a temperature below the strain point of the glass substrate) for 1 minute to 10 minutes, preferably 65 This can be done by RTA treatment at 0°C for 3 to 6 minutes. Since dehydration or dehydrogenation can be achieved in a short time, processing can be performed even at temperatures exceeding the distortion point of the glass substrate. It is possible.

[0037] The oxide semiconductor layer 423 is amorphous and has many dangling bonds when it is deposited. By carrying out the heating step of the dehydration or dehydrogenation treatment, dangling bonds that are close to each other are bonded. As the ordering progresses, the A mixture of amorphous and microcrystalline regions with microcrystalline regions scattered throughout, or a material formed entirely of amorphous material. Here, the particle size of the microcrystals is between 1 nm and 20 nm, so-called nanocrystals. These particles are smaller than the fine crystal particles commonly called microcrystals. do.

[0038] In addition, in the fifth region 424e of the oxide semiconductor layer 423 which overlaps with the oxide insulating layer 426a, The surface portion of the oxide semiconductor layer 423 becomes a crystalline region, and the c-axis is oriented in a direction perpendicular to the surface of the layer. Preferably, nanocrystals having a long axis in the c-axis direction and a short axis in the The axial direction is 1 nm or more and 20 nm or less.

[0039] By using an oxide semiconductor layer having such a structure, the surface layer of the channel formation region becomes nano-crystalline. The dense crystalline region made up of nanocrystals prevents moisture from re-entering from the surface. This prevents the deterioration of electrical characteristics due to the N-type structure caused by oxygen elimination. In the formation region, the surface layer of the oxide semiconductor layer is on the back channel side, and the prevention of N-type It is also effective in suppressing parasitic channels.

[0040] Here, the In-Ga-Zn-O based film grows easily depending on the metal oxide target used. The crystal structure is different. For example, the molar ratio is In2O3:Ga2O3:ZnO=1:1: In-Ga-Z was obtained using a metal oxide target containing In, Ga, and Zn. When an InO-based film is formed and crystallized through a heating process, Ga and Z are interposed between the In oxide layers. The hexagonal layered compound type crystal structure tends to be a mixture of one or two oxide layers containing n. At this time, the crystal structure of the crystalline region is the structure expressed by In2Ga2ZnO7 (Figure 23 In addition, when the oxide semiconductor layer is amorphous or contains a mixture of amorphous and microcrystalline, The molar ratio of the structure of the region where In:Ga:Zn is present tends to be In:Ga:Zn=1:1:0.5. A metal oxide target with a molar ratio of In2O3:Ga2O3:ZnO=1:1:1 was used. When the film is formed using the In-type SiO2 and crystallized through a heating process, the Ga and Zn-containing layers between the In oxide layers are The stable crystal structure is the latter, where the oxide layer containing Ga and Zn is two layers. The layer structure allows crystal growth to occur easily, and the molar ratio is In2O3:Ga2O3:ZnO When a film is formed using a target with a ratio of 1:1:1 and crystallized through a heating process, Crystals that extend from the interface to the gate insulating layer may be formed. This can also be called a numerical ratio.

[0041] In this embodiment, the source electrode layer 425a and the drain electrode layer 425b are formed by the first The three-layer structure is made up of a conductive layer, a second conductive layer, and a third conductive layer. For the gate electrode layer 421a, the same materials as those for the gate electrode layer 421a can be used as appropriate.

[0042] In addition, similarly to the gate electrode layer 421a, the above-described light-transmitting oxide conductive layer is used as the source electrode layer By using the insulating film 425a and the drain electrode layer 425b, the light transmittance of the pixel portion can be improved, and the aperture ratio can be increased. can also be made higher.

[0043] The above-mentioned metal material to be the source electrode layer 425a and the drain electrode layer 425b is used as a main component. The oxide conductive layer is formed between the film and the oxide semiconductor layer 423, and the contact resistance is reduced. It is also possible to reduce the resistance.

[0044] A channel protective layer is formed on the oxide semiconductor layer 423 and in contact with part of the oxide semiconductor layer 423. The oxide insulating layer 426a functions as an insulating film. An insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an oxide film. Aluminum nitride or the like is used.

[0045] 1, the oxide insulating layer 426a serving as a channel protective layer and the gate electrode layer A fifth region 424e of the oxide semiconductor layer overlapping with the gate insulating layer 402 therebetween forms a channel. The channel length L of the thin film transistor is the distance between the source electrode layer and the drain electrode layer. The channel of the channel-protected thin film transistor 470 is defined by the distance between the channel and the back electrode layer. The length L is equal to the width of the oxide insulating layer 426a in the direction parallel to the carrier flow direction. The channel length L of the thin film transistor 470 is determined by the thickness of the oxide semiconductor layer 423 and the oxide insulating layer 4 1, the oxide insulating layer 426a is It is shown as a trapezoid, and this is the length of the base of the trapezoid.

[0046] In addition, in a channel protection type thin film transistor, the channel length L of the channel formation region is To shorten the width, the width of the oxide insulating layer is narrowed, and the source electrode is formed on the narrow oxide insulating layer. When the source electrode layer and the drain electrode layer are provided, the source electrode layer and the drain electrode layer are formed on the oxide insulating layer. To solve this problem, the thin film transistor shown in Figure 1 has a width of The source electrode layer 425a and the drain electrode layer 425b are separated from the narrow oxide insulating layer 426a. The channel-protective thin film transistor 470 has a channel forming In order to shorten the channel length L of the region to, for example, 0.1 μm or more and 2 μm or less, the oxide insulating layer It is possible to realize a thin film transistor with a narrower width and a faster operating speed.

[0047] 2 and 3, the display including the channel-protected thin film transistor shown in FIG. An example of a manufacturing process of the device will be described. Note that FIG. 3 is a plan view of the display device, and FIG. 1 shows cross-sectional views taken along lines A1-A2 and B1-B2.

[0048] First, a substrate 400 is prepared. The substrate 400 is made of barium borosilicate glass, aluminoboron, Silica glass or aluminosilicate glass, produced by the fusion or float process In addition to the alkali-free glass substrates and ceramic substrates to be manufactured, A heat-resistant plastic substrate or the like can be used. A substrate having an insulating film provided on the surface of a metal substrate may also be used.

[0049] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, a crystallized glass substrate or the like may also be used.

[0050] An insulating film may be formed as a base film on the substrate 400. The base film may be formed by a CVD method or the like. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or The silicon nitride oxide film may be formed as a single layer or a multilayer. When using a substrate containing such mobile ions, a silicon nitride film or a nitride oxide film is used as an underlayer. By using a film containing nitrogen, such as a silicon film, mobile ions can be easily transported to the oxide semiconductor layer or the semiconductor layer. It can prevent the bacteria from penetrating into the body layers.

[0051] Next, the gate wiring including the gate electrode layer 421a, the capacitor wiring 421b, and the first terminal 42 A conductive film for forming 1c is formed on the entire surface of the substrate 400 by sputtering or vacuum deposition. Next, after forming a conductive film on the entire surface of the substrate 400, a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gate electrodes). The gate wiring including the electrode layer 421a, the capacitance wiring 421b, and the first terminal 421c are formed. At this time, in order to prevent disconnection, at least the end of the gate electrode layer 421a is tapered. It is preferable to etch the surface so that a shape is formed.

[0052] The gate wiring including the gate electrode layer 421a, the capacitance wiring 421b, and the first terminal 421 of the terminal portion C is aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium Metallic materials such as zinc and scandium, or alloy materials containing these metallic materials as the main components; Alternatively, nitrides containing these metal materials can be used to form a single layer or a multilayer. Preferably, it is effective to use a low-resistance metal material such as aluminum or copper, but it is also effective to use a heat-resistant material. It is recommended to use it in combination with a high melting point metal material due to the problems of its durability and corrosion. Molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium etc. can be used.

[0053] For example, the gate electrode layer 421a has a laminated structure in which molybdenum is laminated on aluminum. Two-layer structure with molybdenum on copper, or two-layer structure with molybdenum on copper, or nitride on copper Two-layer structure with titanium or tantalum nitride laminated, titanium nitride and molybdenum laminated A two-layer structure is preferable. A three-layer laminate structure is aluminum, aluminum, and silicon alloy, aluminum and titanium alloy, or aluminum and neodymium alloy The intermediate layer is made of tungsten, tungsten nitride, titanium nitride or titanium. A laminated structure is preferred.

[0054] At this time, a light-transmitting oxide conductive layer is used for a part of the electrode layer and the wiring layer to improve the aperture ratio. For example, the oxide conductive layer may be formed of indium oxide, indium oxide tin oxide, or the like. Alloys, indium oxide zinc oxide alloys, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride For example, aluminum, zinc oxide, or zinc gallium oxide can be used.

[0055] Next, a gate insulating layer 402 is formed to cover the gate electrode layer 421a (FIG. 2A). The gate insulating layer 402 is formed by a CVD method, a sputtering method, or the like, with a thickness of 10 nm to 400 nm. The following applies.

[0056] For example, a silicon oxide film is formed as the gate insulating layer 402 by a CVD method or a sputtering method. The gate insulating layer 402 is formed to a thickness of 100 nm. Examples of the film include, but are not limited to, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an oxide film, and the like. Other insulating films such as aluminum oxide and tantalum oxide are used, and single or multilayers of these materials are used. Alternatively, it may be formed as a laminated structure.

[0057] The gate insulating layer 402 is formed using a high-density plasma apparatus. The plasma device is 1×10 11 / cm 3 This refers to a device that can achieve a plasma density of 1000kJ / s or more. For example, a microwave power of 3 kW to 6 kW is applied to generate plasma, and the insulating film is The film is formed as follows.

[0058] The chamber was filled with monosilane gas (SiH4), nitrous oxide (N2O), and rare gases. A high-density plasma is generated under a pressure of 10 Pa to 30 Pa, and insulating materials such as glass are An insulating film is formed on a substrate having a surface. After that, the supply of monosilane gas is stopped and the substrate is exposed to the atmosphere. Plasma treatment is performed on the insulating film surface by introducing nitrous oxide (N2O) and rare gases without exposing it to heat. Plasma irradiation may be performed on the insulating film surface by introducing nitrous oxide (N2O) and rare gases. The masking process is carried out at least after the formation of the insulating film. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm. .

[0059] When forming the gate insulating layer 402, monosilane gas (SiH4) and nitrogen are introduced into the chamber. The flow ratio of nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The rare gases introduced into the bar include helium, argon, krypton, and xenon. Among these, it is preferable to use argon, which is inexpensive.

[0060] In addition, the insulating film obtained by the high density plasma device can be formed with a consistent thickness. The insulating film obtained by the high density plasma device has excellent step coverage. The thickness can be precisely controlled.

[0061] The insulating film obtained through the above process sequence is different from the insulating film obtained using a conventional parallel plate PCVD device. The etching rates are significantly different when the same etchant is used. The insulating film obtained by the parallel plate PCVD equipment is 10% or more or 20% slower and more highly The insulating film obtained by the high-density plasma device can be said to be a dense film.

[0062] The gate insulating layer 402 is formed by depositing silicon oxide by a CVD method using organic silane gas. It is also possible to form a layer. The organic silane gas is ethyl silicate (TEOS: Formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane silane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (Si H(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. The following silicon-containing compounds can be used:

[0063] The gate insulating layer 402 may be formed of an oxide of aluminum, yttrium, or hafnium. At least two or more of the following compounds are used: Compounds containing the above can also be used.

[0064] In this specification, an oxynitride is a compound having a composition in which oxygen atoms are more abundant than nitrogen atoms. Nitrided oxide refers to a substance with a higher number of nitrogen atoms than oxygen atoms. For example, a silicon oxynitride film has a composition that contains a large number of nitrogen atoms. The number of oxygen atoms is greater than that of electrons, and Rutherford backscattering (RBS) Backscattering Spectrometry and Hydrogen Forward Scattering (H When measured using FS (Hydrogen Forward Scattering) In this case, the concentration range is 50 atomic % or more and 70 atomic % or less for oxygen and 0.5 atomic % or more and 1.5 atomic % or less for nitrogen. 5 atomic % or less, silicon is 25 atomic % to 35 atomic % and hydrogen is 0.1 atomic % to 10 The silicon nitride oxide film is a film containing silicon dioxide in an amount of 0.1 atomic % or less. There are more nitrogen atoms than oxygen atoms, and the concentration is The range is 5 atomic % or more and 30 atomic % or less of oxygen, 20 atomic % or more and 55 atomic % or less of nitrogen, Silicon is between 25 atomic % and 35 atomic % and hydrogen is between 10 atomic % and 30 atomic % However, the atoms constituting silicon oxynitride or silicon nitride oxide are When the total of these is taken as 100 atomic %, the content ratios of nitrogen, oxygen, silicon and hydrogen are within the above ranges. shall be included within the scope.

[0065] Note that before the oxide semiconductor film for forming the oxide semiconductor layer 423 is formed, argon Reverse sputtering is performed by introducing gas to generate plasma, and the It is preferable to remove the dust that is present on the target. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is a method to modify the surface by forming a nitrogen atmosphere or helium atmosphere instead of argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, N2O, etc. has been added. Alternatively, the process may be carried out in an argon atmosphere to which Cl2, CF4, etc. have been added. After the photo treatment, an oxide semiconductor film is formed without exposure to the atmosphere, thereby forming a gate insulating layer 4. The oxide semiconductor layer 423 is formed on the insulating substrate 421. This can be done.

[0066] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed on the gate insulating layer 402. An oxide semiconductor film having a thickness of 40 nm or less is formed.

[0067] The oxide semiconductor film is an In-Ga-Zn-O based film, an In-Sn-Zn-O based film, an In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system Alternatively, a Zn—O-based oxide semiconductor film can be used. In a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a rare gas (typically argon) atmosphere The film can be formed by sputtering in a mixed atmosphere of fluorine and oxygen. When using the targeting method, a target containing 2% to 10% by weight of SiO2 is used. The oxide semiconductor film may contain SiOx (x>0) which inhibits crystallization.

[0068] Here, a metal oxide target containing In, Ga, and Zn (molar ratio of In2O3: Ga2O3:ZnO=1:1:0.5, In:Ga:ZnO=1:1:1, or In :Ga:ZnO=1:1:2), the distance between the substrate and the target was 100 mm, Pressure 0.6 Pa, direct current (DC) power 0.5 kW, oxygen (oxygen flow rate 100%) atmosphere When a pulsed direct current (DC) power supply is used, the powdery material (pulse) generated during film formation is This is preferable because it reduces the amount of particles (also called "tickles" or "dust") and makes the film thickness distribution uniform. In this case, an In-Ga-Zn-O metal oxide target is used as the oxide semiconductor film. An In-Ga-Zn-O based film having a thickness of 30 nm is formed on the substrate by sputtering.

[0069] The sputtering method uses RF sputtering, which uses a high frequency power supply, and DC sputtering. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which applies a bias pulse. The sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used when:

[0070] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0071] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0072] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0073] Next, a second photolithography process is performed to form a resist mask, and an In-Ga-Z The etching is performed on the nO-based film using organic acids such as citric acid and oxalic acid. In this example, ITO07N (manufactured by Kanto Chemical Co., Ltd.) was used. Unnecessary parts are removed by wet etching to form islands of the In-Ga-Zn-O film. Then, an oxide semiconductor layer 423 is formed. The edge portions of the oxide semiconductor layer 423 are etched to have a tapered shape. By doing this, it is possible to prevent the wiring from being cut off due to the step shape. The etching is not limited to wet etching, and dry etching may also be used.

[0074] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The first heat treatment is performed at a temperature of 500°C or higher using high-temperature nitrogen or an inert gas such as a rare gas, or light. At 750°C or below (or a temperature below the distortion point of the glass substrate), for 1 minute to 10 minutes Preferably, RTA treatment can be performed at 650°C for 3 to 6 minutes. The TA method allows dehydration or dehydrogenation to be carried out in a short time, exceeding the strain point of the glass substrate. The heat treatment can be carried out at any temperature. This may be performed multiple times before and after the lithography process or film formation process.

[0075] Here, the surface portion of the oxide semiconductor layer 423 is crystallized by the first heat treatment and becomes nanocrystals. The crystalline region 106 is made of crystalline silicon. The other regions are amorphous or a mixture of amorphous and microcrystalline with microcrystalline interspersed among the amorphous regions. Note that the crystalline region 106 is a part of the oxide semiconductor layer 423, and will be referred to as the oxide semiconductor layer 423 hereinafter. The notation of the layer 423 includes the crystalline region 106 .

[0076] In this specification, the heat treatment under an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This heat treatment is also called dehydrogenation heat treatment. Dehydration or dehydrogenation does not mean that only the desorption of hydrogen as hydrogen or H2 is For convenience, this term is used to refer to the elimination of H, OH, etc. .

[0077] When the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated, The water or hydrogen is removed by using the same furnace as that used for hydration or dehydrogenation without exposing it to the atmosphere. It is important to prevent the oxide semiconductor layer from being mixed again. Resistance, i.e., N-type (N - , N + After that, the resistance is increased to form an I-type oxide semiconductor. When a thin film transistor is fabricated using a dielectric layer, the threshold voltage of the thin film transistor can be controlled by the planar This makes it possible to realize a switching element with so-called normally-off characteristics. The gate voltage of the transistor is set to a positive threshold voltage as close as possible to 0V, so that the channel is formed. It is desirable for a display device that the threshold voltage value of a thin film transistor is negative. If there is a gate voltage of 0V, current flows between the source and drain electrodes. In active matrix display devices, the circuit is The electrical characteristics of the thin film transistors that make up the display are important, and these electrical characteristics determine the performance of the display device. In particular, the threshold voltage (Vth) is an important electrical characteristic of thin film transistors. Even if the field effect mobility is high, the threshold voltage is high, or the threshold voltage is negative. If the threshold voltage is high, it is difficult to control it as a circuit. In the case of a thin film transistor with a large absolute value, it is difficult to operate as a TFT when the driving voltage is low. The n-channel thin film transistor may not be able to perform its switching function and may become a load. In the case of a transistor, a channel is formed only when a positive voltage is applied as the gate voltage. A transistor that drains current is desirable. If the driving voltage is not high, the channel will not form. In transistors where a channel is not formed, or where a drain current flows even under negative voltage conditions, Such a transistor is not suitable as a thin film transistor for use in a circuit.

[0078] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. It is also possible to switch to a gas atmosphere, for example, by switching to air in the same furnace where dehydration or dehydrogenation was performed. The furnace is filled with high-purity oxygen gas, N2O gas, or ultra-dry air (dew point Cooling is carried out by filling the container with a temperature of -40°C or less, preferably -60°C or less.

[0079] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device should be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0080] When the heat treatment is performed in an inert gas atmosphere, the oxide semiconductor layer It becomes oxygen deficient and has low resistance, that is, it becomes N-type (N - Then, the oxide semiconductor layer By forming an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer can be made to have an oxygen-excess state. This results in high resistance, or I-type. This results in good electrical properties and reliability. Therefore, thin film transistors with good characteristics can be fabricated.

[0081] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer After the first heat treatment, the oxide becomes oxygen-deficient and has low resistance. The oxide semiconductor layer 423 is formed after the first heat treatment. The carrier concentration is increased, preferably to 1×10 18 / cm 3 The carrier concentration is becomes.

[0082] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the substrate is removed from the heating device. In this case, the oxide semiconductor layer 423 is removed and subjected to a second photolithography step. No crystalline region is formed on the side, and the crystalline region 106 is formed only in the upper layer excluding the side.

[0083] Next, a third photolithography step is performed to form a resist mask and then to perform etching. By removing unnecessary parts, wiring made of the same material as the gate electrode layer 421a and contacts reaching the electrode layer are formed. A contact hole is formed (Fig. 2(B)). This contact hole will be connected to the conductive film to be formed later. For example, in the driver circuit section, the gate electrode layer and the source electrode layer are directly connected. Alternatively, the thin film transistor directly contacts the drain electrode layer, and the gate wiring of the terminal portion is electrically connected to the thin film transistor. When forming a connecting terminal, a contact hole is formed.

[0084] Next, an oxide insulating film was formed over the oxide semiconductor layer 423 and the gate insulating layer 402 by a sputtering method. After forming the resist mask, a fourth photolithography process is performed to selectively Etching is performed to form oxide insulating layers 426a, 426b, 426c, and 426d, After this, the resist mask is removed (FIG. 2(C)). At this stage, the oxide semiconductor layer is A region in contact with the insulating layer 426a is formed, and in this region, the gate electrode layer and the gate insulating layer A region that overlaps with the oxide insulating layer 426a with the insulating layer 426b interposed therebetween is a channel formation region. In addition, a contact hole reaching the first terminal 421c is formed by a fourth photolithography process. Also forms.

[0085] The oxide insulating film should have a thickness of at least 1 nm. The film can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed into the film. In the embodiment, a silicon oxide film is formed as the oxide insulating film by sputtering. The substrate temperature during the heating process may be set to a temperature between room temperature and 300° C., and is set to 100° C. in this embodiment. The silicon oxide film is formed by sputtering under a rare gas (typically argon) atmosphere. It is carried out under an oxygen atmosphere or a mixed atmosphere of a rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used to perform spat deposition in an oxygen and rare gas atmosphere. A silicon oxide film can be formed by a quartz crystal deposition method. The oxide insulating film formed in contact with the surface is resistant to water, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film is used to block these substances from entering from the outside, typically a silicon oxide film. A silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0086] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0087] Next, a conductive film made of a metal material is formed on the oxide semiconductor layer 423 by a sputtering method or a vacuum evaporation method. The conductive film may be made of the same material as the gate electrode layer 421a. This can be done.

[0088] In this embodiment, a conductive film is formed by stacking first to third conductive films. For example, titanium, which is a heat-resistant conductive material, is used for the first conductive film and the third conductive film, and titanium is used for the second conductive film. The conductive film is made of an aluminum alloy containing neodymium. This makes it possible to reduce the occurrence of hillocks while taking advantage of the low resistivity of aluminum. In this embodiment, the first to third conductive films are used to form a three-layer structure, but the present invention is not limited to this. It may be a single layer structure, a two layer structure, or a four or more layer structure. For example, it may be a single layer structure of a titanium film, or a single layer structure of an aluminum film containing silicon. It may also have a layered structure.

[0089] In addition, the oxide semiconductor has a dense crystalline region 106 made of nanocrystals in the surface layer. When forming a conductive film on top of the layer, damage to the crystalline region due to heat and film formation during the film formation process can occur. The crystalline region 106 of the oxide semiconductor layer may become amorphous. In the method for manufacturing a thin film transistor described in this embodiment, An oxide insulating layer 426a functioning as a channel protective layer is in contact with a region to be a channel formation region. Therefore, even when a conductive film is formed, at least the thickness of the oxide semiconductor layer is In the channel forming region (fifth region), a structure having a crystalline region 106 in the surface layer portion is formed. This can be done.

[0090] Next, a fifth photolithography step is performed to form a resist mask, and then etching is performed. unnecessary portions are removed to form the source electrode layer 425a, the drain electrode layer 425b, and the connection electrode The etching method used here is either wet etching or dry etching. For example, titanium is used for the first conductive film and the third conductive film, and copper is used for the second conductive film. When using aluminum alloys containing chromium, use hydrogen peroxide or heated hydrochloric acid as an etcher. It can be used as a wet etching agent.

[0091] In this etching step, part of the oxide semiconductor layer 423 is etched, and the source a third region 424c between the electrode layer 425a and the oxide insulating layer 426a, and a drain electrode layer 425 b and the fourth region 424d between the oxide insulating layer 426a overlap with the source electrode layer 425a. The first region 424a, the fifth region 424e overlapping the oxide insulating layer 426a, and the drain electrode This region is thinner than the second region 424b that overlaps with the layer 425b (FIG. 2(D)). The fifth region 424e of the oxide semiconductor layer 423 is etched by the oxide insulating layer 426a. Therefore, at least the surface layer of the channel formation region is protected from the nanocrystals. In the channel formation region, a dense crystalline region composed of oxide semiconductor layer is present. The surface layer of the back channel side is the back channel side, and this crystalline region suppresses the parasitic channel. It is possible.

[0092] In this fifth photolithography step, the connection electrode 429 is formed on the gate insulating layer. It is directly connected to the first terminal 421c of the terminal portion through the formed contact hole. Although not shown here, the thin film transistors of the driving circuit are formed through the same process as described above. The source wiring or drain wiring and the gate electrode are directly connected.

[0093] Next, an oxide insulating layer 428 is formed to cover the thin film transistor 470 (FIG. 2E). The oxide insulating layer 428 is a silicon oxide film or a silicon oxynitride film obtained by a sputtering method or the like. An oxide insulating layer such as an aluminum oxide film, an aluminum oxide film, or a tantalum oxide film can be used.

[0094] The oxide insulating layer is formed by mixing impurities such as water and hydrogen into the oxide insulating layer by a method such as sputtering. In this embodiment, the oxide insulating layer can be formed by an oxide insulating film. The silicon dioxide film is formed by sputtering. The substrate temperature during film formation is 300°C above room temperature. In this embodiment, the temperature is set to 100° C. Here, impurities such as water and hydrogen are not added during film formation. As a method to prevent the inclusion of impurities, before film formation, the film is heated at a temperature of 150°C to 350°C under reduced pressure for 2 Pre-baking is performed for 10 minutes or more, and an oxide insulating layer is formed without exposure to the air. It is desirable to form a silicon oxide film by sputtering using a rare gas (typically, In a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used to oxidize oxygen and rare gases. A silicon oxide film can be formed by sputtering in a gas atmosphere. The oxide insulating layer formed in contact with the oxide semiconductor layer is oxidized by water, hydrogen ions, and OH - Such as An inorganic insulating film that does not contain impurities and blocks the intrusion of these substances from the outside is preferred.

[0095] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0096] Next, a second heat treatment (preferably 2) is carried out under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. RTA treatment may be performed for a short time. When the second heat treatment is performed, the oxide insulating layer and the oxide insulating layer are The second heat treatment is performed while the oxide semiconductor layer is in contact with the insulating layer. When the first heat treatment is performed, the oxide semiconductor layer 423 whose resistance is reduced by the first heat treatment becomes an oxygen-excess state. , it is possible to make it highly resistant (I-type).

[0097] In this embodiment, the second heat treatment is performed after the silicon oxide film is formed. There is no problem if the silicon oxide film is formed afterwards, and it is not limited to the time immediately after the silicon oxide film is formed. stomach.

[0098] In addition, when a heat-resistant material is used for the source electrode layer 425a and the drain electrode layer 425b, In this case, a step using the first heat treatment conditions can be performed at the timing of the second heat treatment. In this case, the heat treatment may be performed only once after the silicon oxide film is formed.

[0099] Next, a sixth photolithography step is performed to form a resist mask, and the oxide insulating layer 4 A contact hole reaching the drain electrode layer 425b is formed by etching 28. Furthermore, a contact hole reaching the connection electrode 429 is also formed by this etching.

[0100] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is performed using a hydrochloric acid solution. However, etching of ITO in particular Residues tend to be generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0101] Next, a seventh photolithography step is performed to form a resist mask and then etch the The pixel electrode layer 110 is formed by removing unnecessary portions.

[0102] In this seventh photolithography step, the gate insulating layer 402 in the capacitance section The oxide insulating layer 426b and the oxide insulating layer 428 are used as dielectrics to form the capacitor wiring 421b and the pixel A storage capacitor is formed together with the electrode layer 110 .

[0103] In the seventh photolithography step, the first terminal 421c is formed by a resist mask. The transparent conductive film 128 is covered with a mask and left on the terminal portion. The connection electrode 4 directly connected to the first terminal 421c is an electrode or wiring used for connection. The transparent conductive film 128 formed on the gate electrode 29 is a connecting film that functions as an input terminal of the gate wiring. Although not shown, a connection terminal that functions as an input terminal for the source wiring is also provided. The sub-electrodes are also formed at the same time.

[0104] 4(A1) and 4(A2) are a cross-sectional view and a plan view of the gate wiring terminal portion at this stage. 4(A1) is a cross section taken along the line C1-C2 in FIG. 4(A2). In FIG. 4(A1), a transparent conductive film 4 formed on an oxide insulating layer 428 is 15 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, a first terminal 411 made of the same material as the gate wiring and a second terminal 412 made of the same material as the source wiring are provided. The connection electrode 412 made of the same material as the gate insulating layer 402 overlaps with the gate insulating layer 402 and is in direct contact with the gate insulating layer 402. In addition, the connection electrode 412 and the transparent conductive film 415 are provided on the oxide insulating layer 428. The electrodes are directly connected to each other through contact holes to provide electrical continuity.

[0105] FIG. 4(B1) and FIG. 4(B2) are a cross-sectional view and a plan view of the source wiring terminal portion, respectively. FIG. 4(B1) is a cross-sectional view taken along the line C3-C4 in FIG. 4(B2). In FIG. 4(B1), the transparent conductive film 41 formed on the oxide insulating layer 428 8 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, an electrode 416 made of the same material as the gate wiring is electrically connected to the source wiring. The electrode 416 overlaps the second terminal 414 connected to the first terminal 414 via the gate insulating layer 402. The electrode 416 is not electrically connected to the second terminal 414, and the electrode 416 is connected to a different voltage than the second terminal 414. If you set it to a floating, GND, 0V, etc., you can reduce the capacitance for noise suppression. The second terminal 414 can be formed with an oxide film. It is electrically connected to the transparent conductive film 418 via the organic insulating layer 428 .

[0106] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0107] In this way, seven photolithography processes were carried out using seven photomasks to create the channel. Then, the thin film transistor 470 and the storage capacitor portion can be completed. These are arranged in a matrix to correspond to each pixel, forming a pixel section. The present invention can be used as one of the substrates for manufacturing a display device of an active matrix type. For convenience, this document refers to such a substrate as an active matrix substrate.

[0108] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0109] Furthermore, the present embodiment is not limited to the pixel configuration shown in Fig. 3. For example, a pixel may be configured without providing a capacitance wiring. The pixel electrodes are overlapped with the gate wiring of the adjacent pixel via the protective insulating film and the gate insulating layer to form a storage capacitor. In this case, the capacitance wiring and the third terminal connected to the capacitance wiring may be omitted. It is possible.

[0110] 5, a silicon dioxide film was formed on the oxide insulating layer 456a functioning as a channel protective layer. The source electrode layer 425a and the drain electrode layer 425b may overlap with each other. When the source electrode layer 425a and the drain electrode layer 425b are patterned, the oxide semiconductor layer Since the oxide semiconductor layer is not etched, a thin region is not formed in the oxide semiconductor layer. That is, the first region 424a overlapping the source electrode layer 425a and the second region 424b overlapping the source electrode layer 425a have the same thickness. The second region 424b overlaps with the drain electrode layer 425b, and the fifth region becomes a channel forming region. The oxide semiconductor layer has a region 424e.

[0111] As shown in FIG. 22A, the amorphous oxide semiconductor layer in the fifth region 424e of the oxide semiconductor layer Alternatively, the thickness of the region that is a mixture of amorphous and microcrystalline is 4d (i.e., the crystalline region in the fifth region 424e and the amorphous or The interface between the amorphous and microcrystalline mixture region and the amorphous and microcrystalline mixture region is the third region 424c and the fourth region 424 The thin film transistor 490 may have a structure in which the first electrode 491 is located above the outermost surface of the first electrode 492 (the first electrode 491 is located above the outermost surface of the first electrode 492). The thin film transistor 490 having such a configuration is, for example, By adjusting the temperature or heating time, the crystal region of the oxide semiconductor layer can be made extremely shallow. The thin film transistor 490 shown in FIG. Therefore, the off-state current can be reduced.

[0112] The channel length L of the channel protective thin film transistor 490 shown in FIG. It is equal to the width of the oxide insulating layer 426a in the direction parallel to the carrier flow direction. In the thin film transistor 490 shown in (A), the width L3 in the channel length direction of the third region of the oxide semiconductor layer and the width L4 in the channel length direction of the fourth region are not necessarily the same, but the sum of the width L3 in the channel length direction of the third region and the width L4 in the channel length direction of the fourth region is a certain value. Also, as shown in FIG. 22(B), a thin film transistor 430 having a crystal region in the surface layer portion may be used in the first to fifth regions 424a to 424e of the oxide semiconductor layer. By adopting the configuration of the thin film transistor 430 shown in FIG. 22(B), the on-current can be increased. Also, different thin film transistors having different configurations such as the thin film transistors 430, 450, 470, or 490 may be formed on the same substrate. When the pixel portion and the drive circuit are formed on the same substrate, the thin film transistor used in the pixel portion is required to have excellent switching characteristics, and the thin film transistor used in the drive circuit preferably has a high operating speed. For example, as shown in FIG. 22(C), the thin film transistor 430 may be disposed in the drive circuit portion, and the thin film transistor 490 may be disposed in the pixel portion. Since the thin film transistor 430 disposed in the drive circuit portion can increase the on-current, it is suitable for applications that require a large current driving ability. The thin film transistor 490 disposed in the pixel portion can reduce the off-current. Therefore, when used as a switching element in the pixel portion, the contrast can be improved. Or, as shown in FIG. 22(D), the thin film transistor 450 may be disposed in the drive circuit portion, and the thin film transistor 470 having a low off-current may be disposed in the pixel portion. 定の値となる。

[0113] また、図22(B)に示すように、酸化物半導体層の第1領域乃至第5領域424a~4 24eにおいて、表層部に結晶領域を有する薄膜トランジスタ430としてもよい。図2 2(B)に示す薄膜トランジスタ430の構成とすることで、オン電流を増加させること ができる。

[0114] また、同一基板上に、薄膜トランジスタ430、450、470または490等の異なる 構成を有する薄膜トランジスタを形成しても良い。なお、画素部と駆動回路を同一基板上 に形成する場合には、画素部に用いる薄膜トランジスタは優れたスイッチング特性が要求 され、駆動回路に用いる薄膜トランジスタは動作速度が速いことが好ましい。例えば、図 22(C)に示すように、駆動回路部には薄膜トランジスタ430を配置し、画素部には 薄膜トランジスタ490を配置してもよい。駆動回路部に配置された薄膜トランジスタ4 30はオン電流を増加させることができるため、大きな電流駆動能力を要求する用途に適 しており、画素部に配置された薄膜トランジスタ490は、オフ電流を低減することがで きるため、画素部のスイッチング素子として用いた場合、コントラストを向上させること ができる。または、図22(D)に示すように、駆動回路部に薄膜トランジスタ450を 配置し、画素部にオフ電流の低い薄膜トランジスタ470を配置してもよい。また、図示 However, the thin film transistor 430 is disposed in the driver circuit portion, and the thin film transistor Alternatively, the thin film transistor 450 may be disposed in the driver circuit portion and the thin film transistor 470 may be disposed in the pixel portion. A thin film transistor 490 may be provided.

[0115] In the thin film transistors 430, 450, 470, and 490 shown in this embodiment, The interface of the oxide semiconductor layer 423 in contact with the gate insulating layer 402 is amorphous or slightly amorphous. The oxide insulating layer 426a is a crystalline mixture, and at least a surface portion in contact with the oxide insulating layer 426a is a crystalline region. It has.

[0116] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0117] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0118] In addition, response speed is improved by increasing the vertical synchronization frequency by 1.5 times, preferably by more than 2 times the normal frequency. and selecting a gradation to be written for each of the divided fields in each frame. There is also a driving technology called double speed driving.

[0119] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0120] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0121] The n-channel transistor obtained in this embodiment is formed by using an In-Ga-Zn-O based film. These drive technologies are used in the channel formation region and have good dynamic characteristics. It can be done.

[0122] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example, GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0123] Through the above steps, a thin film transistor having good electrical characteristics and high reliability and a thin film transistor It is possible to provide a display device using the star.

[0124] The thin film transistor described in this embodiment is a thin film transistor including an oxide semiconductor layer. At least a surface portion of the channel formation region of the oxide semiconductor layer has a crystalline region, The other part may be amorphous or a mixture of amorphous and microcrystalline. Therefore, the thin film transistor can be made capable of suppressing the occurrence of a gate.

[0125] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0126] (Embodiment 2) In this embodiment mode, an example of a manufacturing process of a display device, which is different from that in Embodiment Mode 1, will be described with reference to FIGS. In this embodiment, the same parts as those in the first embodiment or parts having similar functions are used. The steps and operations can be performed in the same manner as in the first embodiment, and repeated explanations will be omitted.

[0127] First, a gate wiring including a gate electrode layer 421a, a capacitor, and a gate electrode layer 421b are formed on a substrate 400 having an insulating surface. A conductive film for forming the wiring 421b and the first terminal 421c is formed by sputtering or vacuum deposition. Next, after forming a conductive film on the entire surface of the substrate 400, a first photolithography is performed. A photolithography process is performed, a resist mask is formed, and unnecessary parts are removed by etching. Wirings and electrodes (gate wiring including the gate electrode layer 421a, capacitor wiring 421b, and first A terminal 421c) is formed.

[0128] Next, a gate electrode layer 421a, a capacitor wiring 421b, and a first terminal 421c are formed on the gate electrode layer 421a. An insulating layer 402 is formed on the gate insulating layer 402, and a film thickness of 5 nm to 200 nm is preferably Alternatively, the oxide semiconductor film 103 is formed to a thickness of 10 nm to 40 nm. The process can be carried out in the same manner as in the first embodiment.

[0129] Next, the oxide insulating film 105 is formed over the oxide semiconductor film 103 by a sputtering method. A resist mask is formed by the photolithography process of 2, and selective etching is performed. A contact hole reaching the first terminal 421c is formed (FIG. 6(A)). The insulating film 105 is formed by the same method as the oxide insulating film to be the oxide insulating layer 426a described in Embodiment 1. It is possible to form a film.

[0130] Next, the oxide semiconductor film 103 is dehydrated or dehydrogenated. The first heat treatment for the oxidation is carried out by using high-temperature nitrogen or an inert gas such as a rare gas or light. 0℃ to 750℃ (or a temperature below the distortion point of the glass substrate) for 1 minute to 10 minutes The RTA treatment can be carried out at a temperature of about 650°C or lower for 3 minutes or longer and 6 minutes or shorter. RTA treatment allows dehydration or dehydrogenation in a short time, so the glass substrate Heat treatment can also be performed at temperatures above the strain point. Alternatively, the process may be repeated multiple times before and after the photolithography process or the film formation process.

[0131] Here, the surface portion of the oxide semiconductor film 103 is crystallized by the first heat treatment and becomes nanocrystals. The oxide semiconductor film 10 has a dense crystalline region 106 made of crystalline talc. The other regions of 3 are amorphous or a mixture of amorphous and microcrystalline regions with microcrystalline interspersed in the amorphous regions. The crystalline region 106 is a part of the oxide semiconductor film 103. The notation of the compound semiconductor film 103 includes the crystalline region 106.

[0132] When the temperature is lowered from the heating temperature T at which the oxide semiconductor film is dehydrated or dehydrogenated, The water or hydrogen is removed by using the same furnace as that used for hydration or dehydrogenation without exposing it to the atmosphere. It is important not to mix them again. Also, the gas atmosphere used to lower the temperature from the heating temperature T The gas atmosphere may be changed to a different gas atmosphere from the gas atmosphere heated to degree T. For example, The furnace is filled with high-purity oxygen gas or or N2O gas, ultra-dry air (dew point below -40°C, preferably below -60°C) Cooling is performed by

[0133] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device should be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0134] After the first heat treatment, the oxide semiconductor film 103 becomes oxygen-deficient and has low resistance. After the heat treatment in step 1, the carrier concentration of the oxide semiconductor film is higher than that of the oxide semiconductor film immediately after the film formation. 1×10 18 / cm 3 The carrier concentration will be equal to or higher than this.

[0135] Next, a resist mask is formed by a third photolithography process and selectively etched. Then, oxide insulating layers 426a, 426b, 426c, and 426d are formed by etching. The resist mask is removed (FIG. 6B). Here, the oxide insulating layer 426a is In addition, the oxide semiconductor film 103 functions as a channel protective layer for the transistor. The region overlapping with the insulating layer 426a is a region that will later become a channel formation region.

[0136] Next, the oxide semiconductor film 103 and the oxide insulating layers 426a, 426b, 426c, and 426 A conductive film made of a metal material is formed on the substrate by sputtering or vacuum deposition. For the gate electrode layer 421a, a material similar to that of the gate electrode layer 421a can be used.

[0137] In this embodiment, a conductive film is formed by stacking first to third conductive films. For example, titanium, which is a heat-resistant conductive material, is used for the first conductive film and the third conductive film, and titanium is used for the second conductive film. The conductive film is made of an aluminum alloy containing neodymium. This makes it possible to reduce the occurrence of hillocks while taking advantage of the low resistivity of aluminum. In this embodiment, the first to third conductive films are used to form a three-layer structure, but the present invention is not limited to this. It may be a single layer structure, a two layer structure, or a four or more layer structure. For example, it may be a single layer structure of a titanium film, or a single layer structure of an aluminum film containing silicon. It may also have a layered structure.

[0138] In addition, the oxide semiconductor has a dense crystalline region 106 made of nanocrystals in the surface layer. When forming a conductive film on top of a layer, the heat generated during film formation and the damage to the crystalline region caused by film formation can be prevented. Therefore, the crystalline region 106 of the oxide semiconductor layer may become amorphous. In the method for manufacturing a thin film transistor described in this embodiment, An oxide insulating layer 426a functioning as a channel protective layer is provided in contact with the region to be formed. Therefore, even when a conductive film is formed, at least the chalcogenide of the oxide semiconductor layer is The surface layer of the panel-forming region can have a crystalline region 106 .

[0139] Next, a fourth photolithography step is performed to form resist masks 480a and 480b. Then, unnecessary portions are removed by etching to form a conductive layer 425 and a connection electrode 429. (Fig. 6(C)) The etching method used here can be wet etching or dry etching. For example, titanium is used for the first conductive film and the third conductive film, and copper is used for the second conductive film. When using aluminum alloys containing chromium, use hydrogen peroxide or heated hydrochloric acid as an etcher. It can be used as a wet etching agent.

[0140] In this fourth photolithography step, the connection electrode 429 is formed on the gate insulating layer. It is directly connected to the first terminal 421c of the terminal portion through the formed contact hole. Although not shown here, the thin film transistors of the driving circuit are formed through the same process as described above. The source wiring or drain wiring and the gate electrode are directly connected.

[0141] The resist mask 480a in this embodiment is a resist mask having recesses or protrusions. In other words, the resist is made up of multiple regions (two regions in this case) with different thicknesses. In the resist mask 480a, the thick region is made of the resist mask. The thin areas are called the convex portions of the resist mask, and the thin areas are called the concave portions of the resist mask.

[0142] In the resist mask 480a, a portion where a source electrode layer and a drain electrode layer will be formed later is A protrusion is formed in the first portion, and a recess is formed in the peripheral portion of the island-shaped oxide semiconductor layer.

[0143] The resist mask shown in this embodiment mode can be formed using a multi-tone mask. A multi-tone mask is a mask that can perform exposure with multiple levels of light intensity, and a typical example is refers to the exposure of three levels of light intensity: exposed area, semi-exposed area, and unexposed area. By using a mask, multiple (typically two types) Therefore, a resist mask having a thickness of 1000 nm can be formed by using a multi-tone mask. This allows the number of photomasks to be reduced.

[0144] By using a multi-tone mask and then performing exposure and development, a resist mask with regions of different thickness can be produced. However, the present invention is not limited to this, and multi-tone A resist mask may be formed without using a mask.

[0145] The conductive layer 425 and the connection electrode 429 are formed using resist masks 480a and 480b. After that, the resist masks 480a and 480b are recessed (reduced), The resist masks 482a, 482b, and 482c are formed. To prevent this, ashing with oxygen plasma can be performed. Therefore, the recesses in the resist mask 480a disappear, and the resist mask 482a and the resist mask 482b are removed. The resist mask 482a and the resist mask 482b are also separated. The electrode layer 425 in the area sandwiched between 82b is exposed (not shown).

[0146] Then, resist masks 482a, 482b, and 482c are used to cover the exposed conductive layer 42. 5 and a part of the connection electrode 429 are etched to form the source electrode 425a, A drain electrode 425b and an island-shaped oxide semiconductor layer 423 are formed (FIG. 6D).

[0147] In this etching step, a part of the oxide semiconductor film 103 is etched, and the source electrode a third region 424c between the electrode layer 425a and the oxide insulating layer 426a, and a drain electrode layer 425 b and the fourth region 424d between the oxide insulating layer 426a overlap with the source electrode layer 425a. The first region 424a, the second region 424b overlapping the drain electrode layer 425b, and the oxide insulating layer The oxide semiconductor layer 426a is thinner than the fifth region 424e. The fifth region 424e of the insulating film 423 is prevented from being etched by the oxide insulating layer 426a. Therefore, at least the surface layer of the channel formation region is composed of nanocrystals. In the channel formation region, the surface portion of the oxide semiconductor layer is This crystalline region is located on the side of the gate insulating film, and it is possible to suppress the parasitic channel.

[0148] The first region 424a and the second region 424b are a channel forming region. It has the same film thickness as 4e.

[0149] Next, an oxide insulating layer 428 is formed to cover the thin film transistor 410 (FIG. 6E). The oxide insulating layer 428 is a silicon oxide film or a silicon oxynitride film obtained by a sputtering method or the like. An oxide insulating layer such as an aluminum oxide film, an aluminum oxide film, or a tantalum oxide film can be used.

[0150] Next, a second heat treatment (preferably 2) is carried out under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the temperature is increased by heating in a nitrogen atmosphere. The second heat treatment is carried out at 250°C for 1 hour under atmospheric pressure. RTA treatment may be performed for a short time. When the second heat treatment is performed, the oxide insulating layer and the oxide insulating layer are The second heat treatment is performed while the oxide semiconductor layer is in contact with the insulating layer. When the first heat treatment is performed, the oxide semiconductor layer 423 whose resistance is reduced by the first heat treatment becomes an oxygen-excess state. , it is possible to make it highly resistant (I-type).

[0151] In this embodiment, the second heat treatment is performed after the silicon oxide film is formed. There is no problem if the silicon oxide film is formed afterwards, and it is not limited to the time immediately after the silicon oxide film is formed. stomach.

[0152] In addition, when a heat-resistant material is used for the source electrode layer 425a and the drain electrode layer 425b, In this case, a step using the first heat treatment conditions can be performed at the timing of the second heat treatment. In this case, the heat treatment may be performed only once after the silicon oxide film is formed.

[0153] Note that a protective insulating layer may be formed over the oxide insulating layer 428. For example, For example, a silicon nitride film can be formed by RF sputtering. Hydrogen ions and OH - It does not contain impurities such as these, and blocks them from entering from the outside. The inorganic insulating film is a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, etc. The protective insulating layer is formed successively with the oxide insulating layer 428. It is also possible to

[0154] Next, a fifth photolithography step is performed to form a resist mask, and the oxide insulating layer 4 A contact hole reaching the drain electrode layer 425b is formed by etching 28. Furthermore, a contact hole reaching the connection electrode 429 is also formed by this etching.

[0155] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is performed using a hydrochloric acid solution. However, etching of ITO in particular Residues tend to be generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0156] Next, a sixth photolithography step is performed to form a resist mask, and then etching is performed. The pixel electrode layer 110 is formed by removing unnecessary portions.

[0157] In this sixth photolithography step, the gate insulating layer 402 in the capacitance section The oxide semiconductor layer, the oxide insulating layer 426b, and the oxide insulating layer 428 are used as dielectrics. The wiring 421b and the pixel electrode layer 110 form a storage capacitor.

[0158] In the sixth photolithography step, the first terminal 421c is formed by a resist mask. The transparent conductive film 128 is covered with a mask and left on the terminal portion. The connection electrode 4 directly connected to the first terminal 421c is an electrode or wiring used for connection. The transparent conductive film 128 formed on the gate electrode 29 is a connecting film that functions as an input terminal of the gate wiring. Although not shown, a connection terminal that functions as an input terminal for the source wiring is also provided. The sub-electrodes are also formed at the same time.

[0159] In this way, six photolithography processes were carried out using six photomasks to create the channel. The thin film transistor 410 and the storage capacitor portion can be completed.

[0160] The thin film transistor described in this embodiment is a thin film transistor including an oxide semiconductor layer. The surface portion of the channel formation region of the oxide semiconductor layer has a crystalline region, and the other portion has a crystalline region. The composition may be amorphous or a mixture of amorphous and microcrystalline. This suppresses the occurrence of parasitic channels, resulting in good electrical characteristics and reliability. Therefore, a thin film transistor and a display device having high optical properties can be manufactured.

[0161] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0162] (Embodiment 3) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0163] The thin film transistors arranged in the pixel portion are formed according to the first or second embodiment. The thin film transistor described in Embodiment 1 or 2 is an n-channel thin film transistor. Therefore, among the driver circuits, the driver circuits that can be configured with n-channel TFTs are A part of the thin film transistor is formed on the same substrate as the thin film transistor of the pixel portion.

[0164] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, a The pixel portion 5301 has a plurality of signal lines. A plurality of scanning lines are arranged extending from the signal line driving circuit 5304, and the first scanning line driving circuit 5 302 and the second scanning line driver circuit 5303. At the intersections with the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is made of FPC (Flexible Printed Circuit). Through a connection part such as a timing control circuit 5305 (controller, control IC (also called the "interface")

[0165] In FIG. 7A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. The number of externally provided components such as drive circuits is reduced, which contributes to cost reduction. When a driving circuit is provided outside the substrate 5300, the wiring is extended to connect the driving circuit at the connecting portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0166] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. The driver circuit 5304 is provided with a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), Each clock signal is a multiple of clock signals with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0167] In FIG. 7B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, The scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver This shows a structure in which the circuit 5304 is formed on a substrate different from that of the pixel portion 5301. The thin film transistor has a lower field-effect mobility than a transistor using a single-crystal semiconductor due to its structure. A driver circuit formed on the substrate 5300 can be configured using transistors. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce costs, or improve yields. It is possible.

[0168] The thin film transistor described in Embodiment 1 or 2 is an n-channel TFT. In Fig. 8(A) and Fig. 8(B), the structure of the signal line driver circuit configured with n-channel TFTs is shown. An example of the structure and operation will be explained below.

[0169] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0170] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0171] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0172] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0173] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0174] Next, the operation of the signal line driver circuit of FIG. 8(A) will be explained with reference to the timing chart of FIG. 8(B). 8B, the signals Sout_1 to Sout_N and the signal Vda ta_1 to Vdata_k. 5601, and signals Vdata_1 to Vdata_k are , are examples of signals input to the wirings 5604_1 to 5604_k. One operation period of the drive circuit corresponds to one gate selection period in the display device. For example, the period is divided into periods T1 to TN. This is a period for writing video signal data (DATA) to pixels belonging to the selected row.

[0175] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0176] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0177] The shift register 5601 and the switching circuit 5602 are the same as those in Embodiment 1 and 2. Alternatively, a circuit including the thin film transistor described in Embodiment 2 can be used. In this case, the polarity of all the transistors in the shift register 5601 is set to N-channel type, Alternatively, it can be configured with only one polarity of the P-channel type.

[0178] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. In some cases, a level shifter or a buffer may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S) are input to the shift register. P) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line, and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on all at once, so the buffer must be able to pass a large current. is used.

[0179] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 9 and 10.

[0180] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number equal to or greater than 3 (see FIG. 9(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the A first clock signal CK1 is output from the first wiring 11, a second clock signal CK2 is output from the second wiring 12, and a third clock signal CK3 is output from the third wiring 13. The third wiring 13 transmits the third clock signal CK3, and the fourth wiring 14 transmits the fourth clock signal C. In the first pulse output circuit 10_1, a start signal K4 is supplied from the fifth wiring 15. The first start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), The signal from the previous stage (called the previous stage signal OUT(n-1)) (n is a natural number of 2 or more) is input. In addition, the first pulse output circuit 10_1 receives the pulse from the third pulse output circuit 10_3, which is two stages later. Similarly, in the n-th pulse output circuit 10_n of the second stage or later, The signal from the (n+2)th pulse output circuit 10_(n+2) (the subsequent signal OUT(n+2) Therefore, the pulse output circuit of each stage outputs the pulse to the next stage and / or two stages. The first output signal (OUT(1)(SR) to OUT (N)(SR)), and a second output signal (OUT(1) to O) electrically connected to another wiring or the like. UT(N)) is output. As shown in Figure 9(A), The latter stage signal OUT(n+2) is not input to the two stages. A second start pulse SP2 is sent from the wiring 16, and a third start pulse S is sent from the seventh wiring 17. Alternatively, a separate shift register can be used to input P3. For example, the (n+1)th pulse signal that does not contribute to the pulse output to the pixel unit may be Pulse output circuit 10 (n+1) , the (n+2)th pulse output circuit 10 (n+2) (Da The dummy stage generates a second start pulse (SP2) and a third start pulse (SP3). Alternatively, a signal equivalent to the pulse (SP3) may be generated.

[0181] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0182] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 1 to 4. For example, in FIG. 9(A), The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0183] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 9B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23, and a start signal CK4 is input to the fourth input terminal 24. The pulse is input to the fifth input terminal 25, the subsequent signal OUT(3) is input to the first output terminal The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(2)(SR) is output from the second output terminal 27. Therefore, the output signal OUT(1) of 2 is output.

[0184] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 9(B) will be described with reference to FIG. 9(C). ) is explained.

[0185] The pulse output circuit shown in FIG. 9C includes the first transistor 31 to the eleventh transistor 41. The first input terminal 21 to the fifth input terminal 25 and the first In addition to the first output terminal 26 and the second output terminal 27, a power supply to which a first high power supply potential VDD is supplied is connected. A power supply line 51 is connected to a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 is connected to a power supply line 54 to which a low power supply potential VSS is supplied. A signal is sent from the power supply line 53 to the first transistor 31 to the eleventh transistor 41. The power supply potential is supplied to the power supply lines. The first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is The potential is set to be higher than the third power supply potential VSS. The clock signal 4 (CK4) is a signal that alternates between high and low levels at regular intervals. When the voltage is at H level, it is VDD, and when it is at L level, it is VSS. By making VDD higher than the potential VCC of the power supply line 52, the operation can be prevented from being affected. Therefore, the potential applied to the gate electrode of the transistor can be kept low, and the transistor This reduces the shift in the threshold voltage and suppresses degradation.

[0186] In FIG. 9C, the first transistor 31 has a first terminal electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; is electrically connected to the fourth input terminal 24. The second transistor 32 is is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. The gate electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 35. The third transistor 33 has a first terminal electrically connected to the first input terminal 21, The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, The second terminal is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 of No. 6 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second Electrically connected to the gate electrode of the transistor 32 and the gate electrode of the fourth transistor 34 The seventh transistor has a gate electrode electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. The gate electrode of the fourth transistor 34 is electrically connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrode is electrically connected to the power supply line 52. The resistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The first terminal of the eleventh transistor 41 is electrically connected to the power supply line 53. the second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the second transistor The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. There are.

[0187] In FIG. 9C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 10(A)).

[0188] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. An element having terminals, and a channel region between a drain region and a source region, A current can be passed through the drain region, the channel region, and the source region. The source and drain vary depending on the structure and operating conditions of the thin film transistor. Therefore, it is difficult to determine whether the source or drain is the source or drain. The region that functions as a drain is sometimes not called a source or drain. For example, they may be referred to as the first terminal and the second terminal, respectively.

[0189] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 10(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0190] As shown in FIG. 10A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0191] If the ninth transistor 39 having the second potential VCC applied to its gate electrode is not present, the boot When the potential at node A rises due to the strapping operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, rises and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source are electrically connected to each other, and the gate and drain are electrically connected to each other. In addition, a large bias voltage is applied, which causes a large stress and leads to transistor deterioration. Therefore, the ninth transistor, to whose gate electrode the second power supply potential VCC is applied, By providing transistor 39, the potential of node A is However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This can suppress the deterioration of the transistor 31.

[0192] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0193] Note that the semiconductor layers of the first to eleventh transistors 31 to 41 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and This allows for increased field effect mobility and reduced degradation. In addition, a transistor using an oxide semiconductor, Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is This allows the number of power supply lines to be reduced, thereby enabling the circuit to be made smaller.

[0194] The gate electrode of the seventh transistor 37 is connected to the clock signal supplied from the third input terminal 23. A lock signal, supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38 The clock signal to be input is provided by the second input terminal 22 to the gate electrode of the seventh transistor. The clock signal supplied to the eighth gate electrode is supplied by the third input terminal 23. The same effect can be achieved by changing the wiring relationship so that the clock signal is generated. In the shift register shown in (A), the seventh transistor 37 and the eighth transistor The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. On, then the seventh transistor 37 is off, and the eighth transistor 38 is off. By setting the input terminal 22 to the ON state, the potentials of the second input terminal 22 and the third input terminal 23 are reduced. The potential drop at node B is a drop at the gate electrode of the seventh transistor 37. , and occurs twice due to the drop in the potential of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in FIG. The seventh transistor 37 is turned on, and the eighth transistor 38 is turned on. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned off. By turning off the input terminal 38, the second input terminal 22 and the third input terminal 23 The voltage drop at node B caused by the voltage drop at node B is absorbed by the gate of the eighth transistor 38. Therefore, the number of times the seventh transistor is turned on can be reduced to one time by the decrease in the potential of the seventh transistor. A clock signal is supplied to the gate electrode of the eighth transistor 37 from the third input terminal 23. The gate electrode of the clock generator 38 is connected to the second input terminal 22 so that a clock signal is supplied to the gate electrode of the clock generator 38. This is preferable because it reduces the number of fluctuations in the potential of the node B and also reduces noise. This is because it can be reduced.

[0195] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, It is possible to suppress malfunction of the output circuit.

[0196] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0197] (Fourth embodiment) The thin film transistors shown in Embodiments 1 and 2 are manufactured, and the thin film transistors are used in a pixel portion and Furthermore, a semiconductor device (also called a display device) having a display function can be manufactured by using the semiconductor device in a driver circuit. In addition, a part of a driver circuit having the thin film transistor described in Embodiments 1 and 2 can be Alternatively, the entire display can be formed on the same substrate as the pixel section to form a system-on-panel. can.

[0198] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) luminescence elements, organic EL elements, etc. Also, electronic ink A display medium whose contrast changes due to an electrical effect can also be applied.

[0199] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after the film is formed and before the pixel electrode is formed by etching, All forms apply.

[0200] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0201] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. 11. FIG. 11 shows an embodiment formed on a first substrate 4001. Highly reliable thin films containing the In-Ga-Zn-O system films shown in 1 and 2 as oxide semiconductor layers are used. The thin film transistors 4010 and 4011 and the liquid crystal element 4013 are connected to the second substrate 4006. 11(B) is a top view of the panel sealed with a sealant 4005. This corresponds to the cross-sectional view at MN in 1(A1)(A2).

[0202] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0203] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 11(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0204] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 11B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4022 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0205] The thin film transistors 4010 and 4011 have an In-Ga-Zn-O based film as an oxide semiconductor layer. The highly reliable thin film transistors described in Embodiments 1 and 2 can be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. It is a transistor.

[0206] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. The liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033. However, the color filters can be provided on either the first substrate 4001 or the second substrate 4006. It's okay to do that.

[0207] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Also, aluminum foil can be covered with PVF film or polyester film. It is also possible to use a sheet having a structure in which the sheet is sandwiched between two thin films.

[0208] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0209] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs. c. or more and 100 μsec or less, and because it is optically isotropic, no alignment treatment is required. The viewing angle dependency is small.

[0210] Although this embodiment is an example of a transmissive liquid crystal display device, the present invention can also be applied to a reflective liquid crystal display device. It can also be applied to a semi-transmissive liquid crystal display device.

[0211] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0212] In this embodiment, in order to reduce the surface irregularities caused by the thin film transistor, In order to improve the reliability of the transistor, the thin film transistor obtained in the first or second embodiment The insulating layer (insulating layer 4020, insulating layer 4021) functions as a protective film and a planarizing insulating film. The protective film is made to protect against organic matter, metals, water vapor, etc. floating in the air. The protective film is formed to prevent the intrusion of contaminating impurities, and a dense film is preferable. Using this method, silicon oxide films, silicon nitride films, silicon oxynitride films, silicon nitride oxide films, film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, or nitride oxide film The protective film may be formed of a single layer or a multilayer of aluminum films. However, there is no particular limitation and various methods may be used for forming the film.

[0213] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. When a silicon film is used, the aluminum film used as the source electrode layer and the drain electrode layer can be It is effective in preventing locking.

[0214] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. When this happens, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent the problem of

[0215] After forming the protective film, the oxide semiconductor layer is annealed (at 300°C or higher and 400°C or lower). may be performed.

[0216] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as polyethylene, polyimide, benzocyclobutene, polyamide, and epoxy In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0217] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0218] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, At the same time as the annealing process, the oxide semiconductor layer is annealed (at 300°C or higher and 400°C or lower). The insulating layer 4021 may be baked and the oxide semiconductor layer may be annealed at the same time, which may increase efficiency. This makes it possible to manufacture semiconductor devices easily.

[0219] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0220] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0221] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0222] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0223] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 40 The source electrode layer and the drain electrode layer 11 are formed of the same conductive film.

[0224] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0225] In FIG. 11, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0226] FIG. 12 shows a TFT substrate 2600 fabricated using the TFTs shown in the first and second embodiments. 1 shows an example of a liquid crystal display module constructed as a semiconductor device using the semiconductor device.

[0227] FIG. 12 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0228] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0229] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0230] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0231] (Embodiment 5) In this embodiment mode, a semiconductor device to which the thin film transistor shown in Embodiment 1 or 2 is applied An example of electronic paper is shown below.

[0232] Figure 13 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiments 1 and 2. A transistor can be applied.

[0233] The electronic paper in Figure 13 is an example of a display device that uses the twisting ball display method. The spherical display method uses black and white spherical particles on the electrode layer of the display element. A first electrode layer and a second electrode layer are disposed between the first electrode layer and the second electrode layer, and a potential is applied to the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by creating a difference.

[0234] The thin film transistor 581 sealed between the substrate 580 and the substrate 596 has a bottom gate structure. The first electrode layer 58 is a thin film transistor having a source electrode layer or a drain electrode layer. 7 through openings formed in the insulating layers 584 and 585, and are electrically connected. Between the electrode layer 587 and the second electrode layer 588, a black region 590a and a white region 590b are provided. and a spherical particle 589 having a cavity 594 therearound that is filled with liquid. The spherical particles 589 are filled with a filler 595 such as a resin (see FIG. 13). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a pixel electrode. The second electrode layer 588 corresponds to a common electrode. The common potential line shown in either of the first and second embodiments is electrically connected to the common potential line. The conductive particles disposed between the pair of substrates are used to connect the second electrode layer 588 to the It can be electrically connected to a common potential line.

[0235] Also, instead of the twist ball, an electrophoretic element can be used. and a particle with a diameter of 10 μm or more that contains positively charged white particles and negatively charged black particles. Microcapsules with a size of approximately 0.1 μm or less are used. The microcapsules are subjected to an electric field by the first and second electrode layers. When this happens, the white particles and black particles move in opposite directions, allowing the display to be either white or black. The display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, auxiliary lights are It does not require a display, consumes little power, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display, the image once displayed can be retained. Therefore, it is possible to transmit a signal from a radio wave source to a semiconductor device with a display function (simply a display device, or a display device). Even if the device (also called a semiconductor device having a This makes it possible to

[0236] As a result, electronic paper having high reliability as a semiconductor device can be obtained.

[0237] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0238] (Embodiment 6) In this embodiment mode, a semiconductor device to which the thin film transistor shown in Embodiment 1 or 2 is applied As a display element of the display device, an electroluminescent display device is used. This is demonstrated using a light-emitting element that utilizes electroluminescence. The light-emitting elements are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0239] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0240] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0241] FIG. 14 shows a display device to which digital time gray scale driving can be applied as an example of a semiconductor device to which the present invention is applied. FIG. 2 is a diagram illustrating an example of an element configuration.

[0242] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The oxide semiconductor layer (In—Ga—Zn—O-based film) shown in the first and second embodiments is This shows an example in which two n-channel transistors are used in the panel formation region in one pixel. .

[0243] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate. That's fine.

[0244] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0245] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0246] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0247] Also, when analog grayscale driving is used instead of digital time grayscale driving, the signal input is different. By doing so, the same pixel configuration as in FIG. 14 can be used.

[0248] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0249] Note that the pixel configuration shown in Fig. 14 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0250] Next, the configuration of the light emitting element will be described with reference to FIG. 15. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 15(A), (B), and (C). The TFTs 7001, 7011, and 7021, which are driving TFTs used in semiconductor devices, are actually It can be fabricated in the same manner as the thin film transistors shown in the first and second embodiments, and an In-Ga-Zn-O based film The present invention relates to a highly reliable thin film transistor including the oxide semiconductor layer.

[0251] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light emitting elements with a double-sided emission structure in which light is emitted from the side surface. The present invention can also be applied to light emitting devices having the following structure.

[0252] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0253] The driving TFT 7011 is an n-type TFT, and light emitted from the light emitting element 7012 is incident on the first electrode 701. 15(A) shows a cross-sectional view of a pixel when light is emitted to the driving TFT 7011. The light-emitting element 7 is formed on a light-transmitting conductive film 7017 electrically connected to the drain electrode layer of the light-emitting element 7. A first electrode 7013 of the OLED 012 is formed on the OLED 012. An EL layer 7014 is formed on the first electrode 7013. , and a second electrode 7015 are laminated in this order.

[0254] The light-transmitting conductive film 7017 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0255] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a small work function, specifically, For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth metals such as Yb and Er. In FIG. 15A, the film thickness of the first electrode 7013 is set to a thickness that allows light to pass through (preferably For example, an aluminum film having a thickness of 20 nm is used. is used as the first electrode 7013 .

[0256] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7017 and the first electrode 7013 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0257] The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane The partition wall 7019 is formed by using a photosensitive resin material, and is 13, and an opening is formed on the surface, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7019, In this case, the step of forming a resist mask can be omitted.

[0258] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7014 is made up of multiple layers, On the first electrode 7013 functioning as a The hole injection layer is laminated in this order. Note that it is not necessary to provide all of these layers.

[0259] The stacking order is not limited to the above, and the first electrode 7013 may function as an anode. Layers of hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked on top of 7013 in this order. However, when comparing power consumption, the first electrode 7013 may function as a cathode. On the first electrode 7013, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a By stacking the layers in the order of the incoming layers, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. Therefore, it is preferable.

[0260] In addition, various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, ITO, IZO, ZnO, etc. A transparent conductive material is preferable. In addition, a shielding film 7016, for example, a film for blocking light, is provided on the second electrode 7015. A light-shielding metal, a light-reflecting metal, or the like is used. In this embodiment mode, the second electrode 7015 and An ITO film is used as the shielding film 7016, and a Ti film is used as the shielding film 7017.

[0261] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. 15(A), the light-emitting element Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0262] In FIG. 15A, the light emitted from the light emitting element 7012 is reflected by the color filter layer. 7033, and passes through the insulating layer 7032, the oxide insulating layer 7031, the gate insulating layer 7060, and The light is then emitted through the substrate 7010.

[0263] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0264] The color filter layer 7033 is covered with an overcoat layer 7034, which is further provided with a protective insulating layer. 15A, the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 is made of a resin material such as acrylic resin, and is colored. It has the function of flattening the unevenness caused by the filter layer 7033.

[0265] Also, a protective insulating layer 7035 and an insulating layer 7032 are formed on the connecting electrode layer 7030. The contact hole is arranged at a position overlapping with the partition wall 7019 .

[0266] Next, a light emitting element with a dual emission structure will be described with reference to FIG.

[0267] In FIG. 15(B), a transparent TFT 7021 electrically connected to the drain electrode layer of the driving TFT 7021 is A first electrode 7023 of the light-emitting element 7022 is formed over a conductive film 7027 having the An EL layer 7024 and a second electrode 7025 are stacked in this order on the first electrode 7023 .

[0268] The light-transmitting conductive film 7027 may be formed of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide ketone A light-transmitting conductive film such as indium tin oxide to which indium is added can be used.

[0269] In addition, various materials can be used for the first electrode 7023. For example, When 23 is used as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, including these In addition to alloys (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as a cathode, and its film thickness is set to a thickness that allows light to pass through. (Preferably, about 5 nm to 30 nm) For example, an aluminum film having a thickness of 20 nm is A ZnO film is used as the cathode.

[0270] After a light-transmitting conductive film and an aluminum film are stacked, the film is selectively etched. The light-transmitting conductive film 7027 and the first electrode 7023 may be formed by the same method. This is preferable because etching can be performed using the same mask.

[0271] The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane The partition wall 7029 is formed by using a photosensitive resin material, and is 23, and an opening is formed on the surface, and the side wall of the opening is an inclined surface formed with a continuous curvature. When a photosensitive resin material is used as the partition wall 7029, In this case, the step of forming a resist mask can be omitted.

[0272] The EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 is at least It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7024 is made up of multiple layers, An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole transport layer, a hole transport layer, a hole transport layer, a hole injection layer, a hole transport ... The hole injection layer is laminated in this order. Note that it is not necessary to provide all of these layers.

[0273] The stacking order is not limited to the above, and the first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer may be laminated in this order. When comparing power consumption, the first electrode 7023 is used as a cathode, and an electron injection layer 7024 is provided on the cathode. The power consumption is reduced by stacking the electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order. This is preferable because

[0274] In addition, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, a material with a large work function can be used. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment mode, the second electrode 7025 is used as an anode, and an ITO film containing silicon oxide is used as an anode. Form.

[0275] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. 15(B), the light-emitting element The light emitted from 7022 travels between the second electrode 7025 and the first electrode 70 as shown by the arrows. 23It is fired on both sides.

[0276] In FIG. 15B, light emitted from the light-emitting element 7022 toward the first electrode 7023 One light passes through the color filter layer 7043 and enters the insulating layer 7042 and the oxide insulating layer 704 1. The light is emitted through the gate insulating layer 7070 and the substrate 7020.

[0277] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, or a photolithography method. Each is formed by an etching method using graphic technology.

[0278] The color filter layer 7043 is covered with an overcoat layer 7044, which is further provided with a protective insulating layer. Covered by layer 7045.

[0279] Also, a protective insulating layer 7045 and an insulating layer 7042 are formed on the connecting electrode layer 7040. The contact hole is arranged at a position overlapping with the partition wall 7029 .

[0280] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0281] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0282] In FIG. 15(C), a TFT 7001 which is a driving TFT is an n-type, and a light emitting element 7002 emits light. FIG. 15(C) is a cross-sectional view of a pixel in the case where incident light is transmitted to the second electrode 7005 side. The light emitting element 7002 is electrically connected to the drain electrode layer of the driving TFT 7001. A first electrode 7003 is formed on the first electrode 7003, an EL layer 7004 is formed on the first electrode 7003, and a second The electrodes 7005 are stacked in this order.

[0283] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a small work function, specifically, Li or Cs, Alkali metals such as Mg, Ca, Sr, and alkaline earth metals, including these In addition to alloys (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0284] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is It is sufficient to include a light-emitting layer, and it may be composed of a single layer or a plurality of layers stacked. When the EL layer 7004 is made up of a plurality of layers, On the first electrode 7003 used as a light-emitting layer, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport ... The insulating layer, the insulating film, and the insulating film are laminated in this order. Note that it is not necessary to provide all of these layers.

[0285] The stacking order is not limited to the above, and the hole injection layer may be formed on the first electrode 7003 used as an anode. Alternatively, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order.

[0286] In Figure 15(C), hole injection is performed on a laminated film in which a Ti film, an aluminum film, and a Ti film are laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked in this order, and Mg:A A laminate of a g-alloy thin film and an ITO film is formed.

[0287] However, when the TFT 7001 is an n-type, an electron injection layer and an electron transport layer are formed on the first electrode 7003. In terms of voltage in the drive circuit, stacking the light-emitting layer, hole transport layer, and hole injection layer in this order is preferable. This is preferable because it can suppress the temperature rise and reduce power consumption.

[0288] The second electrode 7005 is formed using a light-transmitting conductive material, for example, tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide, indium tin oxide, Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive film may also be used.

[0289] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the element structure shown in FIG. 15(C), the light-emitting element 7 Light emitted from 002 is emitted to the second electrode 7005 side as shown by the arrow.

[0290] In FIG. 15C, the drain electrode layer of the TFT 7001 is an oxide insulating layer 705 1, the first through the contact holes provided in the protective insulating layer 7052 and the insulating layer 7055. The planarization insulating layer 7053 is made of polyimide, acrylic, Resin materials such as benzocyclobutene, polyamide, and epoxy can be used. In addition to the above resin materials, low-k materials, siloxane resins, and PSG (phosphor Glass), BPSG (borophosphorus glass), etc. can be used. The planarization insulating layer 7053 may be formed by stacking a plurality of insulating films formed in the above manner. The method for forming the planarization insulating layer 7053 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be used.

[0291] In addition, a partition is provided to insulate the first electrode 7003 from the first electrode 7003 of an adjacent pixel. A partition wall 7009 is provided. The partition wall 7009 is made of polyimide, acrylic, polyamide, epoxy, etc. The partition wall 7009 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, an opening is formed on the first electrode 7003 using a photosensitive resin material, and the opening It is preferable that the sidewalls are formed as inclined surfaces having a continuous curvature. When a photosensitive resin material is used for the wall 7009, the process of forming a resist mask can be omitted. It is possible.

[0292] In the structure of FIG. 15C, when full color display is performed, for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is added to make four types. A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0293] In the structure of FIG. 15(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By combining a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0294] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be used to form an area color type light emitting device.

[0295] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0296] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0297] The thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically However, the current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the power supply is connected to the power supply.

[0298] Note that the semiconductor device shown in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0299] Next, a semiconductor device to which the thin film transistor shown in Embodiment 1 or 2 is applied will be described. The appearance and cross section of the light-emitting display panel (also called the light-emitting panel) are shown in FIG. FIG. 16(A) shows a thin film transistor and a light emitting element formed on a first substrate. 16(B) is a top view of the panel sealed between the first substrate and the second substrate by a sealing material; corresponds to the cross-sectional view taken along line HI in FIG. 16(A).

[0300] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0301] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 16B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0302] The thin film transistors 4509 and 4510 have an In-Ga-Zn-O based film as an oxide semiconductor layer. The highly reliable thin film transistors described in Embodiments 1 and 2 can be applied. In this embodiment mode, the thin film transistors 4509 and 4510 are n-channel thin film transistors. It is a transistor.

[0303] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the channel forming region. By placing the gate electrode at a position overlapping the channel formation region of the semiconductor layer, the The amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a metal or a silicon dioxide film, and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0304] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0305] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0306] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0307] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon nitride oxide film, a DLC film, etc.

[0308] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0309] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film.

[0310] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0311] The second substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In that case, use a glass plate, plastic plate, polyester film or acrylic A light-transmitting material such as a film is used.

[0312] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV In this embodiment, nitrogen is used as the filler. The material used was

[0313] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0314] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0315] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0316] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0317] (Embodiment 7) The semiconductor device to which the thin film transistor described in Embodiment 1 or 2 is applied can be used as electronic paper. Electronic paper can be used in any field that displays information. For example, electronic paper can be used to read electronic books (electronic Books), posters, train and other vehicle advertisements, credit cards, and other cards Examples of electronic devices are shown in Figures 17 and 18.

[0318] FIG. 17(A) shows a poster 2631 made of electronic paper. When printed materials are used, the advertisements are replaced manually, but when electronic paper is used, The display of the advertisement can be changed in a short time. Also, the display is stable without any distortion. The poster may be configured to be capable of transmitting and receiving information wirelessly.

[0319] FIG. 17(B) shows an advertisement 2632 inside a vehicle such as a train. When using printed paper, advertisements are exchanged manually, but with electronic paper, This allows you to change the display of your advertisements in a short time without requiring a lot of manpower. It is possible to obtain a stable image without any distortion. It may also be possible to use the following.

[0320] 18 shows an example of an electronic book. For example, an electronic book 2700 is housed in a housing 27 It consists of two housings, housing 2701 and housing 2703. 3 is integrated with a shaft portion 2711, and performs opening and closing operations around the shaft portion 2711. With this configuration, it is possible to operate like a paper book.

[0321] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 18) and An image can be displayed on the display unit 2707 in FIG.

[0322] 18 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0323] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0324] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0325] (Embodiment 8) The semiconductor device using the thin film transistor shown in the first or second embodiment can be used in various electronic devices. The present invention can be applied to electronic devices (including gaming machines). equipment (also called televisions or television receivers), monitors, displays, etc. for computers Digital cameras, digital video cameras, digital photo frames, mobile phones (mobile phones , also known as mobile phone devices), portable game machines, personal digital assistants, sound reproduction devices, pachinko machines Examples include large game consoles such as:

[0326] FIG. 19A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0327] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0328] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0329] FIG. 19(B) shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0330] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0331] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0332] FIG. 20(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 20(A) also includes a speaker unit 9884, a recording medium insertion unit 988, 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient if the configuration includes the semiconductor device, and other auxiliary equipment is provided as appropriate. The portable gaming machine shown in FIG. 20(A) can be used to play a game using a program recorded on a recording medium. It has the function of reading out the game program or data and displaying it on the display, and wirelessly communicating with other portable gaming machines. The portable gaming machine shown in FIG. 20(A) has the following functions: The function is not limited to this and may have various functions.

[0333] FIG. 20(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to this, and it is sufficient that the present invention is configured to include at least the semiconductor device according to the present invention. The configuration can be such that appropriate equipment is provided.

[0334] 21A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002 incorporated in the It is equipped with a speaker 1005, a microphone 1006, etc.

[0335] The mobile phone 1000 shown in FIG. 21A displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or sending an email can be performed using the display. This can be done by touching 1002 with a finger or the like.

[0336] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0337] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. Desirable.

[0338] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0339] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0340] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0341] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0342] FIG. 21B is also an example of a mobile phone. The mobile phone in FIG. 21B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can be used independently. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry.

[0343] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0344] (Embodiment 9) In this embodiment, the oxide semiconductor layer is in contact with a metal layer (conductive layer) or an oxide insulating layer. The phenomenon of oxygen migration in the oxide semiconductor layer is different between when the oxide semiconductor layer is amorphous and when it is crystalline. Explain the results of scientific calculations.

[0345] FIG. 24 shows a structure of a thin film transistor according to one embodiment of the present invention, in which an oxide semiconductor layer and a Schematic diagram of the state in which the metal layer and the oxide insulating layer that will become the source electrode layer and the drain electrode layer are in contact with each other. The arrows in the figure indicate the direction of the acid when they are in contact or heated. The direction of movement of the element is shown.

[0346] When oxygen vacancies occur in an I-type oxide semiconductor layer, it exhibits N-type conductivity. An oxide semiconductor layer that is N-type due to defects becomes I-type when oxygen is supplied in excess. In actual device processes, this effect is utilized to form the source and drain electrode layers. In the oxide semiconductor layer in contact with the metal layer, oxygen is attracted to the metal side, and a part of the contact area ( If the film thickness is thin, oxygen vacancies occur throughout the film thickness, making the film N-type and providing good contact with the metal layer. In addition, the oxide semiconductor layer in contact with the oxide insulating layer can be obtained by removing the oxide from the oxide insulating layer. Oxygen is supplied to the nitride semiconductor layer, and a part of the contact area (or the entire thickness direction if the film thickness is thin) The oxygen-excessive structure of the crystalline silicon becomes I-type and functions as the channel formation region of a thin-film transistor. It becomes like this.

[0347] In one embodiment of the present invention, a metal layer and a semiconductor layer are formed as a source electrode layer and a drain electrode layer. A crystalline region is formed in the region where the oxide insulating layer contacts the amorphous state. We used scientific calculations to confirm whether there were any differences in the form of oxygen movement between the two regions.

[0348] The model used for the scientific calculations is an In-Ga-Zn-O system amorphous and crystalline structure, with a rectangular parallelepiped. The specimen was designed with 10% oxygen loss from one side of the longitudinal direction (see Figure 25). The figure compares the oxygen distribution after 10 ns under the accelerated condition of 650°C. The respective conditions are shown in Tables 1 and 2.

[0349] [Table 1]

[0350] [Table 2]

[0351] Figure 26(A) shows the oxygen distribution when amorphous material is used, and Figure 26(B) shows the oxygen distribution when crystalline material is used. The dotted line shows the initial state, and the solid line shows the result (after 10 nsec). The change in distribution indicates that oxygen is moving in both amorphous and crystalline materials.

[0352] In the region with oxygen vacancies, the increase in oxygen atoms before and after the calculation was 15.9% for the amorphous and 15.9% for the crystalline. In other words, oxygen is more mobile in the amorphous state than in the crystalline state, and oxygen vacancies can be filled more easily. In other words, oxygen is relatively less mobile in crystals than in amorphous materials. This will be a problem.

[0353] Therefore, even in the structure in which the oxide semiconductor layer has a crystalline region according to one embodiment of the present invention, It was confirmed that oxygen migration occurs in the same way as when the oxide semiconductor layer is amorphous. Since oxygen is less mobile in the oxide semiconductor layer than in the amorphous state, oxygen is released from the oxide semiconductor layer. It was confirmed that it has the effect of suppressing [Explanation of symbols]

[0354] 400 boards 402 Gate insulating layer 410 Thin Film Transistor 411 terminal 412 connecting electrode 414 terminal 415 Transparent conductive film 416 Electrode 418 Transparent conductive film 421a Gate electrode layer 421b capacitive wiring 421c terminal 423 Oxide semiconductor layer 424a 1st area 424b Second area 424c Third area 424d 4th area 424e 5th area 425a Source electrode layer 425b Drain electrode layer 426a Oxide insulating layer 426b oxide insulating layer 428 Oxide insulating layer 429 Connecting Electrode 430 Thin Film Transistor 450 Thin Film Transistor 456a Oxide insulating layer 470 Thin Film Transistors 480a resist mask 480b resist mask 482a Resist mask 482b Resist mask 482c Resist mask 490 Thin-Film Transistors

Claims

1. A display device having a transistor, a first conductive layer, an insulating layer, an oxide semiconductor layer, a first oxide insulating layer, a second conductive layer, a third conductive layer, and a second oxide insulating layer; the first conductive layer functions as a gate electrode of the transistor, the insulating layer has a region disposed above the first conductive layer; the insulating layer functions as a gate insulating layer of the transistor, the oxide semiconductor layer has a region disposed above the insulating layer, a channel forming region of the transistor; the first oxide insulating layer has a region disposed above the oxide semiconductor layer, the second conductive layer has a region disposed above the oxide semiconductor layer; the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer has a region disposed above the oxide semiconductor layer, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor layer has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, a fifth region overlapping with the first oxide insulating layer, a third region between the first region and the fifth region, and a fourth region between the second region and the fifth region; a thickness of the oxide semiconductor layer in the third region and the fourth region is thinner than a thickness of the oxide semiconductor layer in the fifth region; the second oxide insulating layer has a region in contact with an upper surface of the third region, a region in contact with an upper surface of the first oxide insulating layer, and a region in contact with an upper surface of the fourth region; In a plan view of the transistor, the first conductive layer overlaps with the entire fifth region.

2. A display device having a transistor, a first conductive layer, an insulating layer, an oxide semiconductor layer, a first oxide insulating layer, a second conductive layer, a third conductive layer, and a second oxide insulating layer; the first conductive layer functions as a gate electrode of the transistor, the insulating layer has a region disposed above the first conductive layer; the insulating layer functions as a gate insulating layer of the transistor, the oxide semiconductor layer has a region disposed above the insulating layer, a channel forming region of the transistor; the first oxide insulating layer has a region disposed above the oxide semiconductor layer, the second conductive layer has a region disposed above the oxide semiconductor layer; the second conductive layer functions as one of a source electrode and a drain electrode of the transistor, the third conductive layer has a region disposed above the oxide semiconductor layer, the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor layer has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, a fifth region overlapping with the first oxide insulating layer, a third region between the first region and the fifth region, and a fourth region between the second region and the fifth region; a thickness of the oxide semiconductor layer in the third region and the fourth region is thinner than a thickness of the oxide semiconductor layer in the fifth region; the second oxide insulating layer has a region in contact with an upper surface of the third region, a region in contact with an upper surface of the first oxide insulating layer, and a region in contact with an upper surface of the fourth region; the first conductive layer overlaps with the entire fifth region in a plan view of the transistor; The display device, wherein the first oxide insulating layer is not in contact with the second conductive layer and is not in contact with the third conductive layer.

3. In claim 1 or claim 2, The oxide semiconductor layer includes an In—Ga—Zn—O-based oxide semiconductor.

4. In claim 1 or claim 2, The oxide semiconductor layer includes an In—O-based oxide semiconductor.

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