Display device

Abstract

To provide a display device that can suppress a decrease in reliability.SOLUTION: A display device comprises: a substrate; a first inorganic insulating layer; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer and overlapping a circumferential edge portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer and aligned in a first direction along an end of the substrate in a peripheral area; and a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers. The second inorganic insulating layer has a plurality of first apertures overlapping the second metal layers, and the organic insulating layer has a plurality of second apertures overlapping the first apertures via which the first metal layers and the second metal layers are in contact with each other, and a plurality of first slits formed between adjacent second apertures via which the second inorganic insulating layer and the first inorganic insulating layer are in contact with each other.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer as well as functional layers such as a hole transport layer and an electron transport layer. Technology to prevent a decrease in reliability is needed for such display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, a display device comprises a substrate, a first inorganic insulating layer arranged above the substrate across a display area that displays an image and a peripheral area around the display area, an organic insulating layer arranged on the first inorganic insulating layer, a lower electrode arranged on the organic insulating layer in the display area, a second inorganic insulating layer arranged on the organic insulating layer and overlapping the peripheral edge of the lower electrode, an organic layer arranged on the lower electrode, an upper electrode arranged on the organic layer, and a plurality of first metal layers arranged on the first inorganic insulating layer in the peripheral area and aligned in a first direction along the edge of the substrate, and a plurality of second metal layers arranged on the second inorganic insulating layer and electrically connected to the first metal layer.

[0006] The second inorganic insulating layer has a plurality of first openings overlapping the second metal layer, and the organic insulating layer has a plurality of second openings overlapping the first openings and where the first metal layer and the second metal layer contact, and a plurality of first slits formed between adjacent second openings and where the second inorganic insulating layer and the first inorganic insulating layer contact.

[0007] According to another embodiment, a display device includes a substrate, a first inorganic insulating layer disposed above the substrate across a display area where an image is displayed and a peripheral area around the display area, an organic insulating layer disposed on the first inorganic insulating layer, a lower electrode disposed on the organic insulating layer in the display area, a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral portion of the lower electrode, an organic layer disposed on the lower electrode, an upper electrode disposed on the organic layer, a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area and aligned in a first direction along an edge of the substrate, and a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers. The second inorganic insulating layer has a third opening, and the third opening overlaps the plurality of first metal layers.

[0008] According to yet another embodiment, a display device includes a substrate, a first inorganic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area around the display area, an organic insulating layer disposed on the first inorganic insulating layer, a lower electrode disposed on the organic insulating layer in the display area, a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral portion of the lower electrode, an organic layer disposed on the lower electrode, an upper electrode disposed on the organic layer, and a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area and aligned in a first direction along an edge of the substrate. In the peripheral area, the organic insulating layer is located between the lower electrode and the first metal layer and has slits formed along the first direction. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a plan view showing an example of the configuration of an area including a plurality of pads of the display device shown in FIG. [Figure 5] FIG. 5 is a plan view showing an example of the configuration of an area including a plurality of pads of the display device shown in FIG. [Figure 6] FIG. 6 is a plan view showing the metal layer shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view of the display device taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a plan view showing an example of the configuration of an area including a plurality of pads in a display device according to a comparative example. [Figure 10] FIG. 10 is a cross-sectional view of the display device taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view of the display device taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a plan view showing an example of the configuration of an area including a plurality of pads in the display device according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view of the display device taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view of the display device taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a plan view showing an example of the configuration of an area including a plurality of pads in the display device according to the third embodiment. [Figure 16] FIG. 16 is a plan view showing an example of the configuration of an area including a plurality of pads in the display device according to the third embodiment. [Figure 17] FIG. 17 is a cross-sectional view of the display device taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a cross-sectional view of the display device taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a plan view showing an example of the configuration of an area including pads of a display device according to the fourth embodiment. [Figure 20] FIG. 20 is a cross-sectional view of the display device taken along the line XX-XX in FIG. [Figure 21] FIG. 21 is a cross-sectional view of the display device taken along line XXI-XXI in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those skilled in the art will readily conceive of appropriate modifications that maintain the gist of the invention and are therefore naturally within the scope of the present invention.

[0011] In addition, in order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0012] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0013] In the following explanation, "overlapping" refers not only to a case where another element overlaps a target element from the third direction Z, but also to a case where another element overlaps a target element from the direction opposite to the third direction Z. Furthermore, "overlapping" refers not only to a case where the target elements are in direct contact with each other, but also to a case where the target elements are spaced apart from each other, or a case where another element is located between the target elements.

[0014] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet devices, smartphones, mobile phone devices, and wearable devices.

[0015] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes a display panel PNL. The display panel PNL has an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0016] In this embodiment, the substrate 10 has a rectangular shape in plan view that is elongated in the second direction Y. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0017] The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA, on a substrate 10. The display area DA has a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y.

[0018] Each pixel PX includes multiple subpixels SP. In one example, the pixel PX includes a first color subpixel SP1, a second color subpixel SP2, and a third color subpixel SP3. The first color, second color, and third color are different from one another. Note that the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0019] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0020] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0021] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors. The display element 20 is an organic light emitting diode (OLED) as a light emitting element, and may be called an organic EL element.

[0022] The display device DSP has a plurality of pads PD in the peripheral area SA. The plurality of pads PD constitute, for example, pads for a touch panel. The plurality of pads PD are aligned in one direction along the panel edge PNLE. Here, the edge includes the edge and the area nearby. The panel edge PNLE includes the edge of the substrate 10. In this embodiment, the direction along the edge of the substrate 10 corresponds to the first direction X.

[0023] Each of the pads PD extends in the second direction Y, but is not limited to this. For example, some of the pads PD may extend in an oblique direction. The pads PD are formed, for example, by a plurality of metal layers, which will be described later. Such a plurality of pads PD are electrically connected, for example, to a flexible printed circuit board FPC, which is indicated by a dashed line.

[0024] Fig. 2 is a diagram showing an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP2 and SP3 are aligned in the second direction Y. Subpixels SP1 and SP2 are aligned in the first direction X, and subpixels SP1 and SP3 are aligned in the first direction X.

[0025] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0026] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example shown in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0027] An insulating layer 5 and partition walls 6 are arranged in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0028] The partition walls 6 overlap the insulating layer 5 in a plan view. The partition walls 6 are formed in a lattice shape surrounding the openings AP1, AP2, and AP3. Similar to the insulating layer 5, the partition walls 6 can also be said to have openings in the subpixels SP1, SP2, and SP3.

[0029] The subpixels SP1, SP2, and SP3 each include display elements 201, 202, and 203 as the display element 20. The display element 201 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap the insulating layer 5 in a planar view. Here, the peripheral portions include the edges and the areas nearby.

[0030] The display element 202 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with the aperture AP2. The peripheral edges of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap the insulating layer 5 in a plan view.

[0031] The display element 203 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with the aperture AP3. The peripheral edges of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap the insulating layer 5 in a plan view.

[0032] 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect their exact shapes.

[0033] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode.

[0034] The lower electrode LE1 is connected to the pixel circuit 1 (shown in FIG. 1) of the subpixel SP1 through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0035] 2, the areas of openings AP1, AP2, and AP3 are different from one another. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. In other words, the area of ​​lower electrode LE1 exposed through opening AP1 is larger than the area of ​​lower electrode LE2 exposed through opening AP2, and the area of ​​lower electrode LE2 exposed through opening AP2 is larger than the area of ​​lower electrode LE3 exposed through opening AP3.

[0036] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on a substrate 10. The circuit layer 11 includes various circuits such as the pixel circuits 1 shown in Fig. 1, and various wirings such as scanning lines GL, signal lines SL, and power supply lines PL.

[0037] The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is disposed on the circuit layer 11. The insulating layer 12 has the function of flattening unevenness caused by the circuit layer 11. The insulating layer 12 is an organic insulating layer.

[0038] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and spaced apart from one another. The insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The insulating layer 5 is an inorganic insulating layer. In this embodiment, the insulating layer 5 corresponds to the second inorganic insulating layer.

[0039] The opening AP1 in the insulating layer 5 overlaps the lower electrode LE1, the opening AP2 overlaps the lower electrode LE2, and the opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the insulating layer 5.

[0040] The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Although the contact holes in the insulating layer 12 are omitted in FIG. 3, they correspond to the contact holes CH1, CH2, and CH3 in FIG. 2.

[0041] The partition wall 6 includes a conductive lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The lower portion 61 of the partition wall 6 shown on the right side of the drawing is located between the openings AP1 and AP2. The lower portion 61 of the partition wall 6 shown on the left side of the drawing is located between the openings AP2 and AP3.

[0042] The lower portion 61 may be a single layer or a multi-layer body. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0043] 3, the lower portion 61 has a bottom layer 63 disposed on the insulating layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example shown in FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0044] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0045] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral edge located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0046] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral edge located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0047] 3, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0048] The cap layer CP1 is disposed on the upper electrode UE1, the cap layer CP2 is disposed on the upper electrode UE2, and the cap layer CP3 is disposed on the upper electrode UE3.

[0049] The encapsulating layer SE1 is disposed on the cap layer CP1, in contact with the partition wall 6, and continuously covers each element of the subpixel SP1. The encapsulating layer SE2 is disposed on the cap layer CP2, in contact with the partition wall 6, and continuously covers each element of the subpixel SP2. The encapsulating layer SE3 is disposed on the cap layer CP3, in contact with the partition wall 6, and continuously covers each element of the subpixel SP3.

[0050] 3, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are spaced apart from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 that are located in the opening AP1 (parts that form the display element 201).

[0051] Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition wall 6 surrounding the subpixel SP2, and these portions are spaced apart from the portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (the portions that constitute the display element 202).

[0052] Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition wall 6 surrounding the subpixel SP3, and these portions are spaced apart from the portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (the portions that constitute the display element 203).

[0053] Ends of the sealing layers SE1, SE2, and SE3 are located on the partition wall 6. In the example shown in Fig. 3, the ends of the sealing layers SE1 and SE2 located on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart, and the ends of the sealing layers SE2 and SE3 located on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart.

[0054] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0055] The insulating layer 5, the sealing layers SE1, SE2, SE3 and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al2O3).

[0056] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material that can be used for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb).

[0057] The metal material of the shaft layer 64 may be, for example, aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi). The shaft layer 64 may also be made of an insulating material.

[0058] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer made of a metal material and an upper layer made of a conductive oxide. The metal material that forms the lower layer can be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy.

[0059] The conductive oxide forming the upper layer can be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). The upper portion 62 may have a single layer structure made of a metal material. Furthermore, the upper portion 62 may include a layer made of an insulating material.

[0060] The lower electrodes LE1, LE2, and LE3 are multilayer bodies including a transparent electrode made of an oxide conductive material such as ITO and a metal electrode made of a metal material such as silver.

[0061] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials.

[0062] In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength region, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength region, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength region. Each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0063] The upper electrodes UE1, UE2, and UE3 are made of a metal material such as an alloy of magnesium and silver (MgAg). The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. The multiple thin films are all transparent and have different refractive indices.

[0064] The circuit layer 11, the insulating layer 12, and the insulating layer 5 shown in FIG. 3 are disposed across the display area DA and the peripheral area SA.

[0065] Fig. 4 and Fig. 5 are plan views showing an example of the configuration of an area including a plurality of pads PD of the display device DSP shown in Fig. 1. Fig. 6 is a plan view showing the metal layers M1, M2, M3, and M4 shown in Fig. 5.

[0066] 4 and 5 show the vicinity of the panel edge PNLE in the peripheral area SA. In FIGS. 4 and 5, the display area DA is formed in the upper part of the figure. In FIG. 4, the flexible printed circuit board FPC shown in FIG. 1 is indicated by a dashed line. In FIG. 5, the insulating layer 5 is omitted from the configuration example shown in FIG. 4.

[0067] 4 and 5, the pads PD are aligned in the first direction X and extend in the second direction Y. As described above, the insulating layer 5 and the insulating layer 12 are formed up to the region including the pads PD (peripheral region SA).

[0068] The insulating layer 5 is formed up to the panel edge PNLE as shown in Fig. 4. In contrast, the insulating layer 12 is not formed up to the panel edge PNLE as shown in Fig. 5. In other words, the peripheral area SA has an area A11 in the panel edge PNLE where the insulating layer 12 is not formed.

[0069] The insulating layer 5 has openings 51 overlapping with the pads PD, as shown in Fig. 4. The insulating layer 12 has openings 121 overlapping with the pads PD, as shown in Fig. 5. In this embodiment, the openings 51 correspond to the first openings, and the openings 121 correspond to the second openings.

[0070] The opening 51 of the insulating layer 5 overlaps the opening 121 of the insulating layer 12. In the example shown in Figures 4 and 5, the opening 51 and the opening 121 overlap one pad PD.

[0071] The openings 51 in the insulating layer 5 and the openings 121 in the insulating layer 12 extend in a direction different from the direction in which the pads PD are arranged. The openings 51 and 121 extend, for example, in the second direction Y. Specifically, the openings 51 and 121 have a rectangular shape that is elongated in the second direction Y.

[0072] 4, the area of ​​opening 51 in insulating layer 5 is larger than the area of ​​opening 121 in insulating layer 12 in a plan view. The edge of opening 51 is located outside the edge of opening 121. Insulating layer 12 is exposed from opening 51.

[0073] 5, the insulating layer 12 further has a slit 123. In this embodiment, the slit 123 corresponds to a first slit. The slit 123 is located between adjacent pads PD. In other words, the slit 123 is formed between the openings 121 of the insulating layer 12 (openings 51 of the insulating layer 5) that are adjacent to each other.

[0074] The slit 123 extends in the second direction Y. The multiple slits 123 are aligned in the first direction X. In the example shown in FIG. 5, the slits 123 open toward the panel edge portion PNLE. The length of the slit 123 in the second direction Y is greater than the length of the opening 121 in the insulating layer 12 in the second direction Y. The slit 123 is connected to the region A11 of the panel edge portion PNLE.

[0075] 5, the insulating layer 12 further has, in the peripheral region SA, a slit 125 and slits 127 and 129. In this embodiment, the slit 125 corresponds to a second slit, and the slits 127 and 129 correspond to a third slit.

[0076] The slits 125 are located between the display area DA (lower electrodes LE1, LE2, LE3) and the pads PD. The slits 125 are formed along the first direction X. The width of the slits 125 in the first direction X is greater than the distance between the pads PD arranged at both ends in the first direction X.

[0077] The slits 127 and 129 are connected to both ends of the slit 125 in the first direction X. The slits 127 and 129 are formed in the second direction Y from the slit 125 toward the panel end PNLE.

[0078] The slits 127 and 129 are connected to the region A11 of the panel edge portion PNLE. The insulating layer 5 overlaps the slits 123, 125, 127, and 129 and the region A11 in plan view.

[0079] In plan view, the pads PD are surrounded by the slits 125 and the slits 127 and 129. From another perspective, the pads PD are separated from the insulating layer 12 formed around them by the slits 125 and the slits 127 and 129. Here, the insulating layer 12 formed around them includes the insulating layer 12 formed on the display area DA side.

[0080] The display device DSP further includes a plurality of metal layers M1, M2, M3, and M4, as shown in Fig. 6. In this embodiment, the metal layer M1 corresponds to the fourth metal layer, the metal layer M2 corresponds to the third metal layer, the metal layer M3 corresponds to the first metal layer, and the metal layer M4 corresponds to the second metal layer.

[0081] Each of the metal layers M1, M2, M3, and M4 extends in the second direction Y. Adjacent metal layers M1, M2, M3, and M4 are arranged at intervals in the first direction X. The pad PD is composed of the metal layers M3 and M4.

[0082] Fig. 7 is a cross-sectional view of the display device DSP taken along line VII-VII in Fig. 5. Fig. 8 is a cross-sectional view of the display device DSP taken along line VIII-VIII in Fig. 5. The circuit layer 11 has insulating layers 111, 112, and 113. The above-mentioned metal layers M1 and M2, together with the insulating layers 111, 112, and 113, form the circuit layer 11.

[0083] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The metal layer M1 is disposed on the insulating layer 111. The metal layer M1 is formed in the same layer as the scanning lines GL, for example.

[0084] The insulating layer 112 is an inorganic insulating layer and is disposed on the insulating layer 111 and the metal layer M1. The insulating layer 112 has contact holes CH4 and CH5.

[0085] The metal layer M2 is disposed on the insulating layer 112. From another perspective, the metal layer M1 is disposed between the substrate 10 and the metal layer M2. The metal layer M2 is formed in the same layer as the signal line SL, for example.

[0086] 8, the metal layer M2 does not overlap the slit 125. The metal layer M2 is electrically connected to the metal layer M1 via contact holes CH4 and CH5.

[0087] Specifically, the metal layer M2 has a first portion P1 connected to the metal layer M1 through a contact hole CH4 and a second portion P2 connected to the metal layer M1 through a contact hole CH5. The second portion P2 extends toward the display area DA.

[0088] The first portion P1 is aligned with and spaced apart from the second portion P2 in the second direction Y. In other words, in the metal layer M2, a gap G1 is formed between the first portion P1 and the second portion P2.

[0089] 8, the length of the slit 125 in the second direction Y is smaller than the length of the gap G1 in the second direction Y. A portion of the metal layer M1 overlaps the slit 125 with the gap G1 therebetween.

[0090] The insulating layer 113 is an inorganic insulating layer and is disposed on the insulating layer 112 and the metal layer M2. In this embodiment, the insulating layer 113 corresponds to the first inorganic insulating layer. The metal layer M2 is disposed between the substrate 10 and the insulating layer 113. The insulating layer 113 has a contact hole CH6.

[0091] The metal layer M3 is located directly above the metal layer M1 and is disposed on the insulating layer 113. The metal layer M3 is electrically connected to the metal layer M2. Specifically, the metal layer M3 is in contact with the first portion P1 of the metal layer M2 through the contact hole CH6.

[0092] The insulating layer 12 is disposed on the insulating layer 113 and the metal layer M3. The metal layer M3 is exposed through an opening 121 in the insulating layer 12. As shown in FIGS. 7 and 8, the insulating layer 12 covers the entire periphery of the metal layer M3.

[0093] 7, insulating layer 113 is exposed from insulating layer 12 at slits 123. Insulating layer 5 is disposed on insulating layer 12. Insulating layer 5 contacts insulating layer 113 at slits 123. In other words, insulating layer 113 is covered by insulating layer 5 at slits 123.

[0094] As shown in Fig. 8, insulating layer 113 is exposed from insulating layer 12 at slit 125. Insulating layer 5 contacts insulating layer 113 at slit 125. In other words, insulating layer 113 is covered by insulating layer 5 at slit 125. Although not shown in Figs. 7 and 8, insulating layer 5 also contacts insulating layer 113 at slits 127 and 129.

[0095] The metal layer M4 is located directly above the metal layer M3 and is disposed on the insulating layer 5. The metal layer M4 contacts the metal layer M3 exposed from the opening 121 of the insulating layer 12 through the opening 51 of the insulating layer 5. In other words, the metal layer M4 is electrically connected to the metal layer M3 through the openings 51 and 121. The metal layer M4 overlaps the peripheral portion 121E of the opening 121.

[0096] The insulating layers 111, 112, and 113 are made of silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 5 is made of, for example, silicon oxynitride.

[0097] The metal layers M2, M3, and M4 are formed, for example, from multiple layers. One example includes two titanium layers made of a titanium-based material and an aluminum layer made of an aluminum-based material located between the two titanium layers. Note that at least one of the metal layers M2, M3, and M4 may be formed by disposing an aluminum layer between layers made of a molybdenum-based material.

[0098] Fig. 9 is a plan view showing an example of the configuration of a region including a plurality of pads PD of a display device DSP10 according to a comparative example. Fig. 10 is a cross-sectional view of the display device DSP10 taken along line XX in Fig. 9. Fig. 11 is a cross-sectional view of the display device DSP10 taken along line XI-XI in Fig. 9. Fig. 9 shows only openings 51 in the insulating layer 5.

[0099] The display device DSP10 according to the comparative example differs from the display device DSP according to this embodiment in that the insulating layer 12 does not have the slits 123, 125, 127, and 129.

[0100] In the display device DSP10, as shown in FIG. 10, an insulating layer 12 is located between adjacent openings 121, so that the insulating layer 5 is in contact with the insulating layer 12 between adjacent openings 121.

[0101] In other words, the insulating layer 5 is not in contact with the insulating layer 113 between adjacent openings 121. Moreover, as shown in Fig. 11 , the insulating layer 5 is also in contact with the insulating layer 12 in the region where the slit 125 is formed in this embodiment.

[0102] The adhesive strength between insulating layer 5, which is an inorganic insulating layer, and insulating layer 12, which is an organic insulating layer, is weaker than the adhesive strength between insulating layer 5, which is also an inorganic insulating layer, and insulating layer 113. Therefore, in display device DSP10, insulating layer 5 is likely to peel off from insulating layer 12. Such peeling reduces the reliability of the display device.

[0103] In contrast, in the display device DSP according to this embodiment, the insulating layer 5 and the insulating layer 113 are in contact with each other and are firmly adhered to each other. As a result, compared to when the insulating layer 5 is in contact with the insulating layer 12, the adhesion between the insulating layer 5 and the base layer is improved, and peeling of the insulating layer 5 can be suppressed. As a result, with this embodiment, it is possible to suppress a decrease in reliability.

[0104] 9 and 11, in the display device DSP10 according to the comparative example, the pad PD is connected to the insulating layer 12 formed around it. Therefore, moisture easily penetrates into the pad PD from the periphery through the insulating layer 12.

[0105] The moisture is, for example, moisture in the atmosphere (outside air). In Figure 9, the path of moisture penetration is indicated by arrow W. The penetrated moisture may corrode the metal layers M3 and M4 that constitute the pad PD. Such corrosion may cause peeling of the insulating layer 5 and the metal layers M3 and M4.

[0106] In this embodiment, the pad PD is separated from the insulating layer 12 formed around it by the slits 125, 127, and 129. This makes it difficult for moisture to penetrate the pad PD from the outside through the slits 125, 127, and 129, as shown by the arrow W in FIG. 5. As a result, corrosion that could cause peeling is unlikely to occur in the metal layers M3 and M4. In this way, this embodiment can suppress a decrease in reliability.

[0107] 7 and 8, the insulating layer 12 covers the entire periphery of the metal layer M3. In other words, the periphery of the metal layer M3 is not exposed. This prevents the aluminum layer from being undesirably corroded by the etching solution used in the process of forming the lower electrode on the insulating layer 12.

[0108] 8, the metal layer M2 does not overlap the slit 125. This makes it possible to prevent undesired erosion of the metal layer M2 in the region overlapping the slit 125 by the etching solution (disconnection of the metal layer M2) in the step of forming the slit 125 in the manufacturing process.

[0109] As described above, the configuration of this embodiment can provide a display device DSP that can suppress a decrease in reliability. In addition, various other advantageous effects can be obtained from this embodiment.

[0110] Next, other embodiments will be described. In the configurations of the following embodiments, the same configurations as those of the first embodiment can be applied to parts that are not specifically mentioned.

[0111] [Second embodiment] Fig. 12 is a plan view showing an example of the configuration of a region including a plurality of pads PD of the display device DSP according to this embodiment. Fig. 13 is a cross-sectional view of the display device DSP taken along line XIII-XIII in Fig. 12. Fig. 14 is a cross-sectional view of the display device DSP taken along line XIV-XIV in Fig. 12. Fig. 12 shows an enlarged view of the vicinity of two pads PD.

[0112] This embodiment differs from the first embodiment in that the insulating layer 5 covers the peripheral edge 121E of the opening 121 in the insulating layer 12.

[0113] 12, the area of ​​opening 121 in insulating layer 12 is larger than the area of ​​opening 51 in insulating layer 5 in a plan view. The edge of opening 121 is located outside the edge of opening 51. Insulating layer 12 is not exposed from opening 51.

[0114] 13 and 14, the insulating layer 5 covers the peripheral portion 121E of the opening 121 of the insulating layer 12. In other words, the insulating layer 12 is not exposed from the insulating layer 5. From another perspective, the metal layer M4 is not in contact with the insulating layer 12.

[0115] The configuration of this embodiment can also achieve the same effects as those of the first embodiment. In this embodiment, the insulating layer 5 covers the peripheral portion 121E of the opening 121 in the insulating layer 12. This makes it possible to prevent undesired erosion (disappearance) of the insulating layer 12 in the step of forming the opening 51 in the insulating layer 5 in the manufacturing process. This embodiment can further prevent a decrease in reliability.

[0116] [Third embodiment] Fig. 15 is a plan view showing an example of the configuration of a region including a plurality of pads PD of the display device DSP according to this embodiment. Fig. 16 is a plan view showing an example of the configuration of a region including a plurality of pads PD of the display device DSP according to this embodiment. Fig. 17 is a cross-sectional view of the display device DSP taken along line XVII-XVII in Fig. 16. Fig. 18 is a cross-sectional view of the display device DSP taken along line XVIII-XVIII in Fig. 16. Fig. 16 shows an enlarged view of the vicinity of two pads PD.

[0117] This embodiment differs from the above-described embodiments in that the insulating layer 5 has an opening having a shape different from the opening 51 in the above-described embodiments.

[0118] The insulating layer 5 has an opening 53 as shown in FIG. 15. In this embodiment, the opening 53 corresponds to a third opening. The opening 53 overlaps multiple pads PD. In other words, the opening 53 overlaps multiple metal layers M3 as shown in FIG. 16. The opening 53 is formed along the first direction X. The slit 123 of the insulating layer 12 overlaps the opening 53 of the insulating layer 5. The insulating layer 12 is exposed from the opening 53 as shown in FIGS. 15 and 18.

[0119] The opening 53 has edges 531 and 533. In this embodiment, the edge 531 corresponds to a first edge, and the edge 533 corresponds to a second edge. The edges 531 and 533 each extend in a first direction X. The edge 531 faces the edge 533 in a second direction Y. The edges 531 and 533 are located outside the edge of the opening 121 in the insulating layer 12.

[0120] The edges 531 and 533 have a plurality of protrusions 531P and 533P, respectively, as shown in Fig. 16. In this embodiment, the protrusions 531P correspond to the first protrusions, and the protrusions 533P correspond to the second protrusions.

[0121] The protrusion 531P protrudes in the second direction Y, and the protrusion 533P protrudes in the direction opposite to the second direction Y. From another perspective, the protrusions 531P and 533P protrude in directions approaching each other.

[0122] The protrusion 531P is disposed at a distance from the protrusion 533P in the second direction Y. The protrusions 531P and 533P have a tapered shape toward their tips. The tips of the protrusions 531P and 533P overlap the slit 125.

[0123] 17, the insulating layer 5 is not formed between adjacent pads PD (metal layers M3, M4). In other words, the peripheral area SA has an area A13 between adjacent pads PD where the insulating layer 5 is not formed.

[0124] The configuration of this embodiment can also achieve the same effects as those of the first embodiment. During etching in the manufacturing process, residues from the members constituting the pads PD (for example, the metal layer M4) may be generated between adjacent pads PD. The residues are generated, for example, along the step portions of the insulating layer 5. Such residues may short-circuit adjacent pads PD, causing defects.

[0125] In this embodiment, edges 531, 533 of opening 53 in insulating layer 5 have protrusions 531P, 533P, respectively. This allows the material constituting metal layer M4 to be removed at the tips of protrusions 531P, 533P during etching in the manufacturing process, thereby suppressing the generation of residue. This makes it less likely that a short circuit will occur between adjacent pads PD. This embodiment further suppresses a decrease in reliability.

[0126] [Fourth embodiment] Fig. 19 is a plan view showing an example of the configuration of a region including a plurality of pads PD of a display device DSP according to this embodiment. Fig. 20 is a cross-sectional view of the display device DSP taken along line XX-XX in Fig. 19. Fig. 21 is a cross-sectional view of the display device DSP taken along line XXI-XXI in Fig. 19. Fig. 19 shows an enlarged view of the vicinity of two pads PD.

[0127] This embodiment differs from the third embodiment in that, when the opening 53 is formed in the manufacturing process, the insulating layer 12 is removed in the region overlapping the opening 53.

[0128] 19 to 21, the insulating layer 12 is not disposed in a region overlapping the opening 53. The insulating layers 5 and 12 are not formed between adjacent pads PD (metal layers M3 and M4) as shown in Fig. 20. In other words, the peripheral area SA has an area A15 between adjacent pads PD where the insulating layers 5 and 12 are not formed.

[0129] The configuration of this embodiment can also achieve the same effects as in the first embodiment. In this embodiment, the peripheral edge of the metal layer M3 is not covered with the insulating layer 12. If there is no step in the manufacturing process after the step of forming the opening 53 in which the aluminum layer that constitutes the metal layer M3 is eroded by an etching solution, then the configuration of this embodiment will not pose any problems.

[0130] All display devices that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices described above as embodiments of the present invention are within the scope of the present invention as long as they incorporate the gist of the present invention. Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and these modifications are also considered to be within the scope of the present invention. For example, displays in which a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits processes or modifies conditions, to the above-described embodiments are also within the scope of the present invention as long as they incorporate the gist of the present invention.

[0131] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0132] 1...pixel circuit, 2...pixel switch, 3...driving transistor, 4...capacitor, 5...insulating layer, 6...partition, 10...substrate, 11...circuit layer, 12...insulating layer, 13...resin layer, 14...sealing layer, 15...resin layer, 20...display element, 51...opening, 53...opening, 61...lower part, 62...upper part, 111...insulating layer, 112...insulating layer, 113...insulating layer, 121...opening, 121E...periphery, 123, 125, 127...slits, 531...edge, 531P...protrusion, 533...edge, 533P...protrusion, DA...display area, DSP...display device, G1...gap, M1...metal layer, M2...metal layer, M3...metal layer, M4...metal layer, P1...first part, P2...second part, PD...pad.

Claims

1. A substrate; a first inorganic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area around the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display area; a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers arranged on the first inorganic insulating layer in the peripheral region and aligned in a first direction along an edge of the substrate; a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers; the second inorganic insulating layer has a plurality of first openings overlapping the second metal layer; the organic insulating layer has a plurality of second openings overlapping the first openings and in which the first metal layer and the second metal layer are in contact with each other, and a plurality of first slits formed between adjacent second openings and in which the second inorganic insulating layer and the first inorganic insulating layer are in contact with each other. Display device.

2. Each of the plurality of first slits is open toward an end of the substrate. The display device according to claim 1 .

3. the second metal layer overlaps the peripheral edge of the second opening in the organic insulating layer; The display device according to claim 2 .

4. the second inorganic insulating layer covers a peripheral portion of the second opening of the organic insulating layer; The display device according to claim 1 .

5. A substrate; a first inorganic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area around the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display area; a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers arranged on the first inorganic insulating layer in the peripheral region and aligned in a first direction along an edge of the substrate; a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layers; the second inorganic insulating layer has a third opening; the third opening overlaps the plurality of first metal layers; Display device.

6. the third opening has a first edge and a second edge facing each other in a second direction intersecting the first direction; the first edge is located between adjacent second metal layers and has a plurality of first protrusions protruding toward the second edge; the second edge is located between adjacent second metal layers and has a plurality of second protrusions protruding toward the first edge; The display device according to claim 5 .

7. the organic insulating layer overlaps the first protrusion and the second protrusion, and has a plurality of first slits formed between adjacent first metal layers; The display device according to claim 6.

8. the peripheral region has a region between adjacent first metal layers where the second inorganic insulating layer is not formed; The display device according to claim 6.

9. the organic insulating layer is not disposed in a region overlapping the third opening; The display device according to claim 6.

10. the organic insulating layer further includes a second slit located between the lower electrode and the first metal layer in the peripheral region and formed along the first direction; The display device according to claim 1 or 5.

11. a third metal layer disposed between the first inorganic insulating layer and the substrate, electrically connected to the first metal layer, and not overlapping the second slit; The display device according to claim 10.

12. a fourth metal layer disposed between the third metal layer and the substrate, electrically connected to the third metal layer, and overlapping the second slit; The display device according to claim 11.

13. the organic insulating layer further has a third slit connected to the second slit and formed toward an end of the substrate; The display device according to claim 10.

14. A substrate; a first inorganic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area around the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display area; a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers arranged on the first inorganic insulating layer in the peripheral region and aligned in a first direction along an edge of the substrate; the organic insulating layer is located between the lower electrode and the first metal layer in the peripheral region and has a slit formed along the first direction; Display device.

15. In the peripheral region, the semiconductor device further includes a plurality of second metal layers disposed on the second inorganic insulating layer and electrically connected to the first metal layer. The display device according to claim 14.

16. a third metal layer disposed between the first inorganic insulating layer and the substrate, electrically connected to the first metal layer, and not overlapping the slit; The display device according to claim 15.

17. a fourth metal layer disposed between the third metal layer and the substrate, electrically connected to the third metal layer, and overlapping the slit; The display device according to claim 16.

18. the third metal layer has a first portion connected to the first metal layer and the fourth metal layer, and a second portion connected to the fourth metal layer. The display device according to claim 17.

19. the fourth metal layer overlaps the slit with a gap formed between the first portion and the second portion therebetween; 19. The display device according to claim 18.

20. the second inorganic insulating layer is in contact with the first inorganic insulating layer at the slit; The display device according to claim 14.

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