Systems and methods for extended long range communication in wireless local area networks (WLANS)

Abstract

To provide a mode to support a low PHY (physical layer) rate in a WLAN in order to achieve extended (or enhanced) long range (ELR) communication.SOLUTION: In a communication system, a transmitter identifies a target data rate for transmitting data over a channel with a frequency bandwidth. Based on the target data rate, the transmitter selects a forward error correction (FEC) code, a code rate, a modulation scheme, and a number of resource units (RUs) within the frequency bandwidth, so as to transmit the data within a range of the target data rate. The transmitter encodes the data, by an FEC encoder, using the FEC code and the code rate, so as to generate encoded data. The transmitter modulates the encoded data using the modulation scheme so as to generate modulated data. The transmitter transmits the modulated data using a large number of RUs.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 560,191, filed March 1, 2024, the disclosure of which is incorporated herein by reference in its entirety.

[0002] Field of Disclosure The present disclosure generally relates to systems and methods for providing modes to support PHY (physical layer) rates as low as 1 Mbps, 1.1 Mbps, 1.2 Mbps, 1.5 Mbps, 1.7 Mbps, or multiples thereof, in a wireless local area network (WLAN) to achieve Extended (or Enhanced) Long Range (ELR) communications.

[0003] Background to the disclosure The market for wireless communication devices is growing due to the increasing use of mobile devices and the increased connectivity and data transfer between all types of devices. Digital switching technology has facilitated the large-scale deployment of affordable and easy-to-use wireless communication networks. Wireless communication can operate according to various standards, such as IEEE 802.11x (e.g., Wi-Fi technology), Bluetooth®, Global System for Mobile Communications (GSM), and Code Division Multiple Access (CDMA). Using such technologies, wireless communication devices can connect to local area networks and the Internet without using physical cables and communicate over various spaces and ranges via radio frequencies.

[0004] Ultra High Reliability (UHR) is a new research group within the IEEE 802.11 Working Group focused on improving the reliability of wireless local area network (WLAN) connections. Extended (or Enhanced) Long Range (ELR) refers to a communication scheme designed to extend the range and reliability of WLANs. ELR communication schemes can be implemented based on frequency domain duplication or tone repetition with or without rotation. Orthogonal Frequency Division Multiplexing (OFDM) channels may contain multiple subcarriers (tones). These tones can be grouped into smaller subchannels called resource units (RUs). The coding rate (or coding rate) represents the ratio of useful information (data) bits to the total number of transmitted bits. The coding rate can have a significant impact on the efficiency of data transmission. For example, a Modulation Coding Scheme (MCS) over RU26 (resource units each containing 24 data tones and 2 pilot tones) can support data rates of 800-900 Kbps depending on the size of the cyclic prefix (CP). Low-Density Parity Check (LDPC) codes can be used in the design and implementation of communication standards (e.g., IEEE 802.11bn UHR chips).

[0005] Various objects, aspects, features, and advantages of the present disclosure will become more apparent and will be better understood by reference to the detailed description taken in conjunction with the accompanying drawings, in which like reference numerals identify corresponding elements throughout and generally indicate identical, functionally similar, and / or structurally similar elements. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 illustrates an exemplary communication environment using a communication system, according to one or more embodiments.

[0007] [Figure 2] 1 is a simplified block diagram of a computing system, according to one embodiment.

[0008] [Figure 3] FIG. 1 illustrates an exemplary exponential matrix, according to one or more embodiments.

[0009] [Figure 4] FIG. 10 illustrates an exemplary shifted identity matrix for generating a parity check matrix in accordance with one or more embodiments.

[0010] [Figure 5] FIG. 2 illustrates an exemplary parity check matrix according to one or more embodiments.

[0011] [Figure 6] FIG. 1 illustrates an exemplary exponential matrix, according to one or more embodiments.

[0012] [Figure 7A] FIG. 1 illustrates an exemplary rate matching scheme including shortening, according to one or more embodiments. [Figure 7B] FIG. 1 illustrates an exemplary rate matching scheme including puncturing, according to one or more embodiments. [Figure 7C] FIG. 1 illustrates an exemplary rate matching scheme including repetition, according to one or more embodiments.

[0013] [Figure 8]1A-1C illustrate various examples of the structure of an ELR packet and schemes for encoding, modulating, and transmitting the ELR packet to achieve a target data rate, according to one or more embodiments.

[0014] [Figure 9] 1 illustrates another example of an ELR packet structure and a scheme for encoding, modulating, and transmitting the ELR packet to achieve a target data rate, according to one or more embodiments.

[0015] [Figure 10] A diagram showing a resource unit (RU) allocation structure in a 20 MHz bandwidth according to one or more embodiments.

[0016] [Figure 11] A diagram showing the structure of a repeating resource unit (RU) in a 20 MHz bandwidth according to one or more embodiments.

[0017] [Figure 12] FIG. 1 illustrates an example encoder for encoding with a shortened LDPC code to obtain a particular code rate, according to one or more embodiments.

[0018] [Figure 13] FIG. 1 illustrates an example encoder for encoding with a shortened LDPC code to obtain a particular code rate, according to one or more embodiments.

[0019] [Figure 14] FIG. 2 illustrates an exemplary decoder for decoding a shortened LDPC code, according to one or more embodiments.

[0020] [Figure 15A] FIG. 10 illustrates exemplary simulation results using a system to achieve a target data rate, according to one or more embodiments. [Figure 15B]FIG. 10 illustrates exemplary simulation results using a system to achieve a target data rate, according to one or more embodiments.

[0021] [Figure 16A] FIG. 10 illustrates exemplary simulation results using a system to achieve a target data rate, according to one or more embodiments. [Figure 16B] FIG. 10 illustrates exemplary simulation results using a system to achieve a target data rate, according to one or more embodiments.

[0022] [Figure 17] 1 is a flow diagram illustrating a process for obtaining a particular data rate using various coding, modulation and / or transmission schemes, according to one embodiment.

[0023] The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below.

[0024] Detailed Description The following IEEE standard(s), including any drafts of the IEEE standard(s), are incorporated herein by reference in their entirety and made a part of this disclosure for all purposes: the Wi-Fi Alliance standard, and the IEEE 802.11 standards, including but not limited to the IEEE 802.11a standard, the IEEE 802.11b standard, the IEEE 802.11g standard, the IEEE P802.11n standard, the IEEE P802.11ac standard, and the IEEE P802.11be standard through the IEEE P802.11bn standard, including but not limited to the IEEE 802.11b standard, are incorporated herein by reference in their entirety and made a part of this disclosure for all purposes. While this disclosure may refer to aspects of these standard(s), this disclosure is in no way limited by these standard(s).

[0025] To read the following description of the various embodiments, the following sections' descriptions of this specification and their respective contents may be helpful.

[0026] Section A describes network and computing environments that may be useful for implementing the embodiments described herein.

[0027] Section B describes an LDPC-based encoding / decoding system that can be useful for implementing the embodiments described herein.

[0028] Section C describes embodiments of systems and methods for achieving extended long-range communications in a WLAN to provide aggregate throughput as low as 1 Mbps.

[0029] A. Computing and Network Environment

[0030] The following disclosure provides many different embodiments or examples for implementing different features of the provided content. Specific example components and arrangements are described below to simplify the disclosure. It should be understood that these are merely examples and are not intended to be limiting. For example, in the following description, a first feature element that communicates with or is communicatively coupled to a second feature element may include embodiments in which the first feature element directly communicates with or is directly coupled to the second feature element, and may also include embodiments in which additional features may intervene between the first feature element and the second feature element, such that the first feature element indirectly communicates with or is indirectly coupled to the second feature element. Furthermore, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity and does not, in itself, affect the relationship between the various embodiments and / or configurations described.

[0031] Various embodiments disclosed herein relate to one or more apparatus, devices and / or systems that include a transmitter and / or receiver and one or more processors, and that may be configured, constructed, or implemented to communicate using any encoding process and technique as defined or supported by any IEEE 802.11 standard, such as 902.11n, 802.11AC, 802.11ax, and 802.11be, or other versions and embodiments of the IEEE 802.11 standard.

[0032] Referring to FIG. 1, a diagram illustrating an exemplary communication environment 100 including communication systems (or communication devices) 105, 108 is shown, in accordance with one or more embodiments. In one embodiment, communication system 105 includes baseband circuitry 110 and transmitter circuitry 120, and communication system 108 includes baseband circuitry 150 and receiver circuitry 140. In one aspect, communication system 105 is considered a transmitter communication system, and communication system 108 is considered a receiver communication system. These components operate together to exchange data (e.g., messages or frames) over a wireless medium. These components, in one or more embodiments, are embodied as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any combination thereof. In some embodiments, communication systems 105, 108 include more, fewer, or different components than those shown in FIG. 1. For example, each of communication systems 105, 108 includes transceiver circuitry to enable bidirectional communication between communication systems 105, 108 or with other communication systems. In some embodiments, each of the communication systems 105, 108 may have a configuration similar to the computing system 2000 shown in FIG.

[0033] The baseband circuitry 110 of the communication system 105 generates baseband data 115 for transmission. The baseband data 115 includes information data (e.g., signal(s)) at baseband frequencies for transmission. In one approach, the baseband circuitry 110 includes an encoder 130 that encodes data and generates or outputs parity bits. In one aspect, the baseband circuitry 110 (or the encoder 130) obtains a generator matrix or parity check matrix, or uses a previously generated generator matrix or parity check matrix, and encodes the information data by applying the information data to the generator matrix or parity check matrix to obtain a codeword. In some embodiments, the baseband circuitry 110 stores one or more generator matrices or one or more parity check matrices that comply with any IEEE 802.11 standard for WLAN communications. The baseband circuitry 110 retrieves the stored generator matrix or parity check matrix in response to detecting information data to be transmitted or in response to receiving an instruction to encode the information data. In one approach, the baseband circuitry 110 generates parity bits according to a portion of a generator matrix or using a parity check matrix, appends the parity bits to information bits to form codewords, generates baseband data 115 including codewords for the communication system 108, and provides the baseband data 115 to the transmitter circuitry 120.

[0034] The transmitter circuitry 120 of the communication system 105 includes or corresponds to circuitry that receives baseband data 115 from the baseband circuitry 110 and transmits radio signals 125 in accordance with the baseband data 115. In one configuration, the transmitter circuitry 120 is coupled between the baseband circuitry 110 and an antenna (not shown). In this configuration, the transmitter circuitry 120 upconverts the baseband data 115 from the baseband circuitry 110 to a carrier signal to generate radio signals 125 at an RF frequency (e.g., 10 MHz to 60 GHz) and transmits the radio signals 125 via the antenna.

[0035] The receiver circuit 140 of the communication system 108 is a circuit that receives the radio signal 125 from the communication system 105 and obtains baseband data 145 from the received radio signal 125. In one configuration, the receiver circuit 140 is coupled between the baseband circuit 150 and an antenna (not shown). In this configuration, the receiver circuit 140 receives the radio signal 125 via the antenna and downconverts the radio signal 125 to an RF frequency in accordance with a carrier signal to obtain the baseband data 145 from the radio signal 125. The receiver circuit 140 then provides the baseband data 145 to the baseband circuit 150.

[0036] The baseband circuitry 150 of the communication system 108 includes or corresponds to circuitry that receives baseband data 145 from the receiver circuitry 140 and obtains information data from the received baseband data 145. In one embodiment, the baseband circuitry 150 includes a decoder 160 that extracts information bits and parity bits from the baseband data 145. The decoder 160 decodes the baseband data 145 to obtain the information data generated by the baseband circuitry 110 of the communication system 105.

[0037] In some embodiments, each of baseband circuitry 110 (including encoder 130), transmitter circuitry 120, receiver circuitry 140, and baseband circuitry 150 (including decoder 160) may exist as one or more processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any combination thereof.

[0038] 2 is a simplified block diagram of a computing system according to one embodiment. The illustrated exemplary computing system 2000 includes one or more processors 2010 in direct or indirect communication with memory 2060 via a communication system 2040 (e.g., a bus), at least one network interface controller 2030 with a network interface port for connecting to a network (not shown), and other components (e.g., input / output (“I / O”) components 2050). Generally, the processor(s) 2010 execute instructions (or computer programs) received from memory. The illustrated processor(s) 2010 incorporate or are connected to a cache memory 2020. In some cases, instructions are read from memory 2060 into the cache memory 2020 and executed from the cache memory 2020 by the processor(s) 2010. Computing system 2000 may not necessarily include all of the components shown in FIG. 2, and may include other components not shown in FIG.

[0039] More particularly, the processor(s) 2010 may be any logic circuitry that processes instructions (e.g., instructions fetched from memory 2060 or cache 2020). In many implementations, the processor(s) 2010 is a microprocessor unit or a special purpose processor. The computing device 2050 may be based on any processor or set of processors capable of operating as described herein. The processor(s) 2010 may be a single-core processor(s) or a multi-core processor(s). The processor(s) 2010 may be multiple different processors.

[0040] The memory 2060 may be any device suitable for storing computer-readable data. The memory 2060 may be a device with permanent storage or a device for reading removable storage media. Examples include all forms of volatile memory (e.g., RAM), non-volatile memory, media and memory devices, semiconductor memory devices (e.g., EPROM, EEPROM, SDRAM, and flash memory devices), magnetic disks, magneto-optical disks, and optical disks (e.g., CD-ROM, DVD-ROM, or Blu-ray discs). The computing system 2000 may have any number of memory devices 2060.

[0041] Cache memory 2020 is a type of computer memory that is generally located in close proximity to the processor(s) 2010 for fast read times. In some implementations, cache memory 2020 is part of the processor(s) 2010 or is on the same chip as the processor(s) 2010. In some implementations, there are multiple levels of cache 2020 (e.g., an L2 cache layer and an L3 cache layer).

[0042] The network interface controller 2030 manages data exchange through network interfaces (sometimes called network interface ports). The network interface controller 2030 handles the physical and data link layers of the OSI model for network communication. In some implementations, some of the network interface controller's tasks are handled by one or more processors 2010. In some implementations, the network interface controller 2030 is part of the processor 2010. In some implementations, the computing system 2000 has multiple network interfaces controlled by a single controller 2030. In some implementations, the computing system 2000 has multiple network interface controllers 2030. In some implementations, each network interface is a connection point for a physical network link (e.g., a cat-5 Ethernet link). In some implementations, the network interface controller 2030 supports wireless network connectivity, and the interface port is a wireless (e.g., wireless communication) receiver or transmitter (e.g., for either the IEEE 802.11 protocol, Near Field Communication "NFC," Bluetooth, ANT, or any other wireless protocol). In some implementations, the network interface controller 2030 implements one or more network protocols, such as Ethernet. Generally, the computing device 2050 exchanges data with other computing devices over a physical or wireless link via a network interface. The network interface may link to another device directly or through an intermediate device (e.g., a network device such as a hub, bridge, switch, or router) to connect the computing device 2000 to a data network, such as the Internet.

[0043] The computing system 2000 may include or provide interfaces for one or more input or output ("I / O") devices. Input devices include, but are not limited to, keyboards, microphones, touch screens, foot pedals, sensors, MIDI devices, and pointing devices such as mice or trackballs. Output devices include, but are not limited to, video displays, speakers, refreshable Braille terminals, lights, MIDI devices, and 2D or 3D printers.

[0044] Other components may include I / O interfaces, external serial device ports, and any additional coprocessors. For example, computing system 2000 may include interfaces (e.g., a Universal Serial Bus (USB) interface) for connecting input devices, output devices, or additional memory devices (e.g., a portable flash drive or external media drive). In some implementations, computing device 2000 includes additional devices such as coprocessors, e.g., a mathematical coprocessor, that can assist processor 2010 with high-precision or complex calculations.

[0045] Component 2090 may be configured to interface with external media, display 2070, input device 2080, or any other component within computing system 2000, or a combination thereof. Display 2070 may be a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a flat panel display, a solid state display, a cathode ray tube (CRT) display, a projector, a printer, or other display device now known or later developed for outputting determined information. Display 2070 may serve as an interface for a user to ascertain the functionality of processor(s) 2010, or specifically with software stored in memory 2060.

[0046] Input device(s) 2080 may be configured to allow a user to interact with any of the components of computing system 2000. Input device(s) 2080 may be a cursor control device such as a pad, a keyboard, a mouse, or a joystick. Input device(s) 2080 may also be a remote control, a touchscreen display (which may be a combination of display 2070 and input device(s) 2080), or any other device operative in conjunction with computing system 2000 to interact with computing system 2000 (e.g., any device operative in conjunction with computing system 2000 to act as an interface between a user and computing system 2000).

[0047] B. LDPC-based encoding / decoding system

[0048] In general, the parity check matrix of a code represents the equation that determines whether an error occurred during transmission. More formally, for all valid codewords (i.e., bits generated by the encoder without error), the following equation can be established:

[0049] Hc=0 (Equation 1)

[0050] In Equation 1, "H" is the parity check matrix, "c" is the codeword vector, and "0" is a vector of all 0s. The parity check matrix H is one way of describing the code.

[0051] The generator matrix G of the code satisfies the following equation:

[0052] sG=c (Equation 2)

[0053] In Equation 2, "s" is a vector of information bits, "G" is a generator matrix, and "c" is a codeword corresponding to "s." In some implementations, a system (e.g., communication system 108 including decoder 160 of FIG. 1) can decode codeword c to obtain decoded data s using Equation 2.

[0054] The parity check matrix and generator matrix of a code are related by the matrix equation above. In general, if the parity check matrix is ​​low-density, the corresponding generator matrix will be high-density, and vice versa. Thus, an LDPC code is characterized by a low-density parity check matrix and a high-density generator matrix. The density of a matrix is ​​related to the number of operations (calculations) that need to be performed to implement one of the equations above. While it was recognized as late as 1995 that LDPC codes could be used to transmit data with few errors, i.e., with an error rate comparable to or better than that of turbo codes, one drawback of LDPC codes is that their generator matrices are high-density, making encoding computationally intensive and making the codes impractical for many applications.

[0055] In some implementations, the parity check matrix may have a quasi-cyclic structure, such as the parity check matrix of a QC-LDPC code (n=3888, k=2916, R=3 / 4). Given a lifting size z, the parity check matrix may have multiple submatrices, such that each submatrix is ​​a cyclically shifted version of an identity matrix of size (z×z) (e.g., where z=162). The parity check matrix may be represented in two equalization forms: (1) the parity check matrix H, and (2) the block or exponential matrix P=E(H).

[0056] In some implementations, the parity check matrix H may be a binary matrix of size m×n (m and n are integers). The elements of the parity check matrix are binary values. Given a block length n and a code rate R, an LDPC code (or QC-LDPC code) LDPC(n,R) satisfies the following equation:

[0057] k=nR (Equation 3)

[0058] m=n(1-R) ​​(Formula 4)

[0059] In some implementations, a block matrix or an exponent matrix (QC-LDPC exponent matrix) may be obtained. Given a lifting size z, the exponent matrix P = E(H) may have size m / z × n / z. For n = 24z (e.g., n = 3888, z = 162), the size of P = E(H) is 24(1 − R) × 24 (= n(1 − R) / z × n / z). The elements of the exponent matrix may be integer values ​​corresponding to cyclic shift values ​​of an identity matrix of size z × z. The parity check matrix H may be a sparse binary matrix that can be derived from the exponent matrix P = E(H). The generator matrix G may have size n × k in binary form (e.g., the elements of the generator matrix G are binary values). The exponent matrix P = E(H) may have a structure including multiple submatrices (e.g., A, B, C, D, E, T).

[0060] In some embodiments, the binary QC-LDPC code LDPC(n,R) can be characterized by the null space of an n(1 - R)×n parity-check matrix H. The parity-check matrix H may be a binary sparse matrix that includes a set of circulant matrices of size z×z. The parity-check matrix H of the QC-LDPC code can be equivalently represented by an exponent matrix P = E(H). This representation can be useful for showing the graphical structure of the code that is based on the basic graph along with the shift coefficients.

[0061] In some embodiments, the parity-check matrix H can be generated from the exponent matrix P = E(H). The exponent matrix P = E(H) may (as elements) include shift values d in the range 0 ≦ d < z with d = -1. For example, when z = 7, the shift values d may include -1, 0, 1, 2, 3, 4, 5, 6. The shift value d = 0 may correspond (or map) to an identity matrix of size z×z denoted by I(z). The shift value d = -1 may correspond (or map) to a null matrix (all elements being zero) of size z×z denoted by 0*I(z). Any other integer value d within [1,z - 1] may correspond (or map) to a matrix that is circularly shifted to the right from I(z). The parity-check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element of the exponent matrix P is replaced by a matrix corresponding to the shift value (as the shift value d).

[0062] In some embodiments, the exponent matrix P = E(H) has a plurality of elements TIFF20251337,14000002.tif13163

[0063] TIFF20251337,14000003.tif7163

[0064] TIFF20251337,14000004.tif7163

[0065] The exponent matrix (or permutation matrix) P = E(H) can be represented as follows. TIFF2025133714000005.tif24163

[0066] (Formula 7)

[0067] The corresponding parity check matrix H can be obtained by replacing each element of the matrix (as a shift value d) with the matrix C(d) corresponding to the shift value as follows: TIFF2025133714000006.tif27163

[0068] For example, the matrix C(1) can be expressed as follows: TIFF2025133714000007.tif38163

[0069] In some implementations, the encoder can use a generator matrix to generate codewords (e.g., using Equation 2). In some implementations, the encoder can use a parity check matrix (rather than a generator matrix) to generate codewords from vectors of information bits. After the parity check matrix H is obtained, the parity check matrix H may have submatrices A, B, C, D, T, and E. An upper region O of the submatrix T may correspond to a region where the matrix contains all zeros, and other regions may represent locations where the matrix may contain ones.

[0070] In some implementations, the codeword c may be obtained by the following formula:

[0071] c=[sp1p2] (Equation 10)

[0072] where "s" is the vector of information bits to be coded, "p1" is the vector of the first g parity bits, and "p2" is the vector of the remaining mg parity bits.

[0073] The vectors p1 and p2 can be obtained by the following equations:

[0074] Φ=-ET -1B+D (Equation 11)

[0075] p1 T =-Φ -1 (-ET -1 A+C)s T (Formula 12)

[0076] p2 T =-T -1 (As T +Bp1 T ) (Equation 13)

[0077] Although various embodiments disclosed herein are described with respect to encoding data for wireless communications (e.g., a wireless local area network (WLAN) conforming to any IEEE 802.11 standard), the principles disclosed herein are applicable to other types of communications (e.g., wired communications) or to any process that performs encoding for LDPC codes.

[0078] FIG. 3 illustrates an exemplary exponent matrix (QC-LDPC exponent matrix) 300 according to one or more embodiments. Given a lifting size z, the exponent matrix 300 may have a size of m / z×n / z. For n=24z (e.g., n=3888, z=162), the size of P=E(H) is 24(1−R)×24 (=n(1−R) / z×n / z). The elements of the exponent matrix may be integer values ​​corresponding to cyclic shift values ​​of an identity matrix of size z×z. The parity check matrix H (see FIG. 5) may be a sparse binary matrix that may be derived from the exponent matrix P=E(H). The generator matrix G may have a size n×k in binary form (e.g., the elements of the generator matrix G are binary values). Referring to FIG. 3, the exponential matrix P=E(H) may have a structure that includes multiple submatrices (e.g., A310, B312, C316, D318, E320, T314).

[0079] FIG. 4 is a diagram 400 showing exemplary shifted identity matrices 409, 410, 411, 412, 413, 414, 415, 416 for generating a parity check matrix according to one or more embodiments. The parity check matrix H can be generated from an exponent matrix P = E(H) (e.g., exponent matrix 300) or can be identified (specified) using a codebook. As shown in Equation 7, the exponent matrix P = E(H) may include shift values d in the range 0≦d<z with d = -1 (as elements). Refer to the equation. For example, when z = 7, the shift values d may include -1, 0, 1, 2, 3, 4, 5, 6 (see FIG. 4). The shift value d = 0 may correspond (or map) to an identity matrix of size z×z indicated by I(z) (e.g., matrix 410). The shift value d = -1 may correspond (or map) to a null matrix (all elements are zero) of size z×z indicated by 0*I(z) (e.g., matrix 409). Any other integer value d within [1,z - 1] may correspond (or map) to a matrix that is circularly shifted to the right from I(z) (e.g., matrices 411, 412, 413, 414, 415, 416). As shown in Equation 8, the parity check matrix H can be obtained from the exponent matrix P = E(H) by expanding the exponent matrix P such that each element of the exponent matrix P is replaced with a matrix corresponding to the shift value (as the shift value d).

[0080] FIG. 5 illustrates an example parity-check matrix 500 according to one or more embodiments. In some implementations, an encoder (e.g., encoder 130) may generate codewords using a generator matrix (e.g., using Equation 2). In some implementations, an encoder (e.g., encoder 130) may generate codewords from vectors of information bits using a parity-check matrix (rather than a generator matrix). After the parity-check matrix H is obtained (e.g., using a codebook), the parity-check matrix H (e.g., parity-check matrix 500) may have submatrices A 510, B 512, C 516, D 518, T 514, and E 520. An upper region O 515 of submatrix T 514 (e.g., the white region in FIG. 5) may correspond to a region where the matrix contains all zeros, and other regions (e.g., the gray region in FIG. 5) may represent locations where ones may be included. The size of parity check matrix 500 may be m×n, where submatrix D 518 has size g×g and submatrix T has size (mg)×(mg). In some implementations, given a vector s of information bits to be encoded, an encoder can obtain codeword c using Equation 10, Equation 11, Equation 12, and Equation 13.

[0081] 6 is a diagram illustrating an exemplary exponent matrix (QC-LDPC exponent matrix) 600 according to one or more embodiments. Given a lifting size z, the exponent matrix 600 may have a size of m / z × n / z. For n=48z (e.g., n=3888, z=81), The size of the TIFF2025133714000008.tif8162 matrix is ​​48(1-R) ​​× 48 (=n(1-R)z × n / z). The elements of the exponential matrix may be integer values ​​corresponding to the cyclic shift value of the identity matrix of size z × z. The parity check matrix H is the exponential matrix The generator matrix G may be a sparse binary matrix that may be derived from TIFF2025133714000009.tif7162. The generator matrix G may be in binary form and have size n × k (e.g., the elements of the generator matrix G are binary values). Referring to Figure 6, the exponential matrix TIFF2025133714000010.tif13162

[0082] 7A, 7B, and 7C illustrate exemplary rate matching schemes 700, 740, and 780, respectively, including shortening, puncturing, and repetition, according to one or more embodiments. Referring to FIG. 4A, a system (e.g., communication system 105, baseband circuitry 110, encoder 130) may zero-pad data bits (e.g., zero-padded bits or "shortened bits" 701) before encoding to match the number of systematic bits per codeword (e.g., systematic bits 702) and discard the shortened bits 701 after encoding. In this manner, the bit shortener can reduce the effective code rate and improve coding gain.

[0083] Referring to Figure 7B, the system may discard some parity bits (e.g., "puncture bits" 741) after encoding. In this way, the system may increase the effective code rate and reduce the coding gain. Referring to Figure 7C, the system may copy some bits (e.g., "repeated bits" 781) from the beginning of the codeword. In this way, the system may improve the SNR.

[0084] Aspects of the operating environment and components described above will become apparent in the context of the systems and methods disclosed herein. C. Systems and methods for achieving extended long range in WLANs

[0085] In one aspect, generally in WLAN systems, access points (APs) transmit at higher power (using external power amplifiers) compared to non-AP stations (STAs), which typically use more efficient power amplifiers, or in some cases, integrated complementary metal-oxide semiconductor (CMOS) power amplifiers. This can result in a link budget difference of several dB (3-6 dB) between downlink and uplink communications. This situation (e.g., link budget difference) can exist due to various reasons, such as the increased size of AP chipsets and components (e.g., high-power amplifiers) that can add more advanced features compared to client devices (which are often smaller and have tighter form factor limitations). The uplink range can be extended to address link budget imbalances between the downlink (AP to STA, e.g., router to laptop / phone) and the uplink (STA to AP). Also, in some countries, regulations may allow APs to transmit at significantly higher power levels or higher power spectral densities (dBm / MHz) than non-AP STAs, which may result in an imbalance between the uplink and downlink.

[0086] To address this issue, the disclosed system and method enable enhanced long-range communications and enable WLANs to achieve aggregate throughput at multiples of 1 Mbps data rates (or multiples of 1 Mbps, 1.1 Mbps, 1.2 Mbps, 1.5 Mbps, or 1.7 Mbps), thereby reducing link budget differences or imbalances between uplink and downlink. Here, data rate or PHY data rate refers to bits per second (bps), kilobits per second (Kbps), megabits per second (Mbps), gigabits per second (Gbps), or the amount of data transferred over a network in a specific period (e.g., seconds). In some implementations, the system can provide a packet communication mode using 802.11 packet transmission technology with a maximum PHY data rate substantially equal to or near 1 Mbps, 1.1 Mbps, 1.2 Mbps, 1.5 Mbps, 1.7 Mbps, or multiples thereof.

[0087] In some implementations, to achieve extended (or enhanced) long-range communications, a communication system of a communication standard (e.g., an IEEE 802.11bn UHR chip) can provide a mode to support a PHY rate as low as 1 Mbps. In some implementations, a system can provide a mode to support extended range at a data rate (e.g., PHY rate) as low as 1 Mbps to achieve extended long-range communications in a WLAN (e.g., 802.11bn) and enable minimal airtime for transmission (e.g., utilizing minimal bandwidth (BW) for improved efficiency) and minimal processing. For example, a WLAN communication system (e.g., an IEEE 802.11bn UHR chip) can provide a mode to support a PHY rate as low as 1 Mbps. In some implementations, the system and method can provide a mode to achieve an aggregate throughput of 1 Mbps, 1.1 Mbps, 1.2 Mbps, 1.5 Mbps, 1.7 Mbps, or multiples thereof.

[0088] In some implementations, to achieve extended long-distance communication, the system and method may provide two different designs / schemes / configurations: (1) LDPC and (2) Binary Convolutional Code (BCC), depending on the forward error correction (FEC) scheme. The LDPC and BCC may each have a corresponding code rate R. The code rate R refers to the ratio of k information bits to n coded bits, and thus a block of k information bits can be coded to generate n coded bits (or codewords or coded blocks). A BCC is an error-correcting code that generates parity symbols by applying a Boolean function (e.g., a sliding Boolean polynomial function) to a data stream. For example, a BCC with a code rate (R) of 1 / 3 and a length (L) of 7 can generate parity symbols by applying the Boolean polynomial function given by [171 145 133].

[0089] In some implementations, the system and method may provide a long-distance transmission design / configuration / structure using LDPC codes. The system and method may generate / provide / create LDPC codes with a coding rate of R=1 / 3 using Quadrature Phase Shift Keying (QPSK) as the modulation scheme. The system and method may use RU / dRU (distributed RU or interleaved RU) and / or LTF (long training field) / CP (cyclic prefix). In some implementations, rotated QPSK modulation may be used with RUs (e.g., RU26, which includes 24 data tones and 2 pilot tones). Rotated QPSK (π / 4-QPSK) modulation refers to a variation of QPSK modulation in which the constellation of each symbol rotates by π / 4 radians from the previous symbol. In some implementations, RU selection may be performed based on existing standards (e.g., IEEE 802.11ax / be) and / or based on dRUs. The system and method can use a 4× LTF and a guard interval (CP=3.2 μs). The guard interval (GI) is a time interval inserted between consecutive symbols in a transmitted signal to mitigate the effects of multipath fading. A rate 1 / 3-based LDPC code can be selected as a native standalone code and / or can be a derived code derived from codes at other rates. For example, from a rate 1 / 2 LDPC code, the system can derive / construct / create a matching rate 1 / 3 shortened code. Similarly, from a lower-rate LDPC code, such as rate 1 / 4, the system can use techniques such as puncturing to derive / construct / create a rate 1 / 3 code.

[0090] In some embodiments, the system and method may provide a long-distance transmission design / configuration / structure using BCC codes. In some embodiments, the system and method may generate / provide / create a BCC code with a coding rate of R=2 / 3 using BPSK as the modulation scheme. RU / dRU and LTF / CP may be used similarly to those used in LDPC. For example, the system and method may use 4× LTF and a guard interval (CP=3.2 μs). In some embodiments, RU selection may be performed based on an existing standard (e.g., IEEE 802.11ax / be) and / or based on dRU. In some embodiments, the system and method may use a rate 1 / 3 BCC with a QPSK modulation scheme. The system and method may use / generate / provide / create / design a 1 / 3 BCC code based on an existing 1 / 3 trellis-based convolutional code, or alternatively, by concatenating a rate 2 / 3 BCC code with a 1 / 2 repetition code. The concatenation may be performed using 2 / 3 BCC as the inner or outer code (e.g., the repetition codes may be swapped in each case). When codes are used / generated / provided / created / designed as a serial concatenation, the system and method may optionally place an interleaver between the constituent codes.

[0091] In some implementations, when RU26 (or 26 distributed or interleaved RUs (26-dRU)) containing 24 information tones (or data tones) and 2 pilot tones is used, the physical data rate PHY_RATE 26 can be calculated as follows:

[0092] PHY_RATE 26 =R*log2M*24 / (4*3.2+GI) (Equation 14)

[0093] Here, R is the coding rate of the FEC scheme (e.g., LDPC or BCC), M is the number of phases used in the Phase-Shift Keying (PSK) scheme (e.g., 2 for BPSK, 4 for QPSK, etc.), and GI is the guard interval.

[0094] When using RU26, the data rate is PHY_RATE 26 can be calculated using Equation 14. For example, when M=4 (QPSK), R=1 / 3, and GI=3.2 μs, PHY_RATE 26 = 1 / 3 * log2(4) * 24 / (4 * 3.2 + 3.2) = 1 Mbps; when M = 2 (BPSK), R = 2 / 3, GI = 3.2 μs, PHY_RATE 26 = 2 / 3 * log2(2) * 24 / (4 * 3.2 + 3.2) = 1Mbps; if M = 2 (BPSK), R = 2 / 3, GI = 1.6μs, PHY_RATE 26 = 2 / 3 * log2(2) * 24 / (4 * 3.2 + 1.6) = 1.11 Mbps; when M = 4 (QPSK), R = 1 / 3, GI = 1.6 μs, PHY_RATE 26 = 1 / 3 * log2(4) * 24 / (4 * 3.2 + 1.6) = 1.11 Mbps; when M = 2 (BPSK), R = 2 / 3, GI = 0.8 μs, PHY_RATE 26 = 2 / 3 * log2(2) * 24 / (4 * 3.2 + 0.8) = 1.176 Mbps; when M = 4 (QPSK), R = 1 / 3, GI = 0.8 μs, PHY_RATE 26 = 1 / 3 * log2(4) * 24 / (4 * 3.2 + 0.8) = 1.176 Mbps. Further examples can be seen in Tables 1 and 2 below. In some implementations, in a given PHY bandwidth (e.g., 24 MHz bandwidth), one or more such RU / dRUs (e.g., RU26 / 26-dRU) can be repeated for additional diversity gain.

[0095] In some implementations, when RU52 (or 52-dRU) is used, which includes 48 information tones (or data tones) and 4 pilot tones, the physical data rate PHY_RATE 52 can be calculated as follows:

[0096] PHY_RATE 52 =R*log2M*48 / (4*3.2+GI) (Equation 15)

[0097] Here, R is the coding rate of the FEC scheme (LDPC or BCC), M is the number of phases used in the PSK scheme (e.g., 2 for BPSK, 4 for QPSK, etc.), and GI is the guard interval.

[0098] When using RU52, the data rate PHY_RATE 52 can be calculated using Equation 15. For example, when M=2 (BPSK), R=1 / 2, and GI=3.2 μs, PHY_RATE 52 = 1 / 2 * log2(2) * 48 / (4 * 3.2 + 3.2) = 1.5 Mbps; when M = 2 (BPSK), R = 1 / 2, GI = 1.6 μs, PHY_RATE 52 = 1 / 2 * log2(2) * 48 / (4 * 3.2 + 1.6) = 1.67 Mbps; when M = 2 (BPSK), R = 1 / 2, GI = 0.8 μs, PHY_RATE 52 = 1 / 2 * log2(2) * 48 / (4 * 3.2 + 0.8) = 1.76 Mbps. Further examples can be seen in Tables 1 and 2 below. In some implementations, in a given PHY bandwidth (e.g., 24 MHz bandwidth), one or more such RU / dRUs (e.g., RU52 / 52-dRU) can be repeated for additional diversity gain.

[0099] In some implementations, the systems and methods can provide long-range transmission designs / configurations / structures using multiple-input and multiple-output (MIMO) systems and / or orthogonal frequency-division multiple access (OFDMA) modulation. In some implementations, the systems and methods can optionally use MIMO to achieve long-range transmissions or can be configured / generalized for any choice of antennas.

[0100] In some implementations, the systems and methods may include one spatial stream (e.g., N spatial streams) SS A target rate (also referred to as a "target data rate" or "target PHY rate") of PHY rate, which should be equal to 1 Mbps, can be achieved with a 2x4 MIMO configuration (e.g., d = 1). Here, "target data rate" or "target PHY rate" refers to the data rate or PHY rate that will be achieved as a result of a specific long-distance transmission design / configuration / structure. The target data rate or target PHY rate can be achieved based on any of the following antenna configurations: (1) one transmit antenna, one receive antenna; (2) (Ntx, Nrx) MIMO, where Ntx and Nrx refer to the number of transmit antennas and the number of receive antennas, respectively, and min(Ntx, Nrx) = 1; or (3) when min(Ntx, Nrx) = d, an achievable rate = d * 1 Mbps can be achieved with the same design / configuration (e.g., an LDPC configuration to achieve 1 Mbps). For example, a 2x4 MIMO configuration (e.g., d = 2) with or without beamforming can achieve a rate (speed) of 2 Mbps.

[0101] In some implementations, the system and method can adjust the number of antennas to remain similar or similar to a design / configuration using LDPC or BCC. The basic design / configuration can be achieved with (Ntx, Nrx) (where min(Ntx, Nrx)=1), N SS= 1, 1Mbps can be achieved. MIMO can be generalized to any antenna selection. MIMO can provide additional diversity / combining gain depending on the configuration. For example, if a 1x2 MIMO configuration can provide 3dB, a 1x4 MIMO configuration can provide 6dB, etc.

[0102] In some implementations, the basic RU can be 26 or 52 (e.g., RU26 or RU52), depending on the configuration. In a given PHY bandwidth, a number of such RUs can be repeated (e.g., in a 20 MHz PHY bandwidth, potentially up to 9 such RU26s can be repeated). Such repetition provides diversity gain when the channel has multipath fading. RU52 can similarly be repeated 2-4 times in 20 MHz.

[0103] In some implementations, an LDPC code with a code rate of R=1 / 3 can be a native code or can be obtained by one of the following methods: (1) shortening from a 1 / 2 LDPC code; (2) concatenating a 2 / 3 LDPC code with a rate 1 / 2 repetition code; (3) block-wise repetition using a 2 / 3 LDPC code; (4) bit-level repetition using 2 / 3 LDPC code bits with or without interleaving; or (5) combining shortening, repetition, and puncturing after 1 / 2 coded bits to obtain an effective code rate of 1 / 3. In some implementations, the system can adjust the number of shortened / padded / repeated / punctured bits for a given payload length.

[0104] In some implementations, by using higher Quadrature Amplitude Modulation (QAM), for example, when the M in M-ary QAM is increased, a proportional increase in data rate can be achieved (at the expense of higher SNR and therefore reduced range). M-ary QAM implies a different constellation size (M) in the constellation diagram. Examples include 16-QAM, 64-QAM, and 256-QAM.

[0105] Table 1 below shows various configurations for achieving target data rates using LDPC codes. [Table 1]

[0106] Table 1: Overview of configurations using LDPC codes

[0107] Table 2 below shows various configurations for achieving a target data rate using BCC codes. [Table 2]

[0108] Table 2: Overview of constructions using BCC codes

[0109] In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify a target data rate for transmitting data over a channel having a frequency bandwidth. Based on at least the target data rate, the one or more processors may be configured to select a forward error correction (FEC) code, a code rate, a modulation scheme, and a number of resource units (RUs) within the frequency bandwidth to transmit the data within the target data rate. The one or more processors may be configured to encode the data using the FEC code and the code rate with an FEC encoder to generate coded data. The one or more processors may be configured to modulate the coded data using a modulation scheme to generate modulated data. The transmitter may be configured to transmit the modulated data using a number of RUs.

[0110] In some embodiments, an apparatus may include a transmitter and one or more processors. The one or more processors may identify a target data rate for transmitting data over a channel having a frequency bandwidth. Based on at least the target data rate, the one or more processors may select a forward error correction (FEC) code, a code rate, a modulation scheme, and a number of resource units (RUs) within the frequency bandwidth to transmit the data within the target data rate. The one or more processors may encode the data using the FEC code and the code rate with an FEC encoder to generate coded data. The one or more processors may modulate the coded data using a modulation scheme to generate modulated data. The transmitter may transmit the modulated data using a number of RUs.

[0111] In some implementations, the selected FEC code may be a low-density parity check (LDPC) code or a binary convolutional code (BCC). In some implementations, the one or more processors are further configured to select a guard interval (GI) and a number of tones per RU based on at least the target data rate to transmit data within a range of the target data rate. In some implementations, the target data rate may be 1 Mbps or 1.5 Mbps. The target data rate range may be 20% of the target data rate.

[0112] In some implementations, the FEC code may have a first coding rate that is different from the selected coding rate, and the one or more processors may be configured to, with an FEC encoder, encode the data using the FEC code having the first coding rate to generate encoded data corresponding to the selected coding rate.

[0113] In some implementations, the FEC code may be an LDPC code, the selected code rate may be 1 / 3, and the first code rate may be 1 / 2 or 1 / 4. In some implementations, the FEC code may be a BCC code, the selected code rate may be 1 / 3, and the first code rate may be 2 / 3.

[0114]

[0013] Embodiments of the present disclosure have at least the following advantages and benefits: First, embodiments of the present disclosure can provide a useful technique for reducing link budget differences or imbalances between uplinks and downlinks. In some implementations, a system can provide a packet communication mode using 802.11 packet transmission techniques with a maximum PHY data rate substantially equal to or near 1 Mbps, 1.1 Mbps, 1.2 Mbps, 1.5 Mbps, 1.7 Mbps, or multiples thereof.

[0115] Second, embodiments of the present disclosure can provide useful techniques for achieving target data rates using variable coding, modulation, and / or transmission schemes. Tables 1 and 2 outline such schemes for achieving target data rates.

[0116] Third, embodiments of the present disclosure can provide useful techniques for reusing existing codes to help pave the way for similar designs. For example, from a rate 1 / 2 LDPC code, a system can derive / construct / create a shortened code with a matching rate of 1 / 3. Similarly, from a lower-rate LDPC code, such as a rate 1 / 4, a system can derive / construct / create a rate 1 / 3 code using techniques such as puncturing. Systems and methods can use / generate / provide / create / design a 1 / 3 BCC code based on an existing 1 / 3 trellis-based convolutional code, or alternatively, by concatenating a rate 2 / 3 BCC code with a 1 / 2 repetition code. Concatenation can be performed using the 2 / 3 BCC as the inner or outer code (e.g., the repetition codes can be swapped in each case).

[0117] FIG. 8 illustrates various example schemes 810, 820, 830, and 840 for encoding, modulating, and transmitting an ELR packet 850 to achieve a target data rate, according to one or more embodiments. The ELR packet 850 may be a physical layer protocol data unit (PPDU) including a legacy preamble 851, an ELR preamble 852, and a data payload 853. The legacy preamble 851 may be a WLAN-compatible (e.g., IEEE 802.11be-compatible) preamble. The ELR preamble 852 may be used to detect an ELR packet (e.g., by including a specific sequence of bit values). The data payload 853 may be processed using various schemes to achieve a target data rate (e.g., 1 Mbps or a target rate within 20% of 1 Mbps). Such schemes may include scheme 810, scheme 820, scheme 830, and scheme 840. Scheme 810 may include encoding using a forward error correction (FEC) code with a data rate of ⅔ (810-1), concatenating a repetition code with a data rate of ½ and an FEC code (810-2), modulating using QPSK (810-3), modulating the channel using OFDM (810-4), and / or transmitting over an OFDMA channel using a defined / assigned / designed / configured RU 26 or dRU 26 (810-5). The method 820 may include encoding using a data rate ⅔ FEC code (820-1), concatenating a data rate ½ repetition code and an FEC code (820-2), modulating using BPSK (820-3), modulating the channel using OFDM (820-4), and / or transmitting over an OFDMA channel using a defined / assigned / designed / configured RU52 or dRU52 (820-5).Scheme 830 may include encoding using a data rate ⅓ FEC code (830-2), modulating using BPSK (830-3), modulating the channel using OFDM (830-4), and / or transmitting over an OFDMA channel using a defined / assigned / designed / configured RU 52 or dRU 52 (830-5). Scheme 840 may include encoding using a data rate ⅓ FEC code (840-2), modulating using QPSK (840-3), modulating the channel using OFDM (840-4), and / or transmitting over an OFDMA channel using a defined / assigned / designed / configured RU 26 or dRU 26 (840-5).

[0118] FIG. 9 illustrates an example of an ELR packet 950 structure and a scheme 910 for encoding, modulating, and transmitting the ELR packet 950 to achieve a target data rate, according to one or more embodiments. The ELR packet 950 may be a PPDU including a legacy preamble 951, an ELR preamble 952, and a data payload 953. The legacy preamble 951 may be a WLAN-compatible (e.g., IEEE 802.11be-compatible) preamble. The ELR preamble 952 may be used to detect an ELR packet (e.g., by including a specific sequence of bit values). The data payload 953 may be processed using various schemes (e.g., scheme 910) to achieve a target data rate (e.g., a target rate within 20% of 1.5 Mbps or 1 Mbps). The method 910 may include encoding using a data rate 1 / 2 FEC code (910-2), modulating using BPSK (910-3), modulating the channel using OFDM (910-4), and / or transmitting over an OFDMA channel using a defined / assigned / designed / configured RU52 or dRU52 (910-5).

[0119] Figure 10 illustrates a resource unit (RU) allocation structure 1000 for a 20 MHz bandwidth according to one or more embodiments. A 20 MHz channel can be divided into multiple RUs, each containing a number of subcarriers (or tones). For example, the 256 tones of a 20 MHz channel can be allocated / grouped into (1) an RU containing 26 tones (referred to as an "RU26"), (2) an RU containing 52 tones (referred to as an "RU52"), or (3) an RU containing 106 tones (referred to as an "RU106"). Figure 4 illustrates various RU allocation structures 1010, 1020, 1030, 1040, 1050, and 1060 for a 20 MHz bandwidth. For example, RU allocation structure 1010 may include nine RU26s (e.g., RU26 1012), RU allocation structure 1020 may include six RU26s and a combination of RU26s and RU52s (e.g., RU1022), RU allocation structure 1030 may include six RU26s and a combination of RU52s and RU26s (e.g., RU1032), RU allocation structure 1040 may include four RU26s and a combination of RU106s and RU26s (e.g., RU1042), and RU allocation structure 1050 may include four RU26s and a combination of RU106s and RU26s (e.g., RU1052).

[0120] 11 illustrates a repeating RU structure 1100 in a 20 MHz bandwidth, according to one or more implementations. The system can repeat an RU (e.g., RU52 1101) four times to generate a repeating RU 1103, which is a vector with four RU52 elements. In some implementations, the vector H R 1111 may be defined such that each element of the vector represents a phase shift of an input signal (e.g., an input signal corresponding to RU52). R =[+1 -1 -1 +1] may represent phase shifts of +90°, -90°, -90°, and +90°. In some implementations, the system is R Receive the stream of 1112 and create a vector HR One of the 1112 streams (e.g., H R 1113) and select H R (For example, H R 1113) and the RU52 vector 1103. As a result of the Hadamard product, the system may generate an output 1130 including RU52-1 (1131), RU52-2 (1132), RU52-3 (1133), and RU52-4 (1134), which correspond to RU52 (RU52 1101) phase shifted by +90°, −90°, −90°, and +90°, respectively.

[0121] 12 illustrates an example encoder 1200 for encoding with a shortened LDPC code to obtain a particular code rate (e.g., a target code rate r) in accordance with one or more embodiments. The encoder 1200 may include an LDPC encoder 1240, an information bit optimizer 1220, and / or a MUX 1260. The encoder 1200 and its components may be implemented using circuitry, firmware, and / or software. For example, the encoder 1200 may be implemented in the encoder 130 of the communication system 105. The LDPC encoder 1240 may receive a block of k information bits and generate n coded bits (or codewords or coded blocks) with a coding rate R=k / n.

[0122] 12, the information bit optimizer 1220 may include a bit permutation pattern or permutation pattern 1222 (denoted by Π) and / or masked bits 1224 (or bit mask). The permutation pattern 1222 may define or indicate how the order of the input bits can be permuted. The permutation pattern 1222 and / or masked bits 1224 may be pre-selected. The permutation pattern 1222 and / or masked bits 1224 may be stored in memory. Given k information bits, the permutation pattern 1222 may define, indicate, or store an index to one of all permutations of the k information bits (e.g., an index to one of all k! permutations). For example, the permutation pattern 1222 may indicate one of 1, 2, ... k!, each indicating a permutation of the k information bits. The bit mask 1224 may be a bit array of size equal to k information bits, with each bit of the bit mask indicating whether to keep or clear a corresponding bit of the k information bits. The information bit optimizer 1220 may be configured to perform bitwise or bitwise operations (e.g., NOT, AND, OR, XOR, shift, swap, etc.) to perform permutation (reordering) (using the permutation pattern Π) and / or bit masking (with the bit mask) on the k information bits.

[0123] The encoder 1200 may obtain data on the coding bit error rate (BER) and / or frame error probability (FEP; e.g., from past measurements or simulations) and determine the permutation pattern 1222 and / or the bit mask 1224 based on the bit error rate and / or frame error probability before generating the LDPC code. Here, the coding bit error rate (BER) refers to the number of coding bit errors per unit time. In this case, the number of coding bit errors refers to the number of received coded bits of the data stream that are altered due to errors (e.g., noise, interference, distortion, or any other bit errors). The bit error probability (FEP) refers to an expected value (e.g., average or weighted average) of the bit error rate. In this case, the bit error rate refers to the number of bit errors divided by the total number of bits transferred during a specific time interval. The encoder 1200 may determine the permutation pattern 1222 to reduce the BER or FEP (e.g., by changing the order of certain bits that are more susceptible to the BER or FEP). The encoder 1200 may determine the bit mask 1224 to reduce the BER or FEP (eg, by clearing certain bits that are more sensitive to the BER or FEP).

[0124] The encoder 1200 can monitor a data stream (e.g., a transmission of a digitally encoded signal) on a communication channel, determine or measure an encoding BER and / or FEP from the monitored data stream, and use the measured encoding BER and / or FEP to dynamically determine the permutation pattern 1222 and / or bit mask 1224. The encoder 1200 can be tunable to set the permutation pattern 1222 and / or bit mask 1224 to different pattern / bit masking values.

[0125] The encoder 1200 may receive / determine / identify a desired coding rate (or target coding rate) denoted by r (e.g., r=1 / 3) and a (base) coding rate of a base LDPC code (e.g., R=1 / 2). The encoder 1200 may first determine the target coding rate r and then determine a base coding rate R (or one or more base coding rates) based on the target coding rate r. Alternatively, the encoder 1200 may first determine a base coding rate R and then determine the target coding rate r (or one or more target coding rates) based on the base coding rate R.

[0126] The encoder 1200 may determine the values ​​of k and n (e.g., k=822, n=1944) based on a base coding rate (e.g., R=½). The base LDPC code may have (or be associated with) a coding rate R, a codeword length (or coding block length) n, and an information bit size k (e.g., n=648, 1296, 1944, 3888 if the base code is selected from the 802.11n-be standard).

[0127] The encoder 1200 calculates a parameter r indicating the size of information bits for a target coding rate r (e.g., r=1 / 3). TIFF2025133714000013.tif8162 may be determined. Parameters TIFF2025133714000014.tif6162 may be pre-selected for the target coding rate r. The encoder 1200 uses the following formula: There are cases where the value of TIFF2025133714000015.tif6162 is required.

[0128] TIFF2025133714000016.tif10162

[0129] The encoder 1200 encodes the target coding rate r (for example, r=1 / 3). The encoder 1200 may determine the parameters of TIFF2025133714000017.tif7162 using the following formula: There are cases where the value of TIFF2025133714000018.tif5162 is required.

[0130] TIFF2025133714000019.tif9162

[0131] The encoder 1200 encodes the target coding rate r (for example, r=1 / 3). Indicates the frozen block length or size of one or more bits added to TIFF2025133714000020.tif8162 The encoder 1200 may determine the parameters of TIFF2025133714000021.tif7162 using the following formula: You may be asked for TIFF2025133714000022.tif7161.

[0132] TIFF2025133714000023.tif9161

[0133] The parameters calculated above Using TIFF2025133714000024.tif6162, the target rate r can be calculated using the following formula:

[0134] TIFF2025133714000025.tif12161

[0135] The encoder 1200 uses Equations 16 to 19 to TIFF2025133714000026.tif7161 Possible combinations of parameters TIFF2025133714000027.tif7162, store the resulting parameter combinations in memory (e.g., in the form of a look-up table (LUT)) as shown in Table 1, and determine (obtain) the parameters by selecting the parameter combinations from the LUT. Using Table 1, the encoder 1200 may first determine a target coding rate r and then determine / select / pick one or more base coding rates R based on the target coding rate r. The encoder 1200 may first determine a base coding rate R and then determine one or more target coding rates based on the base coding rate R.

[0136] The encoder 1200 performs the encoding at a target coding rate r. TIFF2025133714000028.tif6161 information bit 1201. Then, the encoder 1200 extracts the TIFF2025133714000029.tif7162 may be added to form / generate k information bits 1210 for base code rate R. TIFF2025133714000030.tif7162 is zero It may become TIFF2025133714000031.tif7161. Added TIFF2025133714000032.tif7162 may contain one or more binary 1's.

[0137] In response to adding TIFF2025133714000033.tif8161, information bit optimizer 1220 may receive the resulting k information bits 1210 and perform at least one of reordering (permutation) using permutation pattern Π(1222) or bit masking using bit mask 1224 to generate optimized k information bits. Encoder 1200 may control information bit optimizer 1220 to dynamically turn on or off, thereby selectively skipping reordering and / or bit masking for simplicity without unduly impairing the performance of the resulting code. Encoder 1200 may determine that the coded BER or degree of FEP is below a threshold and turn off information bit optimizer 1220 to skip reordering and bit masking.

[0138] In response to the information bit optimizer 1220 generating the optimized k information bits, The LDPC encoder may receive k information bits and encode the k information bits to generate k coded bits (not shown) and (nk) parity bits 1250. In response to generating the (nk) parity bits 1250, the MUX 1260 receives two inputs: Receive TIFF2025133714000035.tif7163 and (nk) parity bits 1250, By concatenating (or combining, merging, unifying, or merging) TIFF2025133714000036.tif7163 with (nk) parity bits 1250 TIFF2025133714000037.tif6163 may be generated / output. TIFF2025133714000038.tif7163 may correspond to a codeword of an LDPC code with a target coding rate r. In other words, the encoder 1200 The encoder can generate TIFF2025133714000039.tif14163 with a coding rate of 1200. Supports TIFF2025133714000040.tif12163.

[0139] 13 illustrates an example encoder 1300 for encoding with a shortened LDPC code to obtain a particular code rate (e.g., a target code rate r=1 / 3), in accordance with one or more embodiments. Take TIFF2025133714000041.tif7163 (for example, 486 information bits), TIFF2025133714000042.tif8163 (e.g. 486 bits 1302) TIFF2025133714000043.tif7163 to generate k information bits 1310 (e.g., 972 information bits). The LDPC encoder 1340 may receive the 972 information bits 1310 and generate n coded bits (e.g., 1944 coded bits) including 972 parity bits 1350 according to a basic coding rate R=½. The MUX 1360 may concatenate the 486 information bits 1301 and the 972 parity bits 1350 to generate (1458=486+972) coded bits 1380. In other words, the encoder 1300 may encode the 486 information bits 1301 to generate 1458 coded bits 1380 (or codeword), with the coding rate r of the encoder 1300 corresponding to 1 / 3=486 / 1458.

[0140] 14 illustrates an example decoder 1400 for decoding with a shortened LDPC code in accordance with one or more embodiments. The decoder 1400 may include an LDPC decoder 1450, an LLR value optimizer 1420, a multiplexer (MUX) 1430, and / or a bit de-optimizer (or de-optimizer) 1460. The decoder 1400 and each of its components may be implemented using circuitry, firmware, and / or software. For example, the decoder 1400 may be implemented in the decoder 160 of the communication system 108. In response to the communication system 105 transmitting coded bits generated by the encoder 1200, the communication system 108 may receive the transmitted coded bits, and the decoder 1400 of the communication system 108 may decode LLR values ​​(e.g., LLR values ​​1410) corresponding to the transmitted coded bits. The LDPC decoder 1450 may receive a block of n coded bits and generate k decoded bits (or decoded information bits) with a coding rate R=k / n.

[0141] 14, the LLR value optimizer 1420 may have a similar configuration to the information bit optimizer of the encoder 1200. For example, the LLR value optimizer 1420 may be configured to perform reordering (using a permutation pattern Π) and / or bit masking (using a bit mask) on input LLR values ​​(e.g., k LLR values). The bit de-optimizer 1460 may be configured to perform an inverse operation of the information bit optimizer (e.g., the information bit optimizer 1220) of a corresponding encoder (e.g., the encoder 1200).

[0142] The decoder 1400 TIFF2025133714000044.tif7163 and contains 1412 (nk) LLR values ​​(corresponding to (nk) parity bits) TIFF2025133714000045.tif7165 may receive Log Likelihood Ratio (LLR) values ​​1410. The decoder 1400 may: By deleting TIFF2025133714000046.tif7166, There is a case where k LLR values ​​1413 are obtained / extracted from TIFF2025133714000047.tif7165. Deleted TIFF2025133714000048.tif7166 is encoded as follows by the corresponding encoder 1200: May support TIFF2025133714000049.tif14166.

[0143] The decoder 1400 may generate k optimized LLR values ​​via the LLR value optimizer 1420. The decoder 1400 may turn off the LLR value optimizer 1420 to skip reordering and bit masking.

[0144] In response to the LLR value optimizer 1220 generating the optimized k optimized LLR values ​​1441 (or if the optimization of the LLR values ​​is skipped, TIFF2025133714000050.tif7166), the MUX 1430 may receive as two inputs the k (optimized) LLR values ​​1441 and the (nk) LLR values ​​1412, and generate / output n LLR values ​​1440 by concatenating (or combining, merging, integrating, or merging) the k LLR values ​​1441 and the (nk) LLR values ​​1412.

[0145] The LDPC decoder 1450 may receive the n LLR values ​​1440 as output from the MUX 1430 and decode the n LLR values ​​1440 to generate k information bits. In response to determining that the corresponding encoder 1200 has performed information bit optimization, the bit de-optimizer 1460 may be configured to receive the k information bits from the LDPC decoder 1450 and perform bitwise or bit operations based on the permutation pattern Π (1222) or the bit mask (1224) in the encoder 1200 to perform inverse permutation and / or inverse bit masking on the input bits (e.g., the k information bits). If the corresponding encoder 1200 does not perform information bit optimization, the decoder 1400 may not perform inverse bit optimization (e.g., by turning off the bit de-optimizer).

[0146] In some implementations, in response to the bit de-optimizer 1460 generating the de-optimized k information bits 1470 (or in response to the LDPC decoder 1450 generating the k information bits if the corresponding encoder 1200 does not perform information bit optimization), the decoder 1400 extracts from the k information bits 1470 the first k information bits 1470. Extract TIFF2025133714000051.tif7165, TIFF2025133714000052.tif6165 may be output. TIFF2025133714000053.tif7166 may correspond to information bits of an LDPC code with a target coding rate r. In other words, the decoder 1400 TIFF2025133714000054.tif7165 can be generated, and the coding rate of the decoder is 1400. Supports TIFF2025133714000055.tif11165.

[0147] 15A and 15B illustrate example simulation results using a system to achieve a target data rate over a channel with (1) an LDPC code, (2) DNLOS signal propagation (e.g., non-line-of-sight 802.11 MIMO channel model type D), and (3) the number of spatial streams equal to one (Nss=1), in accordance with one or more embodiments. Referring to FIG. 15A , lines 1501, 1502, 1503, and 1504 correspond to simulation results (spectral efficiency vs. SNR) using the following modulation configurations, respectively: (1) 2×2 MIMO, QPSK, R=⅓, (2) 2×2 MIMO, BPSK, R=⅔, (3) 1×1 SISO, QPSK, R=⅓, and (4) 1×1 SISO, BPSK, R=⅔. Spectral efficiency refers to the information rate (or bit rate or effective data rate) over a given bandwidth in a communication system (units: bits / second / Hz). Referring to Figure 15B, lines 1551, 1552, 1553, and 1554 correspond to simulation results (PER vs. SNR) using the following modulation configurations: (1) 2x2 MIMO, QPSK, R=1 / 3; (2) 2x2 MIMO, BPSK, R=2 / 3; (3) 1x1 SISO, QPSK, R=1 / 3; and (4) 1x1 SISO, BPSK, R=2 / 3. As shown in Figures 15A and 15B, configuration (1) exhibits the highest spectral efficiency and the lowest PER.

[0148] 16A illustrates exemplary simulation results using a system to achieve a target data rate on a channel comprising (1) an LDPC code, (2) QPSK, and (3) 1×1 SISO, in accordance with one or more embodiments. Referring to FIG. 16A , lines 1601, 1602, 1603, and 1604 correspond to simulation results (PER vs. SNR) using the following configurations: (1) an R=⅓ native LDPC code on a DNLOS channel; (2) an R=⅔ native LDPC code concatenated with an R=⅔ repetition code on a DNLOS channel; (3) an R=⅓ native LDPC code on a BLOS channel (e.g., line-of-sight 802.11 channel model type B); and (4) an R=⅔ native LDPC code concatenated with an R=⅔ repetition code on a BLOS channel. As shown in FIG. 16A , the R=⅓ native code has a gain of 1 dB or more over the concatenated code.

[0149] 16B illustrates exemplary simulation results using a system to obtain a target data rate over a channel having (1) a BCC code and (2) a 1×1 SISO signal, in accordance with one or more embodiments. Referring to FIG. 16B , lines 1651, 1652, 1653, and 1654 correspond to simulation results (PER vs. SNR) using the following configurations: (1) a native BCC code with an R=⅔ repetition code concatenated with an R=⅔ repetition code over a QPSK channel (resulting in a ⅓ code rate), (2) a native BCC code with an R=⅓ repetition code over a BPSK channel (DNLOS), (3) a native BCC code with an R=⅔ repetition code over a QPSK channel (resulting in a ⅓ code rate), and (4) a native BCC code with an R=⅓ repetition code over a BLOS BPSK channel. As shown in FIG. 16B, a QPSK configuration using a concatenated BCC code (e.g., configuration (1)) and a BPSK configuration using a native BCC code (e.g., configuration (2)) perform quite similarly to each other, even though the concatenated BCC code configuration is easier to implement than the native BCC code configuration.

[0150] In some implementations, an apparatus (e.g., communication system 105) may include a transmitter (e.g., transmitter circuitry 120) and one or more processors (e.g., processor 2010). The one or more processors may be configured to identify a target data rate (e.g., 1 Mbps) for transmitting data. Based on at least the target data rate, the one or more processors may be configured to select a modulation scheme and a coding rate for transmitting data within the range of the target data rate. For example, the apparatus may select a modulation scheme and a coding rate using Tables 1 and 2 based on the target data rate. The one or more processors may be configured to identify a forward error correction (FEC) code (e.g., an LDPC code) having a first coding rate (e.g., a 1 / 2 coding rate, see FIG. 13 ) different from the selected coding rate based on at least the selected coding rate (e.g., a 1 / 3 coding rate). The one or more processors may be configured to encode data using an FEC code having a first coding rate with an FEC encoder (e.g., LDPC encoder 1340) to generate coded data corresponding to the selected coding rate. The one or more processors may be configured to modulate the coded data using a modulation scheme (e.g., BPSK or QPSK) to generate modulated data. The transmitter may be configured to transmit the modulated data.

[0151] In some implementations, the selected FEC code may be a low-density parity check (LDPC) code or a binary convolutional (BCC) code. In some implementations, the target data rate may be 1 Mbps or 1.5 Mbps, and the range of the target data rate may be 20% of the target data rate. For example, Tables 1 and 2 show that the resulting data rate is within 20% of the target data rate (e.g., 1 Mbps or 1.5 Mbps).

[0152] In some implementations, the FEC code may be an LDPC code with a first code rate (e.g., 1 / 2) greater than a selected code rate (e.g., 1 / 3). When encoding data, one or more processors may be configured to receive a first set of information bits (e.g., information bits 1301 of FIG. 13 ). The one or more processors may be configured to concatenate the first set of information bits with a set of information bits (e.g., set of information bits 1302) to generate a second set of information bits (e.g., set of information bits 1310). The one or more processors may be configured to encode, via an FEC encoder, the second set of information bits 1310 using the LDPC code with the first code rate (e.g., 1 / 2) to generate parity data (e.g., parity data 1350). The one or more processors may be configured to generate coded data by concatenating the first set of information bits 1301 and the parity data 1350 to achieve a selected coding rate.

[0153] In some implementations, the FEC code may be an LDPC code with a first code rate (e.g., 1 / 2) greater than a selected code rate (e.g., 1 / 3). When encoding data, one or more processors may be configured to receive a set of information bits. The one or more processors may be configured to encode the set of information bits using the LDPC code with the first code rate with an FEC encoder to generate coded bits and parity data. The one or more processors may be configured to puncture one or more bits from the parity data to generate punctured parity data. The one or more processors may be configured to generate coded data by concatenating the coded bits and the punctured parity data. For example, referring to FIG. 7B , the system may discard some parity bits (e.g., “punctured bits” 741) after encoding. In this way, the system may increase the effective code rate and reduce coding gain.

[0154] In some implementations, the FEC code may be a first BCC code with a first coding rate (e.g., 2 / 3) greater than a selected coding rate (e.g., 1 / 3). When encoding the data, the one or more processors may be configured to concatenate the first BCC code with a repetition code (e.g., a native 2 / 3 BCC code concatenated with a 1 / 2 repetition code; see Table 2) to generate a second BCC code corresponding to the selected coding rate (e.g., 1 / 3). The one or more processors may be configured to encode the data with the second BCC code by an FEC encoder to generate coded data corresponding to the selected coding rate.

[0155] 17 is a flow diagram illustrating a process 1700 for obtaining a particular data rate using various coding, modulation, and / or transmission schemes, according to one embodiment. In some implementations, the process 1700 for wireless communication over one or more channels is performed by one or more processors of the system (e.g., the processor 2010, transmitter circuitry 120, baseband circuitry 110, or encoder 130 of the communication system 105). In other embodiments, the process 1700 is performed by another entity (e.g., a computing system other than the communication system 105). In some implementations, the process 1700 includes more, fewer, or different steps than those shown in FIG. 17.

[0156] In step 1702, one or more processors of the system may identify a target data rate (e.g., 1 Mbps or 1.5 Mbps) for transmitting data over a channel having a frequency bandwidth (e.g., 20 MHz).

[0157] In step 1704, based on at least the target data rate, one or more processors may select a forward error correction (FEC) code, a coding rate, a modulation scheme, and a number of resource units (RUs) within a frequency bandwidth to transmit data within the range of the target data rate. For example, based on the target data rate (e.g., 1 Mbps or 1.5 Mbps), the device may use Table 1 or Table 2 to select the coding rate, modulation scheme, and number of RUs. In some implementations, the target data rate may be 1 Mbps or 1.5 Mbps, and the range of the target data rate may be 20% of the target data rate. For example, Tables 1 and 2 show that the resulting data rate is within 20% of the target data rate (e.g., 1 Mbps or 1.5 Mbps).

[0158] In some implementations, the method may include selecting a guard interval (GI) and a number of tones per RU based on at least a target data rate to transmit data within the target data rate. For example, based on the target data rate (e.g., 1 Mbps or 1.5 Mbps), the device may select the number of GIs and RUs using Table 1 or Table 2.

[0159] In step 1706, the one or more processors may cause an FEC encoder to encode the data using an FEC code and a code rate to generate coded data. In some implementations, the selected FEC code may be a low-density parity check (LDPC) code or a binary convolutional (BCC) code. In some implementations, the FEC code may have a first code rate that is different from the selected code rate. The method may include encoding the data using an FEC code with the first code rate by the FEC encoder to generate coded data corresponding to the selected code rate. For example, referring to FIG. 13 , the LDPC encoder 1340 may encode the data using an LDPC code with a code rate of ½ to generate coded data corresponding to a selected code rate of ⅓.

[0160] In some implementations, the FEC code may be an LDPC code, the selected code rate may be 1 / 3, and the first code rate may be 1 / 2 or 1 / 4 (see Table 1). In some implementations, the FEC code may be a BCC code, the selected code rate may be 1 / 3, and the first code rate may be 2 / 3 (see Table 2).

[0161] In step 1708, the one or more processors may modulate the coded data using a modulation scheme (e.g., BPSK or QPSK) to generate modulated data.

[0162] In step 1710, a transmitter in the system may transmit modulated data using multiple RUs (e.g., RU26, RU52, RU106, a combination of RU26 and RU52, and a combination of RU26 and RU106, as shown in FIG. 10).

[0163] References to "or" may be construed as inclusive, such that any term described with "or" may refer to one, more than one, or all of the described terms. Reference to at least one of a conjunctive list of terms may be construed as an inclusive or to refer to one, more than one, or all of the described terms. For example, a reference to "at least one of 'A' and 'B'" can include "A" alone, "B" alone, and both "A" and "B." Such references used in conjunction with "comprises" or other open-ended terminology can include additional items.

[0164] It should be noted that certain passages of this disclosure may refer to terms such as "first" and "second" in connection with a subset of transmit spatial streams, sound frames, responses, and devices to identify or distinguish one from the other(s). These terms are not intended to merely relate entities temporally or sequentially (e.g., first device and second device), although in some cases these entities may include such a relationship. Nor do these terms limit the number of possible entities (e.g., STAs, APs, beamformers, and / or beamformees) that may operate within a system or environment. It should be understood that the systems described above may provide multiples of any or each of these components, and these components may be provided on standalone machines or, in some embodiments, on multiple machines in a distributed system. Furthermore, bit field positions may be varied and multi-bit words may be used. Additionally, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on one or more articles of manufacture (e.g., floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes). The programs may be implemented in any programming language, such as LISP, PERL, C, C++, C#, or any byte-code language, such as JAVA. The software programs or executable instructions may be stored on one or more articles of manufacture as object code.

[0165] While the above description of the method and system will enable one skilled in the art to make and use the embodiments, one skilled in the art will understand and recognize that there are variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Accordingly, the present method and system should not be limited by the embodiments, methods, and examples described above, but by all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. 1. An apparatus comprising: a transmitter and one or more processors; the one or more processors Identifying a target data rate for transmitting data over a channel having a frequency bandwidth; selecting a forward error correction (FEC) code, a code rate, a modulation scheme, and a number of resource units (RUs) within the frequency bandwidth based on at least the target data rate to transmit data within the target data rate; encoding data with an FEC encoder using the FEC code and the code rate to generate encoded data; modulating the encoded data using the modulation scheme to generate modulated data; The apparatus, wherein the transmitter is configured to transmit the modulated data using multiple RUs.

2. The apparatus of claim 1 , wherein the selected FEC code is a low-density parity-check (LDPC) code or a binary convolutional (BCC) code.

3. the one or more processors 10. The apparatus of claim 1, further configured to select a guard interval (GI) and a number of tones per RU based on at least the target data rate to transmit data within the target data rate.

4. the target data rate is 1 Mbps or 1.5 Mbps; 2. The apparatus of claim 1, wherein the range of the target data rate is 20% of the target data rate.

5. the FEC code has a first coding rate that is different from the selected coding rate; the one or more processors 2. The apparatus of claim 1, further configured to: encode, by the FEC encoder, data with the FEC code having the first code rate to generate encoded data corresponding to the selected code rate.

6. the FEC code is an LDPC code, the selected coding rate is 1 / 3, The apparatus of claim 1 , wherein the first coding rate is 1 / 2 or 1 / 4.

7. the FEC code is a BCC code, the selected coding rate is 1 / 3, 2. The apparatus of claim 1, wherein the first coding rate is 2 / 3.

8. 1. A method comprising: Identifying, by one or more processors, a target data rate for transmitting data over a channel having a frequency bandwidth; selecting, by the one or more processors based at least on the target data rate, a forward error correction (FEC) code, a code rate, a modulation scheme, and a number of resource units (RUs) within a frequency bandwidth to transmit data within the target data rate; encoding the data with an FEC encoder using an FEC code and a code rate to generate encoded data; modulating, by the one or more processors, the coded data using the modulation scheme to generate modulated data; transmitting, by a transmitter, the modulated data using multiple RUs.

9. The method of claim 8 , wherein the selected FEC code is a low-density parity-check (LDPC) code or a binary convolutional (BCC) code.

10. 10. The method of claim 8, further comprising: selecting a guard interval (GI) and a number of tones per RU based at least on the target data rate to transmit data within the target data rate.

11. the target data rate is 1 Mbps or 1.5 Mbps; 9. The method of claim 8, wherein the range of the target data rate is 20% of the target data rate.

12. the FEC code has a first coding rate that is different from the selected coding rate; The method comprises:

9. The method of claim 8, further comprising: encoding, by the FEC encoder, data using the FEC code having the first code rate to generate encoded data corresponding to the selected code rate.

13. the FEC code is an LDPC code, the selected coding rate is 1 / 3, The method of claim 8 , wherein the first coding rate is ½ or ¼.

14. the FEC code is a BCC code, the selected coding rate is 1 / 3, 9. The method of claim 8, wherein the first coding rate is 2 / 3.

15. 1. An apparatus comprising: a transmitter and one or more processors; the one or more processors Identifying a target data rate for transmitting the data; selecting a modulation scheme and a coding rate based at least on the target data rate to transmit data within the target data rate range; Identifying a forward error correction (FEC) code having a first coding rate different from the selected coding rate based on at least the selected coding rate; encoding data with the FEC code having the first code rate by an FEC encoder to generate coded data corresponding to the selected code rate; modulating the encoded data using the modulation scheme to generate modulated data; The apparatus, wherein the transmitter is configured to transmit the modulated data.

16. 16. The apparatus of claim 15, wherein the selected FEC code is a low-density parity-check (LDPC) code or a binary convolutional (BCC) code.

17. the target data rate is 1 Mbps or 1.5 Mbps; 16. The apparatus of claim 15, wherein the range of the target data rate is 20% of the target data rate.

18. the FEC code is an LDPC code having the first coding rate greater than the selected coding rate; When encoding the data, the one or more processors: receiving a first set of information bits; concatenating the first set of information bits with a set of information bits to generate a second set of information bits; encoding, with the FEC encoder, the second set of information bits using an LDPC code having the first code rate to generate parity data; 16. The apparatus of claim 15, configured to generate the encoded data by concatenating the first set of information bits and the parity data to achieve the selected code rate.

19. the FEC code is an LDPC code having the first coding rate greater than the selected coding rate; When encoding the data, the one or more processors: receiving a set of information bits; encoding, with the FEC encoder, the set of information bits using an LDPC code having the first code rate to generate coded bits and parity data; puncturing one or more bits from the parity data to generate punctured parity data; 16. The apparatus of claim 15, configured to generate the coded data by concatenating the coded bits and the punctured parity data.

20. the FEC code is a first BCC code having the first coding rate greater than the selected coding rate; When encoding the data, the one or more processors: concatenating the first BCC code having the first coding rate with a repetition code to generate a second BCC code corresponding to the selected coding rate; 16. The apparatus of claim 15, configured to encode data with the second BCC code by the FEC encoder to generate the encoded data corresponding to the selected code rate.

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