Control device, electronic apparatus, control method

Abstract

To provide a control device, an electronic apparatus, and a control method that make it possible to reduce the number of output terminals of a processor that controls a driver.SOLUTION: A control unit 6 comprises: a CPU 30 that has an output terminal 31 for outputting a clock signal X1 and controls a driver 5 that drives a motor 50; and an additional relay circuit 40 that outputs an enable signal X3 later than input of a clock signal X2 to the driver 5 in response to input of the clock signal X1 and stops outputting the enable signal X3 in response to stoppage of input of the clock signal X1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a control device, an electronic device, and a control method. [Background technology]

[0002] Electronic devices such as printers include a processor such as a CPU (see, for example, Patent Document 1). In such electronic devices, the processor controls a driver that drives a load such as a motor. For example, when driving the load starts, the processor inputs a clock signal to the driver, and after the clock signal has stabilized, inputs an enable signal to the driver. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-138531 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional electronic devices, in order to realize control of the driver by the processor, it is necessary to provide the processor with separate output terminals for outputting the clock signal and for outputting the enable signal.

[0005] An object of the present invention is to provide a control device, an electronic device, and a control method that can reduce the number of output terminals of a processor that controls a driver. [Means for solving the problem]

[0006] A control device according to one aspect of the present invention includes a processor and a signal output circuit. The processor has an output terminal that outputs a clock signal and controls a driver that drives a load. The signal output circuit outputs an enable signal used to transition the driver from a stopped state to an operating state in response to input of the clock signal after the clock signal is input to the driver, and stops outputting the enable signal in response to input of the clock signal being stopped.

[0007] An electronic device according to another aspect of the present invention includes the control device, the driver, and the load.

[0008] A control method according to another aspect of the present invention is executed by a control device including a processor having an output terminal that outputs a clock signal and that controls a driver that drives a load, and a signal output circuit that outputs an enable signal used to transition the driver from a stopped state to an operating state in response to input of the clock signal after input of the clock signal to the driver and stops output of the enable signal in response to input of the clock signal being stopped, and includes an output step and a stop step. In the output step, the clock signal is output from the output terminal when driving of the load is started. In the stop step, output of the clock signal from the output terminal is stopped when driving of the load is terminated. [Effects of the Invention]

[0009] According to the present invention, it is possible to reduce the number of output terminals of the processor that controls the driver. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view showing the configuration of an image forming apparatus according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing the configuration of the control unit according to the embodiment of the present invention. [Figure 3]FIG. 3 is a circuit diagram showing the configuration of an additional relay circuit of the control unit according to the embodiment of the present invention. [Figure 4] FIG. 4 is a flowchart showing an example of a drive control process executed by the CPU of the control unit according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Note that the following embodiment is an example of a specific embodiment of the present invention and does not limit the technical scope of the present invention.

[0012] [Configuration of image forming apparatus 100] First, the configuration of an image forming apparatus 100 according to an embodiment of the present invention will be described with reference to FIGS.

[0013] The image forming apparatus 100 is a multifunction peripheral that has multiple functions, such as a scanning function for reading an image from a document, a printing function for forming an image based on image data, a facsimile function, and a copy function. The image forming apparatus 100 is an example of an electronic device of the present invention. The present invention may also be applied to electronic devices such as scanners, printers, fax machines, copy machines, personal computers, laptop computers, televisions, microwave ovens, and refrigerators.

[0014] As shown in Fig. 1, image forming apparatus 100 includes an ADF (Auto Document Feeder) 1, an image reading unit 2, an image forming unit 3, and a paper feeding unit 4. Image forming apparatus 100 also includes a driver 5, a control unit 6, and a motor 50 shown in Fig. 2. Control unit 6 is an example of a control device of the present invention.

[0015] The ADF 1 transports documents to be scanned by the scanning function, and includes a document setting unit, a plurality of document transport rollers, a document holder, and a paper ejection unit.

[0016] The image reading unit 2 realizes the scanning function and includes a document table, a light source, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device).

[0017] The image forming unit 3 realizes the printing function. As shown in Fig. 1, the image forming unit 3 includes a photosensitive drum 11, a charging roller 12, an optical scanning device 13, a developing device 14, a toner container 15, a transfer roller 16, a cleaning device 17, a fixing device 18, and a paper output tray 19.

[0018] The photosensitive drum 11 is rotatably mounted. The charging roller 12 is provided in contact with the surface of the photosensitive drum 11 and charges the surface of the photosensitive drum 11.

[0019] The optical scanning device 13 irradiates the surface of the photosensitive drum 11, which has been charged by the charging roller 12, with light based on image data. An electrostatic latent image is formed on the surface of the photosensitive drum 11 by the optical scanning device 13.

[0020] The developing device 14 uses toner to develop the electrostatic latent image formed on the surface of the photosensitive drum 11. The toner container 15 supplies the toner to the developing device 14.

[0021] The transfer roller 16 transfers the electrostatic latent image (toner image) developed by the developing device 14 onto a sheet supplied by the paper feed unit 4. The cleaning device 17 cleans the surface of the photosensitive drum 11 after the toner image has been transferred by the transfer roller 16.

[0022] The fixing device 18 fixes the toner image transferred onto the sheet by the transfer roller 16. The sheet onto which the toner image has been fixed by the fixing device 18 is discharged to a paper discharge tray 19.

[0023] The paper feed unit 4 supplies sheets to the image forming unit 3. As shown in FIG. 1, the paper feed unit 4 includes a paper feed cassette 21, a pickup roller 22, a paper feed roller 23, a plurality of sheet transport rollers 24, and a registration roller 25.

[0024] The paper feed cassette 21 is detachably provided in the housing of the image forming apparatus 100, and holds sheets to be supplied to the image forming unit 3. The pickup roller 22 picks up the top sheet from the paper feed cassette 21 among the multiple sheets stacked in the paper feed cassette 21.

[0025] The paper feed roller 23 conveys the sheet picked up from the paper feed cassette 21 by the pickup roller 22 to a sheet supply path leading to the image forming unit 3. A plurality of sheet conveying rollers 24 are provided in the sheet supply path and convey the sheet to the image forming unit 3.

[0026] The registration rollers 25 are provided at the most downstream portion of the sheet supply path, and supply the sheet to the image forming unit 3 at a predetermined timing.

[0027] The driver 5 drives the motor 50. The motor 50 rotates each of the document transport rollers of the ADF 1. For example, the motor 50 is a stepping motor. The motor 50 is an example of a load of the present invention. The motor 50 may be used to drive the image forming unit 3 or the paper feeding unit 4. The load of the present invention may also be a brushless motor or the like, and the load of the present invention is not limited to a motor and may also be a heater or the like.

[0028] The control unit 6 performs overall control of the image forming apparatus 100. The control unit 6 may be an engine control unit that controls the ADF 1 and the image reading unit 2.

[0029] As shown in FIG. 2, the control unit 6 includes a CPU 30.

[0030] The CPU 30 is a processor that executes various types of arithmetic processing and controls the driver 5. The CPU 30 is an example of the processor of the present invention.

[0031] In the image forming apparatus 100, when the driving of the motor 50 starts, a clock signal X2 (see FIG. 2) is input to the driver 5, and then an enable signal X3 (see FIG. 2) is input to the driver 5. While the enable signal X3 is being input, the driver 5 rotates the motor 50 at a speed according to the frequency of the input clock signal X2.

[0032] In conventional electronic devices, in order to realize control of the driver 5 by the CPU 30, it is necessary to provide the CPU 30 with separate output terminals for outputting the clock signal X2 and for outputting the enable signal X3.

[0033] In contrast to this, in the image forming apparatus 100 according to the embodiment of the present invention, the number of output terminals of the CPU 30 that controls the driver 5 can be reduced, as will be described below.

[0034] Specifically, the CPU 30 includes an output terminal 31 (see FIG. 2) that outputs a clock signal X1 (see FIG. 2).

[0035] The control unit 6 also includes an additional relay circuit 40 shown in FIGS.

[0036] 2, the CPU 30 includes an output processing unit 32 and a stop processing unit 33. Specifically, the CPU 30 functions as each of the above-mentioned processing units by executing a control program stored in advance in a ROM (not shown).

[0037] [Configuration of additional relay circuit 40] Next, the configuration of the additional relay circuit 40 will be described with reference to FIGS.

[0038] As shown in FIG. 3, the additional relay circuit 40 includes a clock signal output circuit 41 and an enable signal output circuit 42.

[0039] In response to an input of a clock signal X1, the clock signal output circuit 41 generates and outputs a clock signal X2 that is identical to the clock signal X1.

[0040] As shown in FIG. 3, the clock signal output circuit 41 includes resistors R1 to R3 and a transistor Q1.

[0041] The transistor Q1 is a PNP transistor. The emitter terminal of the transistor Q1 is connected to a power supply Vcc (see FIG. 3) via a resistor R1. The emitter terminal of the transistor Q1 is also connected to an input terminal 51 of the driver 5 (see FIG. 2). A clock signal X2 is input to the input terminal 51. The base terminal of the transistor Q1 is connected to an output terminal 31 of the CPU 30 (see FIG. 2) via a resistor R2. The base terminal of the transistor Q1 is also connected to ground via a resistor R3. The collector terminal of the transistor Q1 is connected to ground.

[0042] In the clock signal output circuit 41, the transistor Q1 is in an on state when the clock signal X1 is not output from the output terminal 31 (see FIG. 2) of the CPU 30. When the transistor Q1 is in an on state, the input terminal 51 (see FIG. 2) of the driver 5 is connected to ground. In other words, when the clock signal X1 is not output from the output terminal 31 of the CPU 30, the clock signal output circuit 41 does not generate the clock signal X2.

[0043] In the clock signal output circuit 41, the transistor Q1 is in an off state when the clock signal X1 is output from the output terminal 31 (see FIG. 2) of the CPU 30 and the signal level of the clock signal X1 is high. When the transistor Q1 is in an off state, the input terminal 51 (see FIG. 2) of the driver 5 is connected to the power supply Vcc via the resistor R1. As a result, a high-level signal constituting the clock signal X2 is output. Also, in the clock signal output circuit 41, the transistor Q1 is in an on state when the clock signal X1 is output from the output terminal 31 of the CPU 30 and the signal level of the clock signal X1 is low. When the transistor Q1 is in an on state, the input terminal 51 of the driver 5 is connected to ground. As a result, a low-level signal constituting the clock signal X2 is output.

[0044] The enable signal output circuit 42 outputs the enable signal X3 in response to the input of the clock signal X1 after the clock signal X2 is input to the driver 5. The enable signal X3 is used to transition the driver 5 from a stopped state to an operating state. Furthermore, the enable signal output circuit 42 stops outputting the enable signal X3 in response to the stop of the input of the clock signal X1. The enable signal output circuit 42 is an example of a signal output circuit of the present invention.

[0045] As shown in FIG. 3, the enable signal output circuit 42 includes resistors R4 to R6, a transistor Q2, capacitors C1 to C2, and a thermistor T1.

[0046] The transistor Q2 is a PNP transistor. The emitter terminal of the transistor Q2 is connected to the power supply Vcc via a resistor R4. The emitter terminal of the transistor Q2 is also connected to an input terminal 52 (see FIG. 2) of the driver 5. An enable signal X3 is input to the input terminal 52. The base terminal of the transistor Q2 is connected to an output terminal 31 (see FIG. 2) of the CPU 30 via a resistor R5. The base terminal of the transistor Q2 is also connected to ground via a capacitor C1. The base terminal of the transistor Q2 is also connected to ground via a thermistor T1. The collector terminal of the transistor Q2 is connected to ground.

[0047] The emitter terminal of the transistor Q2 is connected to ground via a capacitor C2 and a resistor R6.

[0048] In the enable signal output circuit 42, the transistor Q2 is in an on state when the clock signal X1 is not output from the output terminal 31 (see FIG. 2) of the CPU 30. When the transistor Q2 is in an on state, the input terminal 52 (see FIG. 2) of the driver 5 is connected to ground. In other words, when the clock signal X1 is not output from the output terminal 31 of the CPU 30, the enable signal output circuit 42 does not generate the enable signal X3.

[0049] In the enable signal output circuit 42, the capacitor C1 is charged when the clock signal X1 is output from the output terminal 31 (see FIG. 2) of the CPU 30 and the signal level of the clock signal X1 is high. When the capacitor C1 is charged, the voltage applied to the base terminal of the transistor Q2 gradually increases, and the transistor Q2 switches from the ON state to the OFF state. When the transistor Q2 is in the OFF state, the capacitor C2 is connected to the power supply Vcc via the resistor R4. As a result, the capacitor C2 is charged, and the voltage applied to the input terminal 52 (see FIG. 2) of the driver 5 gradually increases.

[0050] In the enable signal output circuit 42, the capacitor C1 discharges when the clock signal X1 is output from the output terminal 31 (see FIG. 2) of the CPU 30 and the signal level of the clock signal X1 is low, thereby keeping the transistor Q2 in the off state for a while.

[0051] Here, the higher the duty ratio of the clock signal X1, the longer the charging time of the capacitor C1 and the shorter the discharging time of the capacitor C1. In other words, if the duty ratio of the clock signal X1 is sufficiently high, it is possible to maintain the transistor Q2 in the off state regardless of the switching of the signal level of the clock signal X1. Therefore, it is possible to increase the voltage applied to the input terminal 52 of the driver 5 (see FIG. 2) to the signal level of the enable signal X3.

[0052] Specifically, in the enable signal output circuit 42, when the duty ratio of the clock signal X1 is equal to or greater than a specific value, the transistor Q2 can be maintained in the off state regardless of the switching of the signal level of the clock signal X1. Also, in the image forming apparatus 100, the clock signal X1 having a duty ratio equal to or greater than the specific value is output from the output terminal 31 of the CPU 30.

[0053] The electrical resistance of the thermistor T1 changes depending on the temperature of the motor 50. Specifically, the thermistor T1 is an NTC thermistor whose electrical resistance decreases as the temperature rises. For example, the thermistor T1 is provided in contact with the motor 50. Note that the thermistor T1 may be provided in a location where it can detect the temperature of the motor 50.

[0054] The thermistor T1 stops outputting the enable signal X3 when the temperature of the motor 50 exceeds a predetermined reference temperature. Specifically, when the temperature of the motor 50 exceeds the reference temperature, the thermistor T1's electrical resistance becomes extremely low. As a result, the capacitor C1 is not charged even when the signal level of the clock signal X1 is high. Therefore, regardless of whether the signal level of the clock signal X1 changes, the transistor Q2 is turned on and the output of the enable signal X3 is stopped. For example, the reference temperature is 125 degrees.

[0055] By providing the thermistor T1, it is possible to prevent the motor 50 from overheating and catching fire when the output of the clock signal X1 continues at the timing when the motor 50 should be stopped, such as when a jam occurs due to runaway of the CPU 30.

[0056] [Functions of each processing unit included in CPU 30] Next, the function of each processing unit included in the CPU 30 will be described with reference to FIG.

[0057] The output processing unit 32 causes the output terminal 31 to output the clock signal X1 when the driving of the motor 50 starts.

[0058] The stop processing unit 33 stops the output of the clock signal X1 from the output terminal 31 when the driving of the motor 50 is to be terminated.

[0059] [Drive control processing] 4, the control method of the present invention will be described along with an example of the procedure of the drive control process executed by the CPU 30 in the image forming apparatus 100. Here, steps S11, S12, etc. represent the numbers of the process procedures (steps) executed by the CPU 30. The drive control process is executed when a transport process is executed to transport a document using the ADF 1.

[0060] <Step S11> First, in step S11, the CPU 30 outputs the clock signal X1 from the output terminal 31. The process of step S11 is an example of an output step of the present invention, and is executed by the output processing unit 32 of the CPU 30.

[0061] By executing the process of step S11, the clock signal X1 is input to the additional relay circuit 40 (see FIG. 2). As a result, the clock signal X2 is output from the clock signal output circuit 41. Furthermore, after the clock signal X2 is input to the driver 5, the enable signal output circuit 42 outputs the enable signal X3.

[0062] <Step S12> In step S12, the CPU 30 determines whether the enable signal output circuit 42 has output the enable signal X3.

[0063] For example, the CPU 30 determines that the enable signal output circuit 42 has output the enable signal X3 when a predetermined first time has elapsed since the execution of the process of step S11.

[0064] Here, when the CPU 30 determines that the enable signal X3 has been output from the enable signal output circuit 42 (Yes in S12), it shifts the process to step S13. On the other hand, if the enable signal X3 has not been output from the enable signal output circuit 42 (No in S12), the CPU 30 waits for the enable signal X3 to be output from the enable signal output circuit 42 in step S12.

[0065] <Step S13> In step S13, the CPU 30 starts the transport process.

[0066] <Step S14> In step S14, the CPU 30 determines whether the transport process has ended normally or due to the occurrence of an error.

[0067] Here, when the CPU 30 determines that the transport process has ended (Yes in S14), it shifts the process to step S15. On the other hand, when the transport process has not ended (No in S14), the CPU 30 waits for the end of the transport process in step S14.

[0068] <Step S15> In step S15, the CPU 30 stops the output of the clock signal X1 from the output terminal 31. The process of step S15 is executed by the stop processing unit 33 of the CPU 30.

[0069] As described above, the control unit 6 includes an enable signal output circuit 42 that outputs the enable signal X3 in response to the input of the clock signal X1 after the input of the clock signal X2 to the driver 5, and stops outputting the enable signal X3 in response to the stop of the input of the clock signal X1. This makes it possible to output the enable signal X3 without providing an output terminal for the enable signal X3 in the CPU 30. This makes it possible to reduce the number of output terminals of the CPU 30 that control the driver 5.

[0070] [Notes on the Invention] The following is a summary of the invention extracted from the above-described embodiment. Note that the configurations and processing functions described in the following supplementary notes can be selected and combined as desired.

[0071] <Appendix 1> A control device comprising: a processor having an output terminal that outputs a clock signal and that controls a driver that drives a load; and a signal output circuit that outputs an enable signal used to transition the driver from a stopped state to an operating state in response to input of the clock signal after the clock signal is input to the driver, and stops outputting the enable signal in response to input of the clock signal being stopped.

[0072] <Appendix 2> 2. The control device according to claim 1, wherein the signal output circuit includes a thermistor that stops output of the enable signal when the temperature of the load exceeds a predetermined reference temperature.

[0073] <Appendix 3> The control device described in Appendix 1 or 2, wherein the processor outputs the clock signal from the output terminal when driving of the load starts, and stops outputting the clock signal from the output terminal when driving of the load ends.

[0074] <Appendix 4> An electronic device comprising the control device according to any one of Supplementary Notes 1 to 3, the driver, and the load.

[0075] <Appendix 5> A control method executed by a control device comprising: a processor having an output terminal that outputs a clock signal and that controls a driver that drives a load; and a signal output circuit that outputs an enable signal used to transition the driver from a stopped state to an operating state in response to the input of the clock signal after the clock signal is input to the driver, and stops outputting the enable signal in response to the stop of the input of the clock signal, the control method including: an output step of outputting the clock signal from the output terminal when driving of the load starts; and a stop step of stopping output of the clock signal from the output terminal when driving of the load ends. [Explanation of symbols]

[0076] 1 ADF 2 Image reading unit 3 Image forming unit 4 Paper feed section 5 Driver 6 Control Unit 30 CPU 31 Output terminal 32 Output Processing Section 33 Stop processing section 40 Additional relay circuit 41 Clock signal output circuit 42 Enable signal output circuit 50 motor 100 Image forming device

Claims

1. a processor having an output terminal for outputting a clock signal and controlling a driver that drives a load; a signal output circuit that outputs an enable signal used to transition the driver from a stopped state to an operating state in response to an input of the clock signal after the clock signal is input to the driver, and stops outputting the enable signal in response to the stop of the input of the clock signal; A control device comprising:

2. the signal output circuit includes a thermistor that stops output of the enable signal when the temperature of the load exceeds a predetermined reference temperature. The control device according to claim 1 .

3. the processor causes the clock signal to be output from the output terminal when driving of the load is started, and causes the processor to stop outputting the clock signal from the output terminal when driving of the load is ended; The control device according to claim 1 or 2.

4. The control device according to claim 1 or 2; The driver; The load; An electronic device comprising:

5. A control method executed by a control device including: a processor having an output terminal that outputs a clock signal and that controls a driver that drives a load; and a signal output circuit that outputs an enable signal used to transition the driver from a stopped state to an operating state in response to an input of the clock signal after the input of the clock signal to the driver, and stops outputting the enable signal in response to a stop of the input of the clock signal, an output step of outputting the clock signal from the output terminal when driving of the load is started; a stopping step of stopping the output of the clock signal from the output terminal when driving of the load is terminated; A control method comprising:

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