Semiconductor memory device
By connecting semiconductor chips through insulating members and conductive layers, the semiconductor memory device achieves higher integration and improved electrical connectivity, addressing the challenge of high integration in existing technologies.
JP2025136694APending Publication Date: 2025-09-19KIOXIA CORP
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Patent Information
- Application Number
- JP2024035464
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2025-09-19
AI Technical Summary
Technical Problem
Existing semiconductor memory devices face challenges in achieving high integration.
Method used
The semiconductor memory device comprises a first and second semiconductor chip connected by insulating members and conductive layers, with transistors and bonding electrodes, allowing for enhanced electrical connectivity and integration.
Benefits of technology
This configuration enables higher integration and efficient electrical connections between chips, improving the performance and functionality of semiconductor memory devices.
✦ Generated by Eureka AI based on patent content.
Abstract
To provide a semiconductor memory device capable of achieving high integration.SOLUTION: A semiconductor memory device comprises first and second semiconductor chips. The first semiconductor chip includes: a first insulating member that extends in a first direction from a first surface of a semiconductor substrate toward a first position between the first surface and a second surface of the semiconductor substrate, and includes a first portion and a second portion spaced apart from each other in a second direction intersecting the first direction; a second insulating member that extends in the first direction from the second surface of the semiconductor substrate toward the first position of the semiconductor substrate, and includes a third portion provided at a position overlapping the first portion when viewed from the first direction, and a fourth portion provided at a position overlapping the second portion when viewed from the first direction; a target circuit that is provided in a region of the semiconductor substrate located between the first portion and the second portion when viewed from the first direction; a control circuit that adjusts an electrical characteristic of the target circuit; and a plurality of transistors that are provided on the first surface of the semiconductor substrate.SELECTED DRAWING: Figure 7
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