Light-emitting device, wearable device, display device, photoelectric conversion device, and electronic apparatus

Abstract

To provide a technology advantageous for both maintaining voltage resistance within pixels and reducing pixel size in a light-emitting device.SOLUTION: The light-emitting device has a plurality of pixels arranged on a substrate. Each of the plurality of pixels has a first trench-type separation portion that separates two adjacent regions having different conductivity types, and a second trench-type separation portion that separates two adjacent regions having the same conductivity type. The depth of the second separation portion is greater than the depth of the first separation portion.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a light-emitting device, a wearable device, a display device, a photoelectric conversion device, and an electronic device. [Background technology]

[0002] Due to their low power consumption and fast response speed, organic EL elements are becoming the main light-emitting devices (display devices) replacing liquid crystals, and further improvements in performance are being demanded. Organic EL elements have a pixel array that causes organic layers to emit light. The pixel array is provided with multiple transistors for passing currents according to the voltages of various brightness signals, and it is known that shallow trench isolation (STI) with a trench structure is used to electrically isolate the multiple transistors. Patent Document 1 discloses that STI is configured to a certain depth within a pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-71323 Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration disclosed in Patent Document 1, if pixel density is increased in line with future trends toward higher resolution, it may be necessary to reduce the separation width between transistors in the pixel array in order to reduce pixel size. Simply reducing the separation width between transistors to meet this requirement makes it difficult to maintain the breakdown voltage within the pixel, and there is a risk of image quality degradation (i.e., a decrease in display quality) such as a decrease in display contrast due to leakage current between pixels.

[0005] Therefore, an object of the present invention is to provide a technique that is advantageous for achieving both maintaining the breakdown voltage within a pixel in a light-emitting device and reducing the pixel size. [Means for solving the problem]

[0006] In order to achieve the above object, a light-emitting device according to one aspect of the present invention is a light-emitting device having a plurality of pixels arranged on a substrate, each of the plurality of pixels having a trench-type first isolation portion that separates two adjacent regions of different conductivity types, and a trench-type second isolation portion that separates two adjacent regions of the same conductivity type, and the depth of the second isolation portion is greater than the depth of the first isolation portion.

[0007] Further objects and other aspects of the present invention will become apparent from the following description of preferred embodiments with reference to the accompanying drawings. [Effects of the Invention]

[0008] According to the present invention, for example, it is possible to provide a technique that is advantageous in achieving both maintaining the breakdown voltage within a pixel in a light-emitting device and reducing the pixel size. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing a configuration example of a light emitting device according to a first embodiment; [Figure 2] FIG. 1 is an enlarged plan view showing one pixel in the light-emitting device according to the first embodiment; [Figure 3] 1 is a cross-sectional view of each pixel in a light-emitting device according to a first embodiment; [Figure 4] FIG. 1 is a diagram for explaining a method for forming a first element isolation portion and a second element isolation portion on a semiconductor substrate. [Figure 5] 10 is a cross-sectional view of each pixel in the light-emitting device according to the second embodiment; [Figure 6] 1 is a cross-sectional view showing an example of the configuration of a pixel of a light-emitting device according to each embodiment; [Figure 7] FIG. 1 is a diagram illustrating an example of a display device using a light-emitting device according to each embodiment. [Figure 8] 1 is a diagram showing an example of a photoelectric conversion device using a light-emitting device according to each embodiment; [Figure 9]1 is a diagram showing an example of an electronic device using a light-emitting device according to each embodiment; [Figure 10] FIG. 1 is a diagram illustrating an example of a display device using a light-emitting device according to each embodiment. [Figure 11] FIG. 1 is a diagram illustrating an example of a wearable device using the light-emitting device of each embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0011] Hereinafter, embodiments of the light emitting device according to the present invention will be described. Note that the following embodiments are merely examples of the present invention, and the present invention is not limited to the numerical values, shapes, materials, components, arrangement and connection of the components, etc.

[0012] First Embodiment A first embodiment of the present invention will be described. FIG. 1 is a block diagram showing an example of the configuration of a light emitting device 10 of this embodiment. A pixel array 100 (pixel unit) has a plurality of pixels 101 arranged two-dimensionally (in a matrix) across a plurality of rows and a plurality of columns on a substrate. A control signal is input to each pixel 101 from a vertical scanning circuit 102 via a scanning line 103, and a luminance signal voltage is input from a signal output circuit 104 via a signal line 105. The vertical scanning circuit 102 and the signal output circuit 104 are controlled by a control circuit 106 (control unit). The signal output circuit 104 converts image data scanned by the horizontal scanning circuit and input to the pixels of each column into an analog signal voltage, and outputs a luminance signal voltage corresponding to the analog signal voltage to the signal line 105.

[0013] FIG. 2 is an enlarged plan view of one pixel 101 in the light-emitting device 10 of this embodiment, illustrating an example in which two sub-pixels (a first sub-pixel 206 and a second sub-pixel 207) emitting light of different colors are arranged. Each sub-pixel unit can be configured with a switch transistor 201, a drive transistor 202, a reset transistor 203, a selection transistor 204, and a well contact 205. The switch transistor 201 controls the emission of the light-emitting element. The drive transistor 202 drives the light-emitting element by supplying a current to the light-emitting element according to data input from the selection transistor 204 as a luminance signal. The reset transistor 203 resets the light-emitting element. The selection transistor 204 controls the input of data to the pixel (light-emitting element). The well contact 205 electrically connects a well in the semiconductor substrate to a wiring layer arranged on the semiconductor substrate. In this embodiment, the switch transistor 201, drive transistor 202, reset transistor 203, and selection transistor 204 have source / drain regions made of P-type semiconductor regions, and the well contact 205 is made of an N-type semiconductor region. The various transistors and well contacts are electrically isolated by a trench-type (groove structure) element isolation portion, which will be described later. STI (Shallow Trench Isolation) can be used as the trench-type element isolation portion. Note that, although this embodiment will be described assuming that the conductivity type of the various transistors is P-type, they may also be N-type.

[0014] FIG. 3 shows an example of a cross-sectional view of each pixel 101 in the light-emitting device 10 of this embodiment. The cross-sectional view of FIG. 3 is, for example, a cross-sectional view taken along the line Y-Y′ in FIG. 2. Each pixel 101 of this embodiment may include a light-emitting element 312 and a pixel circuit 311 that drives the light-emitting element 312. Furthermore, in each pixel 101 of this embodiment, a first element isolation portion 301 and a second element isolation portion 302 are formed in the semiconductor substrate 300 as trench-type element isolation portions that isolate various transistors and well contacts in the pixel circuit 311. The first element isolation portion 301 and the second element isolation portion 302 are element isolation portions having different depths (trench depths). Specifically, the depth of the second element isolation portion 302 is greater than the depth of the first element isolation portion 301. Note that, although the conductivity type of the pixel circuit 311 will be described below as P-type, it may also be N-type.

[0015] Pixel circuits 311 constituting the pixel array 100 (each pixel 101) are disposed within the semiconductor substrate 300, and various transistors are formed in the pixel circuits 311. Each transistor has an N-type well 320, a P-type lightly doped region 321, a P-type source / drain 322, a gate electrode 303, a sidewall 304, and a silicide prevention film 305. Two adjacent transistors are separated by a first element isolation region 301 or a second element isolation region 302. As shown in FIG. 3 , the first element isolation region 301 and the second element isolation region 302 may be used separately within a single subpixel or between multiple subpixels. In the latter case, for example, one subpixel may be formed using only the first element isolation region 301, and another subpixel may be formed using only the second element isolation region 302. That is, the first element isolation region 301 and the second element isolation region 302 can be variously modified and combined.

[0016] Silicide 306 is formed in the portion where the anti-silicide film 305 is not provided and the semiconductor substrate 300 (e.g., silicon) is exposed. An inter-wiring layer film 307, a plug 308, a wiring 309, and a metal electrode 310 are formed on the silicide 306. The metal electrode 310 is divided into a B sub-pixel 331, a G sub-pixel 332, and an R sub-pixel 333. A light-emitting element 312 that emits light of the corresponding color is formed on the metal electrode 310 of each sub-pixel.

[0017] The light-emitting element 312 has an optical adjustment layer 334 with a height that satisfies the optical interference conditions for each emitted color, a transparent anode electrode 335, a pixel separation layer 336, an organic light-emitting layer 337, and a cathode electrode 338. A protective layer 339 is formed on the cathode electrode 338, and a blue color filter 341b, a green color filter 341g, and a red color filter 341r, each having spectral characteristics corresponding to the color of the sub-pixel, are disposed on the protective layer 339. This allows light emission corresponding to the luminance input signal voltage of each sub-pixel to be obtained.

[0018] In the light emitting device 10 of this embodiment, a first isolation region 301 or a second isolation region 302 is arranged between a plurality of element regions (transistor regions, well contact regions) in a pixel circuit 311 depending on the required withstand voltage. This makes it possible to maintain the withstand voltage within the pixel 101 while also reducing the pixel size. As described above, the second isolation region 302 is configured to have a trench depth greater than that of the first isolation region 301.

[0019] The first isolation portion 301 (first isolation portion) is arranged to electrically isolate two adjacent regions of different conductivity types. In this embodiment, the first isolation portion 301 can be arranged between the well contact 205 and the adjacent switch transistor 201, and / or between the well contact 205 and the adjacent drive transistor 202. The first isolation portion 301 may also be arranged between the well contact 205 and the adjacent reset transistor 203, and / or between the well contact 205 and the adjacent select transistor 204.

[0020] 3, a semiconductor region 351a (first semiconductor region) constituting the source / drain of a transistor 351 and a semiconductor region 352 (third semiconductor region) constituting the adjacent well contact have mutually different conductivity types. Therefore, a first element isolation portion 301 is disposed between the transistor 351 (semiconductor region 351a) and the well contact (semiconductor region 352).

[0021] On the other hand, the second element isolation section 302 (second isolation section) is arranged to electrically isolate two adjacent regions of the same conductivity type. In this embodiment, the second element isolation section 302 can be arranged between two drive transistors 202 arranged adjacent to each other and / or between two reset transistors 203 arranged adjacent to each other. The second element isolation section 302 can be arranged between two switch transistors arranged adjacent to each other. The second element isolation section 302 may be arranged between a reset transistor and an adjacent switch transistor 201 and / or between a switch transistor 201 and an adjacent select transistor 204.

[0022] 3, the semiconductor region 353a (first semiconductor region) constituting the source / drain of the transistor 353 and the semiconductor region 354a (second semiconductor region) constituting the source / drain of the adjacent transistor 354 are of the same conductivity type. Therefore, the second element isolation portion 302 is disposed between the transistor 353 (semiconductor region 353a) and the transistor 354 (semiconductor region 354a).

[0023] The reasons and effects of selectively using the first isolation region 301 and the second isolation region 302 in the light emitting device 10 of this embodiment will be described below.

[0024] The source / drain region of each drive transistor is composed of a P-type semiconductor region. Therefore, a PNP parasitic bipolar transistor consisting of a P-type source / drain 322, an N-type well 320, and a P-type source / drain 322 may be formed between two adjacent drive transistors via an isolation region. Increasing the base width of the parasitic bipolar transistor (i.e., the width of the N-type region) is effective for reducing the current flowing through the PNP parasitic bipolar transistor. However, increasing the width of the isolation region in a direction parallel to the surface of the semiconductor substrate 300 to increase the base width (width of the N-type region) may make it difficult to reduce the pixel size. Therefore, in this embodiment, the depth of the isolation region disposed between two adjacent drive transistors is increased as a means for increasing the base width of the parasitic bipolar transistor (width of the N-type region). In other words, a second isolation region 302 is disposed between the two adjacent drive transistors. This makes it possible to suppress the operation of the parasitic bipolar transistor while suppressing the increase in the width of the isolation region in a direction parallel to the surface of the semiconductor substrate 300.

[0025] Furthermore, the drive transistor is a transistor for passing a current corresponding to the voltage of an arbitrary luminance signal for each pixel. Therefore, a higher voltage is applied to the source / drain region of the drive transistor than to the other reset transistors, switch transistors, or selection transistors. Depending on the luminance signal in the pixel, the highest voltage within the subpixel may be applied to the source / drain region of the drive transistor. Therefore, the highest breakdown voltage within the pixel is required between the source / drain region of the drive transistor and the source / drain region of the adjacent drive transistor.

[0026] For the above reasons, in the light emitting device 10 of this embodiment, the second element isolation section 302 is arranged between a drive transistor (for example, transistor 353) and an adjacent drive transistor (for example, transistor 354). For the same reasons, the second element isolation section 302 can also be arranged between two adjacent regions of the same conductivity type, such as between a reset transistor and an adjacent reset transistor.

[0027] On the other hand, a first isolation region 301 having a depth smaller than that of the second isolation region 302 can be disposed between the well contact and the adjacent reset transistor. Between the well contact and the adjacent reset transistor, only a PN junction consisting of a P-type source / drain 322, an N-type well 320, and an N-type source / drain is formed via the isolation region. As mentioned above, there are two PN junctions between the drive transistor and its adjacent drive transistor, so parasitic bipolar transistor activity must be suppressed. In contrast, since only one PN junction is formed near the well contact, the withstand voltage and the width of the N-type region are less dependent. In other words, the first isolation region 301 can be shallower (less deep) than the second isolation region 302. Generally, a shallower isolation region improves the embedding of the insulating film, allowing for a smaller isolation width, which is advantageous for reducing pixel size.

[0028] In addition, by arbitrarily controlling the well potential via the well contact portion, it is possible to reduce the leakage current flowing between the source and drain of the transistor by using the back-gate effect on the transistor in the pixel circuit 311. In this case, by reducing the depth of the element isolation portion around the well contact portion, the distance from the well contact region is shortened, and the potential drop can be reduced. The reduced potential drop makes it possible to reduce the variation in the back-gate effect.

[0029] In this way, the above-mentioned effects can be obtained by selectively using the first isolation region 301 and the second isolation region 302 in the light emitting device 10 of this embodiment. That is, in areas where a high withstand voltage is required, the second isolation region 302 can reduce leakage current within the pixel, and in areas where there is a margin for high withstand voltage, the first isolation region 301 can be used to reduce the width of the isolation region. Therefore, it is possible to maintain the withstand voltage within the pixel in the light emitting device 10 (suppressing a decrease in display quality) while also reducing the pixel size.

[0030] (Method of manufacturing a light-emitting device) A method for manufacturing light emitting device 10 will now be described by way of example with reference to the cross-sectional views of Figures 3 and 4. First, an example of a method for forming first isolation region 301 and second isolation region 302 on semiconductor substrate 300 will be described with reference to Figure 4.

[0031] 4(a) is a process of forming a trench Tr1 that constitutes the first element isolation portion 301 in the semiconductor substrate 300. Specifically, a hard mask made of an oxide film 401, polysilicon 402, and a silicon nitride film 403 is formed on the semiconductor substrate 300, and a first photoresist 404 is applied to the hard mask. The first photoresist 404 is then patterned by photolithography so that only the region where the first element isolation portion 301 will be formed is opened. After this patterning, dry etching is performed using the first photoresist 404 as a mask, thereby forming the trench Tr1 in the semiconductor substrate 300.

[0032] 4(b) is a step of forming a trench Tr2 that constitutes the second element isolation portion 302 in the semiconductor substrate 300. Specifically, after removing the first photoresist 404, a second photoresist 405 is applied onto the semiconductor substrate 300. Then, the second photoresist 405 is patterned by photolithography so that only the region where the second element isolation portion 302 is to be formed is opened. After this patterning, dry etching is performed using the second photoresist 405 as a mask, thereby forming the trench Tr2 in the semiconductor substrate 300.

[0033] By going through the above steps, it is possible to arbitrarily change the depth of the trenches (grooves) in first device isolation region 301 and second device isolation region 302. As an example, the trench depth is approximately 100 to 400 nm in first device isolation region 301, and approximately 400 to 800 nm in second device isolation region 302. In other words, the trench depth of second device isolation region 302 may be four to eight times the trench depth of first device isolation region 301.

[0034] The step of FIG. 4(c) is a step of forming an insulator in the trenches Tr1-Tr2 formed in the semiconductor substrate 300. Specifically, an insulating film is formed on the inner walls (side surfaces and bottom surfaces) of each of the trenches Tr1-Tr2 using thermal oxidation in an oxidizing gas atmosphere or the like. Then, an insulator is filled into each of the trenches Tr1-Tr2 so as to cover the insulating film formed on the inner walls of each of the trenches Tr1-Tr2. The insulator filled into each of the trenches Tr1-Tr2 is, for example, a silicon oxide film formed by high-density plasma CVD. The insulator is formed to a thickness that allows it to fill each of the trenches Tr1-Tr2, which will become the first isolation region 301 and the second isolation region 302. The insulator filled into each of the trenches Tr1 can be planarized by a combination of etching and CMP (Chemical Mechanical Polisher).

[0035] The step of FIG. 4(d) is a step of removing the hard mask on the semiconductor substrate 300. Specifically, the silicon nitride film 403 and polysilicon 402 on the semiconductor substrate 300 are removed. Before removing the polysilicon 402, the film thickness of the insulator in each of the trenches Tr1 and Tr2 may be adjusted by wet etching. The oxide film 401 on the semiconductor substrate 300 may also be removed. By this step, the trench Tr1 is formed as the first element isolation portion 301, and the trench Tr2 is formed as the second element isolation portion 302. Here, the first element isolation portion 301 and the second element isolation portion 302 have different trench depths, so the first element isolation portion 301 and the second element isolation portion 302 may have different heights (protrusion amounts) from the surface of the semiconductor substrate 300. Alternatively, the heights (i.e., protrusion amounts from the semiconductor substrate 300) of the first element isolation portion 301 and the second element isolation portion 302 may be controlled to be the same by using wet etching.

[0036] Next, an example of a method for manufacturing the pixel array 100 from the semiconductor substrate 300 on which the first element isolation region 301 and the second element isolation region 302 are formed will be described with reference to FIG.

[0037] After the first isolation region 301 and the second isolation region 302 are formed in the semiconductor substrate 300 through the process of FIG. 4(d) described above, a thermal oxide film is formed on the surface of the semiconductor substrate 300. This thermal oxide film is provided for the purpose of suppressing channeling during ion implantation. In addition, with a predetermined region protected by resist, an N-type well 320 is formed by multi-stage ion implantation. The multi-stage ion implantation is performed, for example, at an acceleration energy of 10 to 2000 keV and a dose of 1×10 11 ~5×10 13 / cm 2 The dose can be adjusted within a range of about 100 ohms. The dose may be changed by changing the depth of multi-stage ion implantation. The N-type well 320 may be formed so that the concentration is high in regions shallower than the bottoms of the first element isolation portion 301 and the second element isolation portion 302 and low in regions deeper than the bottoms of the first element isolation portion 301 and the second element isolation portion 302.

[0038] Next, a gate oxide film and a gate electrode 303 are formed, and then, with a predetermined region protected by a resist, an N-type light dope 321 is formed by ion implantation. The ion implantation is performed, for example, at an acceleration energy of 10 to 150 keV and a dose of 1×10 11 ~5×10 14 / cm 2 The dose may be varied by varying the depth of the multi-step ion implantation.

[0039] Next, the sidewalls 304 of the transistor are formed. The sidewalls 304 can be formed by depositing a silicon oxide film and a silicon nitride film and then etching them back. The sidewalls 304 may be a single layer of silicon oxide film or silicon nitride film, or may have a laminated structure of these.

[0040] Next, with a predetermined region protected by resist, a P-type source / drain 322 is formed by ion implantation. At this time, in order to form an offset MOS, a resist pattern may be formed so that the P-type source / drain 322 is implanted at a predetermined distance from the end of the gate electrode 303. The ion implantation is performed, for example, at an acceleration energy of 3 to 30 keV and a dose of 1 e 13 ~7e 15 / cm 2 The thickness of the dopant can be adjusted within a certain range. Then, a heat treatment for activating the dopant can be carried out.

[0041] Here, second isolation portion 302 is desirably formed to have a depth at least 0.3 μm greater than first isolation portion 301. However, second isolation portion 302 is desirably formed to have a depth shallower than the bottom of N-type well 320. This is because if second isolation portion 302 is made deeper than the bottom of well 320, the potential of well 320 may become floating, which may cause leakage current.

[0042] Furthermore, the first isolation region 301 (trench Tr1) is desirably formed so that its opening width in a direction parallel to the surface of the semiconductor substrate 300 is narrower than that of the second isolation region 302 (trench Tr2). This is to shorten the distance between the well contact and the transistor and reduce potential drop. The minimum opening width of the first isolation region 301 is preferably 0.1 μm or more and less than 0.2 μm, and the minimum opening width of the second isolation region 302 is preferably 0.2 μm or more and less than 0.5 μm. The depth and opening width of each isolation region may be changed as appropriate depending on the voltage required for each pixel. Using the first isolation region 301 in a location where a withstand voltage between the source and drain is not required allows the opening width to be reduced, which contributes to a smaller pixel pitch.

[0043] In this embodiment, an example is shown in which two types of element isolation sections (first element isolation section 301, second element isolation section 302) are provided in each pixel 101, but this is not limited to this, and three or more types of element isolation sections with different depths and opening widths may be provided in each pixel 101.

[0044] Next, a silicide protection layer is formed using an oxide film to define the metal silicide region, and the silicide protection layer is formed to prevent the metal silicide from forming on the LDD (Lightly Doped Drain) region. After that, contact plugs are formed, and multiple wiring layers are formed.

[0045] On the metal electrode 310, optical adjustment layers 334 of different heights are formed in accordance with the interference of the emission wavelengths of the B subpixel 331, the G subpixel 332, and the R subpixel 333. Then, on the optical adjustment layer 334, a transparent anode electrode 335, a pixel separation layer 336 for separating the pixels, an organic light-emitting layer 337, and a cathode electrode 338 are formed in this order. Furthermore, a protective layer 339 is formed on the cathode electrode 338, and then a blue color filter 341b, a green color filter 341g, and a red color filter 341r are formed on the protective layer 339.

[0046] As described above, each pixel 101 in the light-emitting device 10 of this embodiment includes a trench-type first isolation region 301 and a trench-type second isolation region 302 that is deeper than the first isolation region 301. The first isolation region 301 is arranged to electrically isolate two adjacent regions of different conductivity types, and the second isolation region 302 is arranged to electrically isolate two adjacent regions of the same conductivity type. This allows for both maintaining the breakdown voltage within the pixel 101 and reducing the pixel size. The light-emitting device 10 of this embodiment does not necessarily need to be formed using the above-described manufacturing method and process sequence; various process permutations and modifications are possible. The trench depth and process sequence may also be reversed. This embodiment merely illustrates several aspects to which the present invention can be applied, and does not preclude appropriate modifications and variations within the spirit and scope of the present invention.

[0047] Second Embodiment A second embodiment of the present invention will be described. This embodiment basically follows on from the first embodiment, and can follow the first embodiment except for the matters mentioned below.

[0048] 5 shows an example of a cross-sectional view of each pixel 101 in the light-emitting device 10 of this embodiment. In this embodiment, an example will be described in which the second element isolation section 302 is configured to include an upper layer section 302a and a lower layer section 302b that are stacked on top of each other. Note that, although an example will be described in which the second element isolation section 302 of this embodiment has a two-stage structure combining the upper layer section 302a and the lower layer section 302b, the present invention is not limited thereto, and the second element isolation section 302 may have a three-stage or more structure combining three or more layer sections.

[0049] The second element isolation region 302 of this embodiment is configured by connecting the lower layer region 302b to a portion of the bottom surface of the upper layer region 302a. The width (diameter, area) of the portion of the bottom surface of the upper layer region 302a to which the lower layer region 302b is connected may be smaller than the width (diameter, area) of the bottom surface of the upper layer region 302a. The "portion of the bottom surface of the upper layer region 302a to which the lower layer region 302b is connected" may be understood as the upper portion (connection portion) of the lower layer region 302b that is connected to the upper layer region 302a. The maximum width (diameter, area) of the lower layer region 302b may be smaller than the width (diameter, area) of the bottom surface of the upper layer region 302a.

[0050] In addition, in the second device isolation region 302 of this embodiment, the depth of the lower layer portion 302b is preferably greater than the depth of the upper layer portion 302a. That is, the ratio of the depth of the lower layer portion 302b to the depth of the upper layer portion 302a is preferably 1 or greater. Furthermore, in the second device isolation region 302 of this embodiment, the opening width of the trench constituting the upper layer portion 302a is preferably greater than the opening width of the trench constituting the lower layer portion 302b. This makes it possible to arbitrarily control the width of the active region of the transistor in the semiconductor region by the opening width of the upper layer portion 302a of the second device isolation region 302.

[0051] As described above, in this embodiment, the second isolation region 302 is composed of an upper layer portion 302a and a lower layer portion 302b. This allows the upper layer portion 302a of the second isolation region 302 to be formed in the same process as the first isolation region 301, resulting in the effect that the first isolation region 301 and the second isolation region 302 have a uniform (same) height from the surface of the semiconductor substrate 300. By making the isolation regions 301-302 uniform in height from the surface of the semiconductor substrate 300, the flatness of the semiconductor substrate 300 during processing is improved, enabling more precise processing of gate electrodes and the like. Furthermore, according to this embodiment, the depth of the upper layer portion 302a of the second isolation region 302 can be made smaller (shallower) than the overall depth of the second isolation region 302 in the first embodiment. This makes it easier to fill the trench Tr2 with an insulator and also enables the trench width itself to be made finer.

[0052] [Configuration of organic light-emitting element] The organic light-emitting element is provided by forming an insulating layer, a first electrode, an organic compound layer, and a second electrode on a substrate. A protective layer, a color filter, a microlens, etc. may be provided on the cathode. When a color filter is provided, a planarizing layer may be provided between the protective layer. The planarizing layer may be made of acrylic resin or the like. The same applies when a planarizing layer is provided between the color filter and the microlens.

[0053] [substrate] Examples of the substrate include quartz, glass, a silicon wafer, a resin, and a metal. Furthermore, the substrate may be provided with a switching element such as a transistor and wiring, and an insulating layer thereon. Any material can be used for the insulating layer, as long as it allows for the formation of a contact hole so that wiring can be formed between the first electrode and the insulating layer, and ensures insulation from wiring that is not connected. For example, resins such as polyimide, silicon oxide, silicon nitride, etc. can be used.

[0054] [electrode] A pair of electrodes can be used. The pair of electrodes may be an anode and a cathode. When an electric field is applied in the direction in which the organic light-emitting element emits light, the electrode with a higher potential is the anode, and the other is the cathode. It can also be said that the electrode that supplies holes to the light-emitting layer is the anode, and the electrode that supplies electrons is the cathode.

[0055] The anode material should have as high a work function as possible. Examples include simple metals such as gold, platinum, silver, copper, nickel, palladium, cobalt, selenium, vanadium, and tungsten, mixtures containing these metals, alloys of these metals, and metal oxides such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide. Conductive polymers such as polyaniline, polypyrrole, and polythiophene can also be used.

[0056] These electrode materials may be used alone or in combination of two or more. The anode may be composed of one layer or multiple layers.

[0057] When used as a reflective electrode, for example, chromium, aluminum, silver, titanium, tungsten, molybdenum, or alloys or laminates thereof can be used. The above materials can also function as a reflective film without functioning as an electrode. When used as a transparent electrode, transparent conductive oxide layers such as indium tin oxide (ITO) and indium zinc oxide can be used, but are not limited to these. Photolithography techniques can be used to form the electrode.

[0058] On the other hand, materials with a low work function are preferred for the cathode. Examples include alkali metals such as lithium, alkaline earth metals such as calcium, and metals such as aluminum, titanium, manganese, silver, lead, and chromium, as well as mixtures containing these metals. Alternatively, alloys combining these metals can be used. For example, magnesium-silver, aluminum-lithium, aluminum-magnesium, silver-copper, and zinc-silver can be used. Metal oxides such as indium tin oxide (ITO) can also be used. These electrode materials can be used alone or in combination. The cathode can have either a single-layer or multi-layer structure. Among these, silver is preferred, and a silver alloy is even more preferred to reduce silver aggregation. The alloy ratio is not critical as long as silver aggregation can be reduced. For example, the silver:other metal ratio can be 1:1, 3:1, or the like.

[0059] The cathode may be a top-emission element using an oxide conductive layer such as ITO, or a bottom-emission element using a reflective electrode such as aluminum (Al), and is not particularly limited. The method for forming the cathode is not particularly limited, but DC and AC sputtering methods are more preferred because they provide good film coverage and make it easier to reduce resistance.

[0060] [Pixel isolation layer] The pixel separation layer is formed of a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, or a silicon oxide (SiO) film formed using a chemical vapor deposition (CVD) method. To increase the in-plane resistance of the organic compound layer, it is preferable that the organic compound layer, particularly the hole transport layer, be thinly formed on the sidewalls of the pixel separation layer. Specifically, the thickness of the sidewalls can be made thin by increasing the taper angle of the sidewalls of the pixel separation layer or the thickness of the pixel separation layer, thereby increasing vignetting during deposition.

[0061] On the other hand, it is preferable to adjust the sidewall taper angle and film thickness of the pixel separation layer to such an extent that voids are not formed in the protective layer formed thereon. Since voids are not formed in the protective layer, the occurrence of defects in the protective layer can be reduced. Since the occurrence of defects in the protective layer is reduced, deterioration of reliability such as the occurrence of dark spots and poor conduction of the second electrode can be reduced.

[0062] According to this embodiment, charge leakage to adjacent pixels can be effectively suppressed even if the taper angle of the sidewall of the pixel separation layer is not steep. As a result of this study, it was found that a taper angle in the range of 60 degrees to 90 degrees can sufficiently reduce charge leakage. The thickness of the pixel separation layer is preferably 10 nm to 150 nm. Similar effects can also be achieved even if the pixel separation layer is composed only of pixel electrodes without a pixel separation layer. However, in this case, it is preferable to make the thickness of the pixel electrode less than half that of the organic layer or to make the edge of the pixel electrode forward tapered at less than 60 degrees, as this reduces short circuits in the organic light-emitting element.

[0063] [Organic compound layer] The organic compound layer may be formed as a single layer or as multiple layers. When multiple layers are included, they may be called hole injection layer, hole transport layer, electron blocking layer, light-emitting layer, hole blocking layer, electron transport layer, or electron injection layer depending on their functions. The organic compound layer is mainly composed of organic compounds but may also contain inorganic atoms or inorganic compounds. For example, the organic compound layer may contain copper, lithium, magnesium, aluminum, iridium, platinum, molybdenum, zinc, or the like. The organic compound layer may be disposed between the first electrode and the second electrode, or may be disposed in contact with the first electrode and the second electrode.

[0064] When the device has multiple light-emitting layers, a charge generation portion may be provided between the first and second light-emitting layers. The charge generation portion may have an organic compound with a lowest unoccupied molecular orbital energy (LUMO) of -5.0 eV or less. The same applies when the charge generation portion is provided between the second and third light-emitting layers.

[0065] [Protective layer] A protective layer may be provided on the second electrode. For example, by adhering glass with a moisture absorbent on the second electrode, the intrusion of water and other contaminants into the organic compound layer can be reduced, thereby reducing the occurrence of display defects. In another embodiment, a passivation film such as silicon nitride may be provided on the cathode to reduce the intrusion of water and other contaminants into the organic compound layer. For example, after forming the cathode, the cathode may be transferred to another chamber without breaking the vacuum, and a 2 μm-thick silicon nitride film may be formed by CVD to serve as a protective layer. A protective layer may be provided using atomic layer deposition (ALD) after the CVD film formation. The material of the film formed by ALD is not limited, and may be silicon nitride, silicon oxide, aluminum oxide, or the like. Silicon nitride may be further formed on the film formed by ALD by CVD. The film formed by ALD may have a thickness smaller than that of the film formed by CVD. Specifically, the thickness may be 50% or less, or even 10% or less.

[0066] [Color Filter] A color filter may be provided on the protective layer. For example, a color filter taking into consideration the size of the organic light-emitting element may be provided on a separate substrate and then bonded to the substrate on which the organic light-emitting element is provided, or a color filter may be patterned on the protective layer described above using photolithography technology. The color filter may be made of a polymer.

[0067] [Planarization layer] A planarization layer may be provided between the color filter and the protective layer. The planarization layer is provided for the purpose of reducing the unevenness of the underlying layer. It may also be called a material resin layer without limiting its purpose. The planarization layer may be composed of an organic compound, and may be either a low molecular weight or a high molecular weight, but a high molecular weight is preferred.

[0068] The planarizing layer may be provided above or below the color filter, and may be made of the same or different materials, such as polyvinyl carbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin.

[0069] [Microlens] The organic light-emitting device may have an optical component such as a microlens on its light-emitting side. The microlens may be made of acrylic resin, epoxy resin, or the like. The microlens may be used to increase the amount of light extracted from the organic light-emitting device and to control the direction of the extracted light. The microlens may have a hemispherical shape. When the microlens has a hemispherical shape, among the tangents to the hemisphere, there is a tangent that is parallel to the insulating layer, and the point of contact between this tangent and the hemisphere is the vertex of the microlens. The vertex of the microlens can be determined in the same way in any cross-sectional view. In other words, among the tangents to the semicircle of the microlens in the cross-sectional view, there is a tangent that is parallel to the insulating layer, and the point of contact between this tangent and the semicircle is the vertex of the microlens.

[0070] It is also possible to define the midpoint of a microlens. In the cross section of the microlens, a line segment is imagined from the point where an arc shape ends to the point where another arc shape ends, and the midpoint of this line segment can be called the midpoint of the microlens. The cross section for determining the vertex and midpoint may be a cross section perpendicular to the insulating layer.

[0071] The microlens has a first surface having a convex portion and a second surface opposite the first surface. The second surface is preferably disposed closer to the functional layer than the first surface. To achieve this configuration, the microlens must be formed on the light-emitting device. When the functional layer is an organic layer, it is preferable to avoid processes that result in high temperatures during the manufacturing process. Furthermore, when the second surface is disposed closer to the functional layer than the first surface, it is preferable that the glass transition temperatures of all organic compounds constituting the organic layer are 100°C or higher, and more preferably 130°C or higher.

[0072] [Counter substrate] An opposing substrate may be provided on the planarization layer. The opposing substrate is called an opposing substrate because it is provided at a position corresponding to the aforementioned substrate. The constituent material of the opposing substrate may be the same as that of the aforementioned substrate. When the aforementioned substrate is defined as a first substrate, the opposing substrate may be a second substrate.

[0073] [Organic layer] The organic compound layers (hole injection layer, hole transport layer, electron blocking layer, light emitting layer, hole blocking layer, electron transport layer, electron injection layer, etc.) constituting the organic light emitting device according to one embodiment of the present invention are formed by the method shown below.

[0074] The organic compound layer constituting the organic light-emitting device according to one embodiment of the present invention can be formed by dry processes such as vacuum deposition, ionization deposition, sputtering, plasma, etc. Alternatively to the dry process, a wet process can be used in which the compound is dissolved in an appropriate solvent and a layer is formed by a known coating method (for example, spin coating, dipping, casting, LB method, inkjet method, etc.).

[0075] Here, when a layer is formed by a vacuum deposition method or a solution coating method, crystallization is unlikely to occur and the layer has excellent stability over time. When a film is formed by a coating method, the film can be formed by combining with an appropriate binder resin.

[0076] Examples of the binder resin include, but are not limited to, polyvinylcarbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin.

[0077] These binder resins may be used singly or in combination as homopolymers or copolymers, and may further contain known additives such as plasticizers, antioxidants, and ultraviolet absorbers, if necessary.

[0078] [Pixel circuit] The light-emitting device may have a pixel circuit connected to the light-emitting element. The pixel circuit may be an active matrix type that controls the emission of the first light-emitting element and the second light-emitting element independently. The active matrix type circuit may be voltage-programmed or current-programmed. The drive circuit has a pixel circuit for each pixel. The pixel circuit may have a light-emitting element, a transistor that controls the emission brightness of the light-emitting element, a transistor that controls the emission timing, a capacitor that holds the gate voltage of the transistor that controls the emission brightness, and a transistor for connecting to GND without going through the light-emitting element.

[0079] The light-emitting device has a display region and a peripheral region arranged around the display region. The display region has pixel circuits, and the peripheral region has a display control circuit. The mobility of a transistor constituting the pixel circuit may be lower than the mobility of a transistor constituting the display control circuit.

[0080] The slope of the current-voltage characteristics of the transistors that make up the pixel circuit may be smaller than the slope of the current-voltage characteristics of the transistors that make up the display control circuit. The slope of the current-voltage characteristics can be measured using the so-called Vg-Ig characteristics.

[0081] The transistors that make up the pixel circuit are transistors connected to light-emitting elements such as the first light-emitting element.

[0082] [Pixels] An organic light emitting device includes a plurality of pixels, each of which includes sub-pixels that emit different colors, for example, RGB colors.

[0083] The pixel emits light from an area called the pixel aperture. This area is the same as the first area. The pixel aperture may be 15 μm or less, or 5 μm or more. More specifically, it may be 11 μm, 9.5 μm, 7.4 μm, 6.4 μm, etc.

[0084] The distance between the subpixels may be 10 μm or less, and specifically may be 8 μm, 7.4 μm, or 6.4 μm.

[0085] The pixels may be arranged in a known manner in a plan view. For example, they may be in a stripe arrangement, a delta arrangement, a pentile arrangement, or a Bayer arrangement. The shape of the subpixels in a plan view may be any known shape. For example, they may be rectangular, quadrilaterals such as diamonds, or hexagons. Of course, a shape that is close to a rectangle, rather than an exact shape, is included in the rectangle. The shape of the subpixels and the pixel arrangement may be used in combination.

[0086] [Use of the organic light-emitting device according to one embodiment of the present invention] The organic light-emitting device according to one embodiment of the present invention can be used as a component of a display device or a lighting device, and can also be used as an exposure light source for an electrophotographic image forming device, a backlight for a liquid crystal display device, a light-emitting device having a white light source and a color filter, etc.

[0087] The display device may be an image information processing device that has an image input unit that inputs image information from an area CCD, a linear CCD, a memory card, etc., has an information processing unit that processes the input information, and displays the input image on the display unit.

[0088] The display unit of the imaging device or inkjet printer may have a touch panel function. The driving method of this touch panel function may be an infrared method, a capacitance method, a resistive film method, or an electromagnetic induction method, and is not particularly limited. The display device may also be used in the display unit of a multifunction printer.

[0089] Next, the display device according to this embodiment will be described with reference to the drawings.

[0090] 1 is a cross-sectional view showing an example of a display device having an organic light-emitting element and a transistor connected to the organic light-emitting element. The transistor is an example of an active element. The transistor may be a thin-film transistor (TFT).

[0091] 6(a) shows an example of a pixel, which is a component of the display device according to this embodiment. The pixel has a sub-pixel 810 (pixel PIX). The sub-pixels are divided into 810R, 810G, and 810B based on their light emission. The emitted light colors may be distinguished by the wavelength of light emitted from the light-emitting layer, or the light emitted from the sub-pixels may be selectively transmitted or color-converted using a color filter or the like. Each sub-pixel has a reflective electrode 802, which is a first electrode, on an interlayer insulating layer 801, an insulating layer 803 covering the edge of the reflective electrode 802, an organic compound layer 804 covering the first electrode and the insulating layer, a second electrode 805, a protective layer 806, and a color filter 807.

[0092] A transistor and a capacitor may be disposed below or inside the interlayer insulating layer 801. The transistor and the first electrode may be electrically connected via a contact hole or the like (not shown).

[0093] The insulating layer 803 is also called a bank or pixel separation film. It covers the edges of the first electrode and surrounds the first electrode. The part where the insulating layer is not provided contacts the organic compound layer 804 and becomes the light-emitting region.

[0094] The organic compound layer 804 includes a hole injection layer 841 , a hole transport layer 842 , a first light-emitting layer 843 , a second light-emitting layer 844 , and an electron transport layer 845 .

[0095] The second electrode 805 may be a transparent electrode, a reflective electrode, or a semi-transparent electrode.

[0096] The protective layer 806 reduces the penetration of moisture into the organic compound layer. Although the protective layer is illustrated as a single layer, it may be a multi-layer structure. Each layer may be an inorganic compound layer and an organic compound layer.

[0097] The color filters 807 are divided into 807R, 807G, and 807B depending on their colors. The color filters may be formed on a planarization film (not shown). A resin protective layer (not shown) may be provided on the color filters. The color filters may be formed on a protective layer 806. Alternatively, the color filters may be provided on an opposing substrate such as a glass substrate and then bonded thereto.

[0098] The display device 800 in FIG. 6(b) (corresponding to the light-emitting device 10 of the above embodiment) includes an organic light-emitting element 826 and a TFT 818 as an example of a transistor. A substrate 811 made of glass, silicon, or the like is provided with an insulating layer 812 on top of it. An active element 818 such as a TFT is disposed on the insulating layer, and a gate electrode 813 of the active element, a gate insulating film 814, and a semiconductor layer 815 are disposed on top of it. The TFT 818 also includes the semiconductor layer 815, a drain electrode 816, and a source electrode 817. An insulating film 819 is disposed on top of the TFT 818. An anode 821 constituting the organic light-emitting element 826 and the source electrode 817 are connected via a contact hole 820 provided in the insulating film.

[0099] The electrical connection between the electrodes (anode, cathode) included in the organic light-emitting element 826 and the electrodes (source electrode, drain electrode) included in the TFT is not limited to the embodiment shown in Figure 6(b). In other words, it is sufficient that either the anode or the cathode is electrically connected to either the TFT source electrode or the drain electrode. TFT stands for thin film transistor.

[0100] 6(b), the organic compound layer 822 is illustrated as a single layer, but may be a multi-layer organic compound layer 822. A first protective layer 824 and a second protective layer 825 are provided on the cathode 823 to reduce deterioration of the organic light-emitting element.

[0101] In the display device 800 of FIG. 6(b), transistors are used as switching elements, but other switching elements may be used instead.

[0102] Furthermore, the transistors used in the display device 800 of Fig. 6(b) are not limited to transistors using single-crystal silicon wafers, but may also be thin-film transistors having an active layer on an insulating surface of a substrate. Examples of active layers include single-crystal silicon, amorphous silicon, microcrystalline silicon, and other non-single-crystal silicon, and non-single-crystal oxide semiconductors such as indium zinc oxide and indium gallium zinc oxide. Thin-film transistors are also called TFT elements.

[0103] The transistors included in the display device 800 of Fig. 6(b) may be formed within a substrate such as a Si substrate. Here, "formed within a substrate" means that the substrate itself, such as a Si substrate, is processed to form the transistors. In other words, having a transistor within a substrate can be seen as the substrate and the transistor being formed integrally.

[0104] The organic light-emitting element according to this embodiment has its emission brightness controlled by a TFT, which is an example of a switching element. By providing multiple organic light-emitting elements on a surface, an image can be displayed based on the emission brightness of each element. Note that the switching element according to this embodiment is not limited to a TFT, and may be a transistor formed from low-temperature polysilicon or an active matrix driver formed on a substrate such as a Si substrate. "On the substrate" can also be referred to as "inside the substrate." Whether to provide a transistor in the substrate or to use a TFT is determined by the size of the display unit. For example, for a display size of about 0.5 inches, it is preferable to provide the organic light-emitting element on a Si substrate.

[0105] 7 is a schematic diagram illustrating an example of a display device according to this embodiment. The display device 1000 may include a touch panel 1003, a display panel 1005, a frame 1006, a circuit board 1007, and a battery 1008 between an upper cover 1001 and a lower cover 1009. The touch panel 1003 and the display panel 1005 are connected by flexible printed circuits FPCs 1002 and 1004. Transistors are printed on the circuit board 1007. The battery 1008 may not be provided if the display device is not a portable device, and may be provided in a different position even if the display device is a portable device.

[0106] The display device according to this embodiment may have color filters having red, green, and blue colors, which may be arranged in a delta arrangement.

[0107] The display device according to the present embodiment may be used as a display unit of a mobile terminal. In this case, the display device may have both a display function and an operation function. Examples of the mobile terminal include a mobile phone such as a smartphone, a tablet, and a head-mounted display.

[0108] The display device according to this embodiment may be used as a display unit of an imaging device having an optical unit with a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may have a display unit that displays information acquired by the imaging element. The display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed within a viewfinder. The imaging device may be a digital camera or a digital video camera.

[0109] 8 is a schematic diagram showing an example of an imaging device according to this embodiment. The imaging device 1100 may have a viewfinder 1101, a rear display 1102, an operation unit 1103, and a housing 1104. The viewfinder 1101 may have a display device according to this embodiment. In this case, the display device may display not only an image to be captured, but also environmental information, imaging instructions, and the like. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject is moving, the possibility that the subject will be blocked by an obstruction, and the like.

[0110] Since the optimum timing for capturing an image is very short, it is better to display information as soon as possible. Therefore, it is preferable to use a display device using the organic light-emitting element of the present invention. This is because the organic light-emitting element has a fast response speed. A display device using an organic light-emitting element can be used more preferably than a liquid crystal display device, which requires a high display speed.

[0111] The imaging device 1100 has an optical section (not shown). The optical section has multiple lenses, which form an image on an imaging element housed in a housing 1104. The focus of the multiple lenses can be adjusted by adjusting their relative positions. This operation can also be performed automatically. The imaging device may also be called a photoelectric conversion device. Instead of sequentially capturing images, the photoelectric conversion device can include an imaging method that detects the difference from the previous image, or a method of cutting out an image from a constantly recorded image, etc.

[0112] FIG. 9 is a schematic diagram illustrating an example of an electronic device according to this embodiment. The electronic device 1200 has a display unit 1201, an operation unit 1202, and a housing 1203. The housing 1203 may have a circuit, a printed circuit board having the circuit, a battery, and a communication unit. The operation unit 1202 may be a button or a touch panel type reaction unit. The operation unit may be a biometric recognition unit that recognizes a fingerprint to perform operations such as unlocking. An electronic device having a communication unit can also be called a communication device. The electronic device may further have a camera function by including a lens and an image sensor. An image captured by the camera function is displayed on the display unit. Examples of the electronic device include a smartphone and a laptop computer.

[0113] 10A and 10B are schematic diagrams illustrating an example of a display device according to this embodiment. Fig. 10A shows a display device such as a television monitor or a PC monitor. The display device 1300 has a frame 1301 and a display unit 1302. The light-emitting device according to this embodiment may be used in the display unit 1302.

[0114] It has a frame 1301 and a base 1303 that supports a display unit 1302. The base 1303 is not limited to the form shown in Fig. 10(a). The bottom side of the frame 1301 may also serve as the base.

[0115] The frame 1301 and the display unit 1302 may be curved. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0116] FIG. 10(b) is a schematic diagram illustrating another example of a display device according to this embodiment. The display device 1310 in FIG. 10(b) is configured to be bendable, and is a so-called foldable display device. The display device 1310 has a first display unit 1311, a second display unit 1312, a housing 1313, and a bending point 1314. The first display unit 1311 and the second display unit 1312 may include a light-emitting device according to this embodiment. The first display unit 1311 and the second display unit 1312 may be a single, seamless display unit. The first display unit 1311 and the second display unit 1312 can be separated by the bending point. The first display unit 1311 and the second display unit 1312 may each display different images, or the first and second display units may display a single image.

[0117] An application example of the display device of each of the above-described embodiments will be described with reference to Fig. 11. The display device can be applied to a system that can be attached as a wearable device, such as smart glasses, an HMD, or a smart contact lens. An image capturing and displaying device used in such an application example includes an image capturing device capable of photoelectrically converting visible light and a displaying device capable of emitting visible light.

[0118] 11(a) illustrates glasses 1600 (smart glasses) according to one application example. An imaging device 1602 such as a CMOS sensor or SPAD is provided on the front side of a lens 1601 of the glasses 1600. Furthermore, a display device according to any of the above-described embodiments is provided on the back side of the lens 1601.

[0119] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the image capture device 1602 and the display device according to each embodiment. The control device 1603 also controls the operations of the image capture device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the image capture device 1602.

[0120] FIG. 11(b) illustrates glasses 1610 (smart glasses) according to one application example. The glasses 1610 include a control device 1612. The control device 1612 is equipped with an imaging device equivalent to the imaging device 1602 and a display device. A lens 1611 is formed with an optical system for projecting light emitted by the display device in the control device 1612, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the imaging device and the display device and controls the operation of the imaging device and the display device. The control device may also include a gaze detection unit for detecting the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitting unit emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitting unit to the display unit in a planar view reduces degradation of image quality.

[0121] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using an image of the eyeball. One example is a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea.

[0122] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0123] A display device according to an embodiment of the present invention may have an imaging device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the imaging device.

[0124] Specifically, the display device determines a first display area on which the user gazes and a second display area other than the first display area based on the line-of-sight information. The first display area and the second display area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than that of the first field of view area.

[0125] The display area includes a first display area and a second display area different from the first display area, and a high-priority area is determined from the first display area and the second display area based on line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0126] Note that AI may be used to determine the first display area and the area with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from the image of the eyeball, using as training data an image of the eyeball and the actual direction in which the eyeball in the image was looking. The AI ​​program may be included in the display device, the imaging device, or an external device. If included in the external device, it is transmitted to the display device via communication.

[0127] When display control is performed based on visual recognition detection, the smart glasses can be preferably applied to smart glasses that further include an imaging device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0128] As described above, by using a device using the organic light-emitting element according to this embodiment, it is possible to provide a stable display with good image quality even over a long period of time.

[0129] <Summary of the embodiment> The disclosure of this specification includes at least the following light-emitting device, wearable device, display device, photoelectric conversion device, and electronic device. (Item 1) A light emitting device having a plurality of pixels arranged on a substrate, each of the plurality of pixels has a trench-type first isolation portion that isolates two adjacent regions of different conductivity types from each other, and a trench-type second isolation portion that isolates two adjacent regions of the same conductivity type from each other; A light emitting device, wherein the second isolation portion has a depth greater than a depth of the first isolation portion. (Item 2) 2. The light emitting device according to item 1, wherein the depth of the second isolation portion is greater than the depth of the first isolation portion by 0.3 μm or more. (Item 3) 3. The light emitting device according to item 1 or 2, wherein the opening width of the first separation portion is narrower than the opening width of the second separation portion in a direction parallel to the surface of the substrate. (Item 4) 4. The light emitting device according to any one of items 1 to 3, wherein the first separation portion and the second separation portion have different heights from the surface of the substrate. (Item 5) the second separation portion includes an upper layer portion and a lower layer portion stacked on each other, 5. The light emitting device according to any one of items 1 to 4, wherein the lower layer portion is connected to a part of a bottom surface of the upper layer portion. (Item 6) 6. The light emitting device according to item 5, wherein the depth of the lower layer portion is greater than the depth of the upper layer portion. (Item 7) 7. The light emitting device according to item 5 or 6, wherein the maximum width of the lower layer portion is smaller than the width of the bottom surface of the upper layer portion. (Item 8) each of the plurality of pixels has a first semiconductor region, a second semiconductor region having the same conductivity type as the first semiconductor region, and a third semiconductor region having a different conductivity type than the first semiconductor region; 8. The light emitting device according to any one of items 1 to 7, characterized in that the first isolation portion is provided between the first semiconductor region and the third semiconductor region that are arranged adjacent to each other, and the second isolation portion is provided between the first semiconductor region and the second semiconductor region that are arranged adjacent to each other. (Item 9) Each of the plurality of pixels includes a light-emitting element and a pixel circuit that drives the light-emitting element, Item 9. The light-emitting device according to item 8, wherein the pixel circuit comprises a selection transistor that controls input of data to the pixel, and a drive transistor that drives the light-emitting element according to the input data. (Item 10) 10. The light emitting device according to item 9, wherein the second isolation portion is provided between two of the driving transistors arranged adjacent to each other. (Item 11) 11. The light emitting device according to item 9 or 10, wherein the pixel circuit further comprises a switch transistor that controls light emission of the light emitting element, and a reset transistor that resets the light emitting element. (Item 12) Item 12. The light emitting device according to item 11, wherein the second isolation portion is provided between two of the reset transistors arranged adjacent to each other. (Item 13) 13. The light emitting device according to item 11 or 12, wherein the second isolation portion is provided between the reset transistor and the switch transistor adjacent thereto. (Item 14) 14. The light emitting device according to any one of items 11 to 13, further comprising the second isolation portion between the switch transistor and the adjacent select transistor. (Item 15) 15. The light emitting device according to any one of items 11 to 14, wherein the first isolation portion is provided between a well contact of a pixel and the reset transistor adjacent thereto. (Item 16) 16. The light emitting device according to any one of items 9 to 15, wherein the first isolation portion is provided between a well contact of a pixel and the selection transistor adjacent thereto. (Item 17) 17. The light-emitting device according to any one of items 9 to 16, wherein the first isolation portion is provided between a well contact of a pixel and the driving transistor adjacent thereto. (Item 18) 1. A wearable device having a display device for displaying an image, A wearable device characterized in that the display device has the light-emitting device described in any one of items 1 to 17. (Item 19) 18. A display device comprising: the light-emitting device according to any one of items 1 to 17; and an active element connected to the light-emitting device. (Item 20) an optical unit having a plurality of lenses, an image sensor that receives light that has passed through the optical unit, and a display unit that displays an image; 18. A photoelectric conversion device, wherein the display unit displays an image captured by the imaging element, and the photoelectric conversion device comprises the light-emitting device according to any one of items 1 to 17. (Item 21) A display unit is provided in the housing, and a communication unit is provided in the housing and communicates with an external device. 18. An electronic device, wherein the display unit comprises the light-emitting device according to any one of items 1 to 17.

[0130] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0131] 10: Light emitting device, 100: Pixel array, 101: Pixel, 102: Vertical scanning circuit, 104: Signal output circuit, 106: Control circuit, 201: Switch transistor, 202: Drive transistor, 203: Reset transistor, 204: Selection transistor, 205: Well contact, 300: Semiconductor substrate, 301: First element isolation section, 302: Second element isolation section

Claims

1. A light emitting device having a plurality of pixels arranged on a substrate, each of the plurality of pixels has a trench-type first isolation portion that isolates two adjacent regions of different conductivity types from each other, and a trench-type second isolation portion that isolates two adjacent regions of the same conductivity type from each other; A light emitting device, wherein the second isolation portion has a depth greater than a depth of the first isolation portion.

2. 2. The light emitting device according to claim 1, wherein the depth of the second isolation portion is greater than the depth of the first isolation portion by 0.3 [mu]m or more.

3. 2. The light emitting device according to claim 1, wherein an opening width of the first separation portion is narrower than an opening width of the second separation portion in a direction parallel to the surface of the substrate.

4. The light emitting device according to claim 1 , wherein the first isolation portion and the second isolation portion have different heights from the surface of the substrate.

5. the second separation portion includes an upper layer portion and a lower layer portion stacked on each other, The light-emitting device according to claim 1 , wherein the lower layer portion is connected to a part of a bottom surface of the upper layer portion.

6. 6. The light emitting device according to claim 5, wherein the depth of the lower layer portion is greater than the depth of the upper layer portion.

7. 6. The light emitting device according to claim 5, wherein the maximum width of the lower layer portion is smaller than the width of the bottom surface of the upper layer portion.

8. each of the plurality of pixels has a first semiconductor region, a second semiconductor region having the same conductivity type as the first semiconductor region, and a third semiconductor region having a conductivity type different from that of the first semiconductor region; 2. The light-emitting device according to claim 1, wherein the first isolation portion is provided between the first semiconductor region and the third semiconductor region that are arranged adjacent to each other, and the second isolation portion is provided between the first semiconductor region and the second semiconductor region that are arranged adjacent to each other.

9. Each of the plurality of pixels includes a light-emitting element and a pixel circuit that drives the light-emitting element, 9. The light emitting device according to claim 8, wherein the pixel circuit comprises a selection transistor that controls input of data to the pixel, and a drive transistor that drives the light emitting element in accordance with the input data.

10. 10. The light emitting device according to claim 9, wherein the second isolation portion is provided between two of the driving transistors arranged adjacent to each other.

11. 10. The light emitting device according to claim 9, wherein the pixel circuit further comprises a switch transistor that controls light emission of the light emitting element, and a reset transistor that resets the light emitting element.

12. 12. The light-emitting device according to claim 11, wherein the second isolation portion is provided between two of the reset transistors arranged adjacent to each other.

13. 12. The light emitting device according to claim 11, wherein the second isolation portion is provided between the reset transistor and the switch transistor adjacent thereto.

14. 12. The light emitting device according to claim 11, further comprising the second isolation portion between the switch transistor and the adjacent select transistor.

15. 12. The light emitting device according to claim 11, wherein the first isolation portion is provided between a well contact of a pixel and the reset transistor adjacent thereto.

16. 10. The light emitting device according to claim 9, wherein the first isolation portion is provided between a well contact of a pixel and the selection transistor adjacent thereto.

17. 10. The light emitting device according to claim 9, wherein the first isolation portion is provided between a well contact of a pixel and the driving transistor adjacent thereto.

18. 1. A wearable device having a display device for displaying an image, A wearable device, wherein the display device comprises the light-emitting device according to claim 1 .

19. A display device comprising: the light-emitting device according to claim 1; and an active element connected to the light-emitting device.

20. an optical unit having a plurality of lenses, an image sensor that receives light that has passed through the optical unit, and a display unit that displays an image; 18. A photoelectric conversion device, wherein the display section displays an image captured by the imaging element, and the photoelectric conversion device comprises the light-emitting device according to claim 1.

21. A display unit is provided in the housing, and a communication unit is provided in the housing and communicates with an external device.

18. An electronic device, wherein the display unit comprises the light-emitting device according to claim 1.

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