Display device and manufacturing method for the same

Abstract

To improve the yield or reliability of a display device.SOLUTION: A display device according to an embodiment includes a first display element, a second display element, a partition wall, a first sealing layer, and a second sealing layer. The first display element includes a first lower electrode, a first upper electrode, and a first organic layer. The second display element includes a second lower electrode, a second upper electrode, and a second organic layer. The partition wall is disposed between the first display element and the second display element. The first sealing layer covers the first display element. The second sealing layer covers the second display element. The first sealing layer includes a first end part that exists over the partition wall. The second sealing layer includes a second end that exists over the partition wall. The first end part and the second end part overlap in a thickness direction of the first sealing layer and the second sealing layer.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. For these types of display devices, technology that can improve yield and reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a manufacturing method thereof that can improve yield or reliability. [Means for solving the problem]

[0005] Generally, a display device according to an embodiment includes a first display element, a second display element, a partition wall, a first sealing layer, and a second sealing layer. The first display element includes a first lower electrode, a first upper electrode facing the first lower electrode, and a first organic layer located between the first lower electrode and the first upper electrode and emitting light in response to application of a voltage. The second display element includes a second lower electrode, a second upper electrode facing the second lower electrode, and a second organic layer located between the second lower electrode and the second upper electrode and emitting light in response to application of a voltage. The partition wall is disposed between the first display element and the second display element. The first sealing layer covers the first display element. The second sealing layer covers the second display element. The first sealing layer has a first end located above the partition wall. The second sealing layer has a second end located above the partition wall. The first end and the second end overlap in the thickness direction of the first sealing layer and the second sealing layer.

[0006] Furthermore, generally, a method for manufacturing a display device according to an embodiment includes forming a first lower electrode and a second lower electrode in a display region, forming a partition wall located between the first lower electrode and the second lower electrode, forming a first laminated film in the display region, the first laminated film including a first organic layer that emits light in response to application of a voltage and a first upper electrode that covers the first organic layer, forming a first insulating layer in the display region, performing a first etching on the first insulating layer to form a first sealing layer that has a first end located above the partition wall and covers a first display element constituted by the first lower electrode, the first organic layer, and the first upper electrode, and performing a second etching on the first laminated film. removing the portion of the second laminate film exposed from the first sealing layer; after the second etching, forming a second laminate film in the display area, the second laminate film including a second organic layer that emits light in response to application of a voltage and a second upper electrode that covers the second organic layer; forming a second insulating layer in the display area that covers the second laminate film; by third etching the second insulating layer, forming a second sealing layer that has a second end that overlaps the first end in the thickness direction of the first sealing layer and covers a second display element constituted by the second lower electrode, the second organic layer, and the second upper electrode; and by fourth etching the second laminate film, removing the portion of the second laminate film exposed from the second sealing layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels according to an embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of a partition wall and a sealing layer according to an embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a manufacturing process of a display device according to an embodiment. [Figure 8B] FIG. 8B is a schematic cross-sectional view of a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view of a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view of a step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a schematic cross-sectional view of a step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a schematic cross-sectional view of a step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a schematic cross-sectional view of a step subsequent to FIG. 8F. [Figure 8H] FIG. 8H is a schematic cross-sectional view of a step subsequent to FIG. 8G. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing a method for manufacturing a display device according to a comparative example. [Figure 9B] FIG. 9B is a schematic cross-sectional view of a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view of a step subsequent to FIG. 9B. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is rectangular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to a rectangle and may be other shapes such as a square, a perfect circle, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In the example of Fig. 1, the scanning lines G extend in the X direction and the signal lines S extend in the Y direction, but this is not limiting.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0020] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the area of ​​pixel opening AP1 is larger than the area of ​​pixel opening AP2, which is larger than the area of ​​pixel opening AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio.

[0021] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0022] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 (first display element) of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 (second display element) of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 (third display element) of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0023] The area relationship between display elements DE1, DE2, and DE3 is the same as the area relationship between pixel openings AP1, AP2, and AP3. That is, display element DE1 has the largest area, and display element DE3 has the smallest area. However, the area relationship between display elements DE1, DE2, and DE3 and the area relationship between pixel openings AP1, AP2, and AP3 are not limited to this example.

[0024] Conductive partition walls 6 are disposed on the rib layer 5. The partition walls 6 entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in a planar view and surround the display elements DE1, DE2, and DE3, respectively. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0025] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0026] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0027] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0028] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0029] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0030] Display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. Display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. Display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from organic layers OR1, OR2, and OR3, respectively.

[0031] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0032] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6 around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6 around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6 around it.

[0033] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0034] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0035] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0036] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0037] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0038] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0039] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0040] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0041] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0042] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal of the signal line S is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0043] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0044] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0045] 4 is a schematic plan view of the partition wall 6 and the sealing layers SE11, SE12, and SE13. In the example shown in this figure, the sealing layer SE11 is formed continuously over a plurality of subpixels SP1 aligned in the Y direction. Meanwhile, one sealing layer SE12 is formed for each subpixel SP2. Similarly, one sealing layer SE13 is formed for each subpixel SP3.

[0046] Each side forming the contour of the sealing layers SE11, SE12, and SE13 overlaps with the partition wall 6. In the following description, the portion of the sealing layer SE11 located above the partition wall 6 along its contour is referred to as the end E1 (first end). The portion of the sealing layer SE12 located above the partition wall 6 along its contour is referred to as the end E2 (second end). The portion of the sealing layer SE13 located above the partition wall 6 along its contour is referred to as the end E3 (third end).

[0047] In the example of Figure 4, the ends E1 and E2 of adjacent sealing layers SE11 and SE12 overlap in the Z direction. Also, the ends E1 and E3 of adjacent sealing layers SE11 and SE13 overlap in the Z direction. Also, the ends E2 and E3 of adjacent sealing layers SE12 and SE13 overlap in the Z direction. Here, the Z direction corresponds to the thickness direction of the sealing layers SE11, SE12, and SE13.

[0048] The relationship between the ends E1, E2, and E3 is not limited to the example in Fig. 4. For example, a portion of the end E1 may not overlap with the ends E2 and E3. Also, a portion of the end E2 may not overlap with the ends E1 and E3. Furthermore, a portion of the end E3 may not overlap with the ends E1 and E2.

[0049] Fig. 5 is a schematic cross-sectional view of the display device DSP taken along line VV in Fig. 4. Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line VI-VI in Fig. 4. Fig. 7 is a schematic cross-sectional view of the display device DSP taken along line VII-VII in Fig. 4. In these figures, the substrate 10, the circuit layer 11, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are omitted.

[0050] 5, an end E1 of the sealing layer SE11 located on the partition wall 6 between the subpixels SP1 and SP2 is located between the partition wall 6 and an end E2 of the sealing layer SE12 in the Z direction. A gap GP1 (first gap) is formed between the upper portion 62 of the partition wall 6 and the end E1 in the Z direction. The gap GP1 is, for example, an air gap. A stacked film FL1 may be disposed in at least a part of the region corresponding to the illustrated gap GP1.

[0051] 5, a stacked film FL2 is disposed between the sealing layer SE12 and the upper portion 62. A gap GP2 (second gap) is formed between the end E1 and the end E2 in the Z direction. At least a portion of the gap GP2 is filled with a resin layer RS1, as shown in FIG. 3, for example. The stacked film FL2 may be disposed in at least a portion of the region corresponding to the illustrated gap GP2.

[0052] 5, the ends E1 and E2 are partially in contact with each other above the partition wall 6. As another example, a stacked film FL2 may be interposed between the ends E1 and E2 depicted as being in contact in the drawing.

[0053] 6, the end E1 located on the partition wall 6 between the subpixels SP1 and SP3 is located between the partition wall 6 and the end E3 of the sealing layer SE13 in the Z direction. Also in the cross section of FIG. 6, a gap GP1 is formed between the upper portion 62 and the end E1.

[0054] 6, a stacked film FL3 is disposed between the sealing layer SE13 and the upper portion 62. A gap GP3 (third gap) is formed between the end E1 and the end E3 in the Z direction. At least a portion of the gap GP3 is filled with a resin layer RS1, as shown in FIG. 3, for example. The stacked film FL3 may be disposed in at least a portion of the region corresponding to the illustrated gap GP3.

[0055] 6, the ends E1 and E3 are partially in contact with each other above the partition wall 6. As another example, a stacked film FL3 may be interposed between the ends E1 and E3 depicted as being in contact in the drawing.

[0056] 7, the end E2 located on the partition wall 6 between the subpixels SP2 and SP3 is located between the partition wall 6 and the end E3 in the Z direction. A gap GP4 (fourth gap) is formed between the upper portion 62 and the end E2 in the Z direction. The gap GP4 is, for example, an air gap. A stacked film FL2 may be disposed in at least a part of the region corresponding to the illustrated gap GP4.

[0057] 7, a stacked film FL3 is also disposed between the sealing layer SE13 and the upper portion 62. A gap GP5 (fifth gap) is also formed between the end E2 and the end E3 in the Z direction. At least a portion of the gap GP5 is filled with the resin layer RS1, similar to the gaps GP2 and GP3 shown in FIG. 3. The stacked film FL3 may be disposed in at least a portion of the region corresponding to the illustrated gap GP5.

[0058] 7, the ends E2 and E3 are partially in contact with each other above the partition wall 6. As another example, a stacked film FL3 may be interposed between the ends E2 and E3 depicted as being in contact in the drawing.

[0059] 5 to 7, the sealing layer SE11 has a thickness T1, the sealing layer SE12 has a thickness T2, and the sealing layer SE13 has a thickness T3. The partition wall 6 has a height H. The height H corresponds to the distance from the upper surface of the rib layer 5 to the upper surface of the upper portion 62.

[0060] For example, thicknesses T1, T2, and T3 are equal to each other (T1=T2=T3). Furthermore, thicknesses T1, T2, and T3 are equal to or greater than height H (T1, T2, T3≧H). When sealing layers SE11, SE12, and SE13 are thick in this way, they can adequately cover display elements DE1, DE2, and DE3 and the partition walls 6 around them.

[0061] The relationship between the thicknesses T1, T2, T3 and the height H is not limited to the example shown here. For example, at least two of the thicknesses T1, T2, and T3 may be different. Furthermore, at least one of the thicknesses T1, T2, and T3 may be less than the height H.

[0062] The width W1 where the ends E1 and E2 overlap as shown in Fig. 5, the width W2 where the ends E1 and E3 overlap as shown in Fig. 6, and the width W3 where the ends E2 and E3 overlap as shown in Fig. 7 are, for example, 1 µm or more, more specifically, 2 µm or more. These widths W1, W2, and W3 are all smaller than the width of the partition wall 6 (the width of the upper portion 62). The widths W1, W2, and W3 may be equal to or different from each other.

[0063] Next, an example of a manufacturing method of the display device DSP will be described. Figures 8A to 8H are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figures 8A to 8H focus on the subpixels SP1, SP2, and SP3, and omit elements below the organic insulating layer 12.

[0064] In forming the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Next, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12, as shown in FIG.

[0065] 8B, the rib layer 5 and the partition walls 6 are formed. The pixel openings AP1, AP2, AP3 of the rib layer 5 may be provided after or before the partition walls 6 are formed.

[0066] After the rib layer 5 and the partition walls 6 are formed, a process for forming the display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order in which the display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0067] To form the display element DE1, first, as shown in FIG. 8C, a laminated film FL1 and an insulating layer IL1 (first insulating layer) covering the laminated film FL1 are formed. As shown in FIG. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The insulating layer IL1 is a layer to be processed into the sealing layer SE11 and is made of an inorganic insulating material. Vapor deposition can be used to form the organic layer OR1, the upper electrode UE1, and the cap layer CP1. CVD (Chemical Vapor Deposition) can be used to form the insulating layer IL1.

[0068] For example, the laminated film FL1 and the insulating layer IL1 are formed over the entire display area DA and the peripheral area SA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The insulating layer IL1 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0069] Next, the stacked film FL1 and the insulating layer IL1 are patterned. In this patterning, a resist R1 is disposed on the insulating layer IL1, as shown in Fig. 8C. The resist R1 covers the subpixel SP1 and part of the partition wall 6 around it.

[0070] Then, a first etching is performed on the insulating layer IL1, and a second etching is performed on the stacked film FL1 in this order. In the first etching, the portion of the insulating layer IL1 exposed from the resist R1 is removed. As a result, as shown in FIG. 8D, the sealing layer SE11 having an end E1 located above the partition wall 6 is formed. The first etching is, for example, dry etching.

[0071] In the second etching, the portion of the stacked film FL1 exposed from the sealing layer SE11 is removed. For example, the second etching includes wet etching or dry etching that is performed sequentially on the cap layer CP1, the upper electrode UE1, and the organic layer OR1.

[0072] In the second etching, the stacked film FL1 located on the partition wall 6 may also be removed. As a result, the gap GP1 described above is formed between the edge E1 and the partition wall 6. On the other hand, the stacked film FL1 that contacts the lower electrode LE1 through the pixel opening AP1 is completely covered by the sealing layer SE11 and is therefore not eroded by the second etching. The stacked film FL1 and the lower electrode LE1 that remain in the subpixel SP1 in this way constitute the display element DE1.

[0073] After the first and second etchings, the resist R1 is removed. Furthermore, as shown in FIG. 8E, a stacked film FL2 and an insulating layer IL2 (second insulating layer) covering the stacked film FL2 are formed. As shown in FIG. 3, the stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2. The insulating layer IL2 is a layer to be processed into the sealing layer SE12 and is made of an inorganic insulating material. Vapor deposition can be used to form the organic layer OR2, the upper electrode UE2, and the cap layer CP2. CVD can also be used to form the insulating layer IL2.

[0074] For example, the stacked film FL2 and the insulating layer IL2 are formed over the entire display area DA and the peripheral area SA. The stacked film FL2 is divided into multiple parts by overhanging partition walls 6. The stacked film FL2 may also be divided at the edge E1, but this is not limited to this example. The insulating layer IL2 continuously covers each divided part of the stacked film FL2 and the partition walls 6. For example, at least a portion of the gap GP1 remains as a void even after the stacked film FL2 and the insulating layer IL2 are formed.

[0075] Next, the stacked film FL2 and the insulating layer IL2 are patterned. In this patterning, a resist R2 is disposed on the insulating layer IL2, as shown in FIG. 8E. The resist R2 covers the subpixel SP2 and part of the partition wall 6 around it. A part of the resist R2 is located above the edge E1.

[0076] Thereafter, a third etching is performed on the insulating layer IL2, and a fourth etching is performed on the stacked film FL2 in this order. In the third etching, the portion of the insulating layer IL2 exposed from the resist R2 is removed. As a result, as shown in FIG. 8F, the sealing layer SE12 having an end E2 located above the partition wall 6 is formed. The third etching is, for example, dry etching.

[0077] In the fourth etching, the portion of the stacked film FL2 exposed from the sealing layer SE12 is removed. For example, the fourth etching includes wet etching and dry etching that are sequentially performed on the cap layer CP2, the upper electrode UE2, and the organic layer OR2.

[0078] In the fourth etching, the stacked film FL2 located on the end E1 may also be removed. As a result, the gap GP2 described above is formed between the end E1 and the end E2. Although not shown in the cross section of FIG. 8F, the gap GP4 shown in FIG. 7 is also formed by the fourth etching.

[0079] The stacked film FL2, which contacts the lower electrode LE2 through the pixel opening AP2, is completely covered by the sealing layer SE12 and is therefore not eroded by the fourth etching. The stacked film FL2 and the lower electrode LE2 remaining in the subpixel SP2 thus form the display element DE2. After the third and fourth etchings, the resist R2 is removed.

[0080] After the third and fourth etchings, the resist R2 is removed. Furthermore, as shown in FIG. 8G, a stacked film FL3 and an insulating layer IL3 (third insulating layer) covering the stacked film FL3 are formed. As shown in FIG. 3, the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3. The insulating layer IL3 is a layer to be processed into the sealing layer SE13 and is made of an inorganic insulating material. Vapor deposition can be used to form the organic layer OR3, the upper electrode UE3, and the cap layer CP3. CVD can also be used to form the insulating layer IL3.

[0081] For example, the stacked film FL3 and the insulating layer IL3 are formed over the entire display area DA and the peripheral area SA. The stacked film FL3 is divided into multiple parts by overhanging partition walls 6. The stacked film FL3 may also be divided at the ends E1 and E2, but this is not limited to this example. The insulating layer IL3 continuously covers each divided part of the stacked film FL3 and the partition walls 6.

[0082] Next, the stacked film FL3 and the insulating layer IL3 are patterned. In this patterning, a resist R3 is disposed on the insulating layer IL3, as shown in FIG. 8G. The resist R3 covers the subpixel SP3 and part of the partition wall 6 around it. A part of the resist R3 is located above the edge E1. Although not shown in the cross section of FIG. 8G, at the boundary between the subpixels SP2 and SP3, a part of the resist R3 is located above the edge E2.

[0083] Thereafter, a fifth etching is performed on the insulating layer IL3, and a sixth etching is performed on the stacked film FL3, in that order. In the fifth etching, the portion of the insulating layer IL3 exposed from the resist R3 is removed. As a result, as shown in FIG. 8H, the sealing layer SE13 having an end E3 located above the partition wall 6 is formed. The fifth etching is, for example, dry etching.

[0084] In the sixth etching, the portion of the stacked film FL3 exposed from the sealing layer SE13 is removed. For example, the sixth etching includes wet etching and dry etching that are sequentially performed on the cap layer CP3, the upper electrode UE3, and the organic layer OR3.

[0085] In the sixth etching, the stacked film FL3 located below the end E3 may also be eroded. As a result, the gap GP3 described above is formed between the end E1 and the end E3. Although not shown in the cross section of FIG. 8H, the gap GP5 shown in FIG. 7 is also formed by the fourth etching.

[0086] The stacked film FL3, which contacts the lower electrode LE3 through the pixel opening AP3, is completely covered by the sealing layer SE13 and is therefore not eroded by the sixth etching. The stacked film FL3 and the lower electrode LE3 remaining in the subpixel SP3 thus form the display element DE3. After the fifth and sixth etchings, the resist R3 is removed.

[0087] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Fig. 3 are formed in this order. As described above, at least a portion of the gaps GP2, GP3, and GP5 may be filled with the resin layer RS1.

[0088] According to the present embodiment, it is possible to improve the yield and reliability of the display device DSP, the effects of which will be described below.

[0089] 9A to 9C are schematic cross-sectional views showing a manufacturing method of a display device according to a comparative example of this embodiment. The manufacturing flow of the display device DSP is the same as that shown in FIGS. 8A to 8H. FIG. 9A shows the state immediately after the first and second etchings, FIG. 9B shows the state immediately after the third and fourth etchings, and FIG. 9C shows the state immediately after the fifth and sixth etchings.

[0090] The cross section of Fig. 9A is generally similar to the cross section of Fig. 8D. However, in Fig. 9A, the widths of the resist R1 and the sealing layer SE11 are smaller than those in Fig. 8D. Therefore, the width of the end E1 located on the partition wall 6 is also smaller than those in Fig. 8D.

[0091] In this comparative example, when forming the display element DE2 and the sealing layer SE12, the resist R2 is arranged so as not to overlap the edge E1. In this case, the insulating layer IL2 covering the edge E1 is completely removed in the third etching. Therefore, the edge E1 may be eroded in the third etching. If the edge E1 is eroded, the edge E1 retreats toward the pixel opening AP1, as shown in FIG. 9B.

[0092] Furthermore, in this comparative example, when forming the display element DE3 and the sealing layer SE13, the resist R3 is arranged so as not to overlap with the ends E1 and E2. In this case, the insulating layer IL3 covering the ends E1 and E2 is completely removed in the fifth etching. Therefore, the ends E1 and E2 may be eroded in the fifth etching. When the end E1 is eroded, the end E1 further retreats toward the pixel opening AP1, as shown in FIG. 9C. When the end E2 is eroded, the end E2 retreats toward the pixel opening AP2.

[0093] In FIG. 9C, the end E1 is separated from the partition wall 6, and the laminated film FL1 constituting the display element DE1 is exposed from the sealing layer SE11. If such a sealing defect occurs, moisture may penetrate the laminated film FL1, potentially corroding the laminated film FL1. This may result in display defects for the display element DE1. If the sealing layer SE12 is severely eroded in the fifth etching, a similar problem may occur for the display element DE2.

[0094] On the other hand, in this embodiment, a part of the end E1 of the sealing layer SE11 overlaps with the end E2 of the sealing layer SE12. In this case, the part of the end E1 is protected by the sealing layer SE12 (insulating layer IL2) in the third etching and the fifth etching.

[0095] In this embodiment, another part of the end E1 of the sealing layer SE11 overlaps with the end E3 of the sealing layer SE13. In this case, in the fifth etching, the other part of the end E1 is protected by the sealing layer SE13 (insulating layer IL3).

[0096] Furthermore, in this embodiment, a part of the end E2 of the sealing layer SE12 overlaps with the end E3 of the sealing layer SE13. In this case, in the fifth etching, the part of the end E2 is protected by the sealing layer SE13 (insulating layer IL3).

[0097] For these reasons, according to this embodiment, recession of the ends E1 and E2 as shown in the comparative example is suppressed, thereby improving the yield of the display device DSP and increasing the reliability of the display device DSP.

[0098] All display devices and manufacturing methods that can be implemented by a person skilled in the art by appropriately modifying the design based on the display device and manufacturing method described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0099] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of each of the above-described embodiments, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0100] Furthermore, with regard to other effects brought about by the aspects described in each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0101] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, DE1, DE2, DE3...display element, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer.

Claims

1. a first display element including a first lower electrode, a first upper electrode facing the first lower electrode, and a first organic layer located between the first lower electrode and the first upper electrode and emitting light in response to application of a voltage; a second display element including a second lower electrode, a second upper electrode facing the second lower electrode, and a second organic layer located between the second lower electrode and the second upper electrode and emitting light in response to application of a voltage; a partition wall disposed between the first display element and the second display element; a first sealing layer covering the first display element; a second sealing layer covering the second display element; Equipped with the first sealing layer has a first end located above the partition wall; the second sealing layer has a second end portion located above the partition wall; the first end portion and the second end portion overlap with each other in a thickness direction of the first sealing layer and the second sealing layer; Display device.

2. the first end is located between the partition wall and the second end in the thickness direction, a first gap is formed between the partition wall and the first end portion in the thickness direction; The display device according to claim 1 .

3. The first gap is an air gap. The display device according to claim 2 .

4. a second gap is formed between the first end and the second end in the thickness direction; The display device according to claim 2 .

5. further comprising a resin layer covering the first sealing layer and the second sealing layer; At least a portion of the second gap is filled with the resin layer. The display device according to claim 4 .

6. the first sealing layer and the second sealing layer are in contact with each other above the partition wall; The display device according to any one of claims 1 to 5.

7. The area of ​​the first display element is larger than the area of ​​the second display element. The display device according to any one of claims 1 to 5.

8. The partition wall includes a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. The display device according to any one of claims 1 to 5.

9. the first sealing layer and the second sealing layer are formed of an inorganic insulating material; The display device according to any one of claims 1 to 5.

10. the thickness of the first sealing layer and the thickness of the second sealing layer are both greater than the height of the partition wall; The display device according to any one of claims 1 to 5.

11. forming a first lower electrode and a second lower electrode in a display area; forming a partition wall located between the first lower electrode and the second lower electrode; forming a first laminated film in the display area, the first laminated film including a first organic layer that emits light in response to application of a voltage and a first upper electrode that covers the first organic layer; forming a first insulating layer covering the first laminated film in the display area; forming a first sealing layer by first etching the first insulating layer, the first sealing layer having a first end portion located above the partition wall and covering a first display element constituted by the first lower electrode, the first organic layer, and the first upper electrode; a second etching of the first stacked film to remove a portion of the first stacked film exposed from the first sealing layer; After the second etching, a second stacked film is formed in the display area, the second stacked film including a second organic layer that emits light in response to application of a voltage and a second upper electrode that covers the second organic layer; forming a second insulating layer covering the second laminated film in the display area; a second sealing layer having a second end portion overlapping the first end portion in a thickness direction of the first sealing layer and covering a second display element constituted by the second lower electrode, the second organic layer, and the second upper electrode, is formed by a third etching of the second insulating layer; a fourth etching of the second stacked film to remove a portion of the second stacked film exposed from the second sealing layer; A method for manufacturing a display device, comprising:

12. a portion of the first stacked film located on the partition wall is removed in the second etching, thereby forming a first gap between the partition wall and the first end portion in the thickness direction; The method for manufacturing a display device according to claim 11 .

13. the first gap remains as a void after the second sealing layer is formed; The method for manufacturing a display device according to claim 12 .

14. a portion of the second stacked film located above the first end portion is removed in the fourth etching, thereby forming a second gap between the first end portion and the second end portion in the thickness direction; The method for manufacturing a display device according to claim 12 .

15. forming a resin layer covering the first sealing layer and the second sealing layer; At least a portion of the second gap is filled with the resin layer. The method for manufacturing a display device according to claim 14 .

16. the first sealing layer and the second sealing layer are in contact with each other above the partition wall; A method for manufacturing a display device according to any one of claims 11 to 15.

17. The area of ​​the first display element is larger than the area of ​​the second display element. A method for manufacturing a display device according to any one of claims 11 to 15.

18. The partition wall includes a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. A method for manufacturing a display device according to any one of claims 11 to 15.

19. the first sealing layer and the second sealing layer are formed of an inorganic insulating material; A method for manufacturing a display device according to any one of claims 11 to 15.

20. the thickness of the first sealing layer and the thickness of the second sealing layer are both greater than the height of the partition wall; A method for manufacturing a display device according to any one of claims 11 to 15.

Images