Display panel and display

Abstract

To provide a display panel and a display, capable of improving the light transmittance of the display panel.SOLUTION: A display panel having a first display area including a first area includes a substrate and a wiring positioned on the substrate. The first area includes at least one wiring area; a plurality of wirings in the at least one wiring are laminated in a direction vertical to the substrate and are provided in an insulating manner; in the display panel, since the wirings in the wiring area are laminated in the direction vertical to the substrate, the orthographic projections of the wirings in the wiring area on the substrate at least partially overlap to reduce the areas of the orthographic projections in the wiring area on the substrate; and the light transmittance of the display panel is improved by increasing the area of a part of the display panel not covered in the wiring area.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202410342963.3, entitled "Display Panel and Display Device," filed on March 25, 2024, and Chinese Patent Application No. 202411083183.8, entitled "Display Panel and Display Device," filed on August 8, 2024. The present application relates to the technical field of displays, and in particular to display panels and display devices. [Background technology]

[0002] With the development of display technology, the requirements for the performance of display panels are becoming higher and higher. However, the light transmittance of general display panels is relatively low, which affects the operating efficiency of the photosensitive module and further affects the performance of the display panel. Summary of the Invention

[0003] The embodiments of the present application provide a display panel and a display device that can improve the light transmittance of the display panel.

[0004] An embodiment according to a first aspect of the present invention provides a display panel, the display panel including a first display area, the first display area including a first area, the display panel including a substrate and wiring located on the substrate, the first area including at least one wiring area, and a plurality of wirings in the at least one wiring area being stacked and insulated along a direction perpendicular to the substrate.

[0005] In some embodiments, the at least one wiring region includes a first wiring region, and a plurality of wirings in the first wiring region are stacked and insulated along a direction perpendicular to the substrate, and the wirings in the first wiring region extend along the first direction; and / or, at least one wiring region includes a second wiring region, and a plurality of wirings in the second wiring region are stacked and insulated along a direction perpendicular to the substrate, and the wirings in the second wiring region extend along a second direction, and the first direction and the second direction intersect; Optionally, the first region further includes light-emitting regions, and the light-emitting regions and the first wiring region are alternately arranged in the first direction, and / or the light-emitting regions and the second wiring region are alternately arranged in the second direction; Optionally, one or more of a first wiring region, a second wiring region, and a light emitting region are provided between adjacent second regions; Optionally, the first display region further includes a second region, the light transmittance of the first region being less than the light transmittance of the second region; Optionally, the second regions and the first wiring regions are alternately arranged in the second direction, and / or the second regions and the second wiring regions are alternately arranged in the first direction; Optionally, the second region is a non-emissive region; Optionally, the first wiring region includes shielding wiring and a plurality of potential change signal lines, the shielding wiring is provided between the potential change signal lines along a direction perpendicular to the substrate, the shielding wiring includes a reset signal line and / or a power supply signal line, and the potential change signal lines include a scanning signal line and / or a light emission signal line; Optionally, in the first wiring region, the reset signal line is provided between the scanning signal line and the light-emitting signal line along a direction perpendicular to the substrate; Optionally, in the first wiring region, a plurality of scanning signal lines are located in at least two conductive layers; Optionally, the first wiring region further includes a second power supply signal line, the second power supply signal line being provided between adjacent scanning signal lines in a direction perpendicular to the substrate in the first wiring region; Optionally, the second wiring region includes a plurality of data lines, the plurality of data lines being located in at least two conductive layers; Optionally, in the second wiring region, a plurality of data lines are stacked and insulated along a direction perpendicular to the substrate; Optionally, the first wiring area includes a first power supply signal line, and the second wiring area includes a first power supply signal line, and the first power supply signal line in the first wiring area and the first power supply signal line in the second wiring area are electrically connected; Optionally, the first wiring area includes a second power supply signal line, and the second wiring area includes a second power supply signal line, and the second power supply signal line in the first wiring area and the second power supply signal line in the second wiring area are electrically connected.

[0006] In some embodiments, The display panel further comprises: a pixel circuit layer including a drive circuit region located in a first region, a first wiring region, and a second wiring region, each of the first wiring region and the second wiring region including a plurality of wirings, the wirings in the first wiring region being stacked along a direction perpendicular to the substrate and being provided in an insulated manner, and the wirings in the second wiring region being stacked along a direction perpendicular to the substrate and being provided in an insulated manner; a light-emitting layer including a plurality of repeat units located in a first region, the repeat units including light-emitting units of at least three colors, and the repeat units being located on a side of the driving circuit region away from the substrate; Optionally, the drive circuit regions adjacent to each other along the first direction are connected via wiring located in a first wiring region, and the drive circuit regions adjacent to each other along the second direction are connected via wiring located in a second wiring region; Optionally, there is a one-to-one correspondence between repeat units and driver circuit regions.

[0007] In some embodiments, the wiring includes a data line, a scanning signal line, a reset signal line, an emission signal line, a first power supply signal line, and a second power supply signal line, and optionally, the first wiring region includes the scanning signal line, the reset signal line, the emission signal line, and the first power supply signal line stacked in order along a direction away from the substrate, and optionally, the first wiring region further includes a second power supply signal line, and the second power supply signal line and the emission signal line are provided in the same layer, and the second wiring region includes the data line and the first power supply signal line stacked in order along a direction away from the substrate, and the first power supply signal line in the first wiring region and the first power supply signal line in the second wiring region are electrically connected, Optionally, in the first wiring region, the orthogonal projection of the first power supply signal line on the substrate covers the orthogonal projection of the scanning signal line, the reset signal line, the light-emitting signal line, and the second power supply signal line on the substrate; in the second wiring region, the orthogonal projection of the first power supply signal line on the substrate covers the orthogonal projection of the data line on the substrate; and optionally, in the first wiring region, the orthogonal projection of the reset signal line on the substrate and the orthogonal projection of the first power supply signal line on the substrate overlap.

[0008] In some embodiments, the scanning signal lines include first and second scanning lines, and are provided in a layer different from the first and second scanning lines, and the orthogonal projection of the first scanning line on the substrate is located outside the orthogonal projection of the second scanning line on the substrate; optionally, in the first wiring region, a distance between the orthogonal projections of adjacent first and second scanning lines on the substrate is 0.5 μm or more and 2.5 μm or less; and optionally, in the first wiring region, a second power supply signal line and an emission signal line are provided in the same layer, and a distance between the second power supply signal line and the emission signal line is 0.5 μm or more and 2.5 μm or less.

[0009] In some embodiments, the data lines include a first data line, a second data line, and a third data line, and in the second wiring region, the first data line and the second data line are provided in the same layer and spaced apart, and the third data line is provided in a layer different from the first data line; Optionally, the third data line is located on a side of the first data line facing the first power supply signal line or on a side of the first data line facing away from the first power supply signal line; Optionally, the second wiring region further includes a second power supply signal line, and the second power supply signal line and the third data line are provided in the same layer and spaced apart, or the second power supply signal line is located on the side of the data line facing the first power supply signal line or on the side of the data line facing away from the first power supply signal line. Optionally, the orthogonal projections of the first data line and the third data line on the substrate overlap, and / or the second power signal line and the third data line are provided on the same layer and spaced apart, and the orthogonal projections of the second data line and the second power signal line on the substrate overlap, and optionally the repeating unit includes a first light-emitting unit, a second light-emitting unit and a third light-emitting unit, and the colors of the lights emitted from the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are different, and the pixel circuit connected to the first light-emitting unit is electrically connected to the first data line, the pixel circuit connected to the second light-emitting unit is electrically connected to the second data line, and the pixel circuit connected to the third light-emitting unit is electrically connected to the third data line. Optionally, in the second wiring region, an orthogonal projection of the first power signal line on the substrate covers an orthogonal projection of the data line and the second power signal line on the substrate; Optionally, the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less.

[0010] In some embodiments, the pixel circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are stacked in order along a direction away from the substrate, and in the first wiring region, a first scan line is formed in the first conductive layer, a second scan line is formed in the second conductive layer, a reset signal line is formed in the third conductive layer, an emission signal line is formed in the fourth conductive layer, and a first power supply signal line is formed in the fifth conductive layer. In some embodiments, in the second wiring region, the first data line and the second data line are formed on the third conductive layer, and the second power signal line and the third data line are formed on the fourth conductive layer; or the first data line and the second data line are formed on the fourth conductive layer, and the second power signal line and the third data line are formed on the third conductive layer; or the first data line and the second data line are formed on the third conductive layer, the third data line is formed on the fourth conductive layer, and the second power signal line is formed on the second conductive layer; or the first data line and the second data line are formed on the fourth conductive layer, the third data line is formed on the third conductive layer, and the second power signal line is formed on the second conductive layer. Optionally, the third conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in order in a direction away from the substrate, and the fourth conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in order in a direction away from the substrate, and optionally, in the first wiring region, a second power supply signal line is located on the fourth conductive layer, and optionally, the second power supply signal line in the first wiring region and the second power supply signal line in the second wiring region are electrically connected.

[0011] In some embodiments, in the second wiring region, the data lines include a first data line, a second data line, a third data line, and a fourth data line, the first data line and the second data line are provided in the same layer and spaced apart, the third data line and the fourth data line are provided in the same layer and spaced apart, and the third data line is located on a side of the first data line facing the first power signal line; Optionally, orthogonal projections of the first data line and the third data line on the substrate overlap, and orthogonal projections of the second data line and the fourth signal line on the substrate overlap; In some embodiments, the second wiring region further includes a second power signal line, the second power signal line being located on a side of the third data line facing the first power signal line, or the second power signal line being located on a side of the first data line facing away from the first power signal line. Optionally, the repeat unit includes first subunits and second subunits arranged along a second direction, the first subunits including a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit arranged in order along the first direction, the second subunits including a third light-emitting unit, a second light-emitting unit, a first light-emitting unit, and a fourth light-emitting unit arranged in order along the first direction, wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit emit light of different colors, and the second light-emitting unit and the fourth light-emitting unit emit light of the same color, the pixel circuits connected to the first column light-emitting units of the repeat unit are electrically connected to a first data line, the pixel circuits connected to the second column light-emitting units of the repeat unit are electrically connected to a second data line, the pixel circuits connected to the third column light-emitting units of the repeat unit are electrically connected to a third data line, and the pixel circuits connected to the fourth column light-emitting units of the repeat unit are electrically connected to a fourth data line, the second direction is parallel to the column direction, Optionally, the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less.

[0012] In some embodiments, the wiring includes a data line, a scanning signal line, a reset signal line, a light-emitting signal line, a first power supply signal line, and a second power supply signal line, and the first wiring region includes the scanning signal line, the second power supply signal line, the reset signal line, the light-emitting signal line, and the first power supply signal line stacked along a direction away from the substrate, the scanning signal line includes a first type scanning signal line and a second type scanning signal line provided in different layers, and the second power supply signal line is provided between the first type scanning signal line and the second type scanning signal line along a direction perpendicular to the substrate, and the reset signal line the reset signal lines are arranged between the light-emitting signal lines and the second-type scanning signal lines along a direction perpendicular to the substrate, and the second wiring region is provided with data lines, second power supply signal lines, and first power supply signal lines which are arranged in a stacked manner in a direction away from the substrate, and optionally, the first power supply signal lines in the first wiring region are electrically connected to the first power supply signal lines in the second wiring region, and optionally, in the first wiring region, the orthogonal projection of the first power supply signal lines on the substrate covers the orthogonal projection of the scanning signal lines, reset signal lines, light-emitting signal lines, and second power supply signal lines on the substrate; In the second wiring region, the orthogonal projection of the first power supply signal line on the substrate covers the orthogonal projection of the data line and the second power supply signal line on the substrate, and optionally, in the first wiring region, the orthogonal projection of the reset signal line on the substrate overlaps with the orthogonal projection of the first power supply signal line on the substrate, and optionally, the second power supply signal line in the first wiring region and the second power supply signal line in the second wiring region are electrically connected.

[0013] In some embodiments, the first type of scanning signal line includes a first sub-scanning line and a second sub-scanning line, the first sub-scanning line and the second sub-scanning line are provided in the same layer, and an orthogonal projection of the first sub-scanning line on the substrate is located outside an orthogonal projection of the second sub-scanning line on the substrate; and / or the second type scanning signal lines include third sub-scanning lines and fourth sub-scanning lines, the third sub-scanning lines and the fourth sub-scanning lines being provided on the same layer, and the orthogonal projection of the third sub-scanning line on the substrate is located outside the orthogonal projection of the fourth sub-scanning line on the substrate; optionally, in the first wiring region, the orthogonal projection of the second power supply signal line on the substrate overlaps with the orthogonal projection of the first power supply signal line on the substrate; optionally, the spacing between the orthogonal projections of the first sub-scanning lines and the second sub-scanning lines on the substrate is 1.5 μm or more and 2.5 μm or less; optionally, the spacing between the orthogonal projections of the third sub-scanning lines and the fourth sub-scanning lines on the substrate is 1.5 μm or more and 2.5 μm or less; optionally, the orthogonal projections of the first type scanning signal lines and the second type scanning signal lines on the substrate partially overlap with each other in the first wiring region.

[0014] In some embodiments, the data lines include a first data line, a second data line, and a third data line, the first data line and the second data line being provided in the same layer and spaced apart, the third data line being located on a side of the first data line facing the first power signal line, the second wiring region further including a reset signal line, the reset signal line and the third data line being provided in the same layer and spaced apart, and optionally, orthogonal projections of the first data line and the third data line on the substrate overlap, and orthogonal projections of the second data line and the reset signal line on the substrate overlap; Optionally, the repeating unit includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit, and the colors of the lights emitted from the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are different, and the pixel circuit connected to the first light-emitting unit is electrically connected to a first data line, the pixel circuit connected to the second light-emitting unit is electrically connected to a second data line, and the pixel circuit connected to the third light-emitting unit is electrically connected to a third data line; Optionally, the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less.

[0015] In some embodiments, the data lines include a first data line, a second data line, a third data line, and a fourth data line, the first data line and the second data line being provided in the same layer and spaced apart, the third data line and the fourth data line being provided in the same layer and spaced apart, the third data line being located on a side of the first data line facing the first power signal line, and optionally, orthogonal projections of the first data line and the third data line on the substrate overlap, and orthogonal projections of the second data line and the fourth data line on the substrate overlap; Optionally, the repeat unit includes a first subunit and a second subunit arranged along a second direction, the first subunit including a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit arranged in order along the first direction, the second subunit including a third light-emitting unit, a second light-emitting unit, a first light-emitting unit, and a fourth light-emitting unit arranged in order along the first direction, wherein the colors of the lights emitted from the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are different, and the colors of the lights emitted from the second light-emitting unit and the fourth light-emitting unit are the same; The pixel circuits connected to the first column light-emitting units of the repeat unit are electrically connected to the first data line, the pixel circuits connected to the second column light-emitting units of the repeat unit are electrically connected to the second data line, the pixel circuits connected to the third column light-emitting units of the repeat unit are electrically connected to the third data line, and the pixel circuits connected to the fourth column light-emitting units of the repeat unit are electrically connected to the fourth data line, and the second direction is parallel to the column direction; Optionally, the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less.

[0016] In some embodiments, the pixel circuit layer includes a first conductive layer, a second conductive layer, a sixth conductive layer, a third conductive layer, a fourth conductive layer, a seventh conductive layer, and a fifth conductive layer that are stacked in order along a direction away from the substrate; wherein in the first wiring region, the first type scanning signal line is formed on the first conductive layer, the second power supply signal line is formed on the second conductive layer, the second type scanning signal line is formed on the sixth conductive layer, the reset signal line is formed on the third conductive layer, the light-emitting signal line is formed on the fourth conductive layer, and the first power supply signal line is formed on the fifth conductive layer; and in the second wiring region, the second power supply signal line is formed on the seventh conductive layer, the first data line and the second data line are formed on the third conductive layer, and the third data line and the fourth data line are formed on the fourth conductive layer; optionally, the third conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in order along a direction away from the substrate; and optionally, the fourth conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in order along a direction away from the substrate.

[0017] In some embodiments, the display panel further includes a partition structure, the partition structure including a first partition section and a second partition section stacked in order on the substrate along a direction away from the substrate, the orthogonal projection of the first partition section on the substrate is located within the orthogonal projection of the second partition section on the substrate, and the area of ​​the orthogonal projection of the first partition section on the substrate is smaller than the area of ​​the orthogonal projection of the second partition section on the substrate; Optionally, the wiring includes a first power supply signal line, and at least a part of the partition structure also functions as the first power supply signal line, and optionally, the first partition section also functions as the first power supply signal line.

[0018] Optionally, the partition structure includes a third partition located between the substrate and the first partition, wherein the orthogonal projection of the first partition on the substrate is located within the orthogonal projection of the third partition on the substrate, and the area of ​​the orthogonal projection of the first partition on the substrate is smaller than the area of ​​the orthogonal projection of the third partition on the substrate.

[0019] Optionally, the light-emitting region includes a plurality of light-emitting units, and at least a portion of the partition structure is located between the light-emitting units. Optionally, the light-emitting units include a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate, and the second electrode is electrically connected to the partition structure.

[0020] An embodiment of the second aspect further provides a display panel, the display panel including a first display area, the first display area including a first area, the display panel including a substrate, wiring located on the substrate, and a partition structure; the first region includes at least one wiring region, and a plurality of wirings in the at least one wiring region are stacked along a direction perpendicular to the substrate and are insulated from each other, and the plurality of wirings include at least one of a data line, a scanning signal line, a reset signal line, a light-emitting signal line, and a second power supply signal line, and a first power supply signal line; At least a part of the partition structure also functions as a first power supply signal line, and in at least one wiring region, at least one type of data line, scanning signal line, reset signal line, light-emitting signal line, and second power supply signal line, and at least a part of the partition structure that also functions as the first power supply signal line, are stacked and insulated along a direction perpendicular to the substrate.

[0021] In some embodiments, the at least one wiring region includes a first wiring region, and a plurality of wirings in the first wiring region are stacked and insulated along a direction perpendicular to the substrate, the wirings in the first wiring region extend along a first direction, and in the first wiring region, at least one of a data line, a scanning signal line, a reset signal line, a light-emitting signal line, and a second power supply signal line, and at least a part of a partition structure that also functions as the first power supply signal line, are stacked and insulated along a direction perpendicular to the substrate, and / or at least one wiring region includes a second wiring region, and a plurality of wirings in the second wiring region are stacked and insulated along a direction perpendicular to the substrate, and the wirings in the second wiring region extend along a second direction, and the first direction and the second direction intersect, and in the second wiring region, at least one type of data line, scanning signal line, reset signal line, light-emitting signal line, and second power supply signal line, and at least a part of a partition structure that also functions as a first power supply signal line, are stacked and insulated along a direction perpendicular to the substrate, In some embodiments, the first region further includes light-emitting regions, and the light-emitting regions and the first wiring region are alternately arranged in the first direction, and / or the light-emitting regions and the second wiring region are alternately arranged in the second direction; and / or the first display region further includes a second region, and the light transmittance of the first region is smaller than the light transmittance of the second region; In some embodiments, one or more of a first wiring region, a second wiring region, and a light emitting region are provided between adjacent second regions; In some embodiments, the second regions and the first wiring regions are alternately arranged in the second direction, and / or the second regions and the second wiring regions are alternately arranged in the first direction; In some embodiments, the second region is a non-emissive region. In some embodiments, the partition structure includes a first partition portion and a second partition portion that are stacked in order along a direction away from the substrate, an orthogonal projection of the first partition portion on the substrate is located within an orthogonal projection of the second partition portion on the substrate, and an area of ​​the orthogonal projection of the first partition portion on the substrate is smaller than an area of ​​the orthogonal projection of the second partition portion on the substrate; In some embodiments, the partition structure includes a third partition located between the substrate and the first partition; an orthogonal projection of the first partition portion on the substrate is located within an orthogonal projection of the third partition portion on the substrate, and an area of ​​the orthogonal projection of the first partition portion on the substrate is smaller than an area of ​​the orthogonal projection of the third partition portion on the substrate; In some embodiments, the light-emitting region includes a plurality of light-emitting units, and at least some of the partition structures are located between the light-emitting units; In some embodiments, the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate, the second electrode being electrically connected to the partition structure; In some embodiments, the partition structure is formed to surround the partition opening, and at least a portion of the light-emitting unit is located within the partition opening. An embodiment of the third aspect further provides a display device, including any display panel according to the first aspect of the present application.

[0022] In some embodiments, the display device further includes a photosensitive module disposed on a side of the display panel opposite to the light-emitting side of the first display area. [Effects of the Invention]

[0023] In the display panel according to the present application, the wiring in the wiring region is stacked in a direction perpendicular to the substrate, so that the orthogonal projections of the wiring in the wiring region on the substrate at least partially overlap, thereby reducing the area of ​​the orthogonal projection of the wiring region on the substrate, thereby increasing the area of ​​the portion of the display panel that is not blocked by the wiring region and thereby improving the light transmittance of the display panel. [Brief explanation of the drawings]

[0024] In order to more clearly explain the technical solutions of the embodiments of the present application, the drawings that need to be used in the embodiments of the present application will be briefly described below, but it is clear that the drawings described below are only some embodiments of the present application, and those skilled in the art can further derive other drawings based on the drawings without any creative work. [Figure 1] 1 is a schematic plan view of a display panel according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line P-P' in FIG. [Figure 3] FIG. 2 is an enlarged view of a partial structure of the N region in FIG. [Figure 4] 1 is an enlarged partial structural view of another display panel provided by an embodiment of the present application; [Figure 5] FIG. 2 is a plan view schematic diagram of another display panel provided by an embodiment of the present application. [Figure 6] FIG. 4 is a cross-sectional view taken along the line QQ′ in FIG. [Figure 7a] 4A to 4C are cross-sectional views taken along line M-M' in FIG. 3 corresponding to multiple types of display panels provided by embodiments of the present application. [Figure 7b] 4A to 4C are cross-sectional views taken along line M-M' in FIG. 3 corresponding to multiple types of display panels provided by embodiments of the present application. [Figure 7c] 4A to 4C are cross-sectional views taken along line M-M' in FIG. 3 corresponding to multiple types of display panels provided by embodiments of the present application. [Figure 7d] 4A to 4C are cross-sectional views taken along line M-M' in FIG. 3 corresponding to multiple types of display panels provided by embodiments of the present application. [Figure 7e] 4A to 4C are cross-sectional views taken along line M-M' in FIG. 3 corresponding to multiple types of display panels provided by embodiments of the present application. [Figure 7f] 4A to 4C are cross-sectional views taken along line M-M' in FIG. 3 corresponding to multiple types of display panels provided by embodiments of the present application. [Figure 8] 10 is a cross-sectional view of a first wiring region of another display panel provided by an embodiment of the present application. [Figure 9] FIG. 10 is a cross-sectional view of a second wiring region of another display panel provided by an embodiment of the present application. [Figure 10] FIG. 10 is a pixel circuit schematic diagram of another display panel provided by an embodiment of the present application. [Figure 11] 1 is an enlarged partial structural view of another display panel provided by an embodiment of the present application; [Figure 12] 10 is a cross-sectional view of a first wiring region of another display panel provided by an embodiment of the present application. [Figure 13] FIG. 10 is a cross-sectional view of a second wiring region of another display panel provided by an embodiment of the present application. [Figure 14a] 4A to 4C are cross-sectional views of the second wiring region of multiple types of display panels provided by the embodiments of the present application. [Figure 14b] 4A to 4C are cross-sectional views of the second wiring region of multiple types of display panels provided by the embodiments of the present application. [Figure 15] FIG. 10 is a pixel circuit schematic diagram of another display panel provided by an embodiment of the present application. [Figure 16] FIG. 10 is a partial cross-sectional view of another display panel provided by an embodiment of the present application. [Figure 17] 1 is a structural schematic diagram of a display device provided by an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0025] The following describes in detail the features and exemplary embodiments of each aspect of the present application. In the following detailed description, many specific details are provided to provide a thorough understanding of the present application. However, those skilled in the art can implement the present application without needing some of these specific details. The following description of the embodiments is intended to provide an example of the present application to better understand the present application.

[0026] It should be noted that, in this specification, relational terms such as "first" and "second" are used to distinguish one entity or operation from another, and do not necessarily require or imply the existence of any such relationship or order between those entities or operations. Furthermore, the terms "comprise," "have," or any other variation thereof are intended to cover a non-exclusive inclusion, whereby a process, method, article, or facility comprising a set of elements not only includes those elements, but also other elements not expressly listed or inherent in such process, method, article, or facility. Absent more limitations, elements qualified by the phrase "comprise" do not exclude the presence of other identical elements in a process, method, article, or facility that includes the elements.

[0027] After investigation, the inventors have found that the reason for the low light transmittance of the display panel is that the display panel includes driving circuits, and adjacent driving circuits are connected via wiring, but the wiring area is large, so light rays are blocked by the wiring, resulting in a relatively low light transmittance of the display panel. Based on investigation into the above problem, the inventors have found a display panel and a display device that improve the light transmittance of the display panel.

[0028] For a better understanding of the present invention, a display panel and a display device according to an embodiment of the present invention will be described in detail below in conjunction with FIGS.

[0029] In a first aspect, an embodiment of the present application provides a display panel 1, which has a first display area AA1, which includes a first area A1, and which includes a substrate 10 and wiring 110 located on the substrate 10. The first area A1 includes at least one wiring area, and a plurality of wirings 110 in the at least one wiring area are stacked along a direction perpendicular to the substrate 10 and are provided in an insulated manner.

[0030] In the display panel 1 according to the present application, the display panel 1 may be a transparent display panel 1, i.e., the display panel 1 has only one type of display area, the first display area AA1. Alternatively, the display panel 1 may include two types of display areas, the first display area AA1 and the second display area AA2, where the light transmittance of the first display area AA1 is greater than that of the second display area AA2. A light-sensing module, such as a camera module or a fingerprint recognition module, may be provided below the first display area AA1 (i.e., the area corresponding to the light-sensing module). The relatively high light transmittance of the first display area AA1 can improve the performance of the light-sensing module, thereby improving the performance of the display panel 1.

[0031] The display panel 1 includes a structure of multiple film layers that are stacked, and the embodiments of the present application do not limit the specific film layer configuration within the display panel 1. Here, the display panel includes at least a substrate 10 and wiring 110 located on the substrate 10. The first display area AA1 includes a first area A1, which includes at least one wiring area, and the multiple wirings 110 in the at least one wiring area are stacked along a direction perpendicular to the substrate 10, thereby improving the light transmittance of the display panel 1.

[0032] Specifically, by stacking the wires 110 in the wiring region in a direction perpendicular to the substrate 10, the orthogonal projections of the wires 110 in the wiring region onto the substrate 10 at least partially overlap, thereby reducing the area of ​​the orthogonal projection of the wiring region onto the substrate 10. This increases the area of ​​the portion of the display panel 1 that is not blocked by the wiring region, thereby improving the light transmittance of the display panel 1.

[0033] In some embodiments, the first display area AA1 further includes a second area A2, and the light transmittance of the first area A1 is smaller than the light transmittance of the second area A2, and / or at least one wiring area includes a first wiring area 112, and the wiring 110 in the first wiring area 112 is stacked along a direction perpendicular to the substrate 10, and the wiring in the first wiring area 112 extends along a first direction x, and / or at least one wiring area includes a second wiring area 113, and the wiring 110 in the second wiring area 113 is stacked along a direction perpendicular to the substrate 10, and the wiring in the second wiring area 113 extends along a second direction y.

[0034] The first display area AA1 includes at least a first area A1 and a second area A2. At least one wiring area in the first area A1 is provided with wiring, and the second area A2 has fewer or no wiring, thereby making the light transmittance of the first area A1 lower than that of the second area A2. Because the second area A2 has a relatively high light transmittance, a photosensitive module provided on one side of the first display area AA1 can capture light transmitted through the second area A2. The photosensitive module may be, for example, a camera module or a fingerprint recognition module. Furthermore, optionally, the second area A2 is a non-light-emitting area, thereby reducing the influence of a light-emitting unit on the light transmittance of the second area A2 and advantageously improving the performance and accuracy of the photosensitive module.

[0035] The first wiring region 112 and the second wiring region 113 both include a plurality of wirings 110. Furthermore, the wirings 110 in the first wiring region 112 are stacked in a direction perpendicular to the substrate 10, thereby allowing the orthogonal projections of the wirings 110 in the first wiring region 112 on the substrate 10 to at least partially overlap, thereby reducing the area of ​​the orthogonal projection of the first wiring region 112 on the substrate 10. Similarly, the wirings 110 in the second wiring region 113 are stacked in a direction perpendicular to the substrate 10, thereby allowing the orthogonal projections of the wirings 110 in the second wiring region 113 on the substrate 10 to at least partially overlap, thereby reducing the area of ​​the orthogonal projection of the second wiring region 113 on the substrate 10. This increases the area of ​​the portions of the display panel 1 that are not blocked by the first wiring region 112 and the second wiring region 113, i.e., increases the area of ​​the second region A2, thereby improving the light transmittance of the display panel 1.

[0036] In some embodiments, the first region A1 further includes a light-emitting region (which may, for example, be located at the same position as the driving circuit region 111 in FIG. 3), and the light-emitting region and the first wiring region 112 are alternately arranged in the first direction x, and / or the light-emitting region and the second wiring region 113 are alternately arranged in the second direction y. The first direction x and the second direction may intersect, for example, be perpendicular.

[0037] The light-emitting region may be provided with light-emitting units for realizing a light-emitting display function. The light-emitting region and the first wiring region 112 are alternately arranged in the first direction x, i.e., two first wiring regions 112 are provided on both sides of the light-emitting region in the first direction x. Furthermore, the light-emitting region may be provided with a driving circuit for driving the light-emitting units to emit light for display, and the wiring 110 located in the first wiring region 112 may be electrically connected to the driving circuit to meet the light-emitting requirements of the light-emitting units.

[0038] Similarly, in the second direction y, the light-emitting areas and the second wiring areas 113 are arranged alternately, that is, two second wiring areas 113 are arranged on both sides of the light-emitting area along the second direction y, respectively. Furthermore, a driving circuit for driving the light-emitting units to emit light may be provided in the light-emitting area, and the wiring 110 located in the second wiring area 113 may be electrically connected to and installed in the driving circuit, thereby meeting the light-emitting requirements of the light-emitting units.

[0039] In some embodiments, one or more of the first wiring region 112, the second wiring region 113, and the light emitting region may be provided between adjacent second regions A2.

[0040] Referring to the drawing, the first wiring region 112, the second wiring region 113, and the light-emitting region may form a ring structure surrounding the second region A2. Optionally, the second region A2 and the first wiring region 112 are alternately arranged in the second direction y, and / or the second region A2 and the second wiring region 113 are alternately arranged in the first direction x.

[0041] With this design, one second region A2 is provided at an interval between adjacent first wiring regions 112, thereby reducing the problem of reduced display effect caused by the short distance between adjacent first wiring regions 112. Similarly, one second region A2 is provided at an interval between adjacent second wiring regions 113, thereby reducing the problem of reduced display effect caused by the short distance between adjacent second wiring regions 114.

[0042] In some embodiments, the first wiring region 112 includes shielding wiring and a plurality of potential change signal lines. Along a direction z perpendicular to the substrate 10 (i.e., the thickness direction of the substrate), the shielding wiring is provided between the potential change signal lines, and the shielding wiring includes a reset signal line Vref and / or a power supply signal line, and the potential change signal lines include a scan signal line Scan and / or an emission signal line EM.

[0043] At different times, the signal voltages of the potential-changing signal lines change over time, i.e., the potential-changing signal lines are used to transfer voltage-changing signals. Unlike the potential-changing signal lines, the signal voltages of the shielding lines do not change over time, i.e., the shielding lines are used to transfer constant voltage signals. Here, the shielding lines include at least one of the reset signal line Vref and the power supply signal lines, the power supply signal lines include the first power supply signal line ELVSS and the second power supply signal line ELVDD, and the potential-changing signal lines include the scan signal line Scan and / or the light-emitting signal line EM.

[0044] The reset signal line Vref may be electrically connected to a reset transistor in the pixel circuit, and the reset transistor is used to transfer the voltage of the reset signal line Vref to at least one of the gate, source, and drain of the driving transistor and / or the first electrode of the light-emitting unit.

[0045] If there is no shielding structure between different potential change signal lines that are installed facing each other along the direction perpendicular to the substrate 10, interference due to coupling between the different potential change signal lines is likely to occur, which will affect the normal use of the display panel 1.

[0046] Therefore, in the embodiment of the present application, the layout of the wiring 110 inside the display panel 1 is adjusted. In the direction perpendicular to the substrate 10, the shield wiring is provided between the potential change signal lines. In this way, the shield wiring can function as a signal shield for different potential change signal lines that are installed opposite each other along the direction perpendicular to the substrate 10, reducing the risk of interference due to coupling between the different potential change signal lines and improving the reliability of use of the display panel 1.

[0047] 6, as an option, a reset signal line Vref is provided between the scanning signal line Scan and the light-emitting signal line EM in the first wiring region 112 along the direction z perpendicular to the substrate 10. In this way, the reset signal line Vref can function as a shield for the scanning signal line Scan and the light-emitting signal line EM, reducing the risk of interference due to signal coupling between the scanning signal line Scan and the light-emitting signal line EM and improving reliability.

[0048] Here, a plurality of scanning signal lines Scan may be provided, or the plurality of scanning signal lines Scan may be provided in the same conductive layer. Alternatively, as an option, as shown in Figure 6, the plurality of scanning signal lines Scan may be located in at least two conductive layers in the first wiring region 112, and the plurality of scanning signal lines Scan may be provided in different film layers, thereby increasing the pitch between different scanning signal lines Scan, reducing mutual influence between the different scanning signal lines Scan, and contributing to improving reliability. An insulating layer may be provided between at least two conductive layers.

[0049] 12 , the first wiring region 112 may further include a second power supply signal line ELVDD, and the second power supply signal line ELVDD may be provided between the plurality of scanning signal lines Scan in the first wiring region 112 along a direction perpendicular to the substrate 10. The second power supply signal line ELVDD may be provided between adjacent scanning signal lines Scan in the first wiring region 112 along a direction perpendicular to the substrate 10. In this manner, the second power supply signal line ELVDD may function as a shield for the plurality of scanning signal lines Scan located in different conductive layers, reducing the risk of interference due to signal coupling between the different scanning signal lines Scan and improving reliability.

[0050] Optionally, as shown in FIG. 7a, the second wiring region 113 includes a plurality of data lines (Data), which are located in at least two conductive layers. A plurality of data lines (Data) may be provided, and the plurality of data lines (Data) may be provided in different film layers, which is advantageous for increasing the pitch between different data lines (Data), reducing mutual influence between different data lines (Data), and improving reliability. Optionally, the plurality of data lines (Data) in the second wiring region 113 are stacked in a direction perpendicular to the substrate 10 and are provided insulated from each other. An insulating layer may be provided between at least two conductive layers.

[0051] Optionally, the first wiring region 112 includes a first power supply signal line ELVSS, and the second wiring region 113 includes a first power supply signal line ELVSS, and the first power supply signal line ELVSS in the first wiring region 112 is electrically connected to the first power supply signal line ELVSS in the second wiring region 113. In this way, the first power supply signal line ELVSS can form a mesh-like structure as a whole, thereby reducing resistance.

[0052] Optionally, the first wiring region 112 includes a second power supply signal line ELVDD, and the second wiring region 113 includes a second power supply signal line ELVDD, and the second power supply signal line ELVDD in the first wiring region 112 is electrically connected to the second power supply signal line ELVDD in the second wiring region 113. In this way, the second power supply signal line ELVDD can form a mesh-like structure as a whole, thereby reducing resistance.

[0053] 1 to 4 , in some embodiments, the display panel 1 includes a substrate 10, a pixel circuit layer 11, and an emitting layer 12. The pixel circuit layer 11 includes a driving circuit region 111, a first wiring region 112, and a second wiring region 113 located in a first region A1. The first wiring region 112 and the second wiring region 113 each include a plurality of wirings 110. The wirings 110 in the first wiring region 112 are stacked in a direction perpendicular to the substrate 10 and are insulated from each other. The wirings 110 in the second wiring region 113 are stacked in a direction perpendicular to the substrate 10 and are insulated from each other. The emitting layer 12 may include a plurality of light-emitting units located in the first region A1. For example, the emitting layer 12 may include a plurality of repeat units 120 located in the first region A1. The repeat units 120 include light-emitting units 1200 of at least three colors, and the repeat units 120 are located on the side of the driving circuit region 111 away from the substrate 10.

[0054] The display panel 1 of the present application includes a substrate 10, a pixel circuit layer 11, and a light-emitting layer 12. Here, the pixel circuit layer 11 includes a driving circuit region 111, a first wiring region 112, and a second wiring region 113, and the light-emitting layer 12 includes a plurality of repeat units 120, and the repeat unit 120 includes light-emitting units 1200 of at least three colors.

[0055] The driving circuit region 111 includes a plurality of driving circuits for driving the light-emitting units 1200 to emit light, and each driving circuit is electrically connected to at least one light-emitting unit 1200 to drive the light-emitting unit 1200 to emit light. Optionally, the driving circuit region 111 is disposed to at least partially overlap the light-emitting region, for example, overlapping with the light-emitting region. The embodiments of the present application do not limit the relationship between the driving circuit region 111 and the repeating units 120. Optionally, the driving circuit region 111 corresponds to the repeating units 120 one-to-one, one-to-many, or many-to-one, etc.

[0056] The first wiring region 112 and the second wiring region 113 both include a plurality of wirings 110. Optionally, adjacent driving circuit regions 111 along a first direction x are connected via wirings 110 located in the first wiring region 112, and adjacent driving circuit regions 111 along a second direction y are connected via wirings 110 located in the second wiring region 113.

[0057] By providing the wirings 110 in the first wiring region 112 in a stacked manner along a direction perpendicular to the substrate 10, orthogonal projections of the wirings 110 in the first wiring region 112 on the substrate 10 at least partially overlap, thereby reducing the area of ​​the orthogonal projection of the first wiring region 112 on the substrate 10, and by providing the wirings 110 in the second wiring region 113 in a stacked manner along a direction perpendicular to the substrate 10, orthogonal projections of the wirings 110 in the second wiring region 113 on the substrate 10 at least partially overlap, thereby reducing the area of ​​the orthogonal projection of the second wiring region 113 on the substrate 10. As a result, the area of ​​the portions of the display panel 1 that are not blocked by the first wiring region 112, the second wiring region 113, and the drive circuit region 111 increases, for example, the area of ​​the second region A2 increases, thereby improving the light transmittance of the display panel 1.

[0058] 5 , the display panel 1 may be a transparent display panel 1, or may include a first display area AA1 and a second display area AA2. The pixel circuit layer 11 in the first display area AA1 includes a driving circuit area 111, a first wiring area 112, and a second wiring area 113, so that the light transmittance of the first display area AA1 is greater than that of the second display area AA2. A photosensitive module, such as a camera module or a fingerprint recognition module, may be provided below the first display area AA1. The high light transmittance of the first display area AA1 can improve the performance of the photosensitive module, thereby improving the performance of the display panel 1.

[0059] In one possible embodiment, as shown in Figures 6 and 7a, the wiring 110 includes one or more of a data line Data, a scan signal line Scan, a reset signal line Vref, an emission signal line EM, a first power supply signal line ELVSS, and a second power supply signal line ELVDD.

[0060] Specifically, the pixel circuit in the driving circuit region 111 may be a 7T1C circuit, an 8T1C circuit, or other circuit, and the present application is not limited thereto. The present application only takes the 7T1C circuit and the 8T1C circuit as examples. One pixel circuit can drive one light-emitting unit 1200 or multiple light-emitting units 1200, and the present application only takes the example of one pixel circuit driving one light-emitting unit 1200.

[0061] Specifically, in the case of a 7T1C circuit, all seven transistors may be polysilicon semiconductor transistors, for example, P-type transistors, and in the case of an 8T1C circuit, two of the eight transistors may be oxide semiconductor transistors, for example, N-type transistors, and the other transistors may be polysilicon semiconductor transistors, for example, P-type transistors.

[0062] In one possible embodiment, as shown in FIG. 6, which may be applied to a 7T1C circuit, the first wiring region 112 includes a scan signal line Scan, a reset signal line Vref, an emission signal line EM, and a first power supply signal line ELVSS, which are stacked along a direction away from the substrate 10.

[0063] In one possible embodiment, the first wiring region 112 further includes a second power supply signal line ELVDD, as shown in Fig. 8. Optionally, the second power supply signal line ELVDD is provided in the same layer as the light emission signal line EM.

[0064] There are several layout methods for the second power supply signal line ELVDD. For example, the second power supply signal line ELVDD may extend in the second direction y as a whole, or the second power supply signal line ELVDD may form a mesh structure, thereby improving the reliability of signal transmission in the second power supply signal line ELVDD.

[0065] Furthermore, when the second power supply signal line ELVDD forms a mesh structure, a portion of the second power supply signal line ELVDD is located in the first wiring region 112 and a portion of the second power supply signal line ELVDD is located in the second wiring region 113. When the second power supply signal line ELVDD generally extends along the second direction y, the second power supply signal line ELVDD can be entirely or partially provided in the second wiring region 113. Furthermore, when the second power supply signal line ELVDD cannot be entirely provided in the second wiring region 113 due to limitations of other wiring layout methods, pixel arrangement methods, or other factors, the second power supply signal line ELVDD may be partially provided in the first wiring region 112.

[0066] 6 and 7a show a state in which the second power supply signal line ELVDD is not provided in the first wiring region 112, but is provided in the second wiring region 113. Figures 8 and 9 show a state in which the second power supply signal line ELVDD is not provided in the second wiring region 113, but is provided in the first wiring region 112.

[0067] 8 and 9, in the first wiring region 112, the light-emitting signal line EM needs to be rerouted to the film layer where the second power supply signal line ELVDD is located by a method such as a via hole due to wiring layout requirements within the display panel 1. Therefore, in the first wiring region 112, the second power supply signal line ELVDD and the light-emitting signal line EM are provided in the same layer.

[0068] 7a, the second wiring region 113 includes a data line Data and a first power supply signal line ELVSS that are stacked in this order in a direction away from the substrate 10. Optionally, the first power supply signal line ELVSS in the first wiring region 112 and the first power supply signal line ELVSS in the second wiring region 113 are electrically connected.

[0069] Optionally, one of the first power signal line ELVSS and the second power signal line ELVDD is at a high level and the other is at a low level. For example, the first power signal line ELVSS may be a low-level signal line ELVSS, and the second power signal line ELVDD may be a high-level signal line ELVDD. The first power signal line ELVSS may be electrically connected to a second electrode (e.g., a cathode) of the light-emitting unit. The second power signal line ELVDD may be electrically connected to a pixel circuit. The pixel circuit may be electrically connected to a first electrode (e.g., an anode) of the light-emitting unit.

[0070] Here, in the pixel circuit layer 11, the scan signal lines Scan, the reset signal lines Vref, and the light-emitting signal lines EM extend along the first direction x, and the data lines Data extend along the second direction y. Therefore, the scan signal lines Scan, the reset signal lines Vref, and the light-emitting signal lines EM are located in the first wiring region 112, and the data lines Data are located in the second wiring region 113.

[0071] As can be seen from the above, in the pixel circuit layer 11, the second power supply signal line ELVDD may be provided in only one of the first wiring region 112 and the second wiring region 113, or the second power supply signal line ELVDD may be provided simultaneously in both the first wiring region 112 and the second wiring region 113. As for the first power supply signal line ELVSS, since the entire area can be designed in a mesh pattern, it may be provided simultaneously in both the first wiring region 112 and the second wiring region 113.

[0072] 6 and 8 , in the first wiring region 112, the orthogonal projection of the first power signal line ELVSS on the substrate 10 covers the orthogonal projection of the scan signal line Scan, the reset signal line Vref, the light-emitting signal line EM, and the second power signal line ELVDD on the substrate 10. For example, in the first wiring region 112, the orthogonal projection of one or more of the scan signal line Scan, the reset signal line Vref, the light-emitting signal line EM, and the second power signal line ELVDD on the substrate 10 overlaps with the orthogonal projection of the first power signal line ELVSS on the substrate 10. For example, in the first wiring region 112, the orthogonal projection of one or more of the scan signal line Scan, the reset signal line Vref, the light-emitting signal line EM, and the second power signal line ELVDD on the substrate 10 is located within the orthogonal projection of the first power signal line ELVSS on the substrate 10.

[0073] For example, in the first wiring region 112, the orthogonal projection of one or more of the scanning signal lines Scan and the light-emitting signal lines EM on the substrate 10 overlaps with the orthogonal projection of the reset signal line Vref on the substrate 10. For example, in the first wiring region 112, the orthogonal projection of one or more of the scanning signal lines Scan and the light-emitting signal lines EM on the substrate 10 is located within the orthogonal projection of the reset signal line Vref on the substrate 10. This arrangement can improve the shielding effect of the reset signal line Vref with respect to the scanning signal lines Scan and the light-emitting signal lines EM.

[0074] As shown in FIGS. 7a and 9, in the second wiring region 113, the orthogonal projection of the first power supply signal line ELVSS on the substrate 10 covers the orthogonal projection of the data line DATA on the substrate 10. As shown in FIG.

[0075] In the above embodiment, all of the other signal lines are arranged below the first power supply signal line ELVSS and are covered by the first power supply signal line ELVSS. By stacking the other signal lines below the first power supply signal line ELVSS, the areas of the other signal lines and the first power supply signal line ELVSS that block light can overlap. This increases the area of ​​the display panel 1 that is not shielded by the film layer in the pixel circuit layer 11, improving light transmittance. On the other hand, the shielding effect can be improved by providing another conductive layer on the side of the light-emitting layer 12 away from the pixel circuit layer 11, and the first power supply signal line ELVSS can provide a shielding effect for the signal lines in the pixel circuit layer 11 and the signal lines in the other conductive layers. Furthermore, the display uniformity of the display panel 1 can be improved, with only evenly distributed reflection from the first power supply signal line ELVSS.

[0076] In one possible embodiment, as shown in FIG. 6, in the first wiring region 112, the orthogonal projection of the reset signal line Vref on the substrate 10 and the orthogonal projection of the first power signal line ELVSS on the substrate 10 at least partially overlap, for example, overlap.

[0077] In the above embodiment, the reset signal line Vref has a fixed signal and is used to achieve a shielding function. Therefore, the reset signal line Vref shields the scan signal line Scan and the emission signal line EM, which are located on both sides of the reset signal line Vref and have alternating high-level and low-level signals, thereby preventing signal crosstalk. The reset signal line Vref is designed to be relatively wide, thereby improving the signal shielding effect. Furthermore, the orthogonal projection of the reset signal line Vref on the substrate 10 at least partially overlaps with the orthogonal projection of the first power supply signal line ELVSS on the substrate 10, for example, overlapping each other. This allows the reset signal line Vref to be designed wide without creating a new light-shielding area. That is, the light-shielding area remains the same as the light-shielding area of ​​the first power supply signal line ELVSS, improving the light transmittance.

[0078] In one possible embodiment, as shown in FIG. 6, the scanning signal line Scan includes a first scanning line Scan10 and a second scanning line Scan20, and the first scanning line Scan10 and the second scanning line Scan20 are provided on different layers, and the orthogonal projection of the first scanning line Scan10 on the substrate 10 is located outside the orthogonal projection of the second scanning line Scan20 on the substrate 10, i.e., the orthogonal projections of the first scanning line Scan10 and the second scanning line Scan20 on the substrate 10 do not overlap.

[0079] In the above embodiment, the first scanning line Scan10 and the second scanning line Scan20 are provided on different layers, which simplifies the wiring and reduces crosstalk between them.

[0080] In the above embodiment, the orthogonal projections of the first scan line Scan10 and the second scan line Scan20 on the substrate 10 do not overlap, and the minimum distance between them can be increased, thereby further reducing crosstalk between them.

[0081] In the above embodiment, the distance between the orthogonal projections of the first scan line Scan10 and the second scan line Scan20 on the substrate 10 is 0.5 μm or more and 2.5 μm or less. By keeping the distance between the first scan line Scan10 and the second scan line Scan20 within this range, a fixed pitch can be maintained between them, reducing crosstalk between them. At the same time, the pitch between them can be prevented from being too large, which can increase the light-blocking area and affect the light transmittance. For example, the distance between the orthogonal projections of the first scan line Scan10 and the second scan line Scan20 on the substrate 10 can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, or 2.5 μm.

[0082] Optionally, the display panel includes a pixel circuit, as shown in Figure 10. Optionally, the pixel circuit includes some or all of the first transistor T1 to the seventh transistor T7 and a storage capacitor Cst.

[0083] Optionally, the pixel circuit includes a first transistor T1, which may be a driving transistor for driving the light-emitting unit to emit light, and the third transistor T3 may be a switch transistor for providing threshold compensation for the first transistor T1.

[0084] Specifically, each transistor has a control terminal, a first electrode, and a second electrode. The control terminal is used to control whether the first electrode and the second electrode are electrically connected. The storage capacitor Cst includes opposing first and second electrodes. Optionally, the pixel circuit includes a fourth transistor T4 and / or a seventh transistor T7. The first scan line Scan10 is connected to the control terminal of the fourth transistor T4. The first scan line Scan10 is connected to the control terminal of the seventh transistor T7. The first electrode of the fourth transistor T4 is connected to the reset signal line Vref. The first electrode of the seventh transistor T7 is connected to the reset signal line Vref. The second electrode of the fourth transistor T4 is connected to the control terminal of the driving transistor and / or the second electrode of the storage capacitor Cst. The second electrode of the seventh transistor T7 is connected to the first electrode (e.g., anode) of the light-emitting unit. The fourth transistor T4 is used to reset the control terminal of the driving transistor. The seventh transistor T7 is used to reset the first electrode of the light-emitting unit.

[0085] The second scan line Scan20 is connected to the control terminal of the second transistor T2. The second scan line Scan20 is connected to the control terminal of the third transistor T3. A first pole of the second transistor T2 (which may be a data write transistor) is connected to the data line Data, and a second pole of the second transistor T2 is connected to the first pole of the first transistor T1. A first pole of the third transistor T3 (which may be a threshold compensation transistor) is connected to the control terminal of the first transistor T1. A second pole of the third transistor T3 is connected to the second pole of the first transistor T1. A control terminal of the first transistor T1 is connected to the second plate of the storage capacitor Cst.

[0086] The light-emitting signal line EM is connected to the control terminal of the fifth transistor T5 (which may be the first light-emitting control transistor). The light-emitting signal line EM is connected to the control terminal of the sixth transistor T6 (which may be the second light-emitting control transistor). A first electrode of the fifth transistor T5 is connected to the second power supply signal line ELVDD. A first electrode of the storage capacitor Cst is connected to the second power supply signal line ELVDD. A second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1. A first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1, and a second electrode of the sixth transistor T6 is connected to the first electrode (e.g., anode) of the light-emitting unit. A second electrode (e.g., cathode) of the light-emitting unit is connected to the first power supply signal line ELVSS.

[0087] Optionally, the first transistor T1 through the seventh transistor T7 may all be P-type transistors (i.e., metal oxide semiconductor transistors), or T3 and T4 may be N-type transistors (i.e., low-temperature polysilicon semiconductor transistors) and the other transistors may all be P-type transistors.

[0088] In the above embodiment, as shown in FIG. 8 , the second power supply signal line ELVDD and the light-emitting signal line EM are provided in the same layer in the first wiring region 112, and the distance between the second power supply signal line ELVDD and the light-emitting signal line EM is 0.5 μm or more and 2.5 μm or less. By keeping the distance between the second power supply signal line ELVDD and the light-emitting signal line EM within the above range, a fixed pitch can be maintained between them, reducing crosstalk between them. At the same time, the pitch between them can be prevented from being too large, which can increase the light-shielding area and affect the light transmittance. For example, the distance between the second power supply signal line ELVDD and the light-emitting signal line EM may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, or 2.5 μm.

[0089] In one possible embodiment, as shown in FIG. 4, the repeat unit 120 includes a first light-emitting unit 1201, a second light-emitting unit 1202, and a third light-emitting unit 1203, and the colors of the light emitted from the first light-emitting unit 1201, the second light-emitting unit 1202, and the third light-emitting unit 1203 are different.

[0090] In the above embodiment, the repeat unit 120 includes three light-emitting units of three colors, and includes three light-emitting units, so that a good display effect can be achieved when the number of light-emitting units is relatively small. Optionally, the first light-emitting unit 1201 can be a red light-emitting unit, the second light-emitting unit 1202 can be a blue light-emitting unit, and the third light-emitting unit 1203 can be a green light-emitting unit.

[0091] According to the pixel layout form of FIG. 4 of the above embodiment, assuming a 7T1C pixel circuit layout, the corresponding first wiring region 112 and second wiring region 113 may be designed by stacking the wires 110 using the methods of FIGS. 6 and 7a, or the corresponding first wiring region 112 and second wiring region 113 may be designed by stacking the wires 110 using the methods of FIGS. 8 and 7a.

[0092] Specifically, as shown in FIG. 7a, the data line Data includes a first data line Data1, a second data line Data2, and a third data line Data3, and the pixel circuit connected to the first light-emitting unit 1201 is electrically connected to the first data line Data1, the pixel circuit connected to the second light-emitting unit 1202 is electrically connected to the second data line Data2, and the pixel circuit connected to the third light-emitting unit 1203 is electrically connected to the third data line Data3.

[0093] In the above embodiment, the second wiring region 113 includes the first data line Data1 and the second data line Data2 arranged in the same layer with a gap therebetween, and the third data line Data3 arranged in a different layer from the first data line Data1, and as shown in Figures 7a, 7c, and 7d, the third data line Data3 is located on the side of the first data line Data1 facing the first power signal line ELVSS, or as shown in Figures 7b, 7e, and 7f, the third data line Data3 is located on the side of the first data line Data1 away from the first power signal line ELVSS. Furthermore, as shown in Figures 7a and 7f, the second wiring region 113 further includes a second power signal line ELVDD, and the second power signal line ELVDD and the third data line Data3 are arranged in the same layer with a gap therebetween. Alternatively, as shown in Figures 7b and 7d, the second power signal line ELVDD is located on the side of the data line Data facing the first power signal line ELVSS, or as shown in Figures 7c and 7e, the second power signal line ELVDD is located on the side of the data line Data facing away from the first power signal line ELVSS.

[0094] By distributing the first data line Data1, the second data line Data2, the third data line Data3, and the second power supply signal line ELVDD across two or three layers, the wiring space can be increased, which makes wiring easier and saves wiring space while satisfying wiring requirements.

[0095] Furthermore, the orthogonal projections of the first data line Data1 and the third data line Data3 on the substrate 10 at least partially overlap, for example, they are overlapping. And / or the orthogonal projections of the second data line Data2 and the second power supply signal line ELVDD on the substrate 10 at least partially overlap, for example, they are overlapping. As a result, assuming that the line width of the first power supply signal line ELVSS is fixed, increasing the line width of the data line Data reduces the resistance within the data line Data. For example, the first data line Data1 and the second data line Data2 are provided in the same layer and spaced apart.

[0096] In the above embodiment, in the second wiring region 113, the orthogonal projection of the first power signal line ELVSS on the substrate 10 covers the orthogonal projection of the data line Data and the second power signal line ELVDD on the substrate 10. The other signal lines are all provided below the first power signal line ELVSS and are covered by the first power signal line ELVSS. By providing the other signal lines in a stacked manner below the first power signal line ELVSS, the light-shielding areas of the other signal lines and the first power signal line ELVSS can overlap, thereby increasing the area of ​​the display panel 1 that is not shielded by the film layer in the pixel circuit layer 11 and improving the light transmittance. On the other hand, to improve the shielding effect, the display panel 1 may be provided with another conductive layer on the side of the light-emitting layer 12 away from the pixel circuit layer 11, and the first power signal line ELVSS can provide a shielding effect for the signal lines in the pixel circuit layer 11 and the signal lines in the other conductive layers.

[0097] In the above embodiment, the line width of the first data line Data1 and the second data line Data2 is 2 μm or more and 3 μm or less. Therefore, assuming that the wiring space is fixed, the line width of the data line Data is relatively large, thereby reducing the resistance of the data line Data. For example, the line width of the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm.

[0098] The distance between the first data line Data1 and the second data line Data2 is 2 μm or more and 3 μm or less. By keeping the distance between the first data line Data1 and the second data line Data2 within this range, a fixed pitch can be maintained between them, reducing crosstalk between them, while preventing the pitch from being too large, which would increase the light-shielding area and affect the light transmittance. For example, the distance between the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm.

[0099] Furthermore, the spacing between the third data line Data3 and the second power signal line ELVDD may be greater than or equal to 2 μm and less than or equal to 3 μm. By keeping the spacing between the third data line Data3 and the second power signal line ELVDD within this range, a fixed pitch can be maintained between them, reducing crosstalk between them. At the same time, the spacing between the third data line Data3 and the second power signal line ELVDD can be prevented from being too large, which would increase the light-shielding area and affect the light transmittance. For example, the spacing between the third data line Data3 and the second power signal line ELVDD may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm.

[0100] 2 and 6 , the pixel circuit layer 11 includes a first conductive layer 114, a second conductive layer 115, a third conductive layer 116, a fourth conductive layer 117, and a fifth conductive layer 118, which are stacked in this order along a direction away from the substrate 10. In the first wiring region 112, a first scan line Scan10 is formed on the first conductive layer 114, a second scan line Scan20 is formed on the second conductive layer 115, a reset signal line Vref is formed on the third conductive layer 116, an emission signal line EM is formed on the fourth conductive layer 117, and a first power supply signal line ELVSS is formed on the fifth conductive layer 118.

[0101] 7a to 7f, in the second wiring region 113, the first data line Data1 and the second data line Data2 are formed on the third conductive layer 116, the second power signal line ELVDD and the third data line Data3 are formed on the fourth conductive layer 117, and the first power signal line ELVSS is formed on the fifth conductive layer 118. Alternatively, the first data line Data1 and the second data line Data2 are formed on the fourth conductive layer 117, and the second power signal line ELVDD and the third data line Data3 are formed on the third conductive layer 116. Alternatively, the first data line Data1 and the second data line Data2 are formed on the third conductive layer 116, the third data line Data3 is formed on the fourth conductive layer 117, and the second power signal line ELVDD is formed on the second conductive layer 115. Alternatively, the first data line Data1 and the second data line Data2 are formed on the fourth conductive layer 117, the third data line Data3 is formed on the third conductive layer 116, and the second power signal line ELVDD is formed on the second conductive layer 115.

[0102] 2, in the driving circuit region 111 and / or the second display region AA2, the first conductive layer 114 is used to form the gate of the transistor, the second conductive layer 115 is formed as the first electrode plate of the storage capacitor Cst, the third conductive layer 116 is used to form the source / drain of the transistor, the fourth conductive layer 117 is used to form the wiring 110, and the fifth conductive layer 118 is used to form the partition structure. The second electrode plate of the storage capacitor Cst may be located on the first conductive layer 114.

[0103] In the above embodiment, the third conductive layer 116 includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in that order in a direction away from the substrate 10, and the fourth conductive layer 117 includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in that order in a direction away from the substrate 10.

[0104] In the above embodiment, as shown in Fig. 8, in the first wiring region 112, the second power supply signal line ELVDD and the third data line Data3 are provided on the fourth conductive layer 117, that is, the second power supply signal line ELVDD may form a mesh structure as shown in Fig. 7a and Fig. 8. The first power supply signal line ELVSS in the first wiring region 112 and the first power supply signal line ELVSS in the second wiring region 113 are electrically connected.

[0105] 11 , the repeat unit 120 includes one or more subunits arranged along the second direction y. Optionally, each subunit includes a first light-emitting unit 1201, a second light-emitting unit 1202, a third light-emitting unit 1203, and a fourth light-emitting unit 1204. The first light-emitting unit 1201, the second light-emitting unit 1202, and the third light-emitting unit 1203 emit light of different colors, while the second light-emitting unit 1202 and the fourth light-emitting unit 1204 emit light of the same color.

[0106] In the above embodiment, one repeat unit 120 may include two subunits, i.e., one repeat unit 120 may include eight light-emitting units, where each subunit includes four light-emitting units, specifically, the four light-emitting units may be arranged along the first direction x. Here, the subunits include a first light-emitting unit 1201, a second light-emitting unit 1202, a third light-emitting unit 1203, and a fourth light-emitting unit 1204 arranged along the first direction x, where the first light-emitting unit 1201 may be a red light-emitting unit, the second light-emitting unit 1202 may be a green light-emitting unit, the third light-emitting unit 1203 may be a blue light-emitting unit, and the fourth light-emitting unit 1204 may be a green light-emitting unit. Here, each subunit may form four white dots based on the shared use of light-emitting units, thereby improving the display effect.

[0107] Here, the arrangement order of the light emitting units in the two subunits may be different. Specifically, the repeat unit 120 includes a first subunit and a second subunit arranged along the second direction y, the first subunit includes a first light emitting unit 1201, a second light emitting unit 1202, a third light emitting unit 1203 and a fourth light emitting unit 1204 arranged in order along the first direction x, and the second subunit includes a third light emitting unit 1203, a second light emitting unit 1202, a first light emitting unit 1201 and a fourth light emitting unit 1204 arranged in order along the first direction x, and the first light emitting unit 1201 and the third light emitting unit 1203 are arranged opposite each other along the second direction y, thereby improving the light mixing effect.

[0108] In one possible embodiment, as shown in FIGS. 9 and 11, in the second wiring region 113, the data lines Data include a first data line Data1, a second data line Data2, a third data line Data3, and a fourth data line Data4, the first data line Data1 and the second data line Data2 being arranged in the same layer and spaced apart, the third data line Data3 and the fourth data line Data4 being arranged in the same layer and spaced apart, and the third data line Data3 being located on the side of the first data line Data1 facing the first power signal line ELVSS.

[0109] According to the different pixel arrangement forms within the display panel 1, four data lines may be provided in the second wiring region 113, and the four data lines are respectively connected to different light-emitting units to realize the driving control of the different light-emitting units.

[0110] Specifically, by installing the first data line Data1, the second data line Data2, the third data line Data3, and the fourth data line Data4 separately on both layers, the wiring space can be increased, which makes wiring easier and enables space saving of wiring while satisfying wiring requirements.

[0111] In the above embodiment, the orthogonal projections of the first data line Data1 and the third data line Data3 on the substrate 10 at least partially overlap, for example, completely overlap. The orthogonal projections of the second data line Data2 and the fourth data line Data4 on the substrate 10 at least partially overlap, for example, completely overlap. As a result, assuming that the line width of the first power supply signal line ELVSS is fixed, the line width of the data line Data is increased, thereby reducing the resistance within the data line Data.

[0112] In some embodiments, the second wiring area 113 further includes a second power signal line ELVDD, which is located on the side of the third data line Data3 that faces the first power signal line ELVSS in the second wiring area 113, as shown in Figure 14a. Alternatively, the second power signal line ELVDD is located on the side of the first data line Data1 that faces away from the first power signal line ELVSS in the second wiring area 113, as shown in Figure 14b.

[0113] Optionally, in the second wiring region 113, the second power signal line ELVDD is located between the first data line Data1 and the third data line Data3.

[0114] In one possible embodiment, the pixel circuits connected to the light-emitting units in the first column of the repeat unit 120 are electrically connected to the first data line Data1, the pixel circuits connected to the light-emitting units in the second column of the repeat unit 120 are electrically connected to the second data line Data2, the pixel circuits connected to the light-emitting units in the third column of the repeat unit 120 are electrically connected to the third data line Data3, and the pixel circuits connected to the light-emitting units in the fourth column of the repeat unit 120 are electrically connected to the fourth data line Data4, and the second direction y is parallel to the column direction.

[0115] Here, four columns of light-emitting units are provided in a single repeat unit 120, and the number of light-emitting units in each column is usually determined by the number of sub-units in the repeat unit 120. For example, if two sub-units are provided in a single repeat unit 120, each column in the single repeat unit 120 includes two light-emitting units. Furthermore, the number of data lines Data corresponding to the single repeat unit 120 is four, and the four data lines Data are corresponding to pixel circuits connected to light-emitting units in different columns.

[0116] Furthermore, a single subunit includes four light-emitting units, each connected to a different data line Data, and the four data lines Data drive and control pixel circuits connected to different light-emitting units in the single subunit. Alternatively, different subunits may be arranged in the second direction y, and pixel circuits connected to adjacent light-emitting units in the different subunits in the second direction y may be connected to the same data line Data, so that the same data line Data can simultaneously control pixel circuits connected to multiple light-emitting units arranged in the second direction y.

[0117] In the above embodiment, the line widths of the first data line Data1 and the second data line Data2 are 2 μm or more and 3 μm or less. Therefore, assuming that the wiring space is fixed, increasing the line width of the data line Data reduces the resistance of the data line Data. The spacing between the first data line Data1 and the second data line Data2 is 2 μm or more and 3 μm or less. By keeping the spacing between the first data line Data1 and the second data line Data2 within the above range, a fixed pitch can be maintained between the two lines, reducing crosstalk between them. At the same time, the spacing between the two lines can be prevented from being too large, which would increase the light-shielding area and affect the light transmittance. Optionally, the spacing between the third data line Data3 and the fourth data line Data4 is 2 μm or more and 3 μm or less. By keeping the spacing between the third data line Data3 and the fourth data line Data4 within the above range, a fixed pitch can be maintained between them, reducing crosstalk between them, while avoiding a pitch that is too large, thereby avoiding an increase in the light-shielding area and affecting light transmittance. For example, the line widths of the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm. For example, the spacing between the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm. For example, the spacing between the third data line Data3 and the fourth data line Data4 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm.

[0118] According to the pixel arrangement form of FIG. 11 of the above embodiment, assuming a 7T1C pixel circuit layout, the corresponding first wiring region 112 and second wiring region 113 can be designed by stacking the wiring 110 using the methods of FIGS. 8 and 9.

[0119] In one possible embodiment, as shown in FIGS. 12 and 13 , which can be applied, for example, when the pixel circuit is an 8T1C circuit, the wiring 110 includes one or more of a data line Data, a scan signal line Scan, a reset signal line Vref, an emission signal line EM, a first power supply signal line ELVSS, and a second power supply signal line ELVDD.

[0120] 12 , the first wiring region 112 includes scanning signal lines Scan, second power supply signal lines ELVDD, reset signal lines Vref, light emission signal lines EM, and first power supply signal lines ELVSS, which are stacked in a direction away from the substrate 10. The scanning signal lines Scan include first type scanning signal lines 1101 and second type scanning signal lines 1102 which are provided in different layers, the second power supply signal lines ELVDD are provided between the first type scanning signal lines 1101 and the second type scanning signal lines 1102 in a direction perpendicular to the substrate 10, and the reset signal line Vref is provided between the light emission signal lines EM and the second type scanning signal lines 1102 in a direction perpendicular to the substrate 10.

[0121] 13, the second wiring region 113 includes a data line Data, a second power supply signal line ELVDD, and a first power supply signal line ELVSS, which are stacked in this order along a direction away from the substrate 10. For example, the first power supply signal line ELVSS in the first wiring region 112 and the first power supply signal line ELVSS in the second wiring region 113 are electrically connected.

[0122] In the above embodiment, the reset signal line Vref and the second power supply signal line ELVDD have fixed signals and are used to realize a shielding function, so that the reset signal line Vref can shield the emission signal line EM and the second type scanning signal line 1102 located on both sides of the reset signal line Vref and having alternating high-level and low-level signals, and the second power supply signal line ELVDD can shield the first type scanning signal line 1101 and the second type scanning signal line 1102 located on both sides of the second power supply signal line ELVDD and having alternating high-level and low-level signals, thereby avoiding signal crosstalk.

[0123] In the above embodiment, the first power supply signal line ELVSS in the first wiring region 112 and the first power supply signal line ELVSS in the second wiring region 113 are electrically connected to each other, so that the first power supply signal line ELVSS can form a mesh-like structure as a whole, thereby reducing the resistance.

[0124] In one possible embodiment, in the first wiring region 112, the orthogonal projection of the first power supply signal line ELVSS on the substrate 10 covers the orthogonal projection of the scan signal line Scan, the reset signal line Vref, and the light emission signal line EM on the substrate 10. For example, in the first wiring region 112, the orthogonal projection of one or more of the scan signal line Scan, the reset signal line Vref, and the light emission signal line EM on the substrate 10 overlaps with the orthogonal projection of the first power supply signal line ELVSS on the substrate 10. For example, in the first wiring region 112, the orthogonal projection of one or more of the scan signal line Scan, the reset signal line Vref, and the light emission signal line EM on the substrate 10 is located within the orthogonal projection of the first power supply signal line ELVSS on the substrate 10.

[0125] In the second wiring region 113, the orthogonal projection of the first power supply signal line ELVSS on the substrate 10 covers the orthogonal projection of the data line Data and the second power supply signal line ELVDD on the substrate 10.

[0126] In the above embodiment, all other signal lines are arranged below the first power signal line ELVSS and are covered by the first power signal line ELVSS. By stacking the other signal lines below the first power signal line ELVSS, the light-shielding areas of the other signal lines and the first power signal line ELVSS can overlap, thereby increasing the area of ​​the display panel 1 that is not shielded by the film layer in the pixel circuit layer 11 and improving light transmittance. On the other hand, the shielding effect can be improved by providing another conductive layer on the side of the light-emitting layer 12 away from the pixel circuit layer 11, and the first power signal line ELVSS can provide a shielding effect for the signal lines in the pixel circuit layer 11 and the signal lines in the other conductive layers. Furthermore, the display uniformity of the display panel 1 can be improved, with only uniformly distributed reflection from the first power signal line ELVSS.

[0127] In one possible embodiment, as shown in FIG. 10, in the first wiring region 112, the orthogonal projection of the reset signal line Vref on the substrate 10 and the orthogonal projection of the first power supply signal line ELVSS on the substrate 10 at least partially overlap, for example, overlap.

[0128] In the above embodiment, the reset signal line Vref has a fixed signal and is used to achieve a shielding function. Therefore, the reset signal line Vref shields the scan signal line Scan and the emission signal line EM, which are located on both sides of the reset signal line Vref and have alternating high and low signals, thereby preventing signal crosstalk. The reset signal line Vref is designed to have a relatively wide line width, which improves the signal shielding effect. Furthermore, the orthogonal projection of the reset signal line Vref on the substrate 10 at least partially overlaps with the orthogonal projection of the first power supply signal line ELVSS on the substrate 10, for example, overlapping each other. This allows the reset signal line Vref to be designed with a wide line width without creating a new light-shielding area. This means that the light-shielding area remains the same as the light-shielding area of ​​the first power supply signal line ELVSS, improving the light transmittance.

[0129] In one possible embodiment, the second power supply signal line ELVDD in the first wiring region 112 is electrically connected to the second power supply signal line ELVDD in the second wiring region 113. The second power supply signal line ELVDD may form a mesh-like structure as a whole, thereby reducing resistance.

[0130] 12 , in one possible embodiment, the first-type scanning signal line 1101 includes a first sub-scanning line Scan1 and a second sub-scanning line Scan2, where the first sub-scanning line Scan1 and the second sub-scanning line Scan2 are provided on the same layer, and the orthogonal projection of the first sub-scanning line Scan1 on the substrate 10 is outside the orthogonal projection of the second sub-scanning line Scan2 on the substrate 10. That is, the orthogonal projection of the first sub-scanning line Scan1 on the substrate 10 does not overlap with the orthogonal projection of the second sub-scanning line Scan2 on the substrate 10. Providing the first sub-scanning line Scan1 and the second sub-scanning line Scan2 on the same layer can reduce wiring space. Since the orthogonal projections of the first sub-scanning line Scan1 and the second sub-scanning line Scan2 on the substrate 10 do not overlap, that is, the first sub-scanning line Scan1 and the second sub-scanning line Scan2 can be provided with an interval between them, thereby reducing signal interference therebetween.

[0131] 12 , in one possible embodiment, the second-type scanning signal line 1102 includes a third sub-scan line Scan3 and a fourth sub-scan line Scan4, where the third sub-scan line Scan3 and the fourth sub-scan line Scan4 are provided on the same layer, and the orthogonal projection of the third sub-scan line Scan3 on the substrate 10 is outside the orthogonal projection of the fourth sub-scan line Scan4 on the substrate 10. That is, the orthogonal projection of the third sub-scan line Scan3 on the substrate 10 does not overlap with the orthogonal projection of the fourth sub-scan line Scan4 on the substrate 10. Providing the third sub-scan line Scan3 and the fourth sub-scan line Scan4 on the same layer can reduce wiring space. Since the orthogonal projections of the third sub-scan line Scan3 and the fourth sub-scan line Scan4 on the substrate 10 do not overlap, that is, the third sub-scan line Scan3 and the fourth sub-scan line Scan4 are provided at an interval, signal interference between them can be reduced.

[0132] Optionally, as shown in FIG. 15, the display panel includes a pixel circuit, which includes some or all of the first transistor T1 to the eighth transistor T8 and a storage capacitor Cst.

[0133] Specifically, each transistor has a control terminal, a first pole, and a second pole. The control terminal is used to control whether the first pole and the second pole are conductive. The storage capacitor Cst includes opposing first and second pole plates. The first sub-scanning line Scan1 is connected to the control terminal of the seventh transistor T7. The first sub-scanning line Scan1 is connected to the control terminal of the eighth transistor T8. The first pole of the seventh transistor T7 is connected to the reset signal line Vref. The second pole of the seventh transistor T7 is connected to the first electrode of the light-emitting unit. The first pole of the eighth transistor T8 is connected to the reset signal line Vref. The second pole of the eighth transistor T8 is connected to the second pole or the first pole of the first transistor T1. The eighth transistor T8 is used to reset the second pole or the first pole of the first transistor T1.

[0134] The second sub-scanning line Scan2 is connected to the control terminal of the second transistor T2, the first electrode of the second transistor T2 is connected to the data line Data, and the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1.

[0135] The third sub-scanning line Scan3 is connected to the control terminal of the fourth transistor T4, the first pole of the fourth transistor T4 is connected to the second pole of the first transistor T1 (shown in FIG. 15) or the control terminal of the first transistor T1, and the second pole of the fourth transistor T4 is connected to the reset signal line Vref.

[0136] The fourth sub-scanning line Scan4 is connected to the control terminal of the third transistor T3, the first pole of the third transistor T3 is connected to the control terminal of the first transistor T1, and the second pole of the third transistor T3 is connected to the second pole of the first transistor T1.

[0137] The light-emitting signal line EM is connected to the control terminals of the fifth transistor T5 and the sixth transistor T6, and a first electrode of the fifth transistor T5 is connected to the second power supply signal line ELVDD. A first electrode of the capacitor Cst is connected to the second power supply signal line ELVDD. A second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1. A first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1, and a second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting unit. A second electrode (e.g., a cathode) of the light-emitting unit is connected to the first power supply signal line ELVSS.

[0138] Optionally, the first pole of the fourth transistor T4, the first pole of the seventh transistor T7, and the first pole of the eighth transistor T8 are all connected to a reset signal line Vref, and the three may be connected to different reset signal lines Vref, i.e., the three may receive reset signals of different potentials. Specifically, the first pole of the fourth transistor T4 may be connected to the reset signal Vref1, the first pole of the seventh transistor T7 may be connected to the reset signal Vref2, and the first pole of the eighth transistor T8 may be connected to the reset signal Vref3.

[0139] Optionally, of the eight transistors from the first transistor T1 to the eighth transistor T8, T3 and T4 are N-type transistors (i.e., low-temperature polysilicon semiconductor transistors), and the other transistors are all P-type transistors (i.e., metal oxide semiconductor transistors).

[0140] In one possible embodiment, as shown in FIG. 12, in the first wiring region 112, the orthogonal projection of the second power signal line ELVDD on the substrate 10 and the orthogonal projection of the first power signal line ELVSS on the substrate 10 at least partially overlap, for example, overlap.

[0141] In the above embodiment, the second power signal line ELVDD has a fixed signal and is used to achieve a shielding function. Therefore, the second power signal line ELVDD shields the first-type scanning signal line 1101 and the second-type scanning signal line 1102, which are located on both sides of the second power signal line ELVDD and have alternating high-level and low-level signals, thereby preventing signal crosstalk. The second power signal line ELVDD is designed to have a wide line width, specifically, the line width of the second power signal line ELVDD is designed to be equal to the line width of the first power signal line ELVSS. This improves the shielding effect of the second power signal line ELVDD against signals. Furthermore, the orthogonal projection of the second power signal line ELVDD on the substrate 10 and the orthogonal projection of the first power signal line ELVSS on the substrate 10 at least partially overlap, for example, the overlapping of the second power signal line ELVDD widens the line width without creating a new light-shielding area. That is, the light-shielding area remains the same as the light-shielding area of ​​the first power signal line ELVSS, thereby improving the light transmittance.

[0142] In one possible embodiment, as shown in FIG. 12 , the spacing between the orthogonal projections of the first sub-scanning line Scan1 and the second sub-scanning line Scan2 on the substrate 10 is 1.5 μm or more and 2.5 μm or less. By keeping the spacing between the first scan line Scan10 and the second scan line Scan20 within this range, a fixed pitch can be maintained between them, reducing crosstalk between them. Meanwhile, the spacing between them is prevented from being too large, which would increase the light-blocking area and affect the light transmittance. For example, the spacing between the orthogonal projections of the first sub-scanning line Scan1 and the second sub-scanning line Scan2 on the substrate 10 may be 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, or 2.5 μm.

[0143] In one possible embodiment, as shown in FIG. 12 , the spacing between the orthogonal projections of the third sub-scanning line Scan3 and the fourth sub-scanning line Scan4 on the substrate 10 is 1.5 μm or more and 2.5 μm or less. By keeping the spacing between the third and fourth scan lines within this range, a fixed pitch can be maintained between them, reducing crosstalk between them. Meanwhile, a pitch that is too large can be avoided, which would increase the light-blocking area and affect the light transmittance. For example, the spacing between the orthogonal projections of the third sub-scanning line Scan3 and the fourth sub-scanning line Scan4 on the substrate 10 can be 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, or 2.5 μm.

[0144] 12 , in one possible embodiment, the orthogonal projections of the first type scanning signal lines 1101 and the second type scanning signal lines 1102 on the substrate 10 partially overlap in the first wiring region 112. In the first wiring region 112, the orthogonal projections of the first type scanning signal lines 1101 and the second type scanning signal lines 1102 on the substrate 10 do not partially overlap but are arranged offset from each other.

[0145] Specifically, the first type scanning signal line 1101 is connected to a P-type transistor. The second type scanning signal line 1102 is connected to an N-type transistor. The first type scanning signal line 1101 is connected to a polysilicon semiconductor transistor, and the second type scanning signal line 1102 is connected to an oxide semiconductor transistor. The orthogonal projections of the first type scanning signal line 1101 and the second type scanning signal line 1102 on the substrate 10 are offset from each other, thereby increasing the minimum distance between them and further reducing interference.

[0146] 4, 12 and 13, the repeat unit 120 includes a first light-emitting unit 1201, a second light-emitting unit 1202 and a third light-emitting unit 1203, and the colors of the lights emitted from the first light-emitting unit 1201, the second light-emitting unit 1202 and the third light-emitting unit 1203 are different. Furthermore, the pixel circuit connected to the first light-emitting unit 1201 is electrically connected to the first data line Data1, the pixel circuit connected to the second light-emitting unit 1202 is electrically connected to the second data line Data2, and the pixel circuit connected to the third light-emitting unit 1203 is electrically connected to the third data line Data3.

[0147] For example, FIGS. 12 and 13 show the pixel arrangement according to FIG. 4 of an embodiment of the present application, and also show the stacking configuration of multiple wirings 110 corresponding to the first wiring region 112 and the second wiring region 113 when the pixel circuit is an 8T1C circuit.

[0148] Specifically, as shown in FIG. 13, the data lines Data include a first data line Data1, a second data line Data2, and a third data line Data3, the first data line Data1 and the second data line Data2 being provided in the same layer and spaced apart, the third data line Data3 being located on the side of the first data line Data1 facing the first power supply signal line ELVSS, the second wiring region 113 further including a reset signal line Vref, the reset signal line Vref and the third data line Data3 being provided in the same layer and spaced apart.

[0149] Specifically, by installing the first data line Data1, the second data line Data2, the third data line Data3 and the reset signal line Vref separately on both layers, the wiring space can be increased, which makes wiring easier and enables space saving of wiring while satisfying wiring requirements.

[0150] In the above embodiment, the orthogonal projections of the first data line Data1 and the third data line Data3 on the substrate 10 at least partially overlap, for example, completely overlap. The orthogonal projections of the second data line Data2 and the reset signal line Vref on the substrate 10 at least partially overlap, for example, completely overlap. As a result, assuming that the line width of the first power supply signal line ELVSS is fixed, the line width of the data line Data is increased to reduce the resistance within the data line Data.

[0151] In one possible embodiment, the reset signal line Vref in the first wiring region 112 and the reset signal line Vref in the second wiring region 113 are electrically connected, so that the reset signal line Vref forms a mesh-like structure overall, thereby reducing resistance. In one possible embodiment, the reset signal line Vref in the first wiring region 112 and the reset signal line Vref in the second wiring region 113 are insulated and connected to different transistors in the pixel circuit.

[0152] In the above embodiment, the line widths of the first data line Data1 and the second data line Data2 are 2 μm or more and 3 μm or less. Assuming that the wiring space is fixed, the line width of the data line Data can be increased to reduce the resistance of the data line Data. The spacing between the first data line Data1 and the second data line Data2 is 2 μm or more and 3 μm or less. By keeping the spacing between the first data line Data1 and the second data line Data2 within the above range, a fixed pitch can be maintained between the two lines, reducing crosstalk between them. At the same time, a pitch that is too large can be avoided, which would increase the light-shielding area and affect the light transmittance. For example, the spacing between the third data line Data3 and the reset signal line Vref is 2 μm or more and 3 μm or less. By keeping the spacing between the third data line Data3 and the reset signal line Vref within the above range, a fixed pitch can be maintained between the two lines, reducing crosstalk between them. At the same time, a pitch that is too large can be avoided, which would increase the light-shielding area and affect the light transmittance. For example, the line width of the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm. For example, the distance between the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm. For example, the distance between the third data line Data3 and the reset signal line Vref may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm.

[0153] In one possible embodiment, as shown in Figures 11, 12, 14a and 14b, the repeat unit 120 includes two subunits arranged along the second direction y, and the subunits include a first light-emitting unit 1201, a second light-emitting unit 1202, a third light-emitting unit 1203 and a fourth light-emitting unit 1204, and the colors of the lights emitted from the first light-emitting unit 1201, the second light-emitting unit 1202 and the third light-emitting unit 1203 are different, and the colors of the lights emitted from the second light-emitting unit 1202 and the fourth light-emitting unit 1204 are the same.

[0154] In the above embodiment, one repeat unit 120 may include two subunits, i.e., one repeat unit 120 may include eight light-emitting units, and each subunit may include four light-emitting units. Specifically, the four light-emitting units may be arranged along the first direction x. Here, the subunits include a first light-emitting unit 1201, a second light-emitting unit 1202, a third light-emitting unit 1203, and a fourth light-emitting unit 1204 arranged along the first direction x. The first light-emitting unit 1201 may be a red light-emitting unit, the second light-emitting unit 1202 may be a green light-emitting unit, the third light-emitting unit 1203 may be a blue light-emitting unit, and the fourth light-emitting unit 1204 may be a green light-emitting unit. Here, each subunit may simultaneously utilize the light-emitting units to form four white dots, thereby improving the display effect. Here, the arrangement order of the light-emitting units in two subunits may be different.

[0155] Optionally, the repeating unit 120 includes a first subunit and a second subunit arranged along the second direction y, the first subunit including a first light-emitting unit 1201, a second light-emitting unit 1202, a third light-emitting unit 1203, and a fourth light-emitting unit 1204 arranged in order along the first direction x, and the second subunit including a third light-emitting unit 1203, a second light-emitting unit 1202, a first light-emitting unit 1201, and a fourth light-emitting unit 1204 arranged in order along the first direction x, so that the first light-emitting unit 1201 and the third light-emitting unit 1203 are arranged opposite each other along the second direction y, thereby improving the light mixing effect.

[0156] Here, Figures 12, 14a and 14b show the pixel arrangement form according to Figure 11 of an embodiment of the present application, and also show the stacking form of multiple wirings 110 corresponding to the first wiring region 112 and the second wiring region 113 when the pixel circuit is an 8T1C circuit.

[0157] Optionally, in the second wiring region 113, the data lines Data include a first data line Data1, a second data line Data2, a third data line Data3, and a fourth data line Data4, the first data line Data1 and the second data line Data2 being arranged in the same layer and spaced apart, the third data line Data3 and the fourth data line Data4 being arranged in the same layer and spaced apart, and the third data line Data3 being located on the side of the first data line Data1 facing the first power signal line ELVSS.

[0158] According to the pixel arrangement pattern inside the display panel 1, the second wiring region 113 may be provided with four data lines, each corresponding to a different light-emitting unit and capable of controlling the driving of the different light-emitting units.

[0159] In the above embodiment, the first data line Data1, the second data line Data2, the third data line Data3, and the fourth data line Data4 are installed separately on both layers, thereby increasing the wiring space, making wiring easier and achieving space saving for wiring while satisfying wiring requirements.

[0160] In the above embodiment, the orthogonal projections of the first data line Data1 and the third data line Data3 on the substrate 10 at least partially overlap, for example, completely overlap. The orthogonal projections of the second data line Data2 and the fourth data line Data4 on the substrate 10 at least partially overlap, for example, completely overlap. As a result, assuming that the line width of the first power supply signal line ELVSS is fixed, the line width of the data line Data is increased to reduce the resistance within the data line Data.

[0161] In one possible embodiment, the pixel circuits connected to the light-emitting units in the first column of the repeat unit 120 are electrically connected to the first data line Data1, the pixel circuits connected to the light-emitting units in the second column of the repeat unit 120 are electrically connected to the second data line Data2, the pixel circuits connected to the light-emitting units in the third column of the repeat unit 120 are electrically connected to the third data line Data3, and the pixel circuits connected to the light-emitting units in the fourth column of the repeat unit 120 are electrically connected to the fourth data line Data4, and the second direction y is parallel to the column direction.

[0162] Here, four columns of light-emitting units are provided in a single repeat unit 120, and the number of light-emitting units in each column is usually determined by the number of sub-units in the repeat unit 120. For example, if two sub-units are provided in a single repeat unit 120, each column in the single repeat unit 120 includes two light-emitting units. Furthermore, the number of data lines Data corresponding to the single repeat unit 120 is four, and the four data lines Data are corresponding to pixel circuits connected to light-emitting units in different columns.

[0163] Furthermore, a single subunit includes four light-emitting units, and pixel circuits connected to the four light-emitting units are respectively connected to different data lines, and the four data lines respectively control driving of pixel circuits connected to different light-emitting units in the single subunit. Furthermore, different subunits may be arranged side by side in the second direction y, and pixel circuits connected to adjacent light-emitting units in the different subunits in the second direction y may be connected to the same data line, so that the same data line can simultaneously control pixel circuits connected to multiple light-emitting units arranged in the second direction y.

[0164] In the above embodiment, the line widths of the first data line Data1 and the second data line Data2 are 2 μm or more and 3 μm or less, thereby increasing the line width of the data line Data and reducing the resistance of the data line Data, assuming that the wiring space is fixed. The spacing between the first data line Data1 and the second data line Data2 is 2 μm or more and 3 μm or less. By keeping the spacing between the first data line Data1 and the second data line Data2 within the above range, a fixed pitch can be maintained between the two lines, reducing crosstalk between them, while avoiding an excessively large pitch between them, which would increase the light-blocking area and affect the light transmittance. For example, the spacing between the third data line Data3 and the fourth data line Data4 is 2 μm or more and 3 μm or less. By keeping the spacing between the third data line Data3 and the fourth data line Data4 within the above range, a fixed pitch can be maintained between the two lines, reducing crosstalk between them, while avoiding an excessively large pitch between them, which would increase the light-blocking area and affect the light transmittance. For example, the line width of the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm. For example, the distance between the first data line Data1 and the second data line Data2 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm. For example, the distance between the third data line Data3 and the fourth data line Data3 may be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm.

[0165] In one possible embodiment, as shown in FIG. 2, the pixel circuit layer 11 includes a first conductive layer 114, a second conductive layer 115, a sixth conductive layer 119, a third conductive layer 116, a fourth conductive layer 117, a seventh conductive layer 121, and a fifth conductive layer 118, which are stacked in order along a direction away from the substrate 10.

[0166] In the first wiring region 112, a first type scanning signal line 1101 is formed on a first conductive layer 114, a second power supply signal line ELVDD is formed on a second conductive layer 115, a second type scanning signal line 1102 is formed on a sixth conductive layer 119, a reset signal line Vref is formed on a third conductive layer 116, an emission signal line EM is formed on a fourth conductive layer 117, and a first power supply signal line ELVSS is formed on a fifth conductive layer 118.

[0167] In the second wiring region 113, the second power signal line ELVDD is formed on the seventh conductive layer 121, the first data line Data1 and the second data line Data2 are formed on the third conductive layer 116, and the third data line Data3 is formed on the fourth conductive layer 117.

[0168] In the above embodiment, in the drive circuit region 111 and / or the second display region AA2, the first conductive layer 114 is used to form the gate of a transistor (e.g., a polysilicon semiconductor transistor), the second conductive layer 115 is used to form the bottom gate of a transistor (e.g., an oxide semiconductor transistor), the third conductive layer 116 is used to form the source / drain of the transistor, the fourth conductive layer 117 is used to form the wiring 110, and the fifth conductive layer 118 is used to form a partition structure. The sixth conductive layer 119 is used to form the top gate of the oxide semiconductor transistor. The seventh conductive layer 121 is used to form the wiring 110. An insulating layer may be provided between adjacent conductive layers. The conductive layers may include a metal layer, an indium tin oxide layer, etc.

[0169] Specifically, the fifth conductive layer 118 may be provided on the side of the light-emitting layer 12 away from the substrate 10, and may be used, for example, to transfer a first low-level signal, and therefore may be part of the pixel circuit layer 11. Specifically, the fifth conductive layer 118 may include a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in a direction away from the substrate 10. The fifth conductive layer 118 may include a first partition section and a second partition section stacked in a direction away from the substrate 10, and the orthogonal projection of the first partition section on the substrate 10 is located within the orthogonal projection of the second partition section on the substrate 10.

[0170] Optionally, the light-emitting unit 1200 includes a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate 10. The second electrode may be electrically connected to the partition structure. A step portion formed between the first partition and the second partition can separate the light-emitting functional layer and the second electrode in the light-emitting unit 1200. This allows different light-emitting units 1200 to be isolated from each other, reducing crosstalk between adjacent light-emitting units 1200 and improving display performance. Furthermore, adjacent light-emitting units 1200 can be packaged independently, thereby improving packaging yield. At the same time, the partition structure allows the light-emitting functional layer and second electrode in each light-emitting unit 1200 of each color in the display panel 1 to be fabricated on the entire surface and then patterned, eliminating the need for a mask and reducing the manufacturing cost of the display panel 1.

[0171] Specifically, the third conductive layer 116 includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in a direction away from the substrate 10, and the fourth conductive layer 117 includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in a direction away from the substrate 10. The material of the sixth conductive layer 119 may be titanium or molybdenum.

[0172] 2, the display panel further includes a partition structure G, which includes a first partition section G1 and a second partition section G2 stacked in order along a direction away from the substrate 10, the orthogonal projection of the first partition section G1 on the substrate 10 being located within the orthogonal projection of the second partition section G2 on the substrate 10, and the area of ​​the orthogonal projection of the first partition section G1 on the substrate 10 being smaller than the area of ​​the orthogonal projection of the second partition section G2 on the substrate 10. For example, the cross section of the partition structure G may be T-shaped.

[0173] For reference, related technical solutions of the partition structure G are described in Patent PCT / CN2023 / 134518, Patent No. 202310759370.2, Patent No. 202310740412.8, Patent No. 202310707209.0, and Patent No. 202311346196.5, the contents of which are incorporated herein by reference and will not be repeated in this embodiment. The partition structure G defines a plurality of partition openings, and the installation of the partition structure can form a plurality of spaced apart light-emitting units of various colors and corresponding second electrodes of the light-emitting units without the need for precision metal masks, thereby reducing the manufacturing costs of the display panel.

[0174] Optionally, the wiring includes a first power supply signal line ELVSS, and at least a part of the partition structure also functions as the first power supply signal line ELVSS. Optionally, the first partition portion also functions as the first power supply signal line ELVSS.

[0175] 16, the partition structure G may optionally include a third partition G3 located between the substrate 10 and the first partition G1. The orthogonal projection of the first partition G1 on the substrate 10 is located within the orthogonal projection of the third partition G3 on the substrate 10, and the area of ​​the orthogonal projection of the first partition G1 on the substrate 10 is smaller than the area of ​​the orthogonal projection of the third partition G3 on the substrate 10. For example, the cross section of the partition structure G may be U-shaped. In the first wiring region and / or the second wiring region, at least one of the first partition G1, the second partition G2, and the third partition G3 may also function as the first power supply signal line ELVSS.

[0176] In the above technical form, the light-emitting region includes a plurality of light-emitting units, and at least a part of the partition structure G is located between the light-emitting units.

[0177] In the above technical form, the light-emitting unit includes a first electrode (e.g., an anode), a light-emitting functional layer, and a second electrode (e.g., a cathode) stacked in a direction away from the substrate 10, and the second electrode is electrically connected to the partition structure. The first electrode and the second electrode jointly drive the light-emitting functional layer to emit light and meet the display requirements of the display panel. One of the first electrode and the second electrode of the light-emitting unit may be an anode, and the other may be a cathode.

[0178] In a second aspect, an embodiment of the present application further provides a display panel 1, which includes a first display area AA1, which includes a first area A1, and which includes a substrate 10, wiring 110 located on the substrate 10, and a partition structure G. The first area A1 includes at least one wiring area, and a plurality of wirings 110 in the at least one wiring area are stacked and insulated along a direction perpendicular to the substrate 10. The plurality of wirings 110 include at least one of a data line Data, a scanning signal line Scan, a reset signal line Vref, an emission signal line EM, a second power supply signal line ELVDD, and a first power supply signal line ELVSS.

[0179] At least a part of the partition structure G also functions as the first power supply signal line ELVSS, and in at least one wiring region, at least one type of line selected from the data line Data, the scanning signal line Scan, the reset signal line Vref, the light emitting signal line EM, and the second power supply signal line ELVDD, and at least a part of the partition structure G that also functions as the first power supply signal line ELVSS, are stacked and insulated along a direction perpendicular to the substrate 10.

[0180] In the embodiment of the present application, the wirings 110 in the wiring region are stacked in a direction perpendicular to the substrate 10. This causes the orthogonal projections of the multiple wirings 110 in the wiring region onto the substrate 10 to at least partially overlap, thereby reducing the orthogonal projection area of ​​the wiring region on the substrate 10. Furthermore, the area of ​​the portion of the display panel 1 that is not blocked by the wiring region can be increased, thereby improving the light transmittance of the display panel 1. Furthermore, at least one of the data lines Data, the scanning signal lines Scan, the reset signal line Vref, the emission signal line EM, and the second power supply signal line ELVDD is stacked in a direction perpendicular to the substrate 10 and insulated from at least a portion of the partition structure G, which also functions as the first power supply signal line ELVSS. This allows the partition structure G to shield some of the wirings 110, thereby improving the light transmittance of the display panel 1.

[0181] In some embodiments, at least one wiring region includes a first wiring region 112, in which the wiring in the first wiring region 112 is stacked along a direction perpendicular to the substrate 10, the wiring in the first wiring region 112 extends along a first direction x, and in the first wiring region 112, at least one of the data line Data, the scanning signal line Scan, the reset signal line Vref, the emission signal line EM, and the second power supply signal line ELVDD, and at least a part of the partition structure G, which also serves as the first power supply signal line ELVSS, are stacked along a direction perpendicular to the substrate 10 and are provided in an insulated manner.

[0182] And / or, at least one wiring region includes a second wiring region 113, the wiring 110 in the second wiring region 113 is stacked along a direction perpendicular to the substrate 10, the wiring in the second wiring region 113 extends along the second direction y, and in the second wiring region 113, at least one type of data line Data, scanning signal line Scan, reset signal line Vref, light emitting signal line EM, second power supply signal line ELVDD, and at least a part of the partition structure G that also functions as the first power supply signal line ELVSS are stacked along a direction perpendicular to the substrate and are provided in an insulated manner.

[0183] In some embodiments, the first region further includes a light-emitting region (which may, for example, be located at the same position as the driving circuit region 111 in FIG. 3), and the light-emitting region and the first wiring region 112 are alternately arranged in a first direction x, and / or the light-emitting region and the second wiring region 113 are alternately arranged in a second direction y. The first direction x and the second direction may intersect, for example, be perpendicular.

[0184] The light-emitting regions are provided with light-emitting units to realize light-emitting display functions. The light-emitting regions and the first wiring regions 112 are alternately arranged in the first direction x, i.e., two first wiring regions 112 are provided on both sides of the light-emitting region in the first direction x. Furthermore, the light-emitting regions are provided with corresponding driving circuits for driving the light-emitting display of the light-emitting units, and the wiring 110 in the first wiring regions 112 is electrically connected to the driving circuits to meet the light-emitting needs of the light-emitting units.

[0185] Similarly, the light-emitting regions and the second wiring regions 113 are alternately arranged in the second direction y, that is, two second wiring regions 113 are provided on both sides of the light-emitting region in the second direction y. Furthermore, a driving circuit for driving the light-emitting display of the light-emitting units is provided correspondingly in the light-emitting region, and the wiring 110 in the second wiring region 113 is electrically connected to the driving circuit to meet the light-emitting needs of the light-emitting units.

[0186] In some embodiments, the first display area AA1 further includes a second area A2, and the light transmittance of the first area A1 is smaller than the light transmittance of the second area A2.

[0187] The first display area AA1 includes at least a first area A1 and a second area A2. Wiring is provided in at least one wiring area in the first area A1, and wiring in the second area A2 is reduced or eliminated, thereby making the light transmittance of the first area A1 lower than that of the second area A2. Because the second area A2 has a high light transmittance, a photosensitive module provided on one side of the first display area AA1 can collect or receive light transmitted through the second area A2. Examples of the photosensitive module include a camera module and a fingerprint recognition module. Optionally, the second area A2 is a non-light-emitting area, thereby reducing the influence of the light-emitting unit on the light transmittance of the second area A2 and improving the performance accuracy of the photosensitive module.

[0188] In some embodiments, one or more of a first wiring region 112, a second wiring region 113, and a light emitting region are provided between adjacent second regions A2.

[0189] Combining the drawings, the first wiring region 112, the second wiring region 113, and the light emitting region may form a ring structure surrounding the second region A2. Optionally, the second region A2 and the first wiring region 112 may be alternately arranged in the second direction y, and / or the second region A2 and the second wiring region 113 may be alternately arranged in the first direction x.

[0190] In some embodiments, the partition structure G includes a first partition section G1 and a second partition section G2 stacked in order in a direction away from the substrate 10, the orthogonal projection of the first partition section G1 on the substrate 10 is located within the orthogonal projection of the second partition section G2 on the substrate 10, and the orthogonal projection area of ​​the first partition section G1 on the substrate 10 is smaller than the orthogonal projection area of ​​the second partition section G2 on the substrate 10. For example, the cross section of the partition structure G may be T-shaped.

[0191] 16, the partition structure G may further include a third partition G3 located between the substrate 10 and the first partition G1, the orthogonal projection of the first partition G1 on the substrate 10 being located within the orthogonal projection of the third partition G3 on the substrate 10, and the orthogonal projection area of ​​the first partition G1 on the substrate 10 being smaller than the orthogonal projection area of ​​the third partition G3 on the substrate 10. For example, the cross section of the partition structure G may be U-shaped. Within the first wiring region and / or the second wiring region, at least a portion of the first partition G2, the second partition G2, and the third partition G3 may also function as the first power supply signal line ELVSS.

[0192] This embodiment may be combined with some or all of the features of the above embodiments, which will not be repeated here.

[0193] In the above technical solution, the light-emitting region includes a plurality of light-emitting units, and at least some of the partition structures G are located between the light-emitting units. Furthermore, the partition structures G are formed to surround the partition openings, and at least some of the light-emitting units are located within the partition openings.

[0194] In the above technical solution, the light-emitting unit includes a first electrode (e.g., an anode), a light-emitting functional layer, and a second electrode (e.g., a cathode) stacked in a direction away from the substrate 10, and the second electrode is electrically connected to the partition structure. Here, the first electrode and the second electrode jointly drive the light-emitting functional layer to meet the display needs of the display panel. One of the first electrode and the second electrode of the light-emitting unit may be an anode, and the other may be a cathode.

[0195] The present application further provides a display device 2, as shown in FIG. 17, including a display panel 1 according to any of the above embodiments of the present application.

[0196] The improved light transmittance of the display device 2 allows the photosensitive module in the display device 2 to better receive light, improving the operating efficiency of the photosensitive module. The display device 2 may be, but is not limited to, a mobile terminal such as a mobile phone or a laptop, a fixed terminal such as a television or a computer monitor, or a wearable device such as a watch.

[0197] In one possible embodiment, the display device further includes a photosensitive module, which is provided on a side of the display panel opposite to the light-emitting surface of the first display area.

[0198] In the embodiment of the present application, at least some of the wiring in the first display region is stacked along a direction perpendicular to the substrate 10, so that the orthogonal projections of the wiring in the first display region on the substrate at least partially overlap, thereby making the area of ​​the orthogonal projection of the first display region on the substrate relatively small. Furthermore, the area of ​​the first display region that is not blocked by the wiring is increased, improving the light transmittance of the first display region.

[0199] In addition, by providing the photosensitive module in the first display area, the photosensitive requirements corresponding to the photosensitive module can be met, and the photosensitive accuracy of the display panel can be improved.

[0200] According to the above-described embodiments of the present application, these embodiments are not intended to be exhaustive and not to limit the present invention to only the specific embodiments. It is apparent from the above description that many modifications and variations are possible. These embodiments are selected and specifically described herein to better explain the principles and practical applications of the present application, so that those skilled in the art can effectively utilize the present application and make modifications based on the present application. The present application is limited only by the claims, their full scope and equivalents.

[0201] The above specific embodiments do not limit the scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions are possible according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention. [Explanation of symbols]

[0202] 1 Display panel 10 Substrate 11 Pixel circuit layer 111 Drive circuit area 112 1st wiring area 113 2nd wiring area 114 First conductive layer 115 Second conductive layer 116 Third conductive layer 117 Fourth conductive layer 118 5th conductive layer 119 6th conductive layer 120 7th conductive layer 110 Wiring Data line Scan signal line Vref reset signal line EM light emitting signal line ELVSS 1st power supply signal line ELVDD Second power supply signal line Data1 First data line Data2 Second data line Data3 Third data line Data4 4th data line 1101 First type scanning signal line 1102 Second type scanning signal line Scan1 First sub-scan line Scan2 Second sub-scan line Scan3 Third sub-scan line Scan4 4th sub-scan line 12 Light-emitting layer 120 repeat units 1201 First Light Emitting Unit 1202 Second Light Emitting Unit 1203 Third Light Emitting Unit 1204 4th Light Emitting Unit x 1st direction y second direction z thickness direction 2 Display device AA1 1st display area AA2 2nd display area A1 1st area A2 2nd area G Partition structure G1 First partition G2 Second partition G3 Third partition

Claims

1. A display panel, the display panel includes a first display area, the first display area includes a first area, and the display panel includes a substrate and wiring located on the substrate; the first region includes at least one wiring region, and the plurality of wirings in the at least one wiring region are stacked along a direction perpendicular to the substrate and are provided in an insulated manner; A display panel characterized by:

2. the at least one wiring region includes a first wiring region, the plurality of wirings in the first wiring region are stacked and insulated along a direction perpendicular to the substrate, and the wirings in the first wiring region extend along a first direction; and / or the at least one wiring region includes a second wiring region, the plurality of wirings in the second wiring region are stacked and insulated along a direction perpendicular to the substrate, the wirings in the second wiring region extend along a second direction, and the first direction and the second direction intersect, the first region further includes a light-emitting region, and the light-emitting region and the first wiring region are alternately arranged in the first direction, and / or the light-emitting region and the second wiring region are alternately arranged in the second direction; and / or the first display region further includes a second region, and the light transmittance of the first region is smaller than the light transmittance of the second region; one or more of the first wiring region, the second wiring region, and the light emitting region are provided between adjacent second regions; the second regions and the first wiring regions are alternately arranged in the second direction, and / or the second regions and the second wiring regions are alternately arranged in the first direction, the second region is a non-light-emitting region; 2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

3. the first wiring region includes shield wiring and a plurality of potential change signal lines, the shield wiring is provided between the potential change signal lines along a direction perpendicular to the substrate, the shield wiring includes a reset signal line and / or a power supply signal line, and the potential change signal lines include a scanning signal line and / or a light emission signal line; In the first wiring region, the reset signal line is provided between the scanning signal line and the light-emitting signal line along a direction perpendicular to the substrate, In the first wiring region, the plurality of scanning signal lines are located in at least two conductive layers, the first wiring region further includes a second power supply signal line, and the second power supply signal line is provided between adjacent scanning signal lines in the first wiring region along a direction perpendicular to the substrate; 3. The display panel according to claim 2.

4. the second wiring region includes a plurality of data lines, the plurality of data lines being located on at least two conductive layers; In the second wiring region, the plurality of data lines are stacked and insulated along a direction perpendicular to the substrate, the first wiring region includes a first power supply signal line, the second wiring region includes a first power supply signal line, the first power supply signal line in the first wiring region and the first power supply signal line in the second wiring region are electrically connected to each other; the first wiring region includes a second power supply signal line, the second wiring region includes a second power supply signal line, and the second power supply signal line in the first wiring region and the second power supply signal line in the second wiring region are electrically connected to each other; 3. The display panel according to claim 2.

5. The display panel further comprises: a pixel circuit layer including a driving circuit region located in the first region, a first wiring region, and a second wiring region, each of the first wiring region and the second wiring region including a plurality of the wirings, the wirings in the first wiring region being stacked and insulated along a direction perpendicular to the substrate, and the wirings in the second wiring region being stacked and insulated along a direction perpendicular to the substrate; a light-emitting layer including a plurality of repeat units located in the first region, the repeat units including light-emitting units of at least three colors, and the repeat units located on a side of the driving circuit region away from the substrate; the drive circuit regions adjacent to each other along a first direction are connected via the wiring located in the first wiring region, and the drive circuit regions adjacent to each other along a second direction are connected via the wiring located in the second wiring region; The repeat unit and the drive circuit region correspond one-to-one.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

6. the wiring includes a data line, a scanning signal line, a reset signal line, a light-emitting signal line, a first power supply signal line, and a second power supply signal line; the first wiring region includes the scanning signal line, the reset signal line, the light-emitting signal line, and the first power supply signal line, which are stacked in order along a direction away from the substrate; the first wiring region further includes a second power supply signal line, and the second power supply signal line and the light-emitting signal line are provided in the same layer; the second wiring region includes the data lines and first power supply signal lines that are stacked in order along a direction away from the substrate, the first power supply signal lines in the first wiring region and the first power supply signal lines in the second wiring region are electrically connected; in the first wiring region, an orthogonal projection of the first power supply signal line on the substrate covers an orthogonal projection of the scanning signal line, the reset signal line, the light-emitting signal line, and the second power supply signal line on the substrate; and in the second wiring region, an orthogonal projection of the first power supply signal line on the substrate covers an orthogonal projection of the data line on the substrate; In the first wiring region, an orthogonal projection of the reset signal line on the substrate and an orthogonal projection of the first power supply signal line on the substrate overlap with each other.

6. The display panel according to claim 5.

7. the scanning signal lines include first scanning lines and second scanning lines, the first scanning lines and the second scanning lines are provided in different layers, and an orthogonal projection of the first scanning lines on the substrate is positioned outside an orthogonal projection of the second scanning lines on the substrate; In the first wiring region, a distance between adjacent first scanning lines and adjacent second scanning lines in orthogonal projection on the substrate is 0.5 μm or more and 2.5 μm or less; In the first wiring region, the second power supply signal line and the light-emitting signal line are provided in the same layer, and the interval between the second power supply signal line and the light-emitting signal line is 0.5 μm or more and 2.5 μm or less.

7. The display panel according to claim 6, wherein the first and second electrodes are arranged parallel to each other.

8. the data lines include first data lines, second data lines, and third data lines, and in the second wiring region, the first data lines and the second data lines are provided in the same layer and spaced apart, and the third data lines are provided in a layer different from that of the first data lines; the third data line is located on a side of the first data line facing the first power signal line or on a side of the first data line facing away from the first power signal line, the second wiring region further includes a second power supply signal line, the second power supply signal line and the third data line are provided in the same layer and spaced apart from each other, or the second power supply signal line is located on a side of the data line facing the first power supply signal line or on a side of the data line facing away from the first power supply signal line; orthogonal projections of the first data line and the third data line on the substrate overlap each other, and / or the second power supply signal line is provided in the same layer as the third data line and is spaced apart from the third data line, and orthogonal projections of the second data line and the second power supply signal line on the substrate overlap each other; the repeating unit includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit, and colors of lights emitted from the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are different from each other; a pixel circuit connected to the first light-emitting unit is electrically connected to the first data line; a pixel circuit connected to the second light-emitting unit is electrically connected to the second data line; and a pixel circuit connected to the third light-emitting unit is electrically connected to the third data line; In the second wiring region, an orthogonal projection of the first power supply signal line on the substrate covers an orthogonal projection of the data line and the second power supply signal line on the substrate; the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less; 8. The display panel according to claim 7,

9. the pixel circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are stacked in order along a direction away from the substrate, In the first wiring region, the first scanning line is formed in the first conductive layer, the second scanning line is formed in the second conductive layer, the reset signal line is formed in the third conductive layer, the light emitting signal line is formed in the fourth conductive layer, and the first power supply signal line is formed in the fifth conductive layer; In the second wiring region, the first data line and the second data line are formed on the third conductive layer, and the second power supply signal line and the third data line are formed on the fourth conductive layer; or the first data line and the second data line are formed on the fourth conductive layer, and the second power supply signal line and the third data line are formed on the third conductive layer; or the first data line and the second data line are formed on the third conductive layer, the third data line is formed on the fourth conductive layer, and the second power supply signal line is formed on the second conductive layer; or the first data line and the second data line are formed on the fourth conductive layer, the third data line is formed on the third conductive layer, and the second power supply signal line is formed on the second conductive layer; the third conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer that are stacked in this order along a direction away from the substrate, the fourth conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer that are stacked in this order along a direction away from the substrate, In the first wiring region, a second power supply signal line is located in a fourth conductive layer; the second power supply signal line in the first wiring region and the second power supply signal line in the second wiring region are electrically connected to each other; 9. The display panel according to claim 8.

10. In the second wiring region, the data lines include a first data line, a second data line, a third data line, and a fourth data line, the first data line and the second data line are provided in the same layer and spaced apart, the third data line and the fourth data line are provided in the same layer and spaced apart, and the third data line is located on a side of the first data line facing the first power supply signal line, orthogonal projections of the first data line and the third data line on the substrate overlap, and orthogonal projections of the second data line and the fourth data line on the substrate overlap, a second power supply signal line is further included in the second wiring region, and the second power supply signal line is located on a side of the third data line facing the first power supply signal line, or the second power supply signal line is located on a side of the first data line facing away from the first power supply signal line; the repeating unit includes a first subunit and a second subunit arranged along the second direction, the first subunit includes a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit arranged in order along the first direction, the second subunit includes a third light-emitting unit, a second light-emitting unit, a first light-emitting unit, and a fourth light-emitting unit, which are sequentially arranged along a first direction; the colors of the lights emitted from the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are different, and the colors of the lights emitted from the second light-emitting unit and the fourth light-emitting unit are the same; pixel circuits connected to the light-emitting units in the first column of the repeat unit are electrically connected to the first data line; pixel circuits connected to the light-emitting units in the second column of the repeat unit are electrically connected to the second data line; pixel circuits connected to the light-emitting units in the third column of the repeat unit are electrically connected to the third data line; pixel circuits connected to the light-emitting units in the fourth column of the repeat unit are electrically connected to the fourth data line; and the second direction is parallel to the column direction; the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less; 8. The display panel according to claim 7,

11. the wiring includes a data line, a scanning signal line, a reset signal line, a light-emitting signal line, a first power supply signal line, and a second power supply signal line; the first wiring region includes the scanning signal line, the second power supply signal line, the reset signal line, the light-emitting signal line, and the first power supply signal line, which are stacked along a direction away from the substrate; the scanning signal lines include first type scanning signal lines and second type scanning signal lines provided in different layers, and the second power supply signal lines are provided between the first type scanning signal lines and the second type scanning signal lines along a direction perpendicular to the substrate; the reset signal line is provided between the light-emitting signal line and the second-type scanning signal line along a direction perpendicular to the substrate; the data line, the second power supply signal line, and the first power supply signal line are provided in the second wiring region and are stacked in this order along a direction away from the substrate; the first power supply signal line in the first wiring region is electrically connected to the first power supply signal line in the second wiring region; in the first wiring region, an orthogonal projection of the first power supply signal line on the substrate covers an orthogonal projection of the scanning signal line, the reset signal line, the light-emitting signal line, and the second power supply signal line on the substrate; In the second wiring region, an orthogonal projection of the first power supply signal line on the substrate covers an orthogonal projection of the data line and the second power supply signal line on the substrate; In the first wiring region, an orthogonal projection of the reset signal line on the substrate overlaps with an orthogonal projection of the first power supply signal line on the substrate; the second power supply signal line in the first wiring region and the second power supply signal line in the second wiring region are electrically connected to each other; 6. The display panel according to claim 5.

12. the first type scanning signal lines include first sub-scanning lines and second sub-scanning lines, the first sub-scanning lines and the second sub-scanning lines are provided in the same layer, and an orthogonal projection of the first sub-scanning lines on the substrate is positioned outside an orthogonal projection of the second sub-scanning lines on the substrate; and / or the second type scanning signal lines include a third sub-scanning line and a fourth sub-scanning line, the third sub-scanning line and the fourth sub-scanning line are provided in the same layer, and an orthogonal projection of the third sub-scanning line on the substrate is positioned outside an orthogonal projection of the fourth sub-scanning line on the substrate; In the first wiring region, an orthogonal projection of the second power supply signal line on the substrate overlaps with an orthogonal projection of the first power supply signal line on the substrate; a distance between the orthogonal projections of the first sub-scanning line and the second sub-scanning line on the substrate is 1.5 μm or more and 2.5 μm or less; a distance between the third sub-scanning line and the fourth sub-scanning line projected on the substrate is equal to or greater than 1.5 μm and equal to or less than 2.5 μm; In the first wiring region, orthogonal projections of the first type scanning signal lines and the second type scanning signal lines on the substrate partially overlap each other.

12. The display panel according to claim 11.

13. the data lines include a first data line, a second data line, and a third data line, the first data line and the second data line being provided in the same layer and spaced apart, the third data line being located on the side of the first data line facing the first power supply signal line, a reset signal line being further included in the second wiring region, the reset signal line and the third data line being provided in the same layer and spaced apart, the first data line and the third data line are projected on the substrate in a normal projection, and the second data line and the reset signal line are projected on the substrate in a normal projection. the repeating unit includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit, and the colors of the lights emitted from the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are different, and a pixel circuit connected to the first light-emitting unit is electrically connected to the first data line, a pixel circuit connected to the second light-emitting unit is electrically connected to the second data line, and a pixel circuit connected to the third light-emitting unit is electrically connected to the third data line; the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less; 13. The display panel according to claim 12.

14. the data lines include a first data line, a second data line, a third data line, and a fourth data line, the first data line and the second data line being provided in the same layer and spaced apart, the third data line and the fourth data line being provided in the same layer and spaced apart, the third data line being located on a side of the first data line facing the first power supply signal line, orthogonal projections of the first data line and the third data line on the substrate overlap, and orthogonal projections of the second data line and the fourth data line on the substrate overlap; the repeating unit includes a first subunit and a second subunit arranged along the second direction, the first subunit includes a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, and a fourth light-emitting unit arranged in order along the first direction, the second subunit includes a third light-emitting unit, a second light-emitting unit, a first light-emitting unit, and a fourth light-emitting unit, which are sequentially arranged along a first direction; the first light emitting unit, the second light emitting unit, and the third light emitting unit emit lights of different colors, and the second light emitting unit and the fourth light emitting unit emit lights of the same color; the pixel circuits connected to the light emitting units of the first column of the repeat unit are electrically connected to the first data line, the pixel circuits connected to the light emitting units of the second column of the repeat unit are electrically connected to the second data line, the pixel circuits connected to the light emitting units of the third column of the repeat unit are electrically connected to the third data line, and the pixel circuits connected to the light emitting units of the fourth column of the repeat unit are electrically connected to the fourth data line, and the second direction is parallel to the column direction; the line width of the first data line and the second data line is 2 μm or more and 3 μm or less, and the distance between the first data line and the second data line is 2 μm or more and 3 μm or less; 13. The display panel according to claim 12.

15. the pixel circuit layer includes a first conductive layer, a second conductive layer, a sixth conductive layer, a third conductive layer, a fourth conductive layer, a seventh conductive layer, and a fifth conductive layer that are stacked in order along a direction away from the substrate, In the first wiring region, the first type scanning signal line is formed in the first conductive layer, the second power supply signal line is formed in the second conductive layer, the second type scanning signal line is formed in the sixth conductive layer, the reset signal line is formed in the third conductive layer, the light emitting signal line is formed in the fourth conductive layer, and the first power supply signal line is formed in the fifth conductive layer; In the second wiring region, the second power supply signal line is formed on the seventh conductive layer, the first data line and the second data line are formed on the third conductive layer, and the third data line and the fourth data line are formed on the fourth conductive layer; the third conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in this order along a direction away from the substrate, the fourth conductive layer includes a titanium metal layer, an aluminum metal layer, and a titanium metal layer stacked in this order along a direction away from the substrate; 15. The display panel according to claim 14.

16. The display panel further includes a partition structure, the partition structure includes a first partition portion and a second partition portion that are stacked in order along a direction away from the substrate, an orthogonal projection of the first partition portion on the substrate is located within an orthogonal projection of the second partition portion on the substrate, and an area of ​​the orthogonal projection of the first partition portion on the substrate is smaller than an area of ​​the orthogonal projection of the second partition portion on the substrate; the wiring includes a first power supply signal line, and at least a part of the partition structure also functions as the first power supply signal line; the first partition portion also functions as the first power supply signal line, the partition structure includes a third partition portion located between the substrate and the first partition portion, an orthogonal projection of the first partition portion on the substrate is located within an orthogonal projection of the third partition portion on the substrate, and an area of ​​the orthogonal projection of the first partition portion on the substrate is smaller than an area of ​​the orthogonal projection of the third partition portion on the substrate; the light-emitting region includes a plurality of light-emitting units, and at least a portion of the partition structure is located between the light-emitting units; the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode that are stacked along a direction away from the substrate, and the second electrode is electrically connected to the partition structure; 5. The display panel according to claim 4.

17. A display panel, the display panel includes a first display area, the first display area includes a first area, and the display panel includes a substrate, wiring located on the substrate, and a partition structure; the first region includes at least one wiring region, and the plurality of wirings in the at least one wiring region are stacked and insulated along a direction perpendicular to the substrate, and the plurality of wirings include at least one of a data line, a scanning signal line, a reset signal line, a light-emitting signal line, and a second power supply signal line, and a first power supply signal line; At least a part of the partition structure functions as the first power supply signal line, and in at least one of the wiring regions, at least one of the data line, the scanning signal line, the reset signal line, the light-emitting signal line, and the second power supply signal line and at least a part of the partition structure functioning as the first power supply signal line are stacked and insulated from each other along a direction perpendicular to the substrate. Display panel.

18. the at least one wiring region includes a first wiring region, the plurality of wirings in the first wiring region are stacked and insulated along a direction perpendicular to the substrate, the wirings in the first wiring region extend along a first direction, and in the first wiring region, at least one of the data lines, the scanning signal lines, the reset signal lines, the light-emitting signal lines, and the second power supply signal lines, and at least a portion of the partition structure that also functions as the first power supply signal line, are stacked and insulated along a direction perpendicular to the substrate, and / or the at least one wiring region includes a second wiring region, the plurality of wirings in the second wiring region are stacked and insulated along a direction perpendicular to the substrate, the wirings in the second wiring region extend along a second direction and intersect with the first direction and the second direction, and in the second wiring region, at least one of the data lines, the scanning signal lines, the reset signal lines, the light-emitting signal lines, and the second power supply signal lines, and at least a portion of the partition structure that also functions as the first power supply signal line, are stacked and insulated along a direction perpendicular to the substrate, the first region further includes a light-emitting region, and the light-emitting region and the first wiring region are alternately arranged in the first direction, and / or the light-emitting region and the second wiring region are alternately arranged in the second direction; and / or the first display region further includes a second region, and the light transmittance of the first region is smaller than the light transmittance of the second region; one or more of the first wiring region, the second wiring region, and the light emitting region are provided between adjacent second regions; the second regions and the first wiring regions are alternately arranged in the second direction, and / or the second regions and the second wiring regions are alternately arranged in the first direction, the second region is a non-light-emitting region; 18. The display panel according to claim 17.

19. the partition structure includes a first partition portion and a second partition portion that are stacked in order along a direction away from the substrate, an orthogonal projection of the first partition portion on the substrate is located within an orthogonal projection of the second partition portion on the substrate, and an area of ​​the orthogonal projection of the first partition portion on the substrate is smaller than an area of ​​the orthogonal projection of the second partition portion on the substrate; the partition structure includes a third partition portion located between the substrate and the first partition portion, an orthogonal projection of the first partition portion on the substrate is located within an orthogonal projection of the third partition portion on the substrate, and an area of ​​the orthogonal projection of the first partition portion on the substrate is smaller than an area of ​​the orthogonal projection of the third partition portion on the substrate; the light-emitting region includes a plurality of light-emitting units, and at least a portion of the partition structure is located between the light-emitting units; the light-emitting unit includes a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate, the second electrode being electrically connected to the partition structure; The partition structure is formed to surround a partition opening, and at least a portion of the light emitting unit is located within the partition opening.

19. The display panel according to claim 18.

20. A display device, A display panel comprising the display panel according to any one of claims 1 to 19. The display device further includes a photosensitive module disposed on a side of the display panel opposite to a light exiting side of the first display area. Display device.

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