Display device

Abstract

To suppress lowering of reliability.SOLUTION: A display device includes: a support substrate which includes a first resin substrate having flexibility, a second resin substrate having flexibility, and a first barrier layer arranged between the first resin substrate and the second resin substrate and formed of an inorganic insulation material; and a plurality of display elements which are arranged in a display region where an image is displayed, above the support substrate, wherein the second resin substrate is brought into close contact with the first barrier layer with first adhesive strength, below the display region, and the support substrate has an overlapping region where the second resin substrate and the first barrier layer are overlapped with second adhesive strength smaller than the first adhesive strength, between an end of the support substrate and the display region.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. Furthermore, in recent years, various studies have been conducted on flexible displays, and in such flexible displays, a technique for preventing disconnection of wiring in the bending region is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 [Patent Document 8] Japanese Patent Application Laid-Open No. 2011-165654 [Patent Document 9] Japanese Patent Application Laid-Open No. 2016-31889 [Patent Document 10] Japanese Patent Application Laid-Open No. 2019-148690 [Patent Document 11] Japanese Patent Publication No. 2020-64704 [Patent Document 12] US Patent Application Publication No. 2021 / 0265579 [Patent Document 13] US Patent Application Publication No. 2023 / 0292585 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, the display device comprises: The display device comprises a support substrate including a first flexible resin substrate, a second flexible resin substrate, and a first barrier layer formed of an inorganic insulating material and disposed between the first resin substrate and the second resin substrate, and a plurality of display elements disposed above the support substrate in a display area for displaying images, wherein the second resin substrate adheres to the first barrier layer below the display area with a first adhesion strength, and the support substrate has an overlap area between an end of the support substrate and the display area in which the second resin substrate and the first barrier layer overlap with a second adhesion strength that is smaller than the first adhesion strength.

[0006] According to one embodiment, the display device comprises: The display panel has a first region including a display region for displaying an image, a second region spaced from the first region, and a third region between the first region and the second region, and is folded at the third region, the display panel comprising: a support substrate including a first flexible resin substrate, a second flexible resin substrate, and a first barrier layer formed of an inorganic insulating material and disposed between the first resin substrate and the second resin substrate; and a plurality of display elements disposed in the display region above the support substrate, wherein the second resin substrate is adhered to the first barrier layer with a first adhesion strength in the first region and the second region, and the second resin substrate overlaps the first barrier layer with a second adhesion strength that is smaller than the first adhesion strength in the third region. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display panel 100 taken along line AB in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the display panel 100 taken along line II' in FIG. [Figure 5] FIG. 5 is an enlarged cross-sectional view of the circuit layer 24 overlapping the overlapping area OA. [Figure 6] FIG. 6 is an enlarged plan view of the third region A3 of the support substrate SUB. [Figure 7] FIG. 7 is a diagram showing the display panel 100 shown in FIG. 1 in a folded state. [Figure 8] FIG. 8 is a diagram for explaining the neutral surface of the third region A3 in this embodiment. [Figure 9] FIG. 9 is a diagram for explaining the neutral surface of the third region A3 in the comparative example. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method for forming the overlapping area OA. [Figure 11] FIG. 11 is a diagram for explaining another manufacturing method for forming the overlapping area OA. [Figure 12] FIG. 12 is a plan view showing another example of the configuration of the display device DSP. [Figure 13] FIG. 13 is a schematic cross-sectional view of the display panel 100 taken along line II-II' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] The embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In addition, to facilitate understanding, the drawings depict, where necessary, mutually orthogonal X, Y, and Z axes. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view. Terms referring to the relative positions of two or more components, such as "above," "above," "between," and "opposite," include not only cases where the two or more components are in direct contact with each other, but also cases where they are separated from each other by a gap or another component. Furthermore, the positive direction of the Z axis is referred to as "up" or "upper," and the negative direction of the Z axis is referred to as "down" or "downward."

[0010] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] FIG. 1 is a plan view showing an example of the configuration of a display device DSP.

[0012] The display device DSP includes a display panel 100, a flexible printed circuit board FP1, and a flexible printed circuit board FP2. The display panel 100 includes a display area DA for displaying an image on an insulating support substrate SUB. The display area DA includes a plurality of display elements DE, as will be described later.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0016] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display element DE is, for example, an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0018] In a plan view, the display panel 100 has a first region A1 including the display area DA, a second region A2 spaced apart from the first region A1, and a third region A3 between the first region A1 and the second region A2. In the illustrated example, the first region A1, the third region A3, and the second region A2 are arranged in this order along the second direction Y. The third region A3 is a strip-shaped region extending in the first direction X.

[0019] In such a display panel 100, the first region A1 and the second region A2 are relatively rigid regions. The third region A3 is a region that is more flexible than the first region A1 and can be bent around an axis AX along the first direction X.

[0020] The second region A2 is a region between the third region A3 and the end portion SUBE of the support substrate SUB, and is a strip-shaped region extending in the first direction X. Although not described in detail, the second region A2 has a terminal portion having a plurality of terminals, and is connected to a flexible printed circuit board FP1 at the terminal portion. The flexible printed circuit board FP1 is connected to another flexible printed circuit board FP2. In the illustrated example, an integrated circuit chip CP for driving each of the pixels PX is mounted on the flexible printed circuit board FP1.

[0021] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0022] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP2 and SP1 are aligned in the first direction X, and the subpixels SP3 and SP1 are aligned in the first direction X.

[0023] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which multiple subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0024] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0025] An insulating layer 5 and partition walls 6 are arranged in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition walls 6 overlap the insulating layer 5 in a plan view. The partition walls 6 are formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition walls 6 are conductive and are electrically connected to, for example, a terminal of a common potential.

[0027] The subpixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0028] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a plan view. The peripheral edges of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 in a plan view.

[0029] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a plan view. The peripheral edges of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap with the insulating layer 5 in a plan view.

[0030] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the opening AP3. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a plan view. The peripheral edges of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap with the insulating layer 5 in a plan view.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dashed lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or common electrodes, and are in contact with the partition walls 6.

[0033] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from one another: the area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3.

[0034] FIG. 3 is a schematic cross-sectional view of the display panel 100 taken along line AB in FIG.

[0035] First, the support substrate SUB will be described. The support substrate SUB includes flexible resin substrates 10 and 20 and a barrier layer 16.

[0036] The resin substrates 10 and 20 are formed of, for example, polyimide, but may be formed of other resin materials as long as they are sufficiently flexible. The resin substrate 20 faces the resin substrate 10 in the third direction Z and is positioned above the resin substrate 10.

[0037] The barrier layer 16 is an inorganic insulating layer disposed between the resin substrate 10 and the resin substrate 20 and formed of an inorganic insulating material. The barrier layer 16 is, for example, a laminate in which thin films 16a, 16b, and 16c are laminated in this order. The thin films 16a and 16c are, for example, silicon oxide films. The thin film 16b is, for example, a silicon nitride film. The barrier layer 16 is not limited to the three-layer structure shown in the figure, but may be a two-layer or four or more-layer laminate, or may be a single layer.

[0038] In the illustrated example, the support substrate SUB further includes an adhesive layer 18 that bonds the barrier layer 16 and the resin substrate 20 to each other. The adhesive layer 18 is, for example, an amorphous silicon layer. Note that the adhesive layer 18 may be formed of other materials as long as it improves the adhesion between the barrier layer 16 and the resin substrate 20. Alternatively, instead of the adhesive layer 18, the barrier layer 16 may be subjected to ashing or other treatment to roughen the surface of the barrier layer 16, thereby improving the adhesion between the barrier layer 16 and the resin substrate 20.

[0039] A reinforcing plate 14 is provided for such a support substrate SUB. The reinforcing plate 14 is adhered to the lower surface of the resin substrate 10 (the surface opposite to the upper surface facing the resin substrate 20) via a pressure-sensitive adhesive 12.

[0040] The barrier layer 22 is an inorganic insulating layer disposed on the upper surface of the resin substrate 20 (the surface opposite to the lower surface facing the resin substrate 10) and formed of an inorganic insulating material. The barrier layer 22 is, for example, a laminate in which thin films 22a, 22b, and 22c are laminated in this order. The thin films 22a and 22c are, for example, silicon oxide films. The thin film 22b is, for example, a silicon nitride film. The barrier layer 22 is not limited to a three-layer structure as shown in the example, but may be a two-layer or four or more-layer laminate, or may be a single layer.

[0041] In this way, by combining two resin substrates and two barrier layers 16 and 22, the barrier performance for suppressing moisture penetration into the display area is strengthened.

[0042] The circuit layer 24 is disposed on the barrier layer 22. The circuit layer 24 includes various circuits such as the pixel circuit 1 shown in Fig. 1, various wirings such as the scanning line GL, the signal line SL, and the power supply line PL, and various insulating layers described later.

[0043] The display element layer 26 is disposed on the circuit layer 24. The display element layer 26 includes an insulating layer IL, an insulating layer 5, display elements DE1, DE2, and DE3, partition walls 6, sealing layers SE1, SE2, and SE3, a resin layer RL1, a sealing layer SEL, and a resin layer RL2.

[0044] The insulating layer IL covers the circuit layer 24. The insulating layer IL is an organic insulating layer that flattens the unevenness caused by the circuit layer 24.

[0045] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer IL and spaced apart from one another. The insulating layer 5 is an inorganic insulating layer and is disposed on the insulating layer IL and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer IL. Note that the contact holes in the insulating layer IL are omitted in FIG. 3.

[0046] The partition wall 6 has a conductive lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61 .

[0047] In the illustrated example, the lower part 61 has a bottom layer 63 disposed on the insulating layer 5 and an axial layer 64 disposed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a width greater than that of the axial layer 64. Both ends of the bottom layer 63 protrude from the side surfaces of the axial layer 64. The upper part 62 has a thin film 65 disposed on the axial layer 64 and a thin film 66 disposed on the thin film 65. The upper part 62 has a width greater than that of the axial layer 64. Both ends of the upper part 62 protrude from the side surfaces of the axial layer 64. In this specification, the side surfaces of the axial layer 64 refer to the surfaces of the axial layer 64 that extend between the bottom layer 63 and the upper part 62. In the illustrated example, the upper portion 62 has a width greater than that of the bottom layer 63. The bottom layer 63 may have a width greater than that of the upper portion 62.

[0048] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0049] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral edge located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0050] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral edge located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0051] Note that contact between each of the upper electrodes UE1, UE2, UE3 and the lower portion 61 includes a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63, and a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper portion 62.

[0052] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0053] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0054] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE1 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE2 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3. The sealing layer SE3 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE3.

[0055] In the following description, the multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0056] In the illustrated example, a part of the laminated film FL1 is located on the partition wall 6 around the subpixel SP1, and is spaced apart from the laminated film FL1 (the part that constitutes the display element DE1) located in the aperture AP1. Similarly, a part of the laminated film FL2 is located on the partition wall 6 around the subpixel SP2, and is spaced apart from the laminated film FL2 (the part that constitutes the display element DE2) located in the aperture AP2. Similarly, a part of the laminated film FL3 is located on the partition wall 6 around the subpixel SP3, and is spaced apart from the laminated film FL3 (the part that constitutes the display element DE3) located in the aperture AP3. The stacked films FL1, FL2, and FL3 on the partition wall 6 may be omitted. In this case, a cavity is formed between the partition wall 6 and the sealing layers SE1, SE2, and SE3.

[0057] Ends of the sealing layers SE1, SE2, and SE3 are each located on the partition wall 6. In the example shown, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE3 on the partition wall 6.

[0058] The resin layer RL1 covers the partition wall 6 and the sealing layers SE1, SE2, and SE3. When cavities are formed between the sealing layers SE1, SE2, and SE3 and the partition wall 6, the resin layer RL1 fills these cavities.

[0059] The sealing layer SEL covers the resin layer RL1, and the resin layer RL2 covers the sealing layer SEL.

[0060] The optical film 30 is, for example, a polarizing plate, and is adhered to the resin layer RL2 via an adhesive layer .

[0061] The insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer SEL are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0062] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0063] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0064] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0065] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the emitting layer EM3 is formed of a material that emits light in the red wavelength range. Each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0066] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0067] The cap layers CP1, CP2, and CP3 are multilayer structures made up of multiple thin films, all of which are transparent and have different refractive indices.

[0068] FIG. 4 is a schematic cross-sectional view of the display panel 100 taken along line II' in FIG.

[0069] First, let us focus on the support substrate SUB. The resin substrate 20 is in close contact with the barrier layer 16 with a first adhesion strength in the region below the display region DA, or in the first region A1. The support substrate SUB also has an overlap region OA between an end SUBE of the support substrate SUB and the display region DA, where the resin substrate 20 and the barrier layer 16 overlap with a second adhesion strength that is smaller than the first adhesion strength.

[0070] In the illustrated example, an adhesive layer 18 is interposed between the barrier layer 16 and the resin substrate 20. In the region below the display region DA, or in the first region A1, the adhesive layer 18 bonds the barrier layer 16 and the resin substrate 20 to each other. On the other hand, the overlap region OA is a region where the adhesive layer 18 does not exist. In other words, the barrier layer 16 and the resin substrate 20 are not bonded to each other in the overlap region OA. Such an overlap region OA corresponds to the third region A3 of the display panel 100.

[0071] In the illustrated example, in the second region A2, the adhesive layer 18 bonds the barrier layer 16 and the resin substrate 20 to each other. That is, in the first region A1 and the second region A2, the resin substrate 20 is in close contact with the barrier layer 16 with a first adhesion strength.

[0072] The reinforcing plate 14 has an opening A14 that overlaps the overlapping area OA or the third area A3. In the illustrated example, the width of the opening A14 in the second direction Y is the same as the width of the overlapping area OA or the third area A3 in the second direction Y, but they may be different from each other.

[0073] The barrier layer 22 has an opening A22 that overlaps the overlapping region OA or the third region A3. In the illustrated example, the width of the opening A22 in the second direction Y is different from the width of the overlapping region OA or the third region A3 in the second direction Y, but they may be the same.

[0074] None of the display element layer 26 including the partition walls 6, the adhesive layer 28, and the optical film 30 shown in FIG. 3 overlaps the overlapping area OA or the third area A3.

[0075] The protective resin layer 32 is disposed on the circuit layer 24, is in contact with the optical film 30, and overlaps a portion of the flexible printed circuit board FP1. The protective resin layer 32 also overlaps the overlapping area OA or the third area A3. The protective resin layer 32 is made of a plastic material.

[0076] Plasticity refers to the property of being deformed when stress is applied and not returning to its original shape when the stress is removed. Plastic deformation refers to deformation that does not return to its original shape when the stress is removed. On the other hand, elasticity refers to the property of being deformed when stress is applied and returning to its original shape when the stress is removed. Elastic deformation refers to deformation that returns to its original shape when the stress is removed.

[0077] Because the protective resin layer 32 is made of a plastic material, it undergoes plastic deformation when the display panel 100 is folded in the third region A3. This reduces the reaction force that causes the folded protective resin layer 32 to return to its original shape, compared to when the protective resin layer 32 is made of an elastic material. This prevents the protective resin layer 32 from peeling off from the optical film 30 and the flexible printed circuit board FP1, and also reduces the reaction force acting on the third region A3.

[0078] FIG. 5 is an enlarged cross-sectional view of the circuit layer 24 overlapping the overlapping area OA.

[0079] The circuit layer 24 includes insulating layers 241, 242, 243, 244, and 245, and metal layers M1, M2, and M3. The insulating layer 241 is disposed on the barrier layer 22. The insulating layer 242 is disposed on the insulating layer 241. The insulating layer 243 is disposed on the insulating layer 242. The insulating layer 244 is disposed on the insulating layer 243. These insulating layers 241, 242, 243, and 244 have openings that overlap the opening A22 of the barrier layer 22. The insulating layer 245 is disposed on the resin substrate 20 in the opening A22.

[0080] The insulating layers 241, 242, 243, and 244 are inorganic insulating layers. The insulating layer 245 is an organic insulating layer similar to the insulating layer IL. The insulating layer 245 and the insulating layer IL are made of an elastically deformable material. The elastically deformable material is, for example, a resin insulating material such as polyimide or acrylic.

[0081] Metal layer M1 is disposed between insulating layer 241 and insulating layer 242. Metal layer M2 is disposed between insulating layer 242 and insulating layer 243 and is electrically connected to metal layer M1. Metal layer M3 is disposed on insulating layer 245 and further disposed on insulating layer 244 and is electrically connected to metal layer M2.

[0082] The insulating layer IL covers the metal layer M3, the insulating layer 245, and the insulating layer 244. The protective resin layer 32 is disposed on the insulating layer IL.

[0083] The metal layer M3 overlaps the overlapping region OA or the third region A3. That is, the metal layer M3 intersects with the third region A3 and electrically connects the metal layer M2 in the first region A1 and the metal layer M2 in the second region A2. The metal layer M3 is also disposed along the uneven upper surface of the insulating layer 245. Therefore, when a tensile stress acts on the metal layer M3, the metal layer M3 is configured to be extensible.

[0084] The metal layer M3 is, for example, a laminate of titanium (Ti), aluminum (Al), and titanium (Ti) stacked in this order. Note that the material of the metal layer M3 is not limited to this. For example, the metal layer M3 may be a single layer of tantalum (Ta), tungsten (W), molybdenum (Mo), copper (Cu), or silver (Ag), or a laminate of these materials.

[0085] 5, the circuit layer 24 is illustrated enlarged in the third direction Z for the purpose of explaining the circuit layer 24, but the thickness of the insulating layer 245 and the insulating layer IL is smaller than the thickness of the resin substrate 20.

[0086] FIG. 6 is an enlarged plan view of the third region A3 of the support substrate SUB.

[0087] The support substrate SUB has side edges E1 and E2 that intersect with the end SUBE. In the illustrated example, the end SUBE extends in a first direction X, and the side edges E1 and E2 each extend in a second direction Y.

[0088] In the support substrate SUB, the region where the adhesive layer 18 is disposed is indicated by a dot pattern. The overlapping region OA or the third region A3 where the adhesive layer 18 is not disposed extends in the first direction X and is formed in a strip shape from the side edge E1 to the side edge E2. Note that the opening A14 in the reinforcing plate 14 and the opening A22 in the barrier layer 22 shown in FIG. 5 and other figures are both formed in a strip shape from the side edge E1 to the side edge E2, similar to the overlapping region OA.

[0089] FIG. 7 is a diagram showing the display panel 100 shown in FIG. 1 in a folded state.

[0090] The display panel 100 is folded in a third region A3 where the adhesive layer 18 is not present. The second region A2 faces the first region A1 in the third direction Z. When the display panel 100 is folded, the third region A3 overlaps the opening A14 in the reinforcing plate 14, the opening A22 in the barrier layer 22, and the protective resin layer 32.

[0091] In this way, by folding the display panel 100 in the third area A3, the width of the periphery of the display area DA in the second direction Y can be reduced, thereby realizing a narrower frame.

[0092] As shown in FIG. 7, when the display panel 100 is bent at the third region A3, tensile stress is generated on the convex side of the neutral plane (neutral axis) of the third region A3 depending on the distance from the neutral plane. Furthermore, compressive stress is generated on the concave side of the neutral plane (neutral axis) of the third region A3 depending on the distance from the neutral plane. As described with reference to FIG. 5, the third region A3 includes a metal layer M3 for electrically connecting the metal layer M2 in the first region A1 and the metal layer M2 in the second region A2. To prevent disconnection of the metal layer M3, it is desirable that the metal layer M3 be close to the neutral plane of the third region A3.

[0093] FIG. 8 is a diagram for explaining the neutral surface of the third region A3 in this embodiment.

[0094] As described above, the third region A3 corresponds to the overlap region OA, and the resin substrate 20 is not bonded to the barrier layer 16 in the third region A3. Therefore, the resin substrate 10 and the barrier layer 16 located below the resin substrate 20 do not affect the position of the midplane of the upper stack including the resin substrate 20. In other words, the resin substrate 20 is not subjected to stress along the interface between the resin substrate 10 and the barrier layer 16 located below the resin substrate 20. In addition, the protective resin layer 32 is formed of a material having plasticity, and does not affect the position of the midplane of the upper stack including the resin substrate 20. In other words, parameters such as the thicknesses of the resin substrate 10, the barrier layer 16, and the protective resin layer 32 are excluded from the calculation of the midplane.

[0095] The neutral plane NS of the third region A3 is calculated to be located inside the insulating layer 245. The distance from the lower surface 20R of the resin substrate 20 to the neutral plane NS along the third direction Z is defined as length tn. When the center of the metal layer M3 is defined as the ideal neutral plane NSp, the distance from the neutral plane NS to the ideal neutral plane NSp is defined as length tnp.

[0096] FIG. 9 is a diagram for explaining the neutral plane of the third region A3 in the comparative example.

[0097] In the comparative example, the resin substrate 20 is adhered to the barrier layer 16 by the adhesive layer 18 in the third region A3. In this case, parameters such as the thickness of each of the resin substrate 10 and the barrier layer 16 need to be considered in the calculation of the neutral plane.

[0098] When the neutral plane NS' of the third region A3 is obtained from the calculation, the neutral plane NS' exists inside the resin substrate 20. Along the third direction Z, let the distance from the lower surface 10R of the resin substrate 10 to the neutral plane NS' be the length t n'. When the center of the metal layer M3 is the ideal neutral plane NSp', let the distance from the neutral plane NS' to the ideal neutral plane NSp' be the length t np'.

[0099] As shown in FIGS. 8 and 9, it can be seen that the length t np is smaller than the length t np' (t np < t np'). That is, in the present embodiment, the metal layer M3 can be brought closer to the neutral plane NS as compared with the comparative example.

[0100] As described above, a compressive stress acts on each component located below the neutral plane NS, and a tensile stress acts on each component located above the neutral plane NS.

[0101] In the examples shown in FIGS. 8 and 9, the metal layer M3 is located above the neutral plane. Therefore, a tensile stress acts on the metal layer M3. According to the present embodiment, since the metal layer M3 (or the ideal neutral plane) approaches the actual neutral plane, the tensile stress acting on the metal layer M3 can be relaxed. Therefore, disconnection of the metal layer M3 can be suppressed, and a decrease in reliability can be suppressed.

[0102] FIG. 10 is a diagram for explaining a manufacturing method for forming the overlapping region OA.

[0103] First, as shown in the upper part of FIG. 10 , a resin substrate 10 is formed on a large mother substrate 1000. Then, a plurality of alignment marks 200 are formed on the resin substrate 10. The alignment marks 200 are formed of, for example, molybdenum tungsten (MoW). However, the material of the alignment marks 200 is not limited to this. For example, the alignment marks 200 may be formed as a single layer of titanium (Ti), aluminum (Al), tantalum (Ta), tungsten (W), molybdenum (Mo), copper (Cu), or silver (Ag), or a laminate of these materials.

[0104] 10, a barrier layer 16 and an adhesive layer 18 are formed in this order on the entire surface of the resin substrate 10. The area surrounded by a dashed line in the figure is a panel region PP that is extracted from the mother substrate 1000 as the display panel 100. The barrier layer 16 and the adhesive layer 18 are formed across multiple panel regions PP.

[0105] 10, a photolithography process is performed using the alignment mark 200 as a reference to remove only the adhesive layer 18 in the area corresponding to the overlapping area OA or the third area A3. In the area where the adhesive layer 18 has been removed, the barrier layer 16 is exposed.

[0106] Thereafter, although not shown in the drawings, a resin substrate 20 is formed, a barrier layer 22 having an opening A22 is formed, and a circuit layer 24 is formed. The steps of forming the opening A22 and the step of forming the circuit layer 24 are performed based on the alignment mark 200. This allows the overlapping area OA, the opening A22, and the circuit layer 24 (particularly the metal layer M3) to be formed in desired positions.

[0107] FIG. 11 is a diagram for explaining another manufacturing method for forming the overlapping area OA.

[0108] 11, a resin substrate 10 is formed on a large mother substrate 1000. After that, a plurality of alignment marks 200 are formed on the resin substrate 10.

[0109] 11, a barrier layer 16 is formed on the entire surface of the resin substrate 10. The barrier layer 16 is formed across a plurality of panel regions PP.

[0110] 11, the resist RS is patterned using the alignment mark 200 as a reference, and only the area of ​​the barrier layer 16 that corresponds to the overlapping area OA or the third area A3 is covered with the resist RS. Then, an ashing process is performed on the barrier layer 16. As a result, the surface of the barrier layer 16 exposed from the resist RS becomes rougher than the surface of the barrier layer 16 covered with the resist RS. Then, the resist RS is peeled off.

[0111] Thereafter, although not shown in the drawings, a resin substrate 20 is formed, a barrier layer 22 having an opening A22 is formed, and a circuit layer 24 is formed. The steps of forming the opening A22 and the step of forming the circuit layer 24 are performed based on the alignment mark 200. This allows the overlapping area OA, the opening A22, and the circuit layer 24 (particularly the metal layer M3) to be formed in desired positions.

[0112] FIG. 12 is a plan view showing another example of the configuration of the display device DSP.

[0113] The configuration example shown in Fig. 12 differs from the configuration example shown in Fig. 1 in that the integrated circuit chip CP is mounted in the second area A2 and a flexible printed circuit board FP2 is connected to the second area A2. The flexible printed circuit board FP1 shown in Fig. 1 is omitted in the configuration example shown in Fig. 12.

[0114] In a plan view, the display panel 100 has a first region A1 including a display area DA, a second region A2 spaced apart from the first region A1, and a third region A3 between the first region A1 and the second region A2. The third region A3 is a strip-shaped region extending in the first direction X and is bendable around an axis AX along the first direction X.

[0115] FIG. 13 is a schematic cross-sectional view of the display panel 100 taken along line II-II' in FIG.

[0116] An overlapping area OA where the barrier layer 16 and the resin substrate 20 overlap corresponds to the third area A3, and overlaps with the opening A14 of the reinforcing plate 14, the opening A22 of the barrier layer 22, and the protective resin layer 32, respectively.

[0117] None of the display element layer 26 including the partition walls 6, the adhesive layer 28, and the optical film 30 shown in FIG. 3 overlaps the overlapping area OA or the third area A3.

[0118] The integrated circuit chip CP is mounted on the circuit layer 24 in the second area A2.

[0119] The protective resin layer 32 is disposed on the circuit layer 24, contacts the optical film 30, and does not overlap the integrated circuit chip CP. Such a protective resin layer 32 is formed of a material having plasticity.

[0120] In these other configuration examples, the same effects as those in the above configuration example can be obtained.

[0121] In the above embodiment, for example, The resin substrate 10 corresponds to a first resin substrate, and the resin substrate 20 corresponds to a second resin substrate. The barrier layer 16 corresponds to the first barrier layer, and the barrier layer 22 corresponds to the second barrier layer. The side edge E1 corresponds to the first side edge, and the side edge E2 corresponds to the second side edge, The insulating layer 245 corresponds to the first organic insulating layer, and the insulating layer IL corresponds to the second organic insulating layer. The sealing layers SE1, SE2, and SE3 correspond to a first sealing layer, and the sealing layer SEL corresponds to a second sealing layer. The resin layer RL1 corresponds to the first resin layer, and the resin layer RL2 corresponds to the second resin layer.

[0122] As described above, according to this embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability.

[0123] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0124] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0125] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0126] DSP...display device 100...display panel DA...Display area A1...First area A2...Second area A3...Third area OA...Superimposed area SUB... supporting substrate 10, 20... resin substrate 16, 22... barrier layer 14... reinforcing plate 24...circuit layer 26...display element layer 245, IL...insulating layer 32...protective resin layer M1, M2, M3...metal layer

Claims

1. a support substrate including a first flexible resin substrate, a second flexible resin substrate, and a first barrier layer formed of an inorganic insulating material and disposed between the first resin substrate and the second resin substrate; a plurality of display elements arranged in a display region above the support substrate to display an image; Equipped with the second resin substrate is in close contact with the first barrier layer below the display area with a first adhesion strength; the support substrate has an overlapping region between an end portion of the support substrate and the display region, in which the second resin substrate and the first barrier layer overlap with each other with a second adhesion strength that is smaller than the first adhesion strength; Display device.

2. the support substrate has a first side edge and a second side edge that intersect with the end portion; The overlapping region is formed in a strip shape extending from the first side edge portion to the second side edge portion. The display device according to claim 1 .

3. the support substrate further includes an adhesive layer that bonds the first barrier layer and the second resin substrate together; The overlapping region is a region where the adhesive layer is not present. The display device according to claim 1 .

4. the adhesion layer is an amorphous silicon layer; The display device according to claim 3 .

5. further comprising a reinforcing plate bonded to the first resin substrate, the reinforcing plate has an opening overlapping the overlapping region; The display device according to claim 1 .

6. a second barrier layer disposed on the second resin substrate and formed of an inorganic insulating material; the second barrier layer has an opening overlapping the overlapping region; The display device according to claim 1 .

7. moreover, a first organic insulating layer disposed on the second resin substrate; a metal layer disposed on the first organic insulating layer; a second organic insulating layer covering the metal layer, the metal layer overlaps the overlap region; The display device according to claim 1 .

8. the second organic insulating layer extends to the display area; Each of the plurality of display elements includes a lower electrode disposed on the second organic insulating layer, an organic layer disposed on the lower electrode and including a light-emitting layer, and an upper electrode disposed on the organic layer. The display device according to claim 7 .

9. moreover, an inorganic insulating layer disposed on the second organic insulating layer in the display area and covering a peripheral portion of the lower electrode; a partition wall surrounding each of the plurality of display elements; Equipped with the partition wall has a lower portion that is disposed on the inorganic insulating layer and is made of a conductive material and is in contact with the lower electrode, and an upper portion that is disposed on the lower portion and protrudes from a side surface of the lower portion. The display device according to claim 8 .

10. the partition does not overlap the overlapping region; The display device according to claim 9 .

11. moreover, a cap layer disposed on the upper electrode; a first sealing layer disposed on the cap layer and individually covering each of the plurality of display elements; a first resin layer disposed on the first sealing layer; a second sealing layer disposed on the first resin layer; a second resin layer disposed on the second sealing layer; an optical film adhered to the second resin layer; Equipped with The display device according to claim 9 .

12. a protective resin layer disposed on the second organic insulating layer and in contact with the optical film; The protective resin layer overlaps the overlapping region. The display device according to claim 11.

13. The protective resin layer is formed of a material having plasticity. The display device according to claim 12.

14. a display panel having a first region including a display region for displaying an image, a second region spaced apart from the first region, and a third region between the first region and the second region, the display panel being bent at the third region; The display panel includes: a support substrate including a first flexible resin substrate, a second flexible resin substrate, and a first barrier layer formed of an inorganic insulating material and disposed between the first resin substrate and the second resin substrate; a plurality of display elements arranged in the display region above the support substrate; Equipped with In the first region and the second region, the second resin substrate adheres to the first barrier layer with a first adhesion strength; In the third region, the second resin substrate overlaps the first barrier layer with a second adhesion strength that is smaller than the first adhesion strength. Display device.

15. the support substrate further includes an adhesive layer that bonds the first barrier layer and the second resin substrate to each other in the first region and the second region; The third region is a region where the adhesive layer is not present. The display device according to claim 14.

16. the display panel further includes a reinforcing plate bonded to the first resin substrate, the reinforcing plate has an opening overlapping the third region. The display device according to claim 14.

17. the display panel further includes a second barrier layer disposed on the second resin substrate and made of an inorganic insulating material; the second barrier layer has an opening overlapping the third region; The display device according to claim 14.

18. The display panel further comprises: a first organic insulating layer disposed on the second resin substrate; a metal layer disposed on the first organic insulating layer; a second organic insulating layer covering the metal layer, the metal layer overlaps the third region. The display device according to claim 14.

19. the display panel further includes a protective resin layer disposed on the second organic insulating layer; the protective resin layer overlaps the third region.

19. The display device according to claim 18.

20. the display panel further includes a partition wall surrounding each of the plurality of display elements; the partition wall has a lower portion and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion, and does not overlap the third region; The display device according to claim 14.

Images