Photoelectric conversion device

Abstract

To provide a photoelectric conversion device capable of improving signal quality.SOLUTION: A photoelectric conversion device includes: a plurality of pixels arranged in a plurality of columns; first signal lines respectively arranged corresponding to the plurality of columns and through which signals are read out from a first pixel group of the plurality of pixels in a first scanning mode; second signal lines respectively arranged corresponding to the plurality of columns and through which signals are read out from a second pixel group of the plurality of pixels in a second scanning mode; and a potential control unit that supplies a predetermined potential to the second signal lines during a period when reading out is performed in the first scanning mode and reading out is not performed in the second scanning mode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses an image sensor in which a plurality of signal lines are arranged for one pixel column, and different readout modes are assigned to the plurality of signal lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 133323 Summary of the Invention [Problem to be solved by the invention]

[0004] In a photoelectric conversion device such as that disclosed in Patent Document 1, there is a demand for improvement in the quality of the output signal. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a photoelectric conversion device capable of improving signal quality. [Means for solving the problem]

[0005] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising: a plurality of pixels arranged in a plurality of columns; first signal lines arranged corresponding to each of the plurality of columns, through which signals are read out from a first pixel group of the plurality of pixels in a first scanning mode; second signal lines arranged corresponding to each of the plurality of columns, through which signals are read out from a second pixel group of the plurality of pixels in a second scanning mode; and a potential control unit that supplies a predetermined potential to the second signal lines during a period when reading out is performed in the first scanning mode and when reading out is not performed in the second scanning mode. [Effects of the Invention]

[0006] According to the present invention, a photoelectric conversion device capable of improving signal quality is provided. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a pixel according to the first embodiment. [Figure 3] FIG. 2 is a circuit diagram of a current source according to the first embodiment. [Figure 4] 4 is a timing chart showing the operation of the photoelectric conversion device according to the first embodiment. [Figure 5] 4 is a timing chart showing the operation of the photoelectric conversion device according to the first embodiment. [Figure 6] 1 is a schematic diagram of a stacked photoelectric conversion device according to a first embodiment. [Figure 7] FIG. 10 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a second embodiment. [Figure 8] FIG. 10 is a block diagram showing the configuration of one column of a photoelectric conversion device according to a third embodiment. [Figure 9] 10 is a timing chart showing the operation of the photoelectric conversion device according to the third embodiment. [Figure 10] 10 is a timing chart showing the operation of the photoelectric conversion device according to the fourth embodiment. [Figure 11] FIG. 11 is a block diagram of a device according to a fifth embodiment. [Figure 12] FIG. 13 is a block diagram of a device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same or corresponding elements in multiple drawings are designated by common reference numerals, and their description may be omitted or simplified.

[0009] In the first to fourth embodiments described below, an imaging device will be mainly described as an example of a photoelectric conversion device. However, the photoelectric conversion device in each embodiment is not limited to an imaging device, and can also be applied to other photodetection devices based on photoelectric conversion. Examples of other photodetection devices include a range finder and a photometer. A range finder may be, for example, a focus detection device or a distance measurement device using TOF (Time-Of-Flight). A photometer may be a device that measures the amount of light incident on the device. The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors can be changed as appropriate. For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type. The conductivity types of the semiconductor regions described in the following examples are merely examples and are not limited to the conductivity types described in the examples. The conductivity types described in the examples can be changed as appropriate, and the potential of the semiconductor regions is accordingly changed accordingly. In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0010] [First embodiment] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a pixel array 10, a vertical scanning circuit 11, a control circuit 12, and readout circuits 20 and 40.

[0011] The pixel array 10 has a plurality of pixels 100 arranged in a plurality of rows and a plurality of columns, each of which outputs a signal corresponding to incident light through photoelectric conversion. Each of the plurality of pixels 100 has a photoelectric conversion unit that generates and accumulates signal charges based on the incident light. Microlenses and color filters may be arranged on the pixels 100.

[0012] The photoelectric conversion device includes a reference signal generation circuit 25, a counter 26, a horizontal scanning circuit 27, a processing circuit 28, and an output circuit 29. The photoelectric conversion device also includes a column circuit corresponding to each column of the pixel array 10. The column circuit includes a current source 21, a comparator 22, a first memory 23, and a second memory 24.

[0013] The photoelectric conversion device has column signal lines 13 (first signal lines) and column signal lines 14 (second signal lines). The column signal lines 13 and 14 are provided for each column of pixels 100, and the pixels 100 in the same column output signals to either the column signal line 13 or the column signal line 14. The pixels 100 in odd-numbered columns and even-numbered rows (first pixel group) are connected to the column signal line 13, and the pixels 100 in odd-numbered columns and odd-numbered rows (second pixel group) are connected to the column signal line 14. The pixels 100 in odd-numbered columns and even-numbered rows are read out by the readout circuit 20 shown in the lower part of FIG. 1 via the column signal line 13, and the pixels 100 in odd-numbered columns and odd-numbered rows are read out by the readout circuit 40 shown in the upper part of FIG. 1 via the column signal line 14. The connection relationship between the pixels 100 in even-numbered columns and the column signal lines is opposite to the connection relationship between the pixels 100 in odd-numbered columns and the column signal lines. The number of column signal lines arranged in one column of pixels 100 is not limited to two, and may be three or more. Although four columns of column circuits are shown in FIG. 1, a greater number of column circuits are actually arranged. Typically, the number of columns of the column circuits ranges from several hundred to several thousand. The circuit configuration of the readout circuit 40 is generally similar to that of the readout circuit 20, and therefore is not shown in FIG. 1. In the following description, the column signal lines 14 and the readout circuit 40 may be omitted as appropriate.

[0014] The photoelectric conversion device also has transistors 31 and 51 corresponding to each column of the pixel array 10. The transistors 31 and 51 are P-type MOS (Metal Oxide Semiconductor) transistors. The drain (second main electrode) of the transistor 31 is connected to the column signal line 13, and the source (first main electrode) of the transistor 31 is connected to a potential line having a power supply potential. A control signal VLRES1 is input to the gate of the transistor 31 from the control circuit 12. The drain (second main electrode) of the transistor 51 is connected to the column signal line 14, and the source (first main electrode) of the transistor 51 is connected to a potential line having a power supply potential. A control signal VLRES2 is input to the gate of the transistor 51 from the control circuit 12. Note that the potential of the potential line to which the sources of the transistors 31 and 51 are connected may be a fixed potential other than the power supply potential.

[0015] The transistors 31 and 51 function as potential control units that control the column signal lines to a predetermined potential so that the connected column signal lines do not float. The transistors 31 and 51 function as switches that control the connection between the column signal lines and potential lines having the power supply potential. When the transistor 31 is turned on, a predetermined potential corresponding to the power supply potential is supplied from the drain of the transistor 31 to the column signal line 13. When the transistor 51 is turned on, a predetermined potential corresponding to the power supply potential is supplied from the drain of the transistor 51 to the column signal line 14.

[0016] The control circuit 12 controls the vertical scanning circuit 11, the readout circuits 20 and 40, and the transistors 31 and 51. As described above, the control circuit 12 outputs control signals VLRES1 and VLRES2 to the transistors 31 and 51. The control circuit 12 also supplies control signals and the like that instruct the operation timing of each part in the vertical scanning circuit 11 and the readout circuits 20 and 40.

[0017] The vertical scanning circuit 11 includes a shift register, a gate circuit, a buffer circuit, etc. The vertical scanning circuit 11 outputs control signals to the pixels 100 based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc., and performs scanning to cause the pixels 100 to output signals sequentially row by row.

[0018] A column circuit including a current source 21, a comparator 22, a first memory 23, and a second memory 24 processes signals output from the pixels 100 via the column signal lines 13. Specifically, the column circuit functions as an amplifier that amplifies the signals on the column signal lines 13, and also functions as an analog-to-digital converter (AD converter) that converts analog signals input via the column signal lines 13 into digital signals. The current source 21 is connected to the column signal lines 13, and functions as a load circuit that supplies a drive current for signal output from the pixels 100. The comparator 22 compares a reference signal with the signal on the column signal line 13. The first memory 23 and the second memory 24 hold count signals according to the comparison result by the comparator 22.

[0019] The comparator 22 includes a differential amplifier circuit or the like, and has an inverting input node, a non-inverting input node, and an output node. The inverting input node is connected to the column signal line 13, and a reference signal RAMP is input to the non-inverting input node from the reference signal generation circuit 25. The comparator 22 compares the reference signal RAMP with the signal from the pixel 100, and outputs a comparison signal representing the comparison result from the output node.

[0020] The reference signal generating circuit 25 generates a reference signal RAMP (ramp signal) whose potential changes over time based on clock pulses output from the control circuit 12 or a clock generating circuit (not shown). The reference signal generating circuit 25 can be configured using various methods, such as a capacitive charging / discharging method, a DAC method, or a current steering method. The reference signal RAMP may be an up-slope signal whose potential increases over time, or a down-slope signal whose potential decreases over time. The reference signal RAMP may also include multiple slope waveforms with different potential change rates per unit time.

[0021] The counter 26 counts clock pulses output from the control circuit 12 or a clock generation circuit (not shown) and counts up or down a count signal, which is a digital signal having a predetermined number of bits. The control circuit 12 or the clock generation circuit includes an oscillator circuit and supplies clock pulses to the counter 26. The counter 26 starts counting clock pulses simultaneously with the start of a potential change in the reference signal RAMP from the reference signal generation circuit 25, and outputs the clock signal to the first memory 23 via a wiring. When the level of the comparison signal output from the comparator 22 changes, the first memory 23 holds the value of the clock signal being input at that time. This causes the signal from the pixel 100 to be AD converted. The signal from the first memory 23 is then transferred to the second memory 24.

[0022] The horizontal scanning circuit 27 includes a shift register, a gate circuit, a buffer circuit, etc. Based on the pulses of the control signal supplied from the control circuit 12, the horizontal scanning circuit 27 sequentially outputs control signals to the second memories 24 of the corresponding columns via the wiring corresponding to each column. As a result, the count values ​​held in the second memories 24 are transferred to the processing circuit 28 sequentially for each column. The pulses of the control signal are signals that indicate the start timing of horizontal transfer of signals from the second memories 24 to the processing circuit 28.

[0023] The processing circuit 28 includes a digital signal processor and memory, and has the function of performing processes such as digital correlated double sampling. The memory in the processing circuit 28 is used for temporary storage of signals for digital correlated double sampling. The signals held in the processing circuit 28 are output to the outside of the photoelectric conversion device via an output circuit 29 in a format such as LVDS (Low Voltage Differential Signaling) under the control of the control circuit 12.

[0024] 1 illustrates an example in which a count signal is input from a common counter 26 to the plurality of first memories 23, but this is not limiting. For example, a plurality of counters 26 may be provided so as to correspond to the plurality of first memories 23, respectively. In this case, a common clock pulse is input to the plurality of counters 26, and each of the plurality of counters 26 generates a count signal based on the common clock pulse.

[0025] FIG. 2 is a circuit diagram of a pixel 100 according to this embodiment. The pixel 100 may include a photoelectric conversion unit PD, a transfer transistor M1, a floating diffusion FD, a reset transistor M2, a source follower transistor M3, and a selection transistor M4. In the following description, unless otherwise specified, these transistors are assumed to be N-type MOS transistors. A reference potential (e.g., ground potential) is supplied to the back gates (not shown) of these transistors. The drains of the reset transistor M2 and the source follower transistor M3 are connected to a potential line having a power supply potential Vdd. Note that P-type MOS transistors may be used instead of N-type MOS transistors. In this case, the potential of a control signal applied to the gate of the P-type MOS transistor is inverted relative to the potential of a control signal applied to the gate of the N-type MOS transistor.

[0026] The photoelectric conversion unit PD is, for example, a photodiode, which generates charges by photoelectric conversion of incident light and stores the generated charges. Note that instead of a photodiode, a configuration that generates a photoelectric effect, such as a photoelectric conversion film made of an organic material or a photogate, may be used. The photoelectric conversion unit PD is provided with a microlens, and light collected by the microlens is incident on the photoelectric conversion unit PD. Note that dark current noise can be reduced by employing an embedded photodiode in the photoelectric conversion unit PD.

[0027] The transfer transistor M1 is provided corresponding to the photoelectric conversion unit PD, and a control signal TX is input to the gate of the transfer transistor M1. When the control signal TX goes high, the charge generated by receiving light in the photoelectric conversion unit PD and accumulated therein is transferred to the floating diffusion FD via the transfer transistor M1.

[0028] A power supply potential Vdd is applied to the drain of the source follower transistor M3, and the source potential of the source follower transistor M3 changes depending on the amount of charge transferred to the floating diffusion FD.

[0029] The selection transistor M4 is provided between the source follower transistor M3 and the column signal line 13. The selection transistors M4 of the pixels 100 in the even-numbered rows of one column are connected to a common column signal line 13. The current source 21 and the source follower transistor M3 form a source follower. A control signal SEL is input to the gate of the selection transistor M4. When the control signal SEL goes high, the selection transistor M4 outputs a signal corresponding to the source potential of the source follower transistor M3 to the column signal line 13.

[0030] The source of the reset transistor M2 is connected to the floating diffusion FD, and the power supply potential Vdd is applied to the drain of the reset transistor M2. A control signal RES is input to the gate of the reset transistor M2. When the control signal RES goes high, the reset transistor M2 resets the potential of the floating diffusion FD.

[0031] 3 is a circuit diagram of the current source 21 according to this embodiment. The current source 21 has transistors 211 and 212. Each of the transistors 211 and 212 is configured by an N-type MOS transistor.

[0032] The drain of the transistor 211 is connected to the column signal line 13. The source of the transistor 211 is connected to the drain of the transistor 212. The source of the transistor 212 is connected to a potential line having a ground potential. A bias potential VB is supplied to the gate of the transistor 211. This causes the transistor 211 to function as a current source transistor. A control signal SW is input from the control circuit 12 to the gate of the transistor 212. This causes the transistor 212 to function as a switch that switches the current source 21 between an on state and an off state. During a period when readout via the column signal line 13 is not performed, the transistor 212 is controlled to an off state, thereby switching the current source 21 to an off state, thereby reducing power consumption.

[0033] Fig. 4 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment. Fig. 4 shows a method for reading out one row of the photoelectric conversion device. Fig. 4 also shows the potentials of the control signals TX, RES, and reference signal RAMP. Furthermore, "V13" in Fig. 4 indicates the potential of the column signal line 13.

[0034] During the period from time t0 to time t1, the control signal RES goes high. This turns on the reset transistor M2 and resets the floating diffusion FD. In response, the potential of the column signal line 13 goes to the reset level.

[0035] At time t1, the control signal RES goes low, turning off the reset transistor M2. At this time, the potential of the floating diffusion FD drops due to the influence of the transition of the potential of the control signal RES via the parasitic capacitance between the gate and source of the reset transistor M2. Accordingly, the potential of the column signal line 13 also drops.

[0036] At time t2, the potential of the reference signal RAMP starts to change, and also at time t2, the count signal output from the counter 26 starts to count up.

[0037] At time t3, the potential of the reference signal RAMP becomes equal to the potential of the column signal line 13, causing the output signal of the comparator 22 to change. The counter 26 measures the time from time t2, when counting up begins, to time t3, when the output signal of the comparator 22 changes. The first memory 23 holds the count signal from the counter 26. This causes AD conversion of the reset level. The result of this AD conversion is transferred from the first memory 23 to the second memory 24, and then transferred to the processing circuit 28 under the control of the horizontal scanning circuit 27. Thereafter, at time t4, the reference signal RAMP is reset and returns to its original potential.

[0038] During the period from time t5 to time t6, the control signal TX goes high. This turns on the transfer transistor M1, and charges generated by photoelectric conversion are transferred from the photoelectric conversion unit PD to the floating diffusion FD. During the period from time t5 to time t6, the potential of the floating diffusion FD fluctuates due to the transition of the control signal TX, and therefore the potential of the column signal line 13 also fluctuates. Since FIG. 4 shows a waveform equivalent to a dark state in which no light is incident on the photoelectric conversion unit PD, after time t6, the potential of the column signal line 13 settles to the same reset level as at time t3. Note that when light is incident on the photoelectric conversion unit PD, the potential of the floating diffusion FD decreases in accordance with the amount of generated charges, and the potential of the column signal line 13 also decreases.

[0039] At time t6, the control signal TX goes low, turning off the transfer transistor M1. At this time, the potential of the floating diffusion FD drops due to the influence of the transition of the control signal TX via the parasitic capacitance between the gate and source of the transfer transistor M1. Accordingly, the potential of the column signal line 13 also drops.

[0040] At time t7, the potential of the reference signal RAMP starts to change, and also at time t7, the count signal output from the counter 26 starts to count up.

[0041] At time t8, the potential of the reference signal RAMP becomes equal to the potential of the column signal line 13, causing the output signal of the comparator 22 to change. The counter 26 measures the time from time t7, when counting up begins, to time t8, when the output signal of the comparator 22 changes. The first memory 23 holds the count signal from the counter 26. This causes AD conversion of the optical signal level. The AD conversion result is transferred from the first memory 23 to the second memory 24, and then transferred to the processing circuit 28 under control of the horizontal scanning circuit 27. The processing circuit 28 performs digital correlated double sampling to calculate the difference between the optical signal level and the reset level. Thereafter, at time t9, the reference signal RAMP is reset and returns to its original potential. The processing at times t10 and t11 is similar to that at times t0 and t1, and therefore will not be described here.

[0042] FIG. 5 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment. FIG. 5 illustrates a scanning method for sequentially reading out multiple rows of the photoelectric conversion device. In this embodiment, two pixel readout scanning modes are performed in parallel. These two readout scanning modes are referred to as a first scanning mode and a second scanning mode. That is, at least a portion of the period during which signals are read out in the first scanning mode overlaps with at least a portion of the period during which signals are read out in the second scanning mode. In this embodiment, the period during which scanning in the first scanning mode is performed is longer than the period during which scanning in the second scanning mode is performed. That is, the frame rate of the second scanning mode is higher than the frame rate of the first scanning mode. Furthermore, multiple periods during which scanning in the second scanning mode is performed are included within a period during which scanning in the first scanning mode is performed once. During the period between two scanning periods in the second scanning mode, the column signal lines 14 are not used for readout.

[0043] The column signal lines 13 are assigned to readout in the first scanning mode, and the column signal lines 14 are assigned to readout in the second scanning mode. That is, in the first scanning mode, signals are read out from the multiple pixels 100 to the readout circuit 20 via the column signal lines 13, and in the second scanning mode, signals are read out from the multiple pixels 100 to the readout circuit 40 via the column signal lines 14.

[0044] In this way, different column signal lines are assigned to the two readout scanning modes, so that even when signals are read out in two readout scanning modes in parallel, signals in different scanning modes are not simultaneously output to one column signal line, making it easy to realize a readout technique in which two readout scanning modes are performed in parallel.

[0045] The horizontal direction in Figure 5 indicates the passage of time in one vertical scanning period. The vertical direction in "First Scanning Mode" and "Second Scanning Mode" in Figure 5 schematically indicates the row-direction position of the pixel 100 where processing is performed, and the vertical direction of "VLRES2" in Figure 5 indicates the potential of the control signal VLRES2. That is, "First Scanning Mode" in Figure 5 indicates the change over time of the row where the shutter operation SH1 and readout operation RD1 are performed in the first scanning mode. "Second Scanning Mode" in Figure 5 indicates the change over time of the row where the shutter operation SH2 and readout operation RD2 are performed in the second scanning mode.

[0046] At time t20, the shutter operation SH1 starts. More specifically, in the pixels 100 connected to the column signal line 13, the reset transistor M2 and the transfer transistor M1 are turned on, thereby resetting the photoelectric conversion unit PD. In the shutter operation SH1, this reset operation is performed sequentially for each row.

[0047] At time t21, the read operation RD1 starts. More specifically, signals are read out from the pixels 100 via the column signal lines 13 through the operation shown in Fig. 4. In the read operation RD1, this reset operation is performed sequentially for each row.

[0048] At time t22, the shutter operation SH2 begins. More specifically, in the pixels 100 connected to the column signal line 14, the reset transistor M2 and the transfer transistor M1 are turned on, thereby resetting the photoelectric conversion units PD. In the shutter operation SH2, this reset operation is performed sequentially. However, unlike the shutter operation SH1, in the shutter operation SH2, the photoelectric conversion units PD are simultaneously reset in multiple rows of pixels 100. The number of rows of photoelectric conversion units PD that are simultaneously reset may be, for example, eight, but is not limited to this and may be an integer of two or more. Examples of the number of rows of photoelectric conversion units PD that are simultaneously reset include two, three, four, six, twelve, and sixteen rows.

[0049] At time t23, the readout operation RD2 begins. More specifically, signals are read out from the pixels 100 via the column signal lines 14 through the operations shown in FIG. 4 . In the readout operation RD2, this reset operation is performed sequentially. However, unlike the readout operation RD1, the readout operation RD2 simultaneously reads out signals from multiple rows of pixels 100. The number of rows of photoelectric conversion units PD simultaneously readout may be, for example, eight, but is not limited to this and may be an integer of two or more. Examples of the number of rows of photoelectric conversion units PD simultaneously readout include two, three, four, six, twelve, and sixteen rows. Furthermore, thinning-out readout may be performed, in which a portion of, for example, eight rows is readout. For example, one row out of eight rows may be readout, two rows out of eight rows may be readout, or four rows out of eight rows may be readout.

[0050] At time t24, the read operation RD2 ends. At the same time as the read operation RD2 ends, the control signal VLRES2 transitions from high to low. This turns on the transistor 51, and the column signal line 14 is reset to the power supply potential.

[0051] The period from time t23 to time t24 during which signals are read out in the second scanning mode overlaps with the period during which signals are read out in the first scanning mode, so during the period from time t23 to time t24, signal readout in the two scanning modes is performed in parallel.

[0052] At time t25, the shutter operation SH2 starts again. Then, at time t26, the read operation RD2 starts again. Simultaneously with the start of the read operation RD2, the control signal VLRES2 transitions from low to high. This turns off the transistor 51, and the reset of the column signal line 14 is released.

[0053] During the period from time t24 to time t26, the readout operation RD2 of the second scanning mode is not performed, and therefore the column signal line 14 is not used. If the column signal line 14 is in a floating state at this time, the potential of the column signal line 14 may become unstable, which may affect the potential of the column signal line 13 via the coupling capacitance between the column signal line 14 and the column signal line 13. In contrast, in this embodiment, the column signal line 14 is reset during the period from time t24 to time t26, thereby controlling the column signal line 14 so that it does not become a floating state. This stabilizes the potential of the column signal line 14, thereby improving the quality of the output signal. Therefore, according to this embodiment, a photoelectric conversion device capable of improving signal quality is provided.

[0054] Furthermore, during the period from time t24 to time t26, no signal is read out via the column signal line 14, so that the current source, comparator, and other circuits of the readout circuit 40 connected to the column signal line 14 can be put into a power saving state. Therefore, according to this embodiment, the power consumption of the photoelectric conversion device can be reduced.

[0055] Furthermore, in this embodiment, signal readout is performed in parallel in two scanning modes that differ in the number of pixels read out, thereby making it possible to obtain a plurality of image signals with different frame rates.

[0056] The photoelectric conversion device of this embodiment may be arranged on a single substrate, or may be a stacked type in which multiple substrates are stacked on top of each other. FIG. 6 is a schematic diagram of a stacked-type photoelectric conversion device according to this embodiment. As shown in FIG. 6, the photoelectric conversion device has a stacked structure in which a pixel substrate S1 (first substrate) on which a pixel array 10 is arranged and a circuit substrate S2 (second substrate) on which other circuits are arranged are stacked. That is, transistors 31 and 51 are arranged on the circuit substrate S2. As shown in FIG. 2, all transistors included in the pixel 100 are N-type MOS transistors. Therefore, by arranging the transistors 31 and 51, which are P-type MOS transistors, on the circuit substrate S2, no P-type MOS transistors are arranged on the pixel substrate S1, thereby simplifying the manufacturing process of the pixel substrate S1. Although FIG. 6 shows an example of a stacked-type photoelectric conversion device in which two substrates are stacked, the number of stacked substrates may be three or more.

[0057] It should be noted that the transistors 31 and 51 do not necessarily have to be P-type MOS transistors; for example, they may be N-type MOS transistors. In this case, when the N-type MOS transistor is turned on, the column signal line 13 or the column signal line 14 is connected to a potential line having a ground potential. In this case, the same effect can be obtained. However, in order to perform this operation, if all of the selection transistors M4 of the multiple pixels 100 connected to the column signal line 13 or the column signal line 14 are not turned off, a large current may flow from the power supply potential of the pixel 100 to the ground potential. Therefore, it is desirable that the transistors 31 and 51 be P-type MOS transistors and that a power supply potential be supplied to the column signal line 13 or the column signal line 14.

[0058] [Second embodiment] A photoelectric conversion device according to a second embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first embodiment will be denoted by the same reference numerals, and detailed description may be omitted or simplified.

[0059] The photoelectric conversion device of this embodiment is a modified example in which the functions of the transistors 31 and 51 of the first embodiment are realized by dummy pixels. Other points are generally similar to those of the first embodiment, and therefore description thereof will be omitted.

[0060] 7, in the photoelectric conversion device of this embodiment, a plurality of dummy pixels 101 are arranged in the pixel array 10. In the example of Fig. 7, the dummy pixels 101 are arranged across two rows, the first row and the second row. Furthermore, in the photoelectric conversion device of this embodiment, the transistors 31 and 51 of the first embodiment are not arranged.

[0061] The dummy pixels 101 in the odd-numbered columns and the first row are connected to the column signal lines 14, and the dummy pixels 101 in the odd-numbered columns and the second row are connected to the column signal lines 13. The dummy pixels 101 in the odd-numbered columns and the first row output a signal of a fixed potential that is not dependent on incident light to the column signal lines 14, and the dummy pixels 101 in the odd-numbered columns and the second row output a signal of a fixed potential that is not dependent on incident light to the column signal lines 13. The connection relationship between the dummy pixels 101 in the even-numbered columns and the column signal lines is opposite to the connection relationship between the dummy pixels 101 in the odd-numbered columns and the column signal lines. In other words, the dummy pixels 101 function as potential control units that supply a predetermined potential to prevent the column signal lines 13 and 14 from floating. An example of the configuration of the dummy pixels 101 is an optical black pixel having a circuit configuration similar to that of FIG. 2, in which the photoelectric conversion unit PD is shielded from light by a metal film or the like. In this case, the dummy pixel 101 outputs a black level signal to the column signal line 13 or 14 .

[0062] In this embodiment, during the period from time t24 to time t26 in FIG. 5 when the readout operation RD2 of the second scanning mode is not performed, the control signal VLRES2 goes low, and instead the selection transistor M4 of the dummy pixel 101 goes high. This turns on the selection transistor M4 of the dummy pixel 101, and a signal of a fixed potential is output from the dummy pixel 101 to the column signal line 14. This controls the column signal line 14 so that it does not enter a floating state. Therefore, according to this embodiment, a photoelectric conversion device capable of improving signal quality is provided, similar to the first embodiment. Furthermore, in this embodiment, the transistors 31 and 51 of the first embodiment can be omitted.

[0063] In the configuration of this embodiment, when the current flowing through the column signal line 14 becomes zero, the source follower transistor M3 is turned off, and the column signal line 14 is put into a floating state. To avoid this, it is necessary to keep a constant current flowing through the column signal line 14. Therefore, the configuration of this embodiment consumes more power than the configuration using the transistors 31 and 51 of the first embodiment. Therefore, from the viewpoint of power consumption, the configuration using the transistors 31 and 51 of the first embodiment may be more effective.

[0064] [Third embodiment] A photoelectric conversion device according to a third embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first embodiment will be given the same reference numerals, and detailed description may be omitted or simplified. The photoelectric conversion device according to this embodiment is a modified example in which four column signal lines are arranged in one column. Differences from the first embodiment will be described below.

[0065] Fig. 8 is a block diagram showing the configuration of one column of a photoelectric conversion device according to this embodiment. Fig. 8 shows only one column of pixels, transistors, current sources, and column signal lines extracted from the overall configuration of the photoelectric conversion device shown in Fig. 1. The configuration of other blocks is the same as in Fig. 1, and therefore a description thereof will be omitted.

[0066] 8, the photoelectric conversion device of this embodiment has four column signal lines 15-1, 15-2, 16-1, and 16-2 in one column. The photoelectric conversion device of this embodiment also has transistors 31-1, 31-2, 51-1, and 51-2 and current sources 21-1, 21-2, 21-3, and 21-4. The transistors 31-1, 31-2, 51-1, and 51-2 are P-type MOS transistors.

[0067] In the column shown in FIG. 8, red pixels 100R sensitive to red (first color) light and green pixels 100G sensitive to green (second color) light are alternately arranged. A red color filter is arranged in the red pixels 100R, and a green color filter is arranged in the green pixels 100G. Some of the red pixels 100R are read out in the first scanning mode, and some are read out in the second scanning mode. Some of the green pixels 100G are read out in the first scanning mode, and some are read out in the second scanning mode. Note that although the column shown in FIG. 8 includes red pixels 100R and green pixels 100G, these colors are merely examples, and pixels of other colors may also be arranged. For example, green pixels and blue pixels may be arranged in one column.

[0068] Column signal line 15-1 (first signal line) is assigned to readout of red pixels 100R (first pixel group) in the first scanning mode, and column signal line 15-2 (second signal line) is assigned to readout of red pixels 100R (second pixel group) in the second scanning mode. Column signal line 16-1 (third signal line) is assigned to readout of green pixels 100G (third pixel group) in the first scanning mode, and column signal line 16-2 (fourth signal line) is assigned to readout of green pixels 100G (fourth pixel group) in the second scanning mode. In FIG. 8, the red pixels 100R and green pixels 100G that are readout in the first scanning mode are labeled "first scanning mode." Furthermore, the red pixels 100R and green pixels 100G that are readout in the second scanning mode are labeled "second scanning mode."

[0069] The column signal lines 15-1 and 15-2 extend downward in FIG. 8 and are connected to the readout circuit 20. The column signal lines 16-1 and 16-2 extend upward in FIG. 8 and are connected to the readout circuit 40. As a result, the signal of the red pixel 100R is read out by the readout circuit 20 in both the first scanning mode and the second scanning mode, and the signal of the green pixel 100G is read out by the readout circuit 40 in both the first scanning mode and the second scanning mode. In this way, by dividing the readout direction according to the color of the pixel, it is possible to reduce color mixture of different colors.

[0070] The current sources 21-1, 21-2, 21-3, and 21-4 are connected to the column signal lines 15-1, 15-2, 16-1, and 16-2, respectively. The drains of the transistors 31-1, 31-2, 51-1, and 51-2 are connected to the column signal lines 15-1, 15-2, 16-1, and 16-2, respectively. The sources of the transistors 31-1, 31-2, 51-1, and 51-2 are connected to a potential line having a power supply potential. The control circuit 12 inputs control signals VLRES1-1, VLRES1-2, VLRES2-1, and VLRES2-2 to the gates of the transistors 31-1, 31-2, 51-1, and 51-2, respectively.

[0071] The shutter operation and readout operation in the first scanning mode and the shutter operation and readout operation in the second scanning mode are performed in the same manner as in FIG. 5. During the period when the readout operation in the second scanning mode is not performed, the column signal lines 15-2 and 16-2 are not used. During this period, the control signals VLRES1-2 and VLRES2-2 are at a low level, and the transistors 31-2 and 51-2 are turned on. This operation resets the column signal lines 15-2 and 16-2. In other words, the column signal lines 15-2 and 16-2 are controlled so as not to be in a floating state. Therefore, according to this embodiment, a photoelectric conversion device capable of improving signal quality is provided, similar to the first embodiment.

[0072] Here, the timing at which the control signals VLRES1-2 go to low level and the timing at which the control signals VLRES2-2 go to low level may be simultaneous or may be different. An example in which the timing at which the control signals VLRES1-2 go to low level and the timing at which the control signals VLRES2-2 go to low level are different will be described with reference to FIG.

[0073] Fig. 9 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment. Fig. 9 shows a method for reading out one row of the photoelectric conversion device. Fig. 9 shows the potentials of the control signals VLRES1-2, VLRES2-2, TX, RES, the power supply potential Vdd, and the reference signal RAMP. Also, "V15-1, V16-1" in Fig. 9 indicate the potentials of the column signal lines 15-1 and 16-1. The potentials of the control signals TX, RES, the reference signal RAMP, and the column signal lines 15-1 and 16-1 are generally similar to those shown in Fig. 4, and therefore will not be described here.

[0074] At time t2 (first time), the control signal VLRES1-2 transitions from high to low. This turns on the transistor 31-2, and the column signal line 15-2 is reset to the power supply potential. Thereafter, at time t7 (second time), the control signal VLRES2-2 transitions from high to low. This turns on the transistor 51-2, and the column signal line 16-2 is reset to the power supply potential.

[0075] When the column signal lines 15-2 and 16-2 are reset, the potentials of the column signal lines 15-2 and 16-2 rise to the power supply potential. Therefore, the source follower transistors M3 are turned off in the red pixel 100R connected to the column signal line 15-2 and the green pixel 100G connected to the column signal line 16-2. In this state, the current flowing from the power supply potential Vdd line to the column signal lines 15-2 and 16-2 becomes zero or is significantly reduced from its original current. As a result, as shown in FIG. 9 , the power supply potential Vdd of the pixels may fluctuate significantly in the period after time t2 and the period after time t7. This fluctuation in the power supply potential Vdd is superimposed as noise on the signals read out via the column signal lines 15-1 and 16-1 in the first scanning mode, potentially degrading signal quality.

[0076] In contrast, in this embodiment, as shown in FIG. 9 , the timing at which the column signal line 15-2 is reset to the power supply potential differs from the timing at which the column signal line 16-2 is reset to the power supply potential. More specifically, the column signal line 15-2 is reset to the power supply potential before time t3, when the AD conversion result of the reset level is generated, and then the column signal line 16-2 is reset to the power supply potential before time t8, when the AD conversion result of the optical signal level is generated. As a result, fluctuations in the power supply potential Vdd affect both the AD conversion result of the reset level at time t3 and the AD conversion result of the optical signal level at time t8. The processing circuit 28 performs digital correlated double sampling to calculate the difference between the AD conversion result of the optical signal level and the AD conversion result of the reset level, thereby reducing the influence of fluctuations in the power supply potential Vdd. Therefore, the signal quality can be further improved in the example of FIG. 9 .

[0077] [Fourth embodiment] A photoelectric conversion device according to a fourth embodiment will be described. In the description of this embodiment, parts having the same functions as those in the first embodiment will be given the same reference numerals, and detailed description may be omitted or simplified. The photoelectric conversion device according to this embodiment is a modified example in which readout in the first scanning mode and readout in the second scanning mode are performed alternately. Differences from the first embodiment will be described below.

[0078] In the first embodiment, readout in the first scanning mode and readout in the second scanning mode are performed in parallel, but in this embodiment, readout in the first scanning mode and readout in the second scanning mode are performed alternately. Figure 10 is a timing chart showing the operation of the photoelectric conversion device according to this embodiment. Figure 10 shows control signals VLRES1 and VLRES2.

[0079] During the period from time t31 to time t32, the control signal VLRES1 is at a high level and the control signal VLRES2 is at a low level. Therefore, the transistor 31 is in an off state and the transistor 51 is in an on state. That is, during the period from time t31 to time t32, the signal of the first scanning mode is read out via the column signal line 13, and the column signal line 14 is in a reset state.

[0080] During the period from time t32 to time t33, the control signal VLRES1 is at a low level and the control signal VLRES2 is at a high level. Therefore, the transistor 31 is in an on state and the transistor 51 is in an off state. That is, during the period from time t32 to time t33, the signal of the second scanning mode is read out via the column signal line 14, and the column signal line 13 is in a reset state.

[0081] After time t33, the period during which signals are read out in the first scanning mode and the period during which signals are read out in the second scanning mode are alternately repeated. During the period during which signals are read out in the first scanning mode, the column signal line 14 is in a reset state, and during the period during which signals are read out in the second scanning mode, the column signal line 13 is in a reset state. This prevents unused column signal lines from floating. Therefore, according to this embodiment, similar to the first embodiment, a photoelectric conversion device capable of improving signal quality is provided. Furthermore, in this embodiment, the period during which signals are read out in the first scanning mode and the period during which signals are read out in the second scanning mode do not overlap. As a result, readout in the first scanning mode and readout in the second scanning mode are not performed simultaneously, thereby reducing interference between signals in the first scanning mode and the second scanning mode.

[0082] [Fifth embodiment] The photoelectric conversion device in the above-described embodiment can be applied to various devices, such as digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 11 shows a block diagram of a digital still camera as an example of such a device.

[0083] The device 70 shown in FIG. 11 includes a barrier 706, a lens 702, an aperture 704, and an image pickup device 700 (an example of a photoelectric conversion device). The device 70 also includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the image pickup device 700. The aperture 704 varies the amount of light passing through the lens 702. The image pickup device 700 is configured as in the above-described embodiment, and converts the optical image formed by the lens 702 into image data (image signals). The signal processing unit 708 performs various corrections, data compression, etc. on the image pickup data output from the image pickup device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals may be input from outside the device. The device 70 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device 70 includes at least a photoelectric conversion device. The device 70 further includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (e.g., a robot arm) that operates in response to a signal from the photoelectric conversion device.

[0084] Each pixel may include a plurality of photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and acquire information about the distance from the image capturing device 700 to the subject.

[0085] [Sixth embodiment] 12(a) and 12(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. The device 80 includes an image capture device 800 (an example of a photoelectric conversion device) according to the above-described embodiment and a signal processing device (processing device) that processes signals from the image capture device 800. The device 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the image capture device 800, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the device 80. The device 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information includes information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0086] The device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high collision possibility, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 80 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0087] In this embodiment, the device 80 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 12(b) shows the device when capturing an image of the area in front of the vehicle (image capturing range 850). A vehicle information acquisition device 810, which serves as an image capturing control means, sends an instruction to the device 80 or the image capturing device 800 to perform an image capturing operation. This configuration can further improve the accuracy of distance measurement.

[0088] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0089] [Modified embodiment] The present invention is not limited to the above-described embodiments and can be modified in various ways. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of one embodiment is replaced with part of the configuration of another embodiment, is also an embodiment of the present invention.

[0090] The configuration of the pixel 100 is not limited to that shown in FIG. 2. For example, the capacitance of the floating diffusion FD of the pixel 100 may be variable. For example, one pixel 100 may have multiple photoelectric conversion units PD, and multiple photoelectric conversion units PD may share one floating diffusion FD. Furthermore, multiple photoelectric conversion units PD may be arranged corresponding to one microlens. In this case, a ranging signal used for autofocusing using a phase difference detection method can be obtained.

[0091] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0092] The disclosure of this specification includes the following configurations. (Configuration 1) a plurality of pixels arranged in a plurality of columns; a first signal line arranged corresponding to each of the plurality of columns, through which signals are read out from a first pixel group of the plurality of pixels in a first scanning mode; second signal lines arranged corresponding to the plurality of columns, through which signals are read out from a second pixel group of the plurality of pixels in a second scanning mode; a potential control unit that supplies a predetermined potential to the second signal line during a period when readout in the first scanning mode is performed and readout in the second scanning mode is not performed; A photoelectric conversion device comprising: (Configuration 2) The potential control unit includes a switch that controls connection between a potential line having a fixed potential and the second signal line. 2. The photoelectric conversion device according to configuration 1, (Configuration 3) The fixed potential is the power supply potential 3. The photoelectric conversion device according to configuration 2. (Configuration 4) the switch includes a P-type MOS transistor having a first main electrode and a second main electrode; the first main electrode is connected to the potential line; The second main electrode is connected to the second signal line. 4. The photoelectric conversion device according to configuration 2 or 3. (Configuration 5) each of the plurality of pixels includes an N-type MOS transistor; the N-type MOS transistor is disposed on a first substrate; The P-type MOS transistor is disposed on a second substrate stacked on the first substrate. 5. The photoelectric conversion device according to configuration 4. (Configuration 6) The potential control unit includes a dummy pixel that outputs a signal of a fixed potential to the second signal line. 2. The photoelectric conversion device according to configuration 1, (Configuration 7) The dummy pixel includes a light-shielded photoelectric conversion unit and outputs a black level signal. 7. The photoelectric conversion device according to configuration 6, (Configuration 8) At least a part of a period in which signals are read out in the first scanning mode overlaps with at least a part of a period in which signals are read out in the second scanning mode. 8. The photoelectric conversion device according to any one of configurations 1 to 7. (Configuration 9) The period during which signals are read out in the first scanning mode is longer than the period during which signals are read out in the second scanning mode. 9. The photoelectric conversion device according to configuration 8, (Configuration 10) A period in which signals are read out in the first scanning mode includes a plurality of periods in which signals are read out in the second scanning mode. 10. The photoelectric conversion device according to configuration 9, (Configuration 11) The period in which signals are read out in the first scanning mode and the period in which signals are read out in the second scanning mode do not overlap with each other. 8. The photoelectric conversion device according to any one of configurations 1 to 7. (Configuration 12) The period in which signals are read out in the first scanning mode and the period in which signals are read out in the second scanning mode are alternately repeated. 12. The photoelectric conversion device according to configuration 11. (Configuration 13) The potential control unit supplies a predetermined potential to the first signal line during a period in which readout in the second scanning mode is performed and readout in the first scanning mode is not performed. 13. The photoelectric conversion device according to configuration 11 or 12. (Configuration 14) a third signal line arranged corresponding to each of the plurality of columns, through which signals are read out from a third pixel group of the plurality of pixels in the first scanning mode; a fourth signal line arranged corresponding to each of the plurality of columns, through which signals are read out from a fourth pixel group of the plurality of pixels in the second scanning mode; and The potential control unit further supplies a predetermined potential to the fourth signal line during a period when readout is performed in the first scanning mode and when readout is not performed in the second scanning mode. 14. The photoelectric conversion device according to any one of configurations 1 to 13. (Configuration 15) the first pixel group and the second pixel group are sensitive to light of a first color; The third pixel group and the fourth pixel group are sensitive to light of a second color. 15. The photoelectric conversion device according to configuration 14. (Configuration 16) The potential control unit supplies a predetermined potential to the second signal line at a first time and supplies a predetermined potential to the fourth signal line at a second time. 16. The photoelectric conversion device according to configuration 14 or 15. (Configuration 17) further comprising an analog-to-digital converter that converts the analog signal read out to the first signal line into a digital signal; the first time point is before the analog-to-digital converter converts an analog signal based on the reset state of the first pixel group into a digital signal; The second time is later than the first time and is before the analog-to-digital converter converts an analog signal based on incident light into a digital signal for the first pixel group. 17. The photoelectric conversion device according to configuration 16, (Configuration 18) The photoelectric conversion device according to any one of configurations 1 to 17, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. A device characterized by: (Configuration 19) The processing device processes the image signals generated by the plurality of photoelectric conversion units, and acquires distance information from the photoelectric conversion units to a subject. 19. The device of claim 18.

[0093] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0094] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0095] Column 13, 14 signal lines 31, 51 transistors 100 pixels

Claims

1. a plurality of pixels arranged in a plurality of columns; a first signal line arranged corresponding to each of the plurality of columns, through which signals are read out from a first pixel group of the plurality of pixels in a first scanning mode; second signal lines arranged corresponding to the plurality of columns, through which signals are read out from a second pixel group of the plurality of pixels in a second scanning mode; a potential control unit that supplies a predetermined potential to the second signal line during a period in which readout in the first scanning mode is performed and readout in the second scanning mode is not performed; A photoelectric conversion device comprising:

2. The potential control unit includes a switch that controls connection between a potential line having a fixed potential and the second signal line.

2. The photoelectric conversion device according to claim 1.

3. The fixed potential is the power supply potential 3. The photoelectric conversion device according to claim 2.

4. the switch includes a P-type MOS transistor having a first main electrode and a second main electrode; the first main electrode is connected to the potential line; The second main electrode is connected to the second signal line.

3. The photoelectric conversion device according to claim 2.

5. each of the plurality of pixels includes an N-type MOS transistor; the N-type MOS transistor is disposed on a first substrate; The P-type MOS transistor is disposed on a second substrate stacked on the first substrate.

5. The photoelectric conversion device according to claim 4.

6. The potential control unit includes a dummy pixel that outputs a signal of a fixed potential to the second signal line.

2. The photoelectric conversion device according to claim 1.

7. The dummy pixel includes a light-shielded photoelectric conversion unit and outputs a black level signal.

7. The photoelectric conversion device according to claim 6.

8. At least a part of a period in which signals are read out in the first scanning mode overlaps with at least a part of a period in which signals are read out in the second scanning mode.

2. The photoelectric conversion device according to claim 1.

9. A period during which signals are read out in the first scanning mode is longer than a period during which signals are read out in the second scanning mode.

9. The photoelectric conversion device according to claim 8.

10. A period in which signals are read out in the first scanning mode includes a plurality of periods in which signals are read out in the second scanning mode.

10. The photoelectric conversion device according to claim 9.

11. The period in which signals are read out in the first scanning mode and the period in which signals are read out in the second scanning mode do not overlap with each other.

2. The photoelectric conversion device according to claim 1.

12. The period in which signals are read out in the first scanning mode and the period in which signals are read out in the second scanning mode are alternately repeated.

12. The photoelectric conversion device according to claim 11.

13. The potential control unit supplies a predetermined potential to the first signal line during a period in which reading is performed in the second scanning mode and reading is not performed in the first scanning mode.

12. The photoelectric conversion device according to claim 11.

14. a third signal line arranged corresponding to each of the plurality of columns, through which signals are read out from a third pixel group of the plurality of pixels in the first scanning mode; a fourth signal line arranged corresponding to each of the plurality of columns, through which signals are read out from a fourth pixel group of the plurality of pixels in the second scanning mode; and The potential control unit further supplies a predetermined potential to the fourth signal line during a period when readout is performed in the first scanning mode and when readout is not performed in the second scanning mode.

2. The photoelectric conversion device according to claim 1.

15. the first group of pixels and the second group of pixels are sensitive to light of a first color; The third pixel group and the fourth pixel group are sensitive to light of a second color.

15. The photoelectric conversion device according to claim 14.

16. The potential control unit supplies a predetermined potential to the second signal line at a first time and a predetermined potential to the fourth signal line at a second time.

15. The photoelectric conversion device according to claim 14.

17. further comprising an analog-to-digital converter that converts the analog signal read out to the first signal line into a digital signal; the first time point is before the analog-to-digital converter converts an analog signal based on the reset state of the first pixel group into a digital signal; The second time is later than the first time and is before the analog-to-digital converter converts an analog signal based on incident light into a digital signal for the first pixel group.

17. The photoelectric conversion device according to claim 16.

18. The photoelectric conversion device according to any one of claims 1 to 17, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. The device characterized by:

19. The processing device processes the image signals generated by the plurality of photoelectric conversion units, and acquires distance information from the photoelectric conversion units to a subject.

20. The device of claim 18.

Images