Display device

Abstract

To provide a display device that can reduce brightness and color coordinate fluctuations due to temperature fluctuations.SOLUTION: This specification relates to a display device that can improve optical quality by reducing brightness and color coordinate fluctuations due to temperature fluctuations. The display device includes a first subpixel including a first light-emitting element configured to emit light of a first color and a first driving transistor configured to drive the first light-emitting element, and a second subpixel including a second light-emitting element configured to emit light of a second color and a second driving transistor configured to drive the second light-emitting element, the first driving transistor and the second driving transistor can have a different dummy hole total opening area.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present specification relates to a display device capable of reducing variations in brightness and color coordinates due to temperature variations. [Background technology]

[0002] 2. Description of the Related Art Electroluminescence displays (ELDs) have advantages of high brightness, low driving voltage, and the ability to be made ultra-thin by using self-emitting elements, as well as the ability to be implemented in any shape.

[0003] In an electroluminescent display device, the luminance of a light emitting element varies depending on the temperature, and the luminance may vary depending on the temperature.

[0004] The content of the above-mentioned background art is technical information possessed by the inventors of this specification in order to derive the examples of this specification, or acquired in the process of deriving the examples of this specification, and is not necessarily publicly known technology that was made public to the general public prior to the filing of this specification. Summary of the Invention [Problem to be solved by the invention]

[0005] In an electroluminescent display device, red, green, and blue light-emitting elements made of different luminescent materials have different brightness fluctuation characteristics depending on temperature, so that temperature fluctuations can cause differences in brightness fluctuations among the three color sub-pixels. As a result, the white color coordinates of the electroluminescent display device can fluctuate due to temperature fluctuations, which can degrade the optical quality.

[0006] The present specification provides a display device capable of improving optical quality by reducing variations in brightness and color coordinates due to temperature variations.

[0007] The problems to be solved in this specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the technical idea of ​​this specification belongs from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment includes a first sub-pixel including a first light-emitting element that emits light of a first color and a first driving transistor that drives the first light-emitting element, and a second sub-pixel including a second light-emitting element that emits light of a second color and a second driving transistor that drives the second light-emitting element, and the first driving transistor and the second driving transistor may have different total opening areas of dummy holes.

[0009] A display device according to one embodiment includes a first subpixel including a first light-emitting element emitting light of a first color, a first driving transistor driving the first light-emitting element, and at least one first dummy hole overlapping the first gate electrode of the first driving transistor; a second subpixel including a second light-emitting element emitting light of a second color, a second driving transistor driving the second light-emitting element, and at least one second dummy hole overlapping the second gate electrode of the second driving transistor; and a third subpixel including a third light-emitting element emitting light of a third color, a third driving transistor driving the third light-emitting element, and at least one third dummy hole overlapping the third gate electrode of the third driving transistor, wherein a total opening area of ​​the at least one first dummy hole is different from a total opening area of ​​the at least one second dummy hole and a total opening area of ​​the at least one third dummy hole, and the total opening area of ​​the at least one second dummy hole may be the same as or different from a total opening area of ​​the at least one third dummy hole.

[0010] According to one embodiment, a display device includes a first sub-pixel including a first light-emitting element that emits light of a first color and a first driving transistor that drives the first light-emitting element, and a second sub-pixel including a second light-emitting element that emits light of a second color and a second driving transistor that drives the second light-emitting element, and the first driving transistor and the second driving transistor may have different total opening areas of dummy holes depending on the luminance variation characteristics of the first light-emitting element and the second light-emitting element due to temperature.

[0011] A display device according to one embodiment includes a first sub-pixel including a first light-emitting element that emits light of a first color and a first driving transistor that drives the first light-emitting element, and a second sub-pixel including a second light-emitting element that emits light of a second color and a second driving transistor that drives the second light-emitting element, and the first driving transistor and the second driving transistor may have a total opening area of ​​a dummy hole that differs depending on the opening areas of the first light-emitting element and the second light-emitting element.

[0012] Specific details of various embodiments of the present specification other than the above-mentioned means for solving the problems are included in the following description and drawings. [Effects of the Invention]

[0013] A display device according to an embodiment can reduce or minimize the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of a subpixel by applying dummy holes to an insulating layer of the driving transistor to control the amount of temperature-dependent variation in the critical voltage of the driving transistor.

[0014] In one embodiment, the display device controls the temperature-dependent critical voltage fluctuation amount of the driving transistor by applying different numbers or area ratios of dummy holes to the insulating layer of the subpixels depending on the aperture ratio (area) of the light-emitting element or the brightness fluctuation characteristics of the light-emitting element depending on the temperature, thereby minimizing the brightness fluctuation difference due to temperature fluctuation between the subpixels. As a result, the variation of the white color coordinate due to temperature fluctuation can be minimized, thereby improving optical quality.

[0015] A display device according to one embodiment can improve optical quality by controlling the temperature-dependent variation in the threshold voltage of a driving transistor to reduce or minimize the temperature brightness sensitivity and temperature color sensitivity of a subpixel, thereby providing improved image quality with low power consumption. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a block diagram illustrating a schematic configuration of a display device according to an embodiment. [Figure 2A] 10A and 10B are diagrams illustrating a driving transistor structure having a dummy hole according to an embodiment; [Figure 2B] 10A and 10B are diagrams illustrating a driving transistor structure having a dummy hole according to an embodiment; [Figure 3A] 10A and 10B are diagrams illustrating a driving transistor structure having a dummy hole according to an embodiment; [Figure 3B] 10A and 10B are diagrams illustrating a driving transistor structure having a dummy hole according to an embodiment; [Figure 4A] 10A and 10B are diagrams illustrating a driving transistor structure having a dummy hole according to an embodiment; [Figure 4B] 10A and 10B are diagrams illustrating a driving transistor structure having a dummy hole according to an embodiment; [Figure 4C] 10A and 10B are diagrams illustrating a driving transistor structure having a dummy hole according to an embodiment; [Figure 5] FIG. 2 illustrates a portion of a pixel array of a display device according to one embodiment. [Figure 6] FIG. 2 illustrates a portion of a pixel array of a display device according to one embodiment. [Figure 7] FIG. 1 is an equivalent circuit diagram illustrating a sub-pixel configuration according to one embodiment. [Figure 8A] 10A and 10B are diagrams illustrating layout structures of subpixels according to a comparative example and an embodiment; [Figure 8B] 10A and 10B are diagrams illustrating layout structures of subpixels according to a comparative example and an embodiment; [Figure 8C] 10A and 10B are diagrams illustrating layout structures of subpixels according to a comparative example and an embodiment; [Figure 8D] 10A and 10B are diagrams illustrating layout structures of subpixels according to a comparative example and an embodiment; [Figure 9] 1 is a cross-sectional view illustrating a structure of a subpixel according to an embodiment; [Figure 10] 10 is a graph comparing temperature and brightness sensitivities of display devices according to a comparative example and an embodiment; [Figure 11] 10 is a graph comparing temperature color sensitivities of display devices according to a comparative example and an embodiment; [Figure 12A] 10 is a diagram illustrating a comparison of white color coordinate variations due to temperature variations in display devices according to a comparative example and an embodiment; FIG. [Figure 12B] 10 is a diagram illustrating a comparison of white color coordinate variations due to temperature variations in display devices according to a comparative example and an embodiment; FIG. [Figure 12C] 10 is a diagram illustrating a comparison of white color coordinate variations due to temperature variations in display devices according to a comparative example and an embodiment; FIG. [Figure 12D] 10 is a diagram illustrating a comparison of white color coordinate variations due to temperature variations in display devices according to a comparative example and an embodiment; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] The advantages and features of the present specification, as well as methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various different forms. These embodiments are provided solely to ensure that the disclosure of the present specification is complete and to fully convey the scope of the invention to those skilled in the art. The present specification is defined only by the scope of the claims.

[0018] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and do not limit the present specification to the details shown in the drawings. The same reference numerals refer to the same elements throughout this specification. In addition, if a detailed description of related prior art is deemed to unnecessarily obscure the gist of this specification, the detailed description will be omitted. When terms such as "comprise," "have," and "consist of" are used in this specification, other parts may be added unless "only" is used. When a component is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0019] When interpreting elements, the error range is interpreted as being included even if there is no separate explicit description of the error range.

[0020] In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described using "above," "on top," "below," or "beside," one or more other parts may be located between the two parts, unless the words "immediately" or "directly" are used.

[0021] When describing a temporal relationship, for example, when the temporal precedence is described using "after," "following," "next to," or "before," it can also include cases where the relationship is not consecutive, unless the words "immediately" or "directly" are used.

[0022] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may also be a second component within the technical concept of this specification.

[0023] In describing components in this specification, terms such as first, second, A, B, a, b, etc. may be used. These terms are used merely to distinguish the component from other components, and do not limit the nature, order, sequence, or number of the components. When a component is described as being "connected," "coupled," or "connected" to another component, it should be understood that the component can be directly connected or connected to the other component, but that other components may be "intervening" between each component that can be indirectly connected or connected unless otherwise explicitly stated.

[0024] The term "at least one" should be understood to include all combinations of one or more of the associated components. For example, the meaning of "at least one of the first, second, and third components" can include not only the first, second, or third component, but also all combinations of two or more of the first, second, and third components.

[0025] The features of each of the embodiments of this specification can be partially or wholly combined or combined with each other, and various technical interlocking and driving mechanisms are possible, and each embodiment can be implemented independently of each other or can be implemented together in a linked relationship.

[0026] Hereinafter, preferred embodiments will be described with reference to the accompanying drawings. The scales of the components shown in the drawings are different from the actual scales for the convenience of explanation, and are not limited to the scales shown in the drawings.

[0027] FIG. 1 is a block diagram illustrating a schematic configuration of a display device according to an embodiment.

[0028] The display device according to an embodiment may be an electroluminescent display device, which may be any one of an organic light emitting diode (OLED) display device, a quantum-dot light emitting diode (QLD) display device, an inorganic light emitting diode (ILD) display device, a micro light emitting diode (micro LED) display device, and a mini light emitting diode (mini LED) display device, but is not limited thereto.

[0029] 1, a display apparatus 1000 according to an embodiment may include, but is not limited to, a display panel 100, a gate driver 200, a data driver 300, a timing controller 400, a gamma voltage generator 500, and a power management circuit 700. A display device may include more components. The gate driver 200 and the data driver 300 may be integrated into a panel driver that drives the display panel 100. The gate driver 200, the data driver 300, the timing controller 400, the gamma voltage generator 500, and the power management circuit 700 may be integrated into a display driver.

[0030] The display panel 100 may be a rigid display panel or a flexible display panel that can be deformed into a different shape, such as a foldable, bendable, rollable, or stretchable display panel.

[0031] The display panel 100 can display an image through a pixel array in which sub-pixels (SP) are arranged in a matrix in a display area (DA). In one embodiment, the display panel 100 can further include a touch sensor array arranged in the display area (DA) to sense a user's touch.

[0032] The pixels arranged in the display area (DA) may include a plurality of sub-pixels (SP) that emit light of different colors to realize white light. The sub-pixels (SP) may include a red (hereinafter referred to as R) sub-pixel that emits red light, a green (hereinafter referred to as G) sub-pixel that emits green light, a blue (hereinafter referred to as B) sub-pixel that emits blue light, and may further include a white (hereinafter referred to as W) sub-pixel that emits white light.

[0033] The subpixel (SP) may include a pixel circuit including a light-emitting element (EL) and a driving transistor (DT) for independently driving the light-emitting element (EL). The light-emitting element (EL) may be, but is not limited to, an organic light-emitting diode, a quantum dot light-emitting diode, an inorganic light-emitting diode, a micro light-emitting diode (micro LED), or a mini light-emitting diode (mini LED). The pixel circuit may have various circuit configurations including a driving transistor (DT) and a transistor and a capacitor connected to at least one of nodes (N1, N2, N3) connected to the driving transistor (DT). The pixel circuit of the subpixel (SP) may be connected to signal lines, including gate lines, data lines, and power lines, arranged on the display panel 100.

[0034] Light emitting devices (ELs) have a luminance variation characteristic with temperature, and can have a high temperature luminance sensitivity (TLS). R, G, and B ELs, which are made of different types of luminescent materials, have different luminance variation characteristics with temperature, and can have a high temperature color sensitivity (TCS).

[0035] The display panel 100 according to an embodiment can control the temperature-dependent brightness variation of the light emitting element (EL) by controlling the threshold voltage variation (ΔVth) of the driving transistor (DT) depending on the temperature.

[0036] According to one embodiment, a display panel 100 may increase the temperature-dependent threshold voltage variation (ΔVth) of a drive transistor (DT) in a subpixel (SP) by applying dummy holes to multiple insulating layers of the drive transistor (DT). The dummy holes of the drive transistor (DT) may be formed in multiple insulating layers in the same process as contact holes. This reduces process steps and simplifies the manufacturing process. The dummy holes of the drive transistor (DT) serve as paths for discharging hydrogen atoms from multiple insulating layers during a heat treatment process, and by increasing the degree of dehydrogenation, the temperature-dependent threshold voltage variation (ΔVth) of the drive transistor (DT) may be increased.

[0037] As a result, the display panel 100 can reduce or minimize the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the sub-pixels (SP) by increasing the threshold voltage variation (ΔVth) of the driving transistor (DT) due to temperature and suppressing the luminance variation of the light-emitting element (EL) due to temperature.

[0038] The display panel 100 according to an embodiment may control the threshold voltage fluctuation amount (ΔVth) of the driving transistor (DT) differently by applying different numbers of dummy holes or different area ratios (aperture ratio, aperture area) to the driving transistor (DT) depending on the aperture ratio (aperture area, light-emitting area) of the light-emitting element (EL) or the luminance fluctuation characteristics of the light-emitting element (EL) due to temperature. A detailed description of this will be given later.

[0039] As a result, the display panel 100 can reduce or minimize the difference in brightness fluctuation due to temperature fluctuation between the sub-pixels (SP) by controlling the threshold voltage fluctuation (ΔVth) of the driving transistor (DT) differently in at least two sub-pixels (SP) of different colors, thereby reducing or minimizing the white color coordinate fluctuation due to temperature fluctuation and improving the optical quality of the display panel 100.

[0040] The gate driver 200 is controlled according to a plurality of gate control signals supplied from the timing controller 400, and can individually drive the gate lines of the display panel 100. The gate driver 200 can supply a gate-on voltage to each gate line during a driving period of the corresponding gate line, and supply a gate-off voltage to the corresponding gate line during a non-driving period of the corresponding gate line. The gate driver 200 can be built in the bezel area of ​​the display panel 100 in the form of a gate-in-panel (GIP) formed together with thin film transistors in the display area (DA).

[0041] In one embodiment, the gate driver 200 built into the display panel 100 can receive a plurality of gate control signals from the timing controller 400 via a level shifter. The level shifter receives the timing control signals from the timing controller 400, generates a plurality of gate control signals by level shifting or logic processing, and supplies the generated signals to the gate driver 200.

[0042] The gamma voltage generator 500 can generate a plurality of reference gamma voltages having different gamma voltage levels and supply them to the data driver 300. The gamma voltage generator 500 can generate a plurality of reference gamma voltages corresponding to the gamma characteristics of the display apparatus 1000 under the control of the timing controller 400 and supply them to the data driver 300. The gamma voltage generator 500 can adjust the reference gamma voltage level according to the gamma data supplied from the timing controller 400 and output the reference gamma voltage to the data driver 300. The gamma voltage generator 500 can adjust a high potential power supply voltage, which is the maximum gamma voltage, according to the peak brightness control from the timing controller 400, and adjust a plurality of reference gamma voltages according to the adjusted high potential power supply voltage and output the reference gamma voltages to the data driver 300.

[0043] The data driver 300 is controlled according to a plurality of data control signals supplied from the timing controller 400, and can convert the digital data supplied from the timing controller 400 into an analog data signal using a digital-to-analog conversion circuit. The data driver 300 can subdivide the plurality of reference gamma voltages supplied from the gamma voltage generator 500 into gamma voltages and convert the digital data into an analog data signal using the subdivided gamma voltages. The data driver 300 can supply the converted data signal to the data lines of the display panel 100.

[0044] In one embodiment, the data driver 300 can additionally supply a reference voltage to a reference line of the display panel 100 under the control of the timing controller 400. The data driver 300 can supply separate reference voltages for display and sensing under the control of the timing controller 400.

[0045] In one embodiment, the data driver 300 further includes a sensing unit, and can sense a signal reflecting the driving characteristics of the sub-pixel (SP) via a reference line or a power supply line in a voltage sensing manner or a current sensing manner under the control of the timing controller 400, and transmit the sensing result to the timing controller 400.

[0046] The timing controller 400 can receive source video data and timing control signals from an external host system. The host system can be any one of a computer, a television system, a set-top box, a mobile terminal system such as a tablet or a mobile phone, and an in-vehicle system. The timing control signals can include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0047] The timing controller 400 can control the gate driver 200 and the data driver 300 using timing control signals provided from the host system and timing setting information stored therein. The timing controller 400 can generate a plurality of gate control signals for controlling the driving timing of the gate driver 200 and provide them to the gate driver 200. The timing controller 400 can generate a plurality of data control signals for controlling the driving timing of the data driver 300 and provide them to the data driver 300. In one embodiment, the timing controller 400 can be represented as a controller.

[0048] The timing controller 400 can perform at least one of various types of image processing, including image quality correction, degradation correction, and brightness correction for reducing power consumption, on input image data supplied from a host system.

[0049] In one embodiment, the timing controller 400 may further correct the characteristic deviation of the sub-pixels (SP) by applying a compensation value stored in a memory to the characteristic deviation of the sub-pixels (SP) before supplying the image-processed data to the data driver 300 .

[0050] In one embodiment, the timing controller 400 can execute a sensing mode according to a request from a host system or a user or a predetermined driving sequence. The timing controller 400 can control the panel drivers 200 and 300 and the power management circuit 700 to drive the display panel 100 in the sensing mode and update compensation data stored in the memory. In the sensing mode, the timing controller 400 can sense the threshold voltage and mobility of the drive transistor (DT), which reflects the characteristics and degradation of the subpixel (SP) of the display panel 100, via the data driver 300, and can further sense the threshold voltage of the light-emitting element (EL). The timing controller 400 can process the sensing results and update the compensation data of the subpixel (SP).

[0051] In one embodiment, the timing controller 400 can accumulate image data of the sub-pixels (SP) to predict degradation of the sub-pixels (SP), and can sense the threshold voltage of the light-emitting element (EL) for the sub-pixels (SP) predicted to be relatively more deteriorated, and update the compensation data.

[0052] The power management circuit 700 can use the input voltage to generate and supply various driving voltages required for the operation of all components of the display device 1000, including the display panel 100, gate driver 200, data driver 300, timing controller 400, and gamma voltage generator 500.

[0053] 2A to 4C are diagrams illustrating the structure of a driving transistor having a dummy hole according to an embodiment.

[0054] 2A and 3A, a first driving transistor (DT_SP1) of a first subpixel according to an embodiment includes an active layer (ACT) on a substrate (SUB), a gate insulating layer (GI) on the active layer (ACT), a gate electrode (GE1) on the gate insulating layer (GI), and a first source / drain electrode (SD11) and a second source / drain electrode (SD12) disposed in conductive regions of the active layer (ACT) facing each other across a channel (CH1). The first driving transistor (DT_SP1) may further include a first source / drain connecting electrode (SD14) connected to the first source / drain electrode (SD11) through a contact hole 11 and a second source / drain connecting electrode (SD15) connected to the second source / drain electrode (SD12) through a contact hole 12, disposed on a plurality of insulating layers including an interlayer insulating layer (ILD) on the gate electrode (GE1).

[0055] 2B and 3B, the second driving transistor (DT_SP2, DTa_SP2) of the second subpixel according to an embodiment includes an active layer (ACT) on a substrate (SUB), a gate insulating layer (GI) on the active layer (ACT), a gate electrode (GE2) on the gate insulating layer (GI), and a first source / drain electrode (SD21) and a second source / drain electrode (SD22) disposed in conductive regions of the active layer (ACT) that face each other across the channel (CH2). The second driving transistor (DT_SP2, DTa_SP2) may further include a first source / drain connecting electrode (SD23) disposed on an interlayer insulating layer (ILD) and connected to the first source / drain electrode (SD21) through a contact hole 21, and a second source / drain connecting electrode (SD24) connected to the second source / drain electrode (SD22) through a contact hole 22.

[0056] The gate electrodes (GE1, GE2) of the driving transistors (DT_SP1, DT_SP2, DTa_SP2) are connected to the second node (N2) of the corresponding subpixel, the first source / drain electrodes (SD11, SD21) are connected to the first node (N1) of the corresponding subpixel via the first source / drain connecting electrodes (SD14, SD23), and the second source / drain electrodes (SD12, SD22) are connected to the third node (N3) of the corresponding subpixel via the second source / drain connecting electrodes (SD15, SD24).

[0057] The contact holes 11, 12, 21, 22 of the drive transistors (DT_SP1, DT_SP2, DTa_SP2) can be provided through a plurality of insulating layers including an interlayer insulating layer (ILD) and a gate insulating layer (GI).

[0058] According to an embodiment, the first and second drive transistors (DT_SP1, DT_SP2, DTa_SP2) may further include dummy holes 13, 23, 23a formed in a plurality of insulating layers including an interlayer insulating layer (ILD) on the gate electrodes (GE1, GE2).

[0059] The dummy holes 13, 23, and 23a of the drive transistors DT_SP1, DT_SP2, and DTa_SP2 may be formed in multiple insulating layers, including the interlayer dielectric layer (ILD), in the same process as the contact holes 11, 12, 21, and 22. The dummy holes 13, 23, and 23a, along with the contact holes 11, 12, 21, and 22, can be used as paths for discharging and degassing hydrogen atoms from insulating layers, including the interlayer dielectric layer (ILD), during a heat treatment process after the contact hole process. As a result, the drive transistors DT_SP1, DT_SP2, and DTa_SP2 according to one embodiment can increase the degree of dehydrogenation through the dummy holes 13, 23, and 23a, thereby increasing the temperature-dependent threshold voltage variation (ΔVth). As a result, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the first and second subpixels can be reduced.

[0060] Furthermore, in one embodiment of the display device, the aperture ratio (number or area) of the dummy holes 13, 23, 23a is applied to the first and second driving transistors (DT_SP1, DT_SP2, DTa_SP2) differently depending on the aperture ratio (aperture area, light-emitting area) of the light-emitting element or the brightness fluctuation characteristics of the light-emitting element due to the temperature, thereby controlling the critical voltage fluctuation amount (ΔVth) due to the temperature of the first and second driving transistors (DT_SP1, DT_SP2, DTa_SP2) differently.

[0061] 2A and 2B, in one embodiment, the number of dummy holes 13 of the first drive transistor (DT_SP1) of the first subpixel may be different from the number of dummy holes 23 of the second drive transistor (DT_SP2) of the second subpixel. Each of the dummy holes 13 and 23 may have the same width (W1) and area as each of the contact holes 11, 12, 21, and 22.

[0062] The number of dummy holes 23 of the second drive transistor (DT_SP2) shown in Fig. 2B may be greater than the number of dummy holes 13 of the first drive transistor (DT_SP1) shown in Fig. 2A. For example, the first drive transistor (DT_SP1) may include one dummy hole 13, and the second drive transistor (DT_SP2) may include two dummy holes 23.

[0063] Referring to Figures 3A and 3B, in one embodiment, the width (W1) and area of ​​the dummy hole 13 of the first driving transistor (DT_SP1) of the first subpixel may be different from the width (W2) and area of ​​the dummy hole 23a of the second driving transistor (DTa_SP2) of the second subpixel.

[0064] The width (W2) and area of ​​the dummy hole 23a of the second drive transistor (DTa_SP2) shown in Fig. 3B may be larger than the width (W1) and area of ​​the dummy hole 13 of the first drive transistor (DT_SP1) shown in Fig. 3A. The width (W2) and area of ​​the dummy hole 23a of the second drive transistor (DTa_SP2) may be larger than the width and area of ​​the contact holes 21 and 22 of the second drive transistor (DTa_SP2).

[0065] 2A to 3B, the drive transistors (DT_SP1, DT_SP2, DTa_SP2) according to one embodiment may include dummy electrodes (SD16, SD25) disposed on a plurality of insulating layers including an interlayer insulating layer (ILD) and connected to the gate electrodes (GE1, GE2) via dummy holes 13, 23, 23a. The dummy electrodes (SD16, SD25) are electrically floating and may be referred to as floating electrodes. The dummy electrodes (SD16, SD25) cover the dummy holes 13, 23, 23a, thereby preventing defects that may occur due to the dummy holes 13, 23, 23a in subsequent processes after the heat treatment process. In one embodiment, the dummy electrodes (SD16, SD25) may be omitted.

[0066] Referring to FIGS. 4A to 4C, in one embodiment, the dummy hole 13b disposed in the first driving transistor DTb_SP1 of the first subpixel and the dummy holes 23b and 23c disposed in the second driving transistors DTb_SP2 and DTc_SP2 of the second subpixel may have a structure in which they are filled with an insulating material of a planarization layer (PLN) disposed on the source / drain connecting electrodes SD14, SD15, SD23, and SD24.

[0067] The second drive transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) having dummy holes 23, 23a, 23b, 23c with a larger aperture ratio (number or area) than the dummy holes 13, 13b of the first drive transistors (DT_SP1, DTb_SP1) may have a larger threshold voltage fluctuation (ΔVth) due to temperature than the first drive transistors (DT_SP1, DTb_SP1). When multiple dummy holes are included as in FIG. 4B , the aperture ratio and area (aperture area) of the dummy holes may refer to the total aperture ratio and total area (total aperture area) of the multiple dummy holes. In one embodiment, the first drive transistors (DT_SP1, DTb_SP1) may be applied to a first subpixel having a light-emitting element with a relatively small luminance variation characteristic due to temperature, and the second drive transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) may be applied to a second subpixel having a light-emitting element with a relatively large luminance variation characteristic due to temperature.

[0068] As a result, the second sub-pixel can further reduce the temperature luminance sensitivity (TLS) through the second driving transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2). As a result, the difference in luminance variation due to temperature between the first and second sub-pixels is reduced or minimized, thereby reducing or minimizing the temperature color sensitivity (TCS) of the sub-pixel and reducing or minimizing the white color coordinate variation due to temperature changes.

[0069] In one embodiment, the dummy holes 13, 13b, 23, 23a, 23b, 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be arranged overlapping the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) or can be arranged in an insulating layer in an adjacent area that does not overlap with the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2).

[0070] In one embodiment, the dummy holes 13, 13b, 23, 23a, 23b, 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be arranged in the insulating layer in the region adjacent to the gate electrodes (GE1, GE2).

[0071] In one embodiment, the dummy holes 13, 13b, 23, 23a, 23b, 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be arranged to overlap or not overlap with at least one of the gate electrodes (GE1, GE2) and the active layer (ACT).

[0072] In one embodiment, at least some of the dummy holes 13, 13b, 23, 23a, 23b, and 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, and DTc_SP2) can be arranged so as not to overlap with the gate electrodes (GE1 and GE2) or the active layer (ACT).

[0073] In one embodiment, the closer the dummy holes 13, 13b, 23, 23a, 23b, and 23c in the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, and DTc_SP2) are to the active layer (ACT) and the channel (CH1 and CH2), the greater the amount of minority atoms in the insulating layer closer to the active layer (ACT) are discharged, thereby further increasing the temperature-dependent threshold voltage variation (ΔVth). Therefore, the display device according to one embodiment can further reduce the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the subpixels, thereby further improving optical quality.

[0074] 5 and 6 are diagrams illustrating a portion of a pixel array of a display device according to one embodiment.

[0075] 5, a display panel 100a according to an embodiment may include a pixel matrix in which pixels (PXa) including R / G / B subpixels (Ra, Ga, Ba) are repeatedly arranged in a first direction (X) and a second direction (Y). The G subpixel (Ga) and the R subpixel (Ra) may be arranged adjacent to each other in the second direction (Y), and the B subpixel (Ba) may be arranged adjacent to the G subpixel (Ga) and the R subpixel (Ra) in the first direction (X), but this arrangement is not limited to this.

[0076] 6, a display panel 100b according to an embodiment may include a pixel matrix in which first-type pixels (PXb) including R / G sub-pixels (Rb, Gb) and second-type pixels (PXc) including B / G sub-pixels (Bb, Gb) are alternately arranged in a first direction (X) and a second direction (Y). The R sub-pixel (Rb) and the B sub-pixel (Bb) may be adjacent to each other in the first direction (X) and the second direction (Y), the G sub-pixel (Gb) may be adjacent to the R sub-pixel (Rb) in a first diagonal direction, and the G sub-pixel (Gb) may be adjacent to the B sub-pixel (Bb) in a second diagonal direction, but this arrangement is not limited to this.

[0077] The R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb) may have the form of light-emitting regions where the R / G / B light-emitting elements emit light, and the remaining regions excluding the light-emitting regions may be non-light-emitting regions where a black matrix is ​​disposed.

[0078] Among the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb), the light-emitting area (aperture ratio) of the B light-emitting element of the B subpixel (Ba, Bb) may be the largest, taking into consideration the efficiency and lifetime of the B light-emitting element. The light-emitting area (aperture ratio) of either the R light-emitting element of the R subpixel (Ra, Rb) or the G light-emitting element of the G subpixel (Ga, Gb) may be the smallest. In one embodiment, as shown in FIG. 5 , the light-emitting area of ​​the G light-emitting element of the G subpixel (Ga) may be larger than the light-emitting area of ​​the R light-emitting element of the R subpixel (Ra). In another embodiment, as shown in FIG. 6 , the light-emitting area of ​​the R light-emitting element of the R subpixel (Rb) may be larger than the light-emitting area of ​​the G light-emitting element of the G subpixel (Gb).

[0079] Referring to Figures 2A to 6, each of the R / G / B sub-pixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb) according to one embodiment may include either a first driving transistor (DT_SP1, DTb_SP1) having dummy holes 13, 13b or a second driving transistor (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) having dummy holes 23, 23a, 23b, 23c.

[0080] As a result, in one embodiment of the display panels 100a and 100b, the temperature-dependent critical voltage variation (ΔVth) of the driving transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) increases, thereby reducing the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb).

[0081] In the R / G / B sub-pixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb) according to an embodiment, at least one of the R / G sub-pixels (Ra / Ga, Rb / Gb) may include a first driving transistor (DT_SP1, DTb_SP1) having a dummy hole 13, 13b. The B sub-pixels (Ba, Bb), which have a relatively large amount of luminance fluctuation due to the aperture ratio or temperature of the B light-emitting element, may include a second driving transistor (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) having a dummy hole 23, 23a, 23b, 23c.

[0082] As a result, in the display panels 100a and 100b according to an embodiment, the first driving transistors (DT_SP1, DTb_SP1) and the second driving transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) have different threshold voltage fluctuations (ΔVth) due to temperature, which reduces or minimizes the temperature-dependent luminance fluctuation difference between the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb). This reduces or minimizes the temperature color sensitivity (TCS) of the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb) and minimizes the temperature-dependent luminance fluctuation. For example, the B subpixel may be configured to include dummy holes in a larger number, shape, or size than the R or G subpixels, thereby reducing the temperature-dependent luminance fluctuation difference between the R / G / B subpixels. The configuration of forming dummy holes at different depths can also be used to adjust the critical voltage variation (dummy holes formed closer to the ACT layer can increase the critical voltage variation).

[0083] FIG. 7 is an equivalent circuit diagram illustrating the configuration of a subpixel according to an embodiment.

[0084] 7, a sub-pixel (SPa) according to one embodiment includes a light-emitting element (OLED) and a pixel circuit for independently driving the light-emitting element (OLED), and the pixel circuit may include, but is not limited to, a driving transistor (DT), a plurality of transistors (T2 to T8), and a storage capacitor (Cst). The sub-pixel may include other numbers of transistors and / or capacitors and / or other circuit configurations in addition to those shown in FIG.

[0085] Each of the transistors (DT, T2 to T8) of the pixel circuit can be made of any one of polysilicon semiconductors, amorphous silicon semiconductors, and oxide semiconductors. In one embodiment, all or some of the transistors (DT, T2 to T8) of the pixel circuit can be made of P-type transistors, such as P-type polysilicon transistors or P-type oxide transistors. In one embodiment, all or some of the transistors (DT, T2 to T8) of the pixel circuit can be made of N-type transistors, such as N-type polysilicon transistors or N-type oxide transistors. In one embodiment, the transistors (DT, T2 to T8) of the pixel circuit can be made of a mixture of P-type polysilicon transistors and N-type oxide transistors.

[0086] In one embodiment, the drive transistor (DT) and some of the transistors (T2, T4 to T8) can be configured with a P-type LTPS (Low-Temperature Polycrystalline Silicon) transistor with high mobility, and at least one of the some of the transistors (T3, T4) can be configured with an N-type oxide transistor with a smaller off-current (leakage current) than the LTPS transistor.

[0087] The sampling transistor (T3, third transistor) is controlled by the first gate line 31 and can connect a second node (N2) connected to the gate electrode of the driving transistor (DT) and a third node (N3) connected to the second source / drain electrode of the driving transistor (DT). The sampling transistor (T3) is turned on by a gate-on voltage of the first scan signal (Scan1) supplied via the first gate line 31, and can connect the gate electrode and the second source / drain electrode of the driving transistor (DT) during a sampling period, thereby connecting the driving transistor (DT) in a diode structure.

[0088] The switching transistor (T2, second transistor) is controlled by the second gate line 32 and can connect the data line 53 to a first node (N1) connected to a first source / drain electrode of the driving transistor (DT). The switching transistor (T2) is turned on by a gate-on voltage of a second scan signal (Scan2) supplied via the second gate line 32 and can supply the data voltage (Vdata) supplied via the data line 53 to the driving transistor (DT) during a data programming period.

[0089] The operation control transistor (T5, fifth transistor) is controlled by the fifth gate line 35 and can connect the first node (N1) of the driving transistor (DT) to a first power line 51 that supplies a first power voltage (VDD). The operation control transistor (T5) is turned on by a gate-on voltage of the light emitting control signal (EM) supplied via the fifth gate line 35 and can supply the first power voltage (VDD) supplied via the first power line 51 to the first node (N1) of the driving transistor (DT) during the light emitting period.

[0090] The light emitting control transistor (T6, sixth transistor) is controlled by the fifth gate line 35 and can connect the third node (N3) of the driving transistor (DT) to a fourth node (N4) connected to the anode electrode of the light emitting element (OLED). The light emitting control transistor (T6) is turned on by a gate-on voltage of the light emitting control signal (EM) supplied via the fifth gate line 35 and can connect the third node (N3) of the driving transistor (DT) to the anode electrode of the light emitting element (OLED) during the light emitting period.

[0091] The first initialization transistor (T4, fourth transistor) is controlled by the fourth gate line 34 and can connect the second node (N2) of the driving transistor (DT) to the first initialization voltage line 41. The first initialization transistor (T4) is turned on by the gate-on voltage of the fourth scan signal (Scan4) supplied via the fourth gate line 34 and can supply the first initialization voltage (Vinit) supplied via the first initialization voltage line 41 to the second node (N2) of the driving transistor (DT) during the initialization period.

[0092] The second initialization transistor (T7, seventh transistor) is controlled by the third gate line 33 and can connect the second initialization voltage line 42 to a fourth node (N4) connected to the anode of the light emitting element (OLED). The second initialization transistor (T7) is turned on by the gate-on voltage of the third scan signal (Scan3) supplied via the third gate line 33 and can supply the second initialization voltage (VAR) supplied via the second initialization voltage line 42 to the fourth node (N4) connected to the anode electrode of the light emitting element (OLED) during the initialization period. The second initialization voltage (VAR) can be referred to as an anode reset voltage.

[0093] The third initialization transistor (T8, eighth transistor) is controlled by the third gate line 33 and can connect the third initialization voltage line 43 to the first node (N1) of the drive transistor (DT). The third initialization transistor (T8) is turned on by the gate-on voltage of the third scan signal (Scan3) supplied via the third gate line 33 and can supply the third initialization voltage (Vobs) supplied via the third initialization voltage line 43 to the first node (N1) connected to the first source / drain electrode of the drive transistor (DT) during the initialization period. The third initialization voltage (Vobs) can be expressed as an on-bias stress voltage that suppresses a critical voltage shift of the drive transistor (DT).

[0094] The storage capacitor Cst may be connected between the first power supply line 51 and the second node N2 of the drive transistor DT. The storage capacitor Cst may charge a differential voltage between the first power supply voltage VDD supplied via the first power supply line 51 and the data voltage Vdata supplied to the second node N2 from the data line 53 via the switching transistor T2, the drive transistor DT, and the sampling transistor T3. During a sampling period in which the drive transistor DT is connected in a diode configuration via the sampling transistor T3, the storage capacitor Cst may sample and store the threshold voltage Vth of the drive transistor DT and provide a data voltage compensated for the threshold voltage to the second node N2 of the drive transistor DT. The storage capacitor (Cst) can charge and hold the difference voltage between the first power supply voltage (VDD) and the data voltage (Vdata) compensated for the threshold voltage (Vth) of the driving transistor (DT) to a target voltage, and can provide the held target voltage as the driving voltage of the driving transistor (DT).

[0095] The driving transistor (DT, first transistor) may have a gate electrode connected to the second node (N2), a first source / drain electrode connected to the first node (N1), and a second source / drain electrode connected to the third node (N3). The driving transistor (DT) may control the amount of current flowing to the light emitting element (OLED) through the light emitting control transistor (T6) according to the target voltage charged in the storage capacitor (Cst), thereby controlling the light emitting intensity of the light emitting element (EL).

[0096] The driving transistor (DT) according to one embodiment is any one of the driving transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) having the above-mentioned dummy holes, and may have a large critical voltage fluctuation (ΔVth) due to temperature.

[0097] The light emitting element (OLED) may include an anode connected to the third node of the driving transistor (DT) via the light emitting control transistor (T6), a cathode connected to a second power supply line 52 that supplies a second power supply voltage (VSS), and an organic light emitting layer between the anode and the cathode. The light emitting element (EL) may emit light with a brightness proportional to the amount of driving current supplied from the driving transistor (DT) via the light emitting control transistor (T6).

[0098] 1 and 7, the first to fourth gate lines 31, 32, 33, and 34 can be driven by a scan driver included in the gate driver 200, and the fifth gate line 35 can be driven by a light-emitting control driver included in the gate driver 200. The data voltage (Vdata) is supplied from the data driver 300, and the first power supply voltage (VDD), the second power supply voltage (VSS), the first initialization voltage (Vinit), the second initialization voltage (VAR), and the third initialization voltage (Vobs) can be supplied from the power management circuit 700.

[0099] 8A to 8D are diagrams illustrating layout structures of sub-pixels according to a comparative example and one embodiment.

[0100] Specifically, the subpixels shown in Figures 8A to 8D illustrate the layout of a first active layer, a first gate metal layer, an upper metal layer, a second active layer, a second gate metal layer, and a first source / drain metal layer arranged in a circuit element layer in a display panel, and the layout of the second source / drain metal layer of the circuit element layer and the light-emitting element layer arranged on the circuit element layer are omitted.

[0101] 8A to 8D, the pixel circuit of the sub-pixel according to the comparative example and the embodiment may include the driving transistor (DT) shown in FIG. 7, a plurality of transistors (T2 to T8), and a storage capacitor (Cst).

[0102] The first initialization voltage line 41 supplying the first initialization voltage (Vini), the fourth gate line 34 supplying the fourth scan signal (Scan4), the second gate line 32 supplying the second scan signal (Scan2), the first gate line 31 supplying the first scan signal (Scan1), the first power supply line 51 supplying the first power supply voltage (VDD), the fifth gate line 35 supplying the light emitting control signal (EM), the third scan line 33 supplying the third scan signal (Scan3), the third initialization voltage line 43 supplying the third initialization voltage (Vobs), and the second-1st and second-2nd initialization voltage lines 42r and 42gb supplying the second-1st and second-2nd initialization voltages (VARr and VARgb), respectively, may extend in the first direction (X) and be spaced apart in the second direction (Y). A redundancy line (WDR) extending in the first direction (X) for dark spot repair may be further disposed between the fifth gate line 35 and the third scan line 33.

[0103] In one embodiment, the driving transistor (DT), the switching transistor (T2), the operation control transistor (T5), the light emitting control transistor (T6), the second initialization transistor (T7), and the third initialization transistor (T8) may include a first active layer (ACT) made of LTPS and integrally connected thereto.

[0104] In one embodiment, the sampling transistor (T3) and the first initialization transistor (T4) may include a second active layer (OACT) made of an oxide semiconductor and integrally connected thereto.

[0105] In one embodiment, the driving transistor (DT) and the plurality of transistors (T2 to T8) of the pixel circuit may include an active layer made of LTPS or may include an active layer made of an oxide semiconductor.

[0106] The third scan line 33, including the gate electrode (GE1) of the drive transistor (DT), the first capacitor electrode (C1) of the storage capacitor (Cst), the gate electrode (GE5) of the operation control transistor (T5), the gate electrode (GE6) of the light-emitting control transistor (T6), and the gate electrodes (GE7, GE8) of the second and third initialization transistors (T7, T8), can be provided as a first gate metal layer on the first active layer (ACT).

[0107] The second capacitor electrode (C2) of the storage capacitor (Cst), the sampling transistor (T3), and the light-shielding electrodes 112, 114 of the first initialization transistor (T4) may be provided as an upper metal layer on the first gate metal layer.

[0108] The lower line 103 of the first gate line 31 including the gate electrode (GE3) of the sampling transistor (T3) and the gate electrode (GE4) of the first initialization transistor (T4) can be provided as a second gate metal layer on the second active layer (OACT).

[0109] The first initialization voltage line 41, the fourth gate line 34, the second gate line 32, the upper line 104 of the first gate line 31, the first power supply line 51, the fifth gate line 35, the third scan line 33 supplying the third scan signal (Scan3), the third initialization voltage line 43, the 2-1 and 2-2 initialization voltage lines 42r, 42gb, and the connecting electrodes 102, 105, 106, and 107 can be provided as a first source / drain metal layer on the second gate metal layer.

[0110] A driving transistor (DT) and a storage capacitor (Cst) may be disposed between the fourth gate line 34 and the fifth gate line 35. The driving transistor (DT) and the storage capacitor (Cst) may overlap in the third direction (Z), and the first power line 51 may overlap the driving transistor (DT) and the storage capacitor (Cst) in the third direction (Z).

[0111] The driving transistor (DT, first transistor) may include a first channel (CH1), a first-1st source / drain electrode (SD11), and a first-2nd source / drain electrode (SD12) disposed in the first active layer (ACT), and a first gate electrode (GE1) overlapping the first channel (CH1) in the third direction (Z). The first gate electrode (GE1) may be connected to the connecting electrode 105 via the second node (N2) and a contact hole 64. The connecting electrode 105 may be connected to the sampling transistor (T3, third transistor) and the first initialization transistor (T4, fourth transistor) via a contact hole 65. The first-1st source / drain electrode (SD11) may be connected to the fifth-1st source / drain electrode (SD51) of the operation control transistor (T5, fifth transistor) and to the second-2nd source / drain electrode (SD22) of the switching transistor (T2, second transistor) via the first node (N1). The first and second source / drain electrodes SD12 may be connected to the sampling transistor T3 and the light emitting control transistor T6 (sixth transistor) through a third node N3.

[0112] The storage capacitor Cst may include a first capacitor electrode C1 integrally disposed with the first gate electrode GE1 of the driving transistor DT and a second capacitor electrode C2 overlapping the first capacitor electrode C1 in the third direction Z. The second capacitor electrode C2 may be connected to the first power line 51 through a contact hole 70.

[0113] The switching transistor (T2, second transistor) may include a second channel (CH2) disposed in the first active layer (ACT), a second-first source / drain electrode (SD21), a second-second source / drain electrode (SD22), and a second gate electrode (GE2) overlapping the second channel (CH2) in the third direction (Z). The second gate electrode (GE2) may be connected to a second gate line 32 overlapping in the third direction (Z) through a contact hole 62. The second-first source / drain electrode (SD21) may be connected to a data line 53 (FIG. 7) disposed on the second source / drain metal layer through a contact hole 61 and a connecting electrode 102. The second-second source / drain electrode (SD22) may be connected to a first-first source / drain electrode (SD11) of the driving transistor (DT) through a first node (N1).

[0114] The operation control transistor (T5, fifth transistor) includes a fifth channel (CH5) disposed in the first active layer (ACT), a fifth-1st source / drain electrode (SD51), a fifth-2nd source / drain electrode (SD52), and a fifth gate electrode (GE5) overlapping the fifth channel (CH5) in the third direction (Z). The fifth gate electrode (GE5) may be connected to the fifth gate line 32 through a contact hole 72. The fifth-1st source / drain electrode (SD51) may be connected to the first-1st source / drain electrode (SD11) of the driving transistor (DT) through a first node (N1). The second-2nd source / drain electrode (SD22) may be connected to the first power line 51 through a contact hole 71.

[0115] The light-emitting control transistor (T6, sixth transistor) includes a sixth channel (CH6), a sixth-1st source / drain electrode (SD61), and a sixth-2nd source / drain electrode (SD62) disposed in the first active layer (ACT), and a sixth gate electrode (GE6) overlapping the sixth channel (CH6) in the third direction (Z). The sixth gate electrode (GE6) may be connected to the fifth gate line 32 through a contact hole 72. The sixth-1st source / drain electrode (SD61) may be connected to the first-2nd source / drain electrode (SD12) of the driving transistor (DT) through a third node (N3). The sixth-2nd source / drain electrode (SD62) may be connected to the anode electrode of the light-emitting element (OLED, FIG. 7) through a contact hole 73 and a connecting electrode 107.

[0116] The third initialization transistor (T8, 8th transistor) may include an 8th channel (CH8), an 8-1st source / drain electrode (SD81), an 8-2nd source / drain electrode (SD82) disposed in the first active layer (ACT), and an 8th gate electrode (GE8) overlapping the 8th channel (CH8) in the third direction (Z). The 8th gate electrode (GE8) may be integrally connected to the third gate line 32. The 8-1st source / drain electrode (SD81) may be connected to the 5-2nd source / drain electrode (SD52) of the operation control transistor (T5). The 8-2nd source / drain electrode (SD82) may be connected to the third initialization voltage line 43 through a contact hole 74.

[0117] The second initialization transistor (T7, seventh transistor) includes a seventh channel (CH7), a seventh-first source / drain electrode (SD71), and a seventh-second source / drain electrode (SD72) disposed in the first active layer (ACT), and a seventh gate electrode (GE7) overlapping the seventh channel (CH7) in the third direction (Z). The seventh gate electrode (GE7) may be integrally connected to the third gate line 32. The seventh-first source / drain electrode (SD71) may be connected to the sixth-second source / drain electrode (SD62) of the emission control transistor (T6). The seventh-second source / drain electrode (SD72) may be connected to the second-second initialization voltage line 42gb through a contact hole 75.

[0118] The sampling transistor (T3) may include a third channel (CH3) disposed in the second active layer (OACT), a third-1 source / drain electrode (SD31), a third-2 source / drain electrode (SD32), and a third gate electrode (GE3) overlapping the third channel (CH3) in the third direction (Z). The third gate electrode (GE3) may be integrally formed with a lower line 103 of the first gate line 31 and may be connected to an upper line 104 of the first gate line 31 through a contact hole 63. The third-1 source / drain electrode (SD31) may be connected to a third node (N3) of the driving transistor (DT) through contact holes 68 and 69 and a connecting electrode 106. The third-2 source / drain electrode (SD32) may be connected to a second node (N2) of the driving transistor (DT) through contact holes 64 and 65 and a connecting electrode 105. The first light-shielding electrode 112 overlapping the sampling transistor T3 in the third direction (Z) may be connected to the upper line 104 of the first gate line 31 through a contact hole 163.

[0119] The first initialization transistor (T4, fourth transistor) may include a fourth channel (CH4), a fourth-1 source / drain electrode (SD41), and a fourth-2 source / drain electrode (SD42) disposed in the second active layer (OACT), and a fourth gate electrode (GE4) overlapping the fourth channel (CH4) in the third direction (Z). The fourth gate electrode (GE4) may be connected to the fourth gate line 34 through a contact hole 66. The fourth-1 source / drain electrode (SD41) may be connected to the second node (N2) of the driving transistor (DT) through contact holes 64 and 65 and a connecting electrode 105. The fourth-2 source / drain electrode (SD42) may be connected to the first initialization voltage line 41 through a contact hole 67. The third light-shielding electrode 114 overlapping the first initialization transistor (T4) in the third direction (Z) may be connected to the fourth gate line 34 through a contact hole 166.

[0120] Referring to FIG. 8A, the driving transistor (DT) of the subpixel according to the comparative example may have a structure without a dummy hole.

[0121] Referring to FIG. 8B, the driving transistor DT of the subpixel according to an embodiment may include one dummy hole 120 and one dummy electrode 122 overlapping the gate electrode GE1 in the third direction (Z).

[0122] Referring to FIG. 8C, the driving transistor (DT) of the subpixel according to an embodiment may include two dummy holes 124 and a dummy electrode 126 overlapping the gate electrode (GE1) in the third direction (Z).

[0123] 8D, the driving transistor (DT) of the subpixel according to one embodiment includes two dummy holes 124 and a dummy electrode 126 overlapping the gate electrode (GE1) in the third direction (Z), and may further include a plurality of contact holes (dummy holes) 69a, 73a, and 77 disposed in a region adjacent to the driving transistor (DT). For example, the number of contact holes 69a in the connecting electrode 106 connecting the sampling transistor (T3) and the third node (N3) of the driving transistor (DT) may be increased to two, and the number of contact holes 73a in the connecting electrode 107 connecting the light-emitting control transistor (T6) may be increased to two. Two dummy holes 77 may be further disposed in a protruding region protruding from the third initialization voltage line 43 in the second direction (Y).

[0124] The subthreshold swing factors (hereinafter referred to as S-factor values) of the drive transistors (DT) in the subpixels of the comparative example shown in FIG. 8A and the examples shown in FIGS. 8B to 8D, the critical voltages (Vth), and the temperature-dependent critical voltage fluctuation amounts (ΔVth) are shown in Table 1 below.

[0125] [Table 1]

[0126] Referring to Table 1, compared to the drive transistor (DT) without dummy holes shown in FIG. 8A, the drive transistor (DT) having dummy holes 120, 124, 69a, 73a, and 77 shown in FIGS. 8B to 8D shows that as the number of dummy holes 120, 124, 69a, 73a, and 77 increases, the S-factor value and the critical voltage variation (ΔVth) due to temperature increase, and the critical voltage (Vth) decreases.

[0127] FIG. 9 is a cross-sectional view illustrating a structure of a subpixel according to an embodiment.

[0128] Specifically, FIG. 9 illustrates the cross-sectional structure of the subpixel taken along the II' and II-II' cutting lines shown in FIG. 8C.

[0129] 8C and 9, a subpixel according to an embodiment may include a circuit element layer including a pixel circuit disposed on a substrate (SUB), a light emitting element layer including a light emitting element disposed on the circuit element layer, and an encapsulation layer (ENCAP) disposed on the light emitting element layer. The circuit element layer may include a driving transistor (DT), a switching transistor (T2), a sampling transistor (T3), a first initialization transistor (T4), an operation control transistor (T5), an emission control transistor (T6), a second initialization transistor (T7), a third initialization transistor (T8), and a storage capacitor (Cst).

[0130] In one embodiment, a touch sensor array including a plurality of touch electrodes may be further disposed on the encapsulation layer (ENCAP), and a color filter array including a color filter and a black matrix or a lens array may be further disposed on the touch sensor array.

[0131] FIG. 9 representatively shows the cross-sectional structures of the light-emitting control transistor (T6), the drive transistor (DT), the storage capacitor (Cst), and the sampling transistor (T3).

[0132] In one embodiment, the light-emitting control transistor (T6) and the driving transistor (DT) may include a first active layer (ACT) made of LTPS.

[0133] In one embodiment, the sampling transistor (T3) may include a second active layer (OACT) made of an oxide semiconductor. For example, the second active layer (OACT) may be made of an oxide semiconductor including at least one of an IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, ZTO (ZnSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, and ITZO (InSnZnO)-based. In one embodiment, the sampling transistor (T3) may include an active layer made of LTPS.

[0134] The substrate (SUB) may include a plastic substrate or a glass substrate. The plastic substrate may be made of a flexible material. For example, the substrate (SUB) may include at least one organic insulating material selected from the group consisting of acrylic resin, epoxy resin, siloxane resin, polyimide resin, and polyamide resin.

[0135] A lower buffer layer (MBF) may be disposed on the substrate (SUB). The lower buffer layer (MBF) may prevent impurities such as hydrogen from entering the first active layer (ACT) through the substrate (SUB). The lower buffer layer (MBF) may include an inorganic insulating material. For example, the lower buffer layer (MBF) may include an oxide-based insulating material such as silicon oxide (SiOx) or aluminum oxide (Al2O3). In one embodiment, a barrier layer may be further disposed between the substrate (SUB) and the lower buffer layer (MBF) to block the inflow of particles. The barrier layer may be a multi-barrier layer in which at least one organic insulating layer and at least one inorganic insulating layer are alternately stacked.

[0136] The drive transistor (DT) may include a first channel (CH1), a first-1 source / drain electrode (SD11) and a first-2 source / drain electrode (SD12) arranged in a first active layer (ACT), and a first gate electrode (GE1) overlapping the first channel (CH1) in the third direction (Z) with a first gate insulating layer (GI1) sandwiched therebetween.

[0137] The light-emitting control transistor (T6) may include a sixth channel (CH6) arranged in the first active layer (ACT), a sixth-1st source / drain electrode (SD61) and a sixth-2nd source / drain electrode (SD62), and a sixth gate electrode (GE6) overlapping the sixth channel (CH6) in the third direction (Z) with the first gate insulating layer (GI1) sandwiched therebetween.

[0138] The first-2 source / drain electrode (SD12) of the driving transistor (DT) and the sixth-1 source / drain electrode (SD61) of the light-emitting control transistor (T6) may be connected via a first active layer (ACT). The first gate electrode (GE1) of the driving transistor (DT) may be integrally formed with the first capacitor electrode (C1) of the storage capacitor (Cst).

[0139] The drive transistor (DT) may further include a dummy hole 124 penetrating a plurality of insulating layers including first and second upper buffer layers (ABF1, ABF2) stacked on the first gate electrode (GE1), a second gate insulating layer (GI2), and an interlayer insulating layer (ILD), and a dummy electrode 126 disposed on the interlayer insulating layer (ILD) and connected to the first gate electrode (GE1) through the dummy hole 124.

[0140] The gate insulating layers (GI1, GI2), upper buffer layers (ABF1, ABF2), and interlayer insulating layers (ILD) may include inorganic insulating materials such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0141] The storage capacitor (Cst) may include a first capacitor electrode (C1) connected to the first gate electrode (GE1) of the driving transistor (DT) and a second capacitor electrode (C2) overlapping in the third direction (Z) with a first upper buffer layer (ABF1) interposed therebetween. A second upper buffer layer (ABF2) may be disposed on the second capacitor electrode (C2).

[0142] The sampling transistor (T3) disposed on the second upper buffer layer (ABF2) may include a third channel (CH3) of the second active layer (OACT) disposed on the second upper buffer layer (ABF2), a third-1 source / drain electrode (SD31), a third-2 source / drain electrode (SD32), and a third gate electrode (GE3) overlapping the third channel (CH3) in the third direction (Z) with the second gate insulating layer (GI2) interposed therebetween. The sampling transistor (T3) may further include a light-shielding electrode 112 disposed between the first and second upper buffer layers (ABF1, ABF2) and overlapping the third channel (CH3) of the second active layer (OACT) in the third direction (Z).

[0143] An interlayer insulating layer (ILD) may be disposed on the sampling transistor T3. A third-1 source / drain electrode (SD31) of the sampling transistor T3 may be connected to a connecting electrode 106 disposed on the interlayer insulating layer (ILD) through a contact hole 68. A third-2 source / drain electrode (SD32) of the sampling transistor T3 may be connected to a connecting electrode 105 disposed on the interlayer insulating layer (ILD) through a contact hole 65, and the connecting electrode 105 may be connected to the first capacitor electrode C1 through a contact hole 64. A gate electrode GE3 of the sampling transistor T3 may overlap an upper line 104 of the first gate line 31 in the third direction.

[0144] The first gate line 31 may include a lower line 103 on the second gate insulating layer (GI2) and an upper line 104 disposed on the interlayer insulating layer (ILD) and overlapping the lower line 103 in the third direction.

[0145] The sixth-2nd source / drain electrode SD62 of the light-emitting control transistor T6 may be connected to the connection electrode 102 disposed on the interlayer insulating layer (ILD) through a contact hole 73.

[0146] The connecting electrode 102 of the light-emitting control transistor (T6) can be connected to the connecting electrode 92-3 arranged on the first planarization layer (PLN1) through the contact hole 83-2, and can be connected to the anode electrode (AE3) arranged on the second planarization layer (PLN2) through the contact hole 84-3.

[0147] A light emitting element layer including a light emitting element, a bank layer (BK), and a spacer (SP) can be disposed on the second planarization layer (PLN2).

[0148] The light-emitting element may include an anode electrode (first electrode) (AE3), a light-emitting stack (EML3), and a cathode electrode (second electrode) (CE) disposed on a second planarization layer (PLN2). The anode electrode (AE3) may be separated and independently disposed for each subpixel. The anode electrode (AE3) may be formed with a multi-conductive layer structure with high reflectivity. For example, the anode electrode (AE3) may be formed with a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or a stacked structure of aluminum tin oxide (APC) and ITO (ITO / APC / ITO). APC is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0149] The anode electrode (AE3) has an opening exposing the anode electrode (AE3) on the second planarization layer (PLN2), and a bank layer (BK) covering the edge of the anode electrode (AE3) can be disposed on the second planarization layer (PLN2). The opening of the bank layer (BK) can be defined as the light-emitting area (EA3), and the area where the bank layer (BK) is disposed can be defined as the non-light-emitting area. The bank layer (BK) surrounding the light-emitting area can be formed as a single layer or a double layer structure. A spacer (SP) having an opening wider than the opening of the bank layer (BK) can be further disposed on the bank layer (BK). The spacer (SP) can support a fine metal mask (FMM), which is an evaporation mask, during the formation of the light-emitting stack (EML3). The bank layer (BK) and the spacer (SP) can be formed of an organic insulating material. The bank layer (BK) can contain a light-shielding material to block light leakage between adjacent pixels and reduce reflection of external light.

[0150] The light-emitting stack (EML3) can be formed by stacking a hole control layer, a light-emitting layer, and an electron control layer in this order or the reverse order. The hole control layer can include at least a hole transport layer among a hole injection layer and a hole transport layer, and the electron control layer can include at least an electron transport layer among an electron transport layer and an electron injection layer.

[0151] The cathode electrode (CE) may be a common electrode disposed on the light-emitting stack (EML3) and connected along the surfaces of the bank layer (BK) and spacer (SP). The cathode electrode (CE) may be formed of a conductive material or a semi-transparent conductive material with high light transmittance. For example, the cathode electrode (CE) may be formed of a transparent conductive material such as ITO or IZO. The cathode electrode (CE) may be formed of a semi-transparent metal material such as magnesium (Mg), silver (Ag), or an alloy thereof. A capping layer may be further disposed on the cathode electrode (CE) to enhance the optical resonance and luminous efficiency of the light-emitting device.

[0152] An encapsulation layer (ENCAP) that seals the light emitting element layer is disposed on the light emitting element layer, preventing moisture and oxygen from penetrating into the light emitting element and covering particles to prevent them from flowing. The encapsulation layer (ENCAP) may have a laminated structure of first and second inorganic encapsulation layers (PAS1, PAS2) and an organic encapsulation layer (PCL) disposed between the first and second inorganic encapsulation layers (PAS1, PAS2). The inorganic encapsulation layers (PAS1, PAS2) can prevent moisture and oxygen from penetrating from the outside. The organic encapsulation layer (PCL) can cover particles and buffer stress between layers when the display panel is bent.

[0153] FIG. 10 is a graph showing a comparison of temperature luminance sensitivities of the display devices according to the comparative example and the embodiment, and FIG. 11 is a graph showing a comparison of temperature color sensitivities of the display devices according to the comparative example and the embodiment.

[0154] In Fig. 10, the vertical axis represents the temperature luminance sensitivity (TLS), and in Fig. 11, the vertical axis represents the shift amount (Δu'v') of the white color coordinate corresponding to the temperature color sensitivity (TCS).

[0155] 10 and 11, the display device according to the comparative example may include drive transistors (DT) without dummy holes in the R, G, and B subpixels, as in the comparative example shown in FIG. 8A. In the comparative example, the threshold voltage variation (ΔVth) of the drive transistors (DT) of the R, G, and B subpixels due to temperature may be relatively low at approximately 7.7 mV / °C. As a result, in the display device according to the comparative example, the temperature luminance sensitivity (TLS) of the R, G, and B subpixels (1.19, 1.34, 4.50) and the temperature luminance sensitivity of white light (W) (TLS, 1.62) are relatively high. In particular, the temperature luminance sensitivity (TLS) of the B subpixel is relatively high (4.50), and the white color coordinate shift (Δu'v'=0.044) is also relatively high.

[0156] 8B, the display device according to the first embodiment includes a driving transistor (DT) having one dummy hole 120 in each of the R, G, and B subpixels. In the first embodiment, the threshold voltage variation (ΔVth) of the driving transistor (DT) of each of the R, G, and B subpixels due to temperature is about 10.6 mV / °C, which is higher than that of the comparative example (7.7 mV / °C). As a result, in the display device according to the first embodiment, the temperature luminance sensitivity (TLS) of each of the R, G, and B subpixels (0.92, 1.10, 2.20) and the temperature luminance sensitivity of white light (W) (TLS, 1.22) are reduced compared to the comparative example. In addition, in the display device according to the first embodiment, the difference between the temperature luminance sensitivity (TLS) of the R / G subpixels (0.92, 1.10) and the temperature luminance sensitivity (TLS, 2.20) of the B subpixel is reduced, and the white color coordinate shift (Δu'v' = 0.018) is also reduced compared to the comparative example (Δu'v' = 0.044).

[0157] In the display device according to the second embodiment, the R / G subpixels include a driving transistor (DT) having one dummy hole 120 as in the embodiment shown in FIG. 8B, and the B subpixel includes a driving transistor (DT) having two dummy holes 124 as in the embodiment shown in FIG. 8C. The temperature-dependent threshold voltage variation (ΔVth) of the driving transistor (DT) of the B subpixel is approximately 11.5 mV / °C, which is higher than the comparative example (7.7 mV / °C) and the temperature-dependent threshold voltage variation (10.6 mV / °C) of the driving transistor of the R / G subpixel. As a result, in the display device according to the second embodiment, the temperature luminance sensitivity (TLS) of each of the R / G / B subpixels (1.44, 1.59, 2.04) and the temperature luminance sensitivity of white light (W) (TLS, 1.71) are reduced compared to the comparative example. In addition, in the display device of the second embodiment, the difference between the temperature luminance sensitivity (TLS) of the R / G subpixels (1.44, 1.59) and the temperature luminance sensitivity (TLS, 2.04) of the B subpixel is reduced compared to the first embodiment, and the white color coordinate shift (Δu'v' = 0.009) is also reduced compared to the comparative example (Δu'v' = 0.044) and the first embodiment (Δu'v' = 0.018).

[0158] In the display device according to the third embodiment, the R / G subpixels include a drive transistor (DT) having one dummy hole 120 as shown in FIG. 8B , and the B subpixel includes a drive transistor (DT) having two dummy holes 124 as shown in FIG. 8D , and six dummy holes 69a, 73a, and 77 may be further included in the peripheral region of the drive transistor (DT). The temperature-dependent threshold voltage variation (ΔVth) of the drive transistor (DT) of the B subpixel is approximately 11.8 mV / °C, which is higher than the comparative example (7.7 mV / °C) and the temperature-dependent threshold voltage variation (10.6 mV / °C) of the drive transistor of the R / G subpixel. As a result, in the display device according to the third embodiment, the temperature luminance sensitivity (TLS) of each of the R / G / B subpixels (1.18, 1.22, and 1.87) and the temperature luminance sensitivity of white light (W) (TLS, 1.36) are reduced compared to the comparative example. In addition, in the display device of the third embodiment, the difference between the temperature luminance sensitivity (TLS) of the R / G subpixels (1.18, 1.22) and the temperature luminance sensitivity of the B subpixel (TLS, 1.87) is reduced compared to the first embodiment, and the white color coordinate shift (Δu'v' = 0.010) is also reduced compared to the comparative example (Δu'v' = 0.044) and the first embodiment (Δu'v' = 0.018).

[0159] 12A to 12D are diagrams showing a comparison of white color coordinate variations due to temperature variations in display devices according to a comparative example and an embodiment.

[0160] 12A to 12D, the horizontal axis represents u' chromaticity, the vertical axis represents v' chromaticity, and shows white color coordinates according to temperature in the u'v' chromaticity coordinate system.

[0161] 12A, in the display device according to the comparative example, the R / G / B subpixels may include driving transistors (DT) without dummy holes, as in the comparative example shown in FIG. 8A, and the threshold voltage variation (ΔVth) of the driving transistors (DT) of the R / G / B subpixels due to temperature may be relatively low, at about 7.7 mV / °C. As a result, in the display device according to the comparative example, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels are relatively low, and the white color coordinate variation range due to temperature variation is relatively large. As a result, the variation range between the white color coordinate at room temperature (20°C) and the white color coordinate at high temperature (40°C) is also large, and the variation range between the white color coordinate at room temperature (20°C) and the white color coordinate at low temperature (10°C) is also large.

[0162] 12B, in the display device according to the first embodiment, the R / G / B subpixels may include a driving transistor (DT) having one dummy hole 120, as in the embodiment shown in FIG. 8B, and the threshold voltage variation (ΔVth) of the driving transistor (DT) of each of the R / G / B subpixels due to temperature is about 10.6 mV / °C, which is higher than that of the comparative example (7.7 mV / °C). As a result, in the display device according to the first embodiment, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels reduce the variation range of the white color coordinate due to temperature variation compared to the comparative example, and therefore the variation range of the white color coordinate between the room temperature (20°C) and the high temperature (40°C) and the room temperature (20°C) and the low temperature (10°C) are all reduced compared to the comparative example.

[0163] 12C, the R / G subpixels in the display device according to the first embodiment may include a driving transistor (DT) having one dummy hole 120 as in the embodiment shown in FIG. 8B, and the B subpixel may include a driving transistor (DT) having two dummy holes 124 as in the embodiment shown in FIG. 8C. The critical voltage variation (ΔVth) of the driving transistor (DT) of the B subpixel due to temperature is about 11.5 mV / °C, which is higher than the comparative example (7.7 mV / °C) and the critical voltage variation (10.6 mV / °C) of the driving transistor of the R / G subpixel due to temperature. As a result, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels in the display device of the second embodiment show that the range of variation in the white color coordinate due to temperature fluctuations is reduced compared to the comparative example and the first embodiment, and therefore the range of variation in the white color coordinate between room temperature (20°C) and high temperature (40°C), and the range of variation in the white color coordinate between room temperature (20°C) and low temperature (10°C) are both reduced compared to the comparative example and the first embodiment.

[0164] 12D, in the display device according to the third embodiment, the R / G subpixels may include a drive transistor (DT) having one dummy hole 120 as in the embodiment shown in FIG. 8B, and the B subpixel may further include six dummy holes (69a, 73a, 77) in a peripheral region of the drive transistor (DT) having two dummy holes 124 as in the embodiment shown in FIG. 8D. The critical voltage variation (ΔVth) of the drive transistor (DT) of the B subpixel due to temperature is about 11.8 mV / °C, which is higher than the comparative example (7.7 mV / °C) and the critical voltage variation (10.6 mV / °C) of the drive transistor of the R / G subpixel. In the display device according to the third embodiment, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels reduce the variation range of the white color coordinate due to temperature fluctuations compared to the comparative example and the first embodiment. As a result, it can be seen that the variation range of the white color coordinate at room temperature (20°C) and at high temperature (40°C), and the variation range of the white color coordinate at room temperature (20°C) and at low temperature (10°C) are all reduced compared to the comparative example and the first embodiment.

[0165] As described above, the display device according to one embodiment can reduce or minimize the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of sub-pixels by applying dummy holes to the insulating layer of the driving transistor to control the amount of change in the critical voltage of the driving transistor due to temperature.

[0166] In one embodiment, the display device can minimize the difference in brightness fluctuation due to temperature fluctuation between subpixels by applying different numbers or area ratios of dummy holes to the insulating layer of the subpixels depending on the aperture ratio (area) of the light-emitting element or the brightness fluctuation characteristics of the light-emitting element due to temperature, thereby controlling the critical voltage fluctuation amount of the driving transistor due to temperature differently.As a result, it is possible to minimize the fluctuation in white color coordinates due to temperature fluctuation and improve optical quality.

[0167] The display device according to one embodiment can improve optical quality by controlling the temperature-dependent variation of the threshold voltage of the driving transistor to reduce or minimize the temperature brightness sensitivity and temperature color sensitivity of the sub-pixel, thereby providing improved image quality with low power consumption.

[0168] A display device according to one embodiment includes a first sub-pixel including a first light-emitting element that emits light of a first color and a first driving transistor that drives the first light-emitting element, and a second sub-pixel including a second light-emitting element that emits light of a second color and a second driving transistor that drives the second light-emitting element, and the first driving transistor and the second driving transistor may have different dummy hole area ratios.

[0169] In a display device according to an embodiment, the area of ​​the dummy hole of the first driving transistor may be larger than the area of ​​the dummy hole of the second driving transistor.

[0170] In a display device according to an embodiment, the number of dummy holes in the first driving transistor may be greater than the number of dummy holes in the second driving transistor.

[0171] In the display device according to an embodiment, the first sub-pixel may further include a peripheral dummy hole disposed in the insulating layer around the first driving transistor.

[0172] According to an embodiment, the display device further includes a third sub-pixel including a third light-emitting element that emits light of a third color and a third driving transistor that drives the third light-emitting element, and the third driving transistor may have the same dummy hole area ratio as any one of the first and second driving transistors, or may have a dummy hole area ratio different from the first and second driving transistors.

[0173] In the display device according to an embodiment, each of the first to third driving transistors may further include a dummy electrode connected to the corresponding gate electrode through a corresponding dummy hole.

[0174] In the display device according to an embodiment, the dummy holes of each of the first to third driving transistors may be filled with an upper insulating layer.

[0175] In the display device according to an embodiment, the area of ​​each of the dummy holes may be the same as the area of ​​each of the contact holes disposed in the first to third sub-pixels.

[0176] In one embodiment of a display device, the first to third subpixels are blue, green, and red subpixels, respectively, and the area of ​​the dummy hole of the first driving transistor of the blue subpixel is larger than the area of ​​the dummy hole of the second driving transistor of the green subpixel and larger than the area of ​​the dummy hole of the third driving transistor of the red subpixel, and the area of ​​the dummy hole of the second driving transistor and the area of ​​the dummy hole of the third driving transistor may be the same.

[0177] In a display device according to one embodiment, the first to third subpixels are blue, green, and red subpixels, respectively, and the number of dummy holes in the first driving transistor of the blue subpixel may be greater than the number of dummy holes in the second driving transistor of the red subpixel and greater than the number of dummy holes in the third driving transistor of the green subpixel, and the number of dummy holes in the second driving transistor may be the same as the number of dummy holes in the third driving transistor.

[0178] A display device according to one embodiment includes a first sub-pixel including a first light-emitting element emitting light of a first color, a first driving transistor driving the first light-emitting element, and a first dummy hole overlapping with a first gate electrode of the first driving transistor; a second sub-pixel including a second light-emitting element emitting light of a second color, a second driving transistor driving the second light-emitting element, and a second dummy hole overlapping with the second gate electrode; and a third sub-pixel including a third light-emitting element emitting light of a third color, a third driving transistor driving the third light-emitting element, and a third dummy hole overlapping with a third gate electrode of the third driving transistor, wherein the area ratio of the first dummy hole is different from the area ratios of the second dummy hole and the third dummy hole, and the area ratio of the second dummy hole may be the same as or different from the area ratio of the third dummy hole.

[0179] In the display device according to an embodiment, the number of first dummy holes of the first driving transistor may be greater than the number of second dummy holes of the second driving transistor, and may be greater than the number of third dummy holes of the third driving transistor.

[0180] In a display device according to an embodiment, the area of ​​the first dummy hole of the first driving transistor may be larger than the area of ​​the second dummy hole of the second driving transistor, and may be larger than the area of ​​the third dummy hole of the third driving transistor.

[0181] In a display device according to an embodiment, the number or area of ​​the second dummy holes of the second driving transistor may be the same as the number or area of ​​the third dummy holes of the third driving transistor.

[0182] In the display device according to an embodiment, the areas of the first to third dummy holes may be the same as the areas of the contact holes disposed in the insulating layers of the first to third sub-pixels.

[0183] According to one embodiment, the display device further includes a first dummy electrode connected to the first gate electrode through a first dummy hole of the first driving transistor, a second dummy electrode connected to the second gate electrode through a second dummy hole of the second driving transistor, and a third dummy electrode connected to the third gate electrode through a third dummy hole of the third driving transistor, wherein the area of ​​the first dummy electrode is different from the areas of the second dummy electrode and the third dummy electrode, and the area of ​​the second dummy electrode may be the same as or different from the area of ​​the third dummy electrode.

[0184] In the display device according to an embodiment, the first to third dummy holes may be filled with an upper insulating layer.

[0185] In the display device according to an embodiment, the first sub-pixel may further include a plurality of peripheral dummy holes disposed in a plurality of insulating layers around the first driving transistor.

[0186] In the display device according to an embodiment, the first to third light emitting elements may have different aperture ratios.

[0187] In the display device according to an embodiment, the first to third light emitting elements may have different luminance fluctuation characteristics depending on the temperature.

[0188] In a display device according to one embodiment, the critical voltage fluctuation amount due to temperature of the first driving transistor is different from the critical voltage fluctuation amount due to temperature of the second driving transistor and the critical voltage fluctuation amount due to temperature of the third driving transistor, and the critical voltage fluctuation amount due to temperature of the second driving transistor may be the same as or different from the critical voltage fluctuation amount due to temperature of the third driving transistor.

[0189] In one embodiment, the display device may further include a plurality of transistors connected to the first to third driving transistors, respectively, and the first to third driving transistors and the plurality of transistors may include at least one active layer of a polysilicon semiconductor layer and an oxide semiconductor.

[0190] In each of the first to third subpixels of a display device according to one embodiment, at least one of the plurality of transistors and the corresponding driving transistor are polysilicon transistors including a polysilicon semiconductor layer, at least one of the plurality of transistors is an oxide transistor including an oxide semiconductor layer, the oxide transistor is arranged on at least one lower insulating layer arranged on the polysilicon transistor, and each of the first to third dummy holes can be provided to penetrate at least one insulating layer of the polysilicon transistor, at least one lower insulating layer on the polysilicon transistor, and at least one upper insulating layer on the oxide transistor.

[0191] In a display device according to one embodiment, each of the first to third driving transistors further includes first to third dummy electrodes respectively connected to the first to third gate electrodes via the first to third dummy holes, and the first to third dummy electrodes may be disposed on at least one upper insulating layer on the oxide transistor.

[0192] A display device according to one embodiment includes a first sub-pixel including a first light-emitting element emitting light of a first color, a first driving transistor driving the first light-emitting element, and at least one first dummy hole disposed in the first driving transistor, and a second sub-pixel including a second light-emitting element emitting light of a second color, a second driving transistor driving the second light-emitting element, and at least one second dummy hole disposed in the second driving transistor, and the first driving transistor and the second driving transistor may have different total opening areas of the dummy holes depending on the brightness variation characteristics of the first light-emitting element and the second light-emitting element due to temperature.

[0193] A display device according to one embodiment includes a first sub-pixel including a first light-emitting element emitting light of a first color, a first driving transistor driving the first light-emitting element, and at least one first dummy hole disposed in the first driving transistor, and a second sub-pixel including a second light-emitting element emitting light of a second color, a second driving transistor driving the second light-emitting element, and at least one second dummy hole disposed in the second driving transistor, and the first driving transistor and the second driving transistor may have different total opening areas of the dummy holes depending on the opening areas of the first light-emitting element and the second light-emitting element.

[0194] The display device according to the present specification may be applied to any electronic device, such as a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, an electronic organizer, an e-book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation system, a vehicle navigation system, a vehicle display device, a television, a wallpaper display device, a signage device, a game device, a notebook computer, a monitor, a camera, a video camera, and a home appliance.

[0195] The features, structures, effects, etc. described in the various examples of this specification are included in at least one example of this specification and are not necessarily limited to one example. Furthermore, the features, structures, effects, etc. exemplified in at least one example of this specification can be combined or modified in other examples by a person skilled in the art to which the technical ideas of this specification belong. Therefore, content related to such combinations and modifications should be interpreted as being included in the technical scope or scope of rights of this specification.

[0196] The present specification described above is not limited by the above-mentioned examples and the attached drawings, and various substitutions, modifications, and alterations are possible within the scope of the technical subject matter of the present specification, which will be apparent to those skilled in the art to which the present specification pertains. Therefore, the scope of the present specification is defined by the claims below, and all modifications and alterations derived from the meaning, scope, and equivalent concepts of the claims should be construed as being included in the scope of the present specification. [Explanation of symbols]

[0197] 100: Display panel 200: Gate driver 300: Data driver 400: Timing controller 500: Gamma voltage generator 700: Power management circuit 1000: Display device SUB: Substrate ACT: Active layer CH1: Channel SD11, SD12, SD21, SD22: Source / drain electrodes 11, 12: Contact holes 13, 23, 23a, 13b, 23b, 23c: Dummy holes SD14, SD15, SD23, SD24: Connected electrodes SD16, SD25: Dummy electrodes DT_SP1, DT_SP2, DTa_SP2, DTb_SP1, DTb_SP2, DTc_SP2, DT: drive transistors

Claims

1. a first sub-pixel including a first light-emitting element that emits light of a first color and a first driving transistor that drives the first light-emitting element; a second sub-pixel including a second light-emitting element that emits light of a second color and a second driving transistor that drives the second light-emitting element; At least one first dummy hole disposed in the first driving transistor; at least one second dummy hole disposed in the second driving transistor; A display device, wherein a total opening area of ​​at least one first dummy hole of the first driving transistor is different from a total opening area of ​​at least one second dummy hole of the second driving transistor.

2. The display device according to claim 1 , wherein a total opening area of ​​the at least one first dummy hole of the first driving transistor is larger than a total opening area of ​​the at least one second dummy hole of the second driving transistor.

3. The display device according to claim 1 , wherein the number of the at least one first dummy hole of the first driving transistor is greater than the number of the at least one second dummy hole of the second driving transistor.

4. The display device of claim 1 , wherein the first subpixel further comprises at least one peripheral dummy hole disposed in an insulating layer around the first driving transistor.

5. a third sub-pixel including a third light-emitting element emitting light of a third color and a third driving transistor driving the third light-emitting element; and at least one third dummy hole disposed in the third driving transistor; 2. The display device of claim 1, wherein the total opening area of ​​the at least one third dummy hole of the third driving transistor is the same as either one of the total opening area of ​​the at least one first dummy hole of the first driving transistor and the total opening area of ​​the at least one second dummy hole of the second driving transistor, or is different from the total opening area of ​​the at least one first dummy hole of the first driving transistor and the total opening area of ​​the at least one second dummy hole of the second driving transistor.

6. the first driving transistor further includes a first dummy electrode connected to the first gate electrode of the first driving transistor through the at least one first dummy hole; the second driving transistor further includes a second dummy electrode connected to the second gate electrode of the second driving transistor through the at least one second dummy hole; The display device of claim 5 , wherein the third driving transistor further comprises a third dummy electrode connected to the third gate electrode of the third driving transistor through the at least one third dummy hole.

7. 6. The display device according to claim 5, wherein the opening area of ​​each of the at least one first to third dummy holes is the same as the opening area of ​​each of the at least one contact hole arranged in the first to third sub-pixels.

8. the first to third subpixels are blue, green, and red subpixels, respectively; a total opening area of ​​at least one first dummy hole of the first driving transistor of the blue subpixel is larger than a total opening area of ​​at least one second dummy hole of the second driving transistor of the green subpixel and is larger than a total opening area of ​​at least one third dummy hole of the third driving transistor of the red subpixel; The display device of claim 5 , wherein a total opening area of ​​the at least one second dummy hole of the second driving transistor is equal to a total opening area of ​​the at least one third dummy hole of the third driving transistor.

9. the first to third subpixels are blue, green, and red subpixels, respectively; the number of the at least one first dummy hole in the first driving transistor of the blue subpixel is greater than the number of the at least one second dummy hole in the second driving transistor of the red subpixel and greater than the number of the at least one third dummy hole in the third driving transistor of the green subpixel; The display device of claim 5 , wherein the number of the at least one second dummy hole of the second driving transistor is the same as the number of the at least one third dummy hole of the third driving transistor.

10. a first sub-pixel including a first light-emitting element emitting light of a first color, a first driving transistor driving the first light-emitting element, and at least one first dummy hole overlapping a first gate electrode of the first driving transistor; a second sub-pixel including a second light-emitting element emitting light of a second color, a second driving transistor driving the second light-emitting element, and at least one second dummy hole overlapping with a second gate electrode of the second driving transistor; a third light-emitting element that emits light of a third color, a third driving transistor that drives the third light-emitting element, and a third sub-pixel that includes at least one third dummy hole that overlaps with a third gate electrode of the third driving transistor.

11. a total opening area of ​​the at least one first dummy hole is different from a total opening area of ​​the at least one second dummy hole and a total opening area of ​​the at least one third dummy hole; The display device of claim 10 , wherein a total opening area of ​​the at least one second dummy hole is the same as or different from a total opening area of ​​the at least one third dummy hole.

12. 12. The display device of claim 11, wherein the number of the at least one first dummy hole of the first driving transistor is greater than the number of the at least one second dummy hole of the second driving transistor and greater than the number of the at least one third dummy hole of the third driving transistor.

13. 12. The display device of claim 11, wherein the total opening area of ​​the at least one first dummy hole of the first driving transistor is larger than the total opening area of ​​the at least one second dummy hole of the second driving transistor and larger than the total opening area of ​​the at least one third dummy hole of the third driving transistor.

14. 12. The display device of claim 11, wherein the number or total opening area of ​​the at least one second dummy hole of the second driving transistor is the same as the number or total opening area of ​​the at least one third dummy hole of the third driving transistor.

15. 12. The display device of claim 11, wherein the opening area of ​​each of the first to third dummy holes is the same as the opening area of ​​each of at least one contact hole disposed in a plurality of insulating layers of the first to third subpixels.

16. a first dummy electrode connected to the first gate electrode of the first driving transistor through the at least one first dummy hole; a second dummy electrode connected to the second gate electrode of the second driving transistor through the at least one second dummy hole; a third dummy electrode connected to the third gate electrode of the third driving transistor through the at least one third dummy hole, an area of ​​the first dummy electrode is different from an area of ​​the second dummy electrode and an area of ​​the third dummy electrode; The display device of claim 11, wherein an area of ​​the second dummy electrode is the same as or different from an area of ​​the third dummy electrode.

17. 12. The display device of claim 11, wherein the at least one first to third dummy hole is filled with an upper insulating layer of the first to third gate electrodes.

18. The display device of claim 11 , wherein the first subpixel further comprises a plurality of peripheral dummy holes disposed in a plurality of insulating layers around the first driving transistor.

19. The display device of claim 11, wherein the first, second, and third light emitting elements have different aperture ratios.

20. The first to third light-emitting elements have different luminance fluctuation characteristics depending on the temperature, or a critical voltage fluctuation amount due to temperature of the first driving transistor is different from a critical voltage fluctuation amount due to temperature of the second driving transistor and a critical voltage fluctuation amount due to temperature of the third driving transistor; The display device of claim 11, wherein a critical voltage variation amount due to temperature of the second driving transistor is the same as or different from a critical voltage variation amount due to temperature of the third driving transistor.

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