Display device

Abstract

To reduce the power consumption of a display device with a simple configuration and operation.SOLUTION: A display device includes an input device, and controls the input of an image signal to a driving circuit in response to an image operation signal output from the input device. Specifically, the input frequency of the image signal while the input device is not operated is set lower than the input frequency of the image signal while the input device is operated. This can suppress the deterioration (deterioration in display quality) of display while the display device is used, and reduce the power consumption while the display device is not used.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device that can control input of an image signal to a pixel unit. This relates to a possible display device. [Background technology]

[0002] Active matrix display devices are becoming popular. and a driver circuit for controlling the display of an image in the display section. In the pixel section, image signals input to a plurality of pixels arranged in a matrix are transmitted by a driving circuit. The display is controlled by this.

[0003] In recent years, interest in the global environment has increased, and the development of low-power consumption display devices has been attracting attention. For example, Patent Document 1 discloses a technique for reducing power consumption in a liquid crystal display device. Specifically, during a pause period in which all scanning lines and data signal lines are in a non-selected state, The data signal line is electrically disconnected from the data signal driver and placed in a high impedance state (unreliable). The present invention discloses a liquid crystal display device in which the liquid crystal display device is in a constant state, a floating state, or a floating state. . [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-312253 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in order to realize the liquid crystal display device disclosed in Patent Document 1, This requires complicating the configuration and operation of the drive circuit that constitutes the device.

[0006] In view of the above-described problems, one embodiment of the present invention provides a display device that can be easily configured and operated. One of the objectives is to reduce power consumption. [Means for solving the problem]

[0007] One of the above-mentioned problems is that the display device is provided with an input device, and the display device is provided with an input device. This can be solved by controlling the input of the image signal to the driver circuit in accordance with the image operation signal.

[0008] That is, one embodiment of the present invention is a method in which a driver circuit controls input of an image signal to a pixel portion. The display device displays an image by using an input device that outputs an image operation signal and a front a signal detection circuit for detecting the image operation signal and outputting a detection signal; a signal generating circuit to which the reference image signal is input and which generates a signal obtained by extracting a part of the reference image signal; a signal extraction circuit that outputs an extracted image signal, and a first relay that receives the detection signal. a signal detection circuit and a second relay circuit, and the image operation signal is detected by the signal detection circuit. When the reference image signal is output, the reference image signal input through the first relay circuit is When the image manipulation signal is not detected by the signal detection circuit, The extracted image signal input via the second relay circuit is selected as the image signal. The display device is characterized in that [Effects of the Invention]

[0009] A display device according to one embodiment of the present invention includes a driver circuit that outputs a signal in response to an operation of an input device. It is possible to select the image signal. Specifically, the image when the input device is not operated can be selected. The input frequency of the image signal is set lower than the input frequency of the image signal when the input device is operated. This prevents deterioration of the display (decrease in display quality) when the display device is used. This makes it possible to reduce power consumption when the device is not in use. [Brief explanation of the drawings]

[0010] [Figure 1] 1A to 1C illustrate a display device according to Embodiment 1. [Figure 2] 5A and 5B are flowcharts illustrating the display device according to the first embodiment. [Figure 3] 1A and 1B illustrate a display device according to Embodiment 1. [Figure 4] 1A to 1F illustrate a display device according to Embodiment 1. [Figure 5] 1A and 1B illustrate a display device according to Embodiment 1. [Figure 6] 1A to 1D illustrate a transistor according to Embodiment 2. [Figure 7] 1A to 1E illustrate a transistor according to Embodiment 3. [Figure 8] 10A and 10B illustrate a display device according to Embodiment 4. [Figure 9] 10A to 10D illustrate electronic devices according to Embodiment 5. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0012] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described. A display device that displays an image by controlling the input of an image signal to a pixel unit through a circuit. This will be described with reference to FIGS.

[0013] 1 is a block diagram showing the configuration of a display device according to the present embodiment. The image sensor includes a pixel section 10, a driving circuit 11 for controlling input of an image signal to the pixel section 10, and an image an input device 12 that outputs an operation signal; a processor 13 to which an image operation signal is input; A relay circuit ( The relay circuit (also called a switch circuit) 14 and the relay circuit (also called a switch circuit) 15 are provided. The image operation signal is output when the input device 12 is operated by the user. This is a signal that controls the display in the pixel unit 10. Specific examples include a keyboard, a mouse, and a touchpad.

[0014] Furthermore, the processor 13 detects an image manipulation signal output from the input device 12, A signal detection circuit 16 outputs a detection signal, and a reference image signal is generated based on an image operation signal or the like. a signal generation circuit 17 that receives a reference image signal and outputs an extracted image signal; The detection signal is a binary signal (an image manipulation signal for the processor 13). The reference image signal is a signal indicating whether the image is "input" or "not input." The extracted image signal is an image signal having a certain frame frequency, and a part of the reference image signal is extracted. For example, the reference image signal is a frame frequency (refresh rate). The image signal with a frame rate of 60 Hz (also called a frame rate) is applied, and the extracted image is The image signal has a frame frequency (also called refresh rate) of 1 Hz (frame rate Image signals with a frame rate of 1 fps can be applied. The period of the image signal for one frame of the reference image signal is the same for both the reference image signal and the extracted image signal. This is not a signal that shows one frame of image signal included in the signal for one second, but a reference image signal. The extracted image signal is the same as the signal for 1 / 60 seconds of the reference image signal. and periods when no signal is present.

[0015] The relay circuit 14 is a circuit for controlling the input of the reference image signal to the drive circuit 11. The relay circuit 15 is a circuit for controlling the input of the extracted image signal to the drive circuit 11. The operation of the relay circuit 14 and the relay circuit 15 is controlled by the detection signal. When the image manipulation signal is detected by the signal detection circuit 16, the reference When an image signal is input to the drive circuit 11 and the image operation signal is not detected, the relay circuit The extracted image signal is input to the driving circuit 11 via the pixel 15. The input signal is selected by the detection signal.

[0016] The operation of the display device shown in FIG. 1 will be described with reference to the flowcharts shown in FIGS. 2(A) and 2(B). In the display device shown in FIG. 1, the operation of the flowchart shown in FIG. The operation and the operation of the flowchart shown in FIG. 2(B) are performed in parallel.

[0017] As shown in FIG. 2A, in the display device shown in FIG. 1, first, the signal generating circuit 17 generates a reference image signal. Then, the signal detection circuit 16 detects the image signal input from the input device 12. When the image manipulation signal is detected, the reference image signal is input to the driving circuit 11. When the image operation signal is not detected by the signal detection circuit 16, the drive circuit 1 for the reference image signal The input to 1 is cut off by relay circuit 14.

[0018] 2B, in the display device shown in FIG. 1, first, the signal generating circuit 17 Then, the signal extraction circuit 18 generates an extracted image signal based on the reference image signal. Then, when the signal detection circuit 16 detects an image manipulation signal, The input of the image signal to the drive circuit is interrupted by the relay circuit 15. When the image manipulation signal is not detected in 16, the extracted image signal is input to the drive circuit 11. can be.

[0019] The display device shown in FIG. 1 performs these operations in parallel, so that the driving circuit 11 Linking the input image signal with the operation of the input device 12 (detection of the image operation signal) Specifically, when the input device 12 is operated by the user, the pixel A reference image signal is input to the unit 10 to display the image. When not operated, an extracted image signal can be input to the pixel unit 10 to display the image. This prevents deterioration of the display (decrease in display quality) when the display device is used. This makes it possible to control the power consumption and reduce power consumption when the device is not in use.

[0020] The relay circuit 14, the relay circuit 15, and the signal extraction circuit included in the display device shown in FIG. The circuit 18 may be a circuit having a function as a switch as shown in FIG. In this case, the relay circuits 14 and 15 are connected to the signal detection circuit 16. The signal extraction circuit 18 is configured to control switching in response to the detection signal. The switching is controlled periodically, independent of the detection signal. A switch is a switch that can control electrical connections. These include transistors, MEMS (microelectromechanical systems) switches, Examples include:

[0021] Figure 3(B) shows a concrete example of the operation of each circuit when it is considered as a switch. As described above, the detection signal output from the signal detection circuit 16 is generated based on the user's operation. Therefore, the detection signal is generated based on the state in which the image manipulation signal is detected. The state is indeterminate (Detect) or not detected (Not Detected, ND). The relay circuit 14 and the relay circuit 15 are connected to the relay circuit 14 in response to the change in the detection signal. Specifically, the relay circuit 14 functions as a switch that switches in response to the During the period when the image operation signal is detected (Detect), the signal is turned on (On). During the period when the signal is not detected (ND), the device is in the off state (Off). On the other hand, the relay circuit 15 detects the image operation signal (Detect During the period, the signal is in the off state (Off) and is not detected (Not Detected). d, ND), it functions as a switch that is in the ON state (On).

[0022] As described above, the extracted image signal output from the signal extraction circuit 18 is the reference image signal. Therefore, the extracted image signal is a signal obtained by extracting a part of the image signal. It is possible to generate the reference image signal by selectively outputting the input reference image signal. In other words, if the signal extraction circuit 18 functions as a switch that performs appropriate switching, the extraction In FIG. 3B, the signal extraction circuit 18 periodically generates an output image signal. An example of a switch that is in the on state (On) during periods T1, T3, and T5 Of course, in the periods T1, T3, and T5, the reference image signal The signal and the extracted image signal are the same image signal. The periods T3 and T5 are of the same length. During the periods T2, T4, and T6, the extracted image signal is The impedance state (Z) is reached.

[0023] 3B, the relay circuit 14, the relay circuit 15, and The input signal to the drive circuit 11 when the signal extraction circuit 18 is operating is also shown. The input signals to the drive circuit 11 will now be described in detail for each period.

[0024] During the period t1, an image signal is input to the driving circuit 11. The signal is a reference image signal input via a relay circuit 14. The input to circuit 11 results from the detection of an image manipulation signal in signal detection circuit 16.

[0025] During the period t2, no image signal is input to the driving circuit 11. In this case, the signal detection circuit 16 does not detect the image operation signal, and in the period t2, This is due to the signal extraction circuit 18 functioning as a switch that is in the off state (Off). Note that only when the above-mentioned state is reached, an image signal is input to the driving circuit 11. I can't.

[0026] During the period t3, an image signal is input to the driving circuit 11. The signal is an extracted image signal input via a relay circuit 15. The input to the circuit 11 is that no image manipulation signal is detected in the signal detection circuit 16, and During the period t3, the signal extraction circuit 18 functions as a switch that is in the on state (On). This is due to the fact that

[0027] During period t4, no image signal is input to the drive circuit 11 (see the description of period t2). .

[0028] In period t5, an image signal is input to the driving circuit 11 (see the description of period t1).

[0029] In period t6, an image signal is input to the driving circuit 11 (see the description of period t3).

[0030] During period t7, no image signal is input to the driving circuit 11 (see the description of period t2). .

[0031] The display device shown in FIGS. 3A and 3B receives an image operation signal output from the input device 12. a signal detection circuit 16 that detects a signal and outputs it as a binary signal; Two switches (relay circuit 14 and relay circuit 1) whose switching is controlled by a signal 5) and a switch (signal extraction circuit 18) whose switching operation is set in advance. This is a display device that can reduce power consumption. The display device is a display device that can reduce the power consumption of the display device by a simple configuration and operation. It is a display device.

[0032] In addition, in FIG. 3B, the input signal to the drive circuit 11 changes simultaneously with the change in the detection signal. The configuration is shown, but the time from when the detection signal changes to when the input signal to the drive circuit 11 changes is A grace period may be provided between the two. This can prevent a decrease in display quality. Yes, it is possible. The reasons for this are explained below.

[0033] As mentioned above, the image signal has a specific frame frequency. For example, For an image signal of several 60 Hz, an image signal of 1 / 60 seconds (approximately 0.0167 seconds) can be used. An image is formed in the pixel section 10. On the other hand, the detection signal is is an asynchronous signal. Therefore, the input signal to the drive circuit 11 changes at the same time as the detection signal changes. In this case, the input of the image signal may be interrupted during the formation of an image. As a result, the display quality of the display device may be reduced. Among the operations shown in 3(B), the above problem occurs at the boundary between period t1 and period t2. may occur.

[0034] For example, as shown in FIG. 4(A), the signal detection circuit 16 periodically detects the image operation signal. The detection signal is input to a signal detection unit 21 that outputs the detection signal, and a latch unit 22 that receives the detection signal. By configuring the latch unit 2 in this way, it is possible to provide the grace period. 2 is a signal that is input discontinuously and the output signal is controlled based on the input signal, and the output signal is continuously It is a circuit that can output (hold the output signal). In the signal detection circuit 16 shown in FIG. 1, the output signal of the latch section 22 serves as the detection signal.

[0035] The operation of the signal detection circuit 16 shown in FIG. 4(A) will be described with reference to FIG. 4(B). In the signal detection circuit 16 shown in A), each of the frame periods F1 to F8 is started. At the timing when the image manipulation signal starts, the image manipulation signal is detected and the result of the detection is output to the latch unit 22. As a result, in the middle of the frame period (in the middle of the frame period F4 in FIG. 4(B)), Even if the input of the image control signal is interrupted, the timing at which the detection signal changes is automatically It is possible to set this to coincide with the start of the frame period.

[0036] Furthermore, even if the input period of the image operation signal is shorter than the frame period, As shown in FIG. 1, the signal detection circuit 16 receives a memory section 23 and outputs an image operation signal to the memory section 23. a signal detector 21 that detects the signal and outputs a detection signal; By configuring the image manipulation signal to include a latch section 22, the input of the image manipulation signal is not missed. It is possible to control the image signals input to the drive circuit 11. 3 is a circuit capable of storing image manipulation signals for a specific period. (D) is a diagram showing a specific example of the above content.

[0037] 4A and 4C, the output signal of the latch section 22 is held for a certain period of time. After the detection signal is output from the latch section 22, the output signal is reset (the detection signal is reset to the value when the image operation signal is detected). A reset unit 24 is provided to change the state of the detector to a Not Detected (ND) state. It may be configured as follows (see FIGS. 4(E) and 4(F)).

[0038] Furthermore, the above-mentioned problem (the input of the image signal is interrupted during the formation of one image) In order to prevent such problems from occurring, the generation of the extracted image signal in the signal extraction circuit 18 is also performed based on the standard. It is preferable to take into consideration the frame frequency of the image signal. The ON state is set to the ON state at the same time as the start of the frame period, and the ON state is set to the ON state for the same period as the frame period or It is preferable that the circuit functions as a switch that maintains a period that is an integer multiple of the frame period. .

[0039] As shown in FIG. 5A, the pixel section 10, the drive circuit 11, the relay circuit 14, and the relay The pixel section 10 and the driver circuit 15 can be formed on the same substrate 30. A part of the drive circuit 11, the relay circuit 14, and the relay circuit 15 are formed on the same substrate. As shown in FIG. 5(B), the drive circuit 11 may be connected to the relay circuit 14 and the relay It is also possible to configure the circuit 15. In the configuration shown in FIG. In this case, the pixel section 10 and the driving circuit 11 can be formed on the same substrate. It is also possible to form the unit 10 and part of the driving circuit 11 on the same substrate.

[0040] In addition, the above-described display device has been described as having a configuration in which only the input of image signals is controlled. However, various control signals (start pulse (SP), clock The inputs to the driver circuit 11 (clock (CK), power supply potential (Vdd), power supply potential (Vss), etc.) It is also possible to configure this to be performed by the relay circuit 14 and the relay circuit 15.

[0041] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0042] (Embodiment 2) In this embodiment mode, a detailed structure of the display device shown in Embodiment 1 will be described. Specifically, an example of a transistor constituting a display device will be described with reference to FIG. The transistor described in this embodiment is provided in each pixel of the display device described in Embodiment 1. The transistor is preferably used to control the input of an image signal.

[0043] The transistor 410 shown in FIG. 6A is a bottom-gate transistor. It is also called an inverted staggered transistor.

[0044] The transistor 410 includes a gate electrode layer 401, a gate electrode layer 402, a gate electrode layer 403, a gate electrode layer 404, a gate electrode layer 405, a gate electrode layer 406, a gate electrode layer 407, a gate electrode layer 408, a gate electrode layer 409 ...10, a gate electrode layer 411, a gate electrode layer 412, a gate electrode the insulating layer 402, the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b. 05b. In addition, an insulating film 405b is stacked on the oxide semiconductor layer 403 to cover the transistor 410. A protective insulating layer 409 is further formed on the insulating layer 407. do.

[0045] The transistor 420 shown in FIG. 6B is a channel-protective transistor (also called a channel-stop transistor). It is one of the bottom gate structures known as inverted staggered transistors.

[0046] The transistor 420 includes a gate electrode layer 401, a gate electrode layer 402, a gate electrode layer 403, a gate electrode layer 404, a gate electrode layer 405, a gate electrode layer 406, a gate electrode layer 407, a gate electrode layer 408, a gate electrode layer 409 ...10, a gate electrode layer 411, a gate electrode layer 412, a gate electrode a gate insulating layer 402, an oxide semiconductor layer 403, and a channel formation region of the oxide semiconductor layer 403. The insulating layer 427 serving as a channel protection layer, the source electrode layer 405a, and the drain electrode layer 405b are A protective insulating layer 409 is formed to cover the transistor 420. There are.

[0047] The transistor 430 shown in FIG. 6C is a bottom-gate transistor. A gate electrode layer 401, a gate insulating layer 402, a source The drain electrode layer 405a, the drain electrode layer 405b, and the oxide semiconductor layer 403 are included. An insulating layer 407 is provided to cover the transistor 430 and to be in contact with the oxide semiconductor layer 403. A protective insulating layer 409 is further formed on the insulating layer 407 .

[0048] In transistor 430, gate insulating layer 402 is connected to substrate 400 and gate electrode layer 404. The source electrode layer 405a and the drain electrode layer 405b are provided on the gate insulating layer 402 in contact with each other. The gate insulating layer 402 and the source electrode layer 405b are provided in contact with each other. An oxide semiconductor layer 403 is provided over the drain electrode layer 405a and the drain electrode layer 405b.

[0049] The transistor 440 shown in FIG. 6D is a top-gate transistor. The transistor 440 is formed on a substrate 400 having an insulating surface, an insulating layer 437, an oxide semiconductor The conductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, the gate insulating layer 40 2, including a gate electrode layer 401, a source electrode layer 405a, and a drain electrode layer 405b. The wiring layers 436a and 436b are provided adjacent to each other and are electrically connected to each other.

[0050] In this embodiment, as described above, the oxide semiconductor layer 403 is used as the semiconductor layer. The oxide semiconductor used for the compound semiconductor layer 403 is a quaternary metal oxide, In-Sn- Ga-Zn-O system, ternary metal oxides In-Ga-Zn-O system, In-Sn-Zn -O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, binary metal oxides In-Zn-O system, In-Ga-O system , Sn-Zn-O system, Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In- Uses Mg-O system, single-component metal oxides such as In-O system, Sn-O system, and Zn-O system The oxide semiconductor may contain SiO2. The n-Ga-Zn-O oxide semiconductor is an oxide containing at least In, Ga, and Zn. There is no particular limitation on the composition ratio. Elements other than In, Ga, and Zn may also be contained.

[0051] The oxide semiconductor layer 403 is formed of a material having the chemical formula InMO3(ZnO) m (m>0) A thin film containing M selected from Ga, Al, Mn, and Co can be used. It represents one or more metal elements. For example, M may be Ga, Ga and Al, Ga and Mn, Or Ga and Co.

[0052] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. A glass substrate such as aluminoborosilicate glass or aluminoborosilicate glass is used.

[0053] In the bottom-gate transistors 410, 420, and 430, the insulating film that serves as the base film The base film may be provided between the substrate and the gate electrode layer. It has a function of preventing the formation of silicon nitride film, silicon oxide film, silicon nitride oxide film, or oxide film. The silicon nitride film can be formed by a laminated structure of one or more films selected from the group consisting of silicon nitride films. .

[0054] The material of the gate electrode layer 401 is molybdenum, titanium, chromium, tantalum, or tungsten. Metallic materials such as aluminum, copper, neodymium, scandium, etc., or materials containing these as their main components The alloy material can be used to form a single layer or a stacked layer.

[0055] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. Silicon layer, silicon nitride layer, silicon oxynitride layer, silicon oxynitride layer, aluminum oxide layer, aluminum nitride layer, aluminum oxynitride layer, aluminum oxynitride layer, or oxide The hafnium layer can be formed as a single layer or a laminated layer. For example, the first gate insulating layer A silicon nitride layer (Si) with a thickness of 50 nm to 200 nm was formed by plasma CVD. N y (y>0)) is formed on the first gate insulating layer as a second gate insulating layer having a thickness of 5n. A silicon oxide layer (SiO x (x>0)) is stacked to form a gate insulator The layer is called a layer.

[0056] The conductive film used for the source electrode layer 405a and the drain electrode layer 405b is, for example, A Elements selected from I, Cr, Cu, Ta, Ti, Mo, and W, or elements listed above are used as components. The alloy film may be an alloy of the above elements or an alloy film of a combination of the above elements. A high melting point metal layer such as Ti, Mo, or W on either or both the top and bottom of a metal layer such as Cu In addition, in order to prevent the occurrence of hillocks and whiskers in the Al film, By using Al material with added elements (Si, Nd, Sc, etc.) that prevent heat buildup, heat resistance can be improved. It is possible to improve it.

[0057] The wiring layer 436a connected to the source electrode layer 405a and the drain electrode layer 405b, The conductive film such as 36b is also made of the same material as the source electrode layer 405a and the drain electrode layer 405b. can be used.

[0058] In addition, the source electrode layer 405a and the drain electrode layer 405b (arrangements formed in the same layer as this) The conductive film (including the wiring layer) may be formed of a conductive metal oxide. The oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (Zn O), indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO) or oxide silicon dioxide to these metal oxide materials It is possible to use one containing a recombinant.

[0059] The insulating layers 407, 427, and 437 are typically formed of a silicon oxide film, a silicon oxynitride film, or An inorganic insulating film such as an aluminum oxide film or an aluminum oxynitride film can be used. Cut.

[0060] The protective insulating layer 409 is made of a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, a nitride An inorganic insulating film such as an aluminum oxide film can be used.

[0061] In addition, a planarizing insulating layer is formed on the protective insulating layer 409 to reduce surface irregularities caused by the transistor. The planarization insulating film may be formed using a material such as polyimide, acrylic, or benzocyclobutene. In addition to the above organic materials, low dielectric constant materials (lo In addition, multiple insulating films made of these materials can be stacked. A planarization insulating film may be formed by layering the same.

[0062] The transistors 410, 420, 430, and 440 including the oxide semiconductor layer 403 are off-state transistors. The current value (off-state current value) in the off state is low. In some cases, it is possible to suppress the leakage of charge through the transistor. Therefore, by applying the transistor to each pixel, In other words, it is possible to reduce the frequency with which an image signal is input to the pixel. Even if the period of no input is prolonged, the display quality of the pixel in question will be degraded. As a result, the power consumption of the display device shown in the first embodiment can be reduced. This is because the transistors provided in each pixel in this embodiment are By applying the transistor of the embodiment, the frame frequency of the extracted image signal can be reduced. This is because it becomes possible to:

[0063] The transistors 410, 420, 430, and 440 each including the oxide semiconductor layer 403 Since a relatively high field effect mobility can be obtained, high speed driving is possible. By applying the transistor of this embodiment to each pixel, It is possible to provide high quality images.

[0064] In the display device described in Embodiment 1, the driver circuit and the relay circuit are formed of an oxide semiconductor. The transistors 410, 420, 430, and 440 are formed using the conductor layer 403. By expanding the range of application of the transistor, the manufacturing cost of the display device can be reduced. It is possible to do this.

[0065] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0066] (Embodiment 3) In this embodiment, an example of the transistor described in Embodiment 2 will be described with reference to FIGS. I will explain.

[0067] 7A to 7E show examples of cross-sectional structures of transistors. The transistor 510 shown in FIG. 6A has a bottom gate structure similar to the transistor 410 shown in FIG. It is an inverted staggered transistor with a gate structure.

[0068] The oxide semiconductor used for the semiconductor layer of this embodiment is an oxide semiconductor that does not contain hydrogen as an n-type impurity. It is removed from the body and highly purified to minimize the presence of impurities other than the main component of oxide semiconductors. This results in an I-type (intrinsic) oxide semiconductor or an oxide semiconductor that is as close to I-type (intrinsic) as possible. In other words, instead of adding impurities to make it I-type, impurities such as hydrogen and water are removed. By removing as many substances as possible, it is possible to obtain a highly purified I-type (intrinsic) semiconductor or something close to it. Therefore, the oxide semiconductor layer of the transistor 510 is highly purified. and an oxide semiconductor layer that is electrically i-type (intrinsic).

[0069] In addition, there are very few carriers (close to zero) in the highly purified oxide semiconductor. The carrier concentration is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Less than, more Preferably 1 x 10 11 / cm 3 is less than.

[0070] The off-state current of a transistor is reduced because there are very few carriers in the oxide semiconductor. The smaller the off-state current, the better.

[0071] Specifically, the transistor including the oxide semiconductor layer has a channel width of 1 μm. The off-state current density was 10 aA / μm (1×10 -17 A / μm) or less Furthermore, 1 aA / μm (1×10 -18 A / μm) or less, and even 10zA / μm (1 × 10 -20 It is possible to reduce the resistance to less than 1 / μm.

[0072] In addition, the transistor 510 including the above-described oxide semiconductor layer has a temperature dependence of on-state current. The off-state current remains very small.

[0073] Hereinafter, a process for manufacturing a transistor 510 on a substrate 505 will be described with reference to FIGS. 7(A) to 7(E). Explain the process.

[0074] First, a conductive film is formed on a substrate 505 having an insulating surface, and then a first photolithography is performed. A gate electrode layer 511 is formed by a deposition process. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0075] The substrate 505 having an insulating surface is the same as the substrate 400 shown in the second embodiment. In this embodiment mode, a glass substrate is used as the substrate 505.

[0076] An insulating film serving as a base film may be provided between the substrate 505 and the gate electrode layer 511. The film has a function of preventing the diffusion of impurity elements from the substrate 505, and is a silicon nitride film, an oxide film, etc. One or more films selected from a silicon film, a silicon nitride oxide film, and a silicon oxynitride film The laminated structure can be formed by the above.

[0077] The gate electrode layer 511 may be made of molybdenum, titanium, tantalum, tungsten, or Metallic materials such as aluminum, copper, neodymium, scandium, etc., or alloys containing these as their main components The material can be used to form a single layer or a laminate.

[0078] Next, the gate insulating layer 507 is formed over the gate electrode layer 511. is a silicon oxide layer, a silicon nitride layer, etc., formed by using a plasma CVD method or a sputtering method. layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer layer, aluminum oxide nitride layer, aluminum nitride oxide layer, or hafnium oxide layer Alternatively, it can be formed by laminating.

[0079] The oxide semiconductor of this embodiment is an i-type or substantially i-type oxide semiconductor obtained by removing impurities. Such a highly purified oxide semiconductor has low interface states and interface charges. Since the interface between the oxide semiconductor layer and the gate insulating layer is extremely sensitive to the Therefore, the gate insulating layer in contact with the highly purified oxide semiconductor is required to have high quality.

[0080] For example, high density plasma CVD using microwaves (for example, frequency 2.45 GHz) This is preferable because it allows the formation of a high-quality insulating layer that is dense and has a high dielectric strength. The close contact between the conductor and the high-quality gate insulating layer reduces the interface state and improves interface characteristics. This is because it can be made into something that is

[0081] Of course, if a good insulating layer can be formed as a gate insulating layer, sputtering is also possible. Other film-forming methods such as a coating method or a plasma CVD method can also be applied. The insulating layer is one in which the film quality of the gate insulating layer and the interface characteristics with the oxide semiconductor are modified by the process. In any case, it is necessary to have good film quality as a gate insulating layer, and also to have good acid resistance. Any material may be used as long as it can reduce the interface state density with the nitride semiconductor and form a good interface.

[0082] In addition, hydrogen, a hydroxyl group, and moisture are preferably contained in the gate insulating layer 507 and the oxide semiconductor film 530. In order to prevent the oxide semiconductor film 530 from being included in the oxide semiconductor film 530, sputtering was performed as a pretreatment for the formation of the oxide semiconductor film 530. The substrate 505 on which the gate electrode layer 511 is formed in the preheating chamber of the etching apparatus, or the gate insulating layer The substrate 505 on which the substrates 507 are formed is preheated to remove hydrogen, moisture, etc. adsorbed on the substrate 505. It is preferable to desorb and exhaust the impurities. The preheating process can be omitted. The heating is performed before the insulating layer 516 is formed. The same process may be carried out on the substrate 505 formed in step 1.

[0083] Next, a film having a thickness of 2 nm to 200 nm, preferably 5 nm, is formed on the gate insulating layer 507. An oxide semiconductor film 530 having a thickness of 30 nm or less is formed (see FIG. 7A).

[0084] Note that before the oxide semiconductor film 530 was formed by a sputtering method, argon gas was The reverse sputtering is performed by introducing the silicon dioxide to generate plasma, and the silicon dioxide adheres to the surface of the gate insulating layer 507. It is preferable to remove the powdery material (also called particles or dust) that is present in the sputtering. In this case, no voltage was applied to the target side, and a voltage was applied to the substrate side using an RF power supply in an argon atmosphere. This method involves applying pressure to form plasma near the substrate to modify the surface. Instead of the atmosphere, nitrogen, helium, oxygen, etc. may be used.

[0085] The oxide semiconductor used for the oxide semiconductor film 530 is the quaternary metal oxide semiconductor described in Embodiment 2. oxides, ternary metal oxides, binary metal oxides, In-O, Sn-O, Zn-O, etc. An oxide semiconductor can be used. The oxide semiconductor may contain SiO2. In this embodiment, the oxide semiconductor film 530 is an In—Ga—Zn—O-based metal oxide film. The cross section at this stage is shown in Figure 7(A). The oxide semiconductor film 530 is formed by heating under a rare gas (typically, argon) atmosphere with an oxygen atmosphere. It can be formed by sputtering in a nitrogen atmosphere or a mixed atmosphere of rare gas and oxygen. can.

[0086] Examples of targets for forming the oxide semiconductor film 530 by a sputtering method include For example, the composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [mol] (i.e. , In:Ga:Zn=1:1:0.5 [atom]) can be used. In:Ga:Zn=1:1:1[atom] or In:Ga:Zn=1:1:2[ A metal oxide target having a composition ratio of [atom] may be used. The filling rate of the pores is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with high conductivity, the deposited oxide semiconductor film is dense and become.

[0087] The oxide semiconductor film 530 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or water. It is preferable to use a high-purity gas from which impurities such as chlorines have been removed.

[0088] The substrate is held in a film-forming chamber maintained at a reduced pressure, and the substrate temperature is maintained at 100°C to 600°C. The temperature is preferably 200° C. or higher and 400° C. or lower. By forming the film while heating the substrate, The concentration of impurities contained in the formed oxide semiconductor film can be reduced. Damage caused by the ring is reduced. Also, hydrogen and moisture are removed while removing the remaining moisture in the film formation chamber. A sputtering gas from which the oxide has been removed is introduced, and an oxide semiconductor is deposited on the substrate 505 using the target. In order to remove the residual moisture in the film-forming chamber, an adsorption type vacuum pump, For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen atoms, water (H2O ) and other compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) are exhausted. Therefore, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0089] An example of the film formation conditions is a distance between the substrate and the target of 100 mm and a pressure of 0.6 P. a) DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere Furthermore, when a pulsed DC power supply is used, the powdery substances (particles, This is preferable because it can reduce dust (also called dust) and make the film thickness distribution uniform.

[0090] Next, the oxide semiconductor film 530 is subjected to a second photolithography process to form island-shaped oxide semiconductor films. The resist mask for forming the island-shaped oxide semiconductor layer is then applied to the insulating film. If the resist mask is formed by the inkjet method, the photoresist mask can be formed by the inkjet method. Since no mask is used, manufacturing costs can be reduced.

[0091] In addition, when forming a contact hole in the gate insulating layer 507, the process is performed in the oxide semiconductor. This can be done simultaneously with the processing of the membrane 530.

[0092] Note that the etching of the oxide semiconductor film 530 here can be performed by dry etching or wet etching. For example, wet etching of the oxide semiconductor film 530 may be performed. The etching solution used for etching is a solution made by mixing phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0093] Next, the oxide semiconductor layer is subjected to first heat treatment. The semiconductor layer can be dehydrated or dehydrogenated. The temperature is between 750°C and 750°C, or between 400°C and the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the devices, and the oxide semiconductor layer was heated to 450°C in a nitrogen atmosphere. After the heat treatment at 1000 K for 1 hour, the oxide semiconductor layer was cooled without being exposed to the air. Re-entry of hydrogen is prevented, and an oxide semiconductor layer 531 is obtained (see FIG. 7B).

[0094] The heat treatment device is not limited to an electric furnace, but may be a device that uses heat conduction from a heating element such as a resistance heating element or the like. A device for heating the object to be treated by thermal radiation may be provided. For example, a GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. For example, rare gases such as argon or nitrogen, which react with the material to be treated by heat treatment, are used. An inert gas that does not contain oxygen is used.

[0095] For example, as the first heat treatment, the material is placed in an inert gas heated to a high temperature of 650°C to 700°C. The substrate is moved in and heated for a few minutes, then the substrate is moved and heated to a high temperature inert gas. You can also perform GRTA from inside.

[0096] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or higher Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0097] After the oxide semiconductor layer is heated by the first heat treatment, the oxide semiconductor layer is heated in the same furnace with high-purity oxygen gas and high-purity oxygen gas. High purity N2O gas or ultra-dry air (dew point below -40°C, preferably below -60°C) It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or N2O gas introduced into the heat treatment device should be 6N or more. Preferably, the impurity concentration in the oxygen gas or N2O gas is 7N or more (i.e., 1 ppm or less). It is preferable to set the concentration of oxygen gas or N2O gas to 0.1 ppm or less. This is simultaneously reduced by the removal of impurities through dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component material that makes up the oxide semiconductor, The body layer is highly purified and electrically made to be type I (intrinsic).

[0098] The first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the The substrate is then removed and subjected to a photolithography process.

[0099] In addition to the above, the first heat treatment may be performed after the oxide semiconductor layer is formed. After the source electrode layer and the drain electrode layer are laminated on the body layer, or after the source electrode layer and the drain electrode layer are laminated on the body layer, After forming an insulating layer on the drain electrode layer, the insulating layer may be removed.

[0100] In addition, when forming a contact hole in the gate insulating layer 507, the process is performed in the oxide semiconductor. This may be done before or after the first heat treatment of the body membrane 530.

[0101] In addition, the oxide semiconductor layer is formed in two separate steps and heat-treated in two separate steps. Regardless of the material of the base material, such as oxide, nitride, or metal, a thick crystalline region, i.e., An oxide semiconductor layer having a crystal region with a c-axis oriented perpendicular to the film surface may be formed. a first oxide semiconductor film having a thickness of 3 nm to 15 nm; The temperature is 450°C to 850°C, preferably 550°C to 750°C, in a dry air atmosphere. The first heat treatment described below is performed to obtain a first crystal having a crystalline region (including plate-like crystals) in a region including the surface. Then, a second oxide semiconductor film having a thickness greater than that of the first oxide semiconductor film is formed. A conductive film is formed, and the first temperature is set to 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower. The heat treatment of step 2 is performed to grow crystals upward using the first oxide semiconductor film as a seed for crystal growth. The second oxide semiconductor film is entirely crystallized, resulting in an oxide film having a thick crystalline region. A compound semiconductor layer may be formed.

[0102] Next, a source electrode layer and a drain electrode layer are formed over the gate insulating layer 507 and the oxide semiconductor layer 531. A conductive film is formed to become the source electrode layer (including wiring formed in the same layer). The conductive film used for the electrode layer and the drain electrode layer may be the same as that used for the source electrode layer shown in Embodiment 2. The materials used for the drain electrode layer 405a and the drain electrode layer 405b can be used.

[0103] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After etching to form a source electrode layer 515a and a drain electrode layer 515b, The mask is removed (see FIG. 7(C)).

[0104] The third photolithography process involves the exposure of resist masks to ultraviolet light or KrF Laser light or ArF laser light is preferably used. The width of the gap between the bottom end of the electrode layer and the bottom end of the drain electrode layer determines the width of the transistor to be formed later. The channel length L is determined. When performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths ranging from a few nm to a few tens of nm. Let) is used to perform exposure when forming a resist mask in the third photolithography process. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is also possible to set the channel length L of the transistor to 10 nm or more and 1000 nm or less. This allows for faster circuit operation and, due to the extremely small off-state current, also reduces power consumption. In addition, the number of photomasks used in the photolithography process and the number of steps can be reduced. To reduce this, a multi-tone mask is used, which is an exposure mask that transmits light with multiple intensities. The etching process may be performed using a resist mask formed on the substrate. The resist mask thus formed has a shape with multiple film thicknesses, and by etching, it is possible to further Since the shape can be easily changed, it can be used in multiple etching processes to process different patterns. Therefore, at least two or more different types of masks can be produced using one multi-tone mask. Therefore, the number of exposure masks can be reduced. This reduces the number of steps required for photolithography, simplifying the process. This becomes possible.

[0105] Note that when the conductive film is etched, the oxide semiconductor layer 531 is etched and divided. However, it is desirable to optimize the etching conditions so that the conductive film does not It is possible to obtain a condition in which the oxide semiconductor layer 531 is etched and the oxide semiconductor layer 532 is not etched at all. It is difficult to etch the oxide semiconductor layer 531, and only a part of the oxide semiconductor layer 531 is etched during etching of the conductive film. The oxide semiconductor layer may have a groove (depression).

[0106] In this embodiment, a Ti film is used as the conductive film, and an In—Ga Since a Zn-O-based oxide semiconductor was used, ammonia hydrogen peroxide (ammonia) was used as an etchant. A mixture of nia, water, and hydrogen peroxide is used.

[0107] Then, plasma treatment using gases such as N2O, N2, or Ar is performed to remove the exposed The plasma treatment may be performed to remove adsorbed water or the like attached to the surface of the oxide semiconductor layer. When the insulating layer is formed, it becomes a protective insulating film that is in contact with a part of the oxide semiconductor layer without being exposed to the air. Form 516.

[0108] The insulating layer 516 has a thickness of at least 1 nm, and is formed by a method such as sputtering. The insulating layer 51 can be formed by using an appropriate method that does not mix impurities such as water and hydrogen. When hydrogen is contained in 6, hydrogen penetrates into the oxide semiconductor layer, or hydrogen penetrates into the oxide semiconductor layer. The oxygen in the oxide semiconductor layer is extracted, and the back channel becomes low-resistance (N-type). Therefore, the insulating layer 516 should be as water-repellent as possible. It is important that the deposition process does not use hydrogen, resulting in a hydrogen-free film.

[0109] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed as the insulating layer 516 by sputtering. The film is formed using the ring method. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas ( Typically, under an argon atmosphere, an oxygen atmosphere, or a mixture of rare gas and oxygen. The target may be a silicon oxide target or a silicon For example, a silicon target can be used in an atmosphere containing oxygen. A silicon oxide film can be formed by sputtering under atmospheric conditions. The insulating layer 516 formed by this method is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film is used to block these substances from entering from the outside, typically silicon oxide. film, silicon oxynitride film, aluminum oxide film, or aluminum oxynitride film, etc. There are.

[0110] As in the formation of the oxide semiconductor film 530, residual moisture in the deposition chamber for the insulating layer 516 is removed. To achieve this, it is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating layer 516 formed in the film formation chamber evacuated using an ion pump was reduced. In addition, the exhaust means for removing the residual moisture in the film forming chamber of the insulating layer 516 is Alternatively, a turbo pump with a cold trap may be used.

[0111] The insulating layer 516 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is preferable to use a high-purity gas from which any impurities have been removed.

[0112] Then, a second heat treatment (preferably The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, in a nitrogen atmosphere The second heat treatment is carried out at 250°C for 1 hour in an atmosphere. A part of the body layer (channel forming region) is heated while being in contact with the insulating layer 516 .

[0113] Through the above steps, the oxide semiconductor film is subjected to the first heat treatment to remove hydrogen. impurities such as moisture, a hydroxyl group, or hydride (also called a hydrogen compound) from the oxide semiconductor layer; The oxide semiconductor is intentionally removed and simultaneously reduced by the impurity removal process. Therefore, the oxide semiconductor layer can be supplied with oxygen, which is one of the main components of the oxide semiconductor layer. Highly purified and electrically made into type I (intrinsic).

[0114] Through the above steps, a transistor 510 is formed (see FIG. 7D).

[0115] Furthermore, when a silicon oxide layer containing many defects is used as an insulating layer, the silicon oxide layer is easily deformed after being formed. The heat treatment reduces impurities such as hydrogen, moisture, a hydroxyl group, or hydride contained in the oxide semiconductor layer. The impurities contained in the oxide semiconductor layer are diffused into the insulating layer, and the impurities are further reduced. do.

[0116] A protective insulating layer 506 may be further formed on the insulating layer 516. For example, the protective insulating layer 506 may be formed by RF sputtering. The RF sputtering method is suitable for mass production, so it is used to form a protective insulating layer. The protective insulating layer does not contain impurities such as moisture, and these impurities are easily absorbed from the outside. The inorganic insulating film blocks the penetration of silicon nitride and aluminum nitride. In this embodiment, the protective insulating layer 506 is formed of silicon nitride. It is formed using a film (see FIG. 7(E)).

[0117] In this embodiment, the substrate 505 on which the insulating layer 516 has been formed is heated at a temperature of 100° C. to 400° C. The silicon is then heated to 100°C, and a sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced. A silicon nitride film is formed as a protective insulating layer 506 using a target. Similarly to the insulating layer 516, the protective insulating layer 506 is formed while removing residual moisture in the film formation chamber. It is preferable to coat the surface.

[0118] After forming the protective insulating layer, the product is further left in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. The heat treatment may be carried out by maintaining a constant heating temperature. It is also possible to raise the temperature from room temperature to a heating temperature of 100°C or more and 200°C or less, and then lower the temperature from the heating temperature to room temperature. The temperature decrease to the temperature may be repeated several times.

[0119] In this manner, the transistor including the highly purified oxide semiconductor layer manufactured according to this embodiment By using a transistor, the current value in the off state (off current value) can be reduced. This allows the transistor to be turned off when the transistor is in an off state. Therefore, it is possible to suppress the leakage of electric charges through the transistor. By applying it as a transistor provided in a pixel, the frequency of inputting image signals to the pixel can be reduced. In other words, the period during which no image signal is input to the pixel is prolonged. Even if a pixel is damaged, the display quality of that pixel can be maintained without degradation. As a result, the power consumption of the display device described in Embodiment 1 can be reduced. This is because the transistor of this embodiment is used as a transistor provided in each pixel. This is because by using this, it is possible to reduce the frame frequency of the extracted image signal.

[0120] Furthermore, a transistor including a highly purified oxide semiconductor layer has a relatively high field-effect mobility. Therefore, the transistors in each pixel of the display device can be By applying the transistor of this embodiment to a transistor, a high-quality image can be provided. can be done.

[0121] In the display device shown in Embodiment 1, the driver circuit and the relay circuit are The transistor may also include an oxide semiconductor layer. By expanding the range of application of the star, it is possible to reduce the manufacturing costs of the display device.

[0122] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0123] (Fourth embodiment) In this embodiment mode, a touch panel function is added to the display device shown in the above embodiment mode. The structure of the display device will be described with reference to FIGS. 8(A) and 8(B).

[0124] Fig. 8(A) is a schematic diagram of the display device of the present embodiment. A touch pad 602 is provided over a liquid crystal display panel 601, which is a display device of the first embodiment, and a housing 6 The touchpad 602 is a resistive type, surface A capacitive touch panel, a projected capacitive touch panel, or the like can be used as appropriate. In the display device shown in the embodiment, the touch pad 602 is the same as that in the display device shown in the embodiment 1. It corresponds to an input device.

[0125] As shown in FIG. 8(A), a display panel 601 and a touch pad 602 are fabricated separately. By overlaying, the cost of manufacturing a display device with a touch panel function can be reduced. This can be achieved.

[0126] Regarding the configuration of a display device with a touch panel function different from that of FIG. 8(A), FIG. 8(B) 8B. The display device 604 shown in FIG. 8B has a plurality of pixels 605 each having an optical sensor 6 606 and a liquid crystal element 607. Therefore, unlike the display device shown in FIG. There is no need to fabricate the touchpad 602 in an overlapping manner, and the display device can be made thinner. In addition to the pixel 605, a scanning line driver circuit 608, a signal line driver circuit 609, and a photo sensor driver circuit 609 are also provided. By fabricating the driver circuit 610 on the same substrate as the pixel 605, the display device can be made smaller. The optical sensor 606 is formed using amorphous silicon or the like and is oxidized. The insulating film may be formed so as to overlap with a transistor using a compound semiconductor.

[0127] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0128] (Embodiment 5) In this embodiment mode, examples of electronic devices equipped with the display device obtained in Embodiment 1 will be described. This will be explained with reference to FIG.

[0129] FIG. 9A is a diagram showing a notebook personal computer, which includes a main body 2201, a case, and It is composed of a body 2202, a display unit 2203, a keyboard 2204, and the like.

[0130] FIG. 9B is a diagram showing a personal digital assistant (PDA), and the main body 2211 has a display unit 22 13, an external interface 2215, and operation buttons 2214. In addition, a stylus 2212 is provided as an accessory for operation.

[0131] FIG. 9C shows an electronic book 2220 as an example of electronic paper. The device 2220 is made up of two housings, housing 2221 and housing 2223. 221 and the housing 2223 are integrated by a shaft portion 2237. With this configuration, the electronic book 2220 can be opened and closed using the paper It can be used like a book.

[0132] The housing 2221 incorporates a display unit 2225, and the housing 2223 incorporates a display unit 2227. The display unit 2225 and the display unit 2227 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2225 in FIG. 9C) and An image can be displayed on the display portion (the display portion 2227 in FIG. 9C).

[0133] FIG. 9C shows an example in which an operation unit and the like are provided in the housing 2221. For example, The housing 2221 includes a power supply 2231, operation keys 2233, a speaker 2235, etc. The operation keys 2233 can be used to turn pages. The keyboard and pointing device may be provided on the rear surface of the housing. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2220 may be configured to have the function of an electronic dictionary. That's fine.

[0134] The electronic book 2220 may also be configured to be capable of transmitting and receiving information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0135] Electronic paper can be applied to any field as long as it displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards.

[0136] 9(D) is a diagram showing a mobile phone. The mobile phone has a housing 2240 and a housing The housing 2241 is made up of two housings, a display panel 2242 and a speaker. Camera 2243, microphone 2244, pointing device 2246, camera The housing 2240 is provided with a lens 2247, an external connection terminal 2248, etc. It is equipped with a solar cell 2249 for charging the mobile phone, an external memory slot 2250, etc. The antenna is built into the housing 2241.

[0137] The display panel 2242 has a touch panel function, and in FIG. 9(D) an image is displayed. The multiple operation keys 2245 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by 2249 to the voltage required for each circuit. In addition to the above configuration, a contactless IC chip, a small recording device, etc. may be built in. It is also possible to do so.

[0138] The display direction of the display panel 2242 changes appropriately depending on the usage mode. The camera lens 2247 is located on the same surface as the lens 2242, allowing video calls. The speaker 2243 and microphone 2244 are not limited to voice calls, but are also used for video calls. Furthermore, the housing 2240 and the housing 2241 can be slid apart. As shown in Figure 9(D), it can be folded from the unfolded state to the folded state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0139] The external connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication. By inserting a recording medium, it is possible to store and transfer a larger amount of data. In addition, it may also be equipped with an infrared communication function, a television receiving function, etc. [Explanation of symbols]

[0140] 10 Pixel section 11 Drive circuit 12 Input Devices 13 processors 14 Relay Circuit 15 Relay Circuit 16 Signal detection circuit 17 Signal generation circuit 18 Signal extraction circuit 21 Signal detection unit 22 Latch section 23 Memory section 24 Reset section 30 boards 400 boards 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating Layer 409 Protective Insulation Layer 410 Transistor 420 transistors 427 Insulating Layer 430 transistors 436a Wiring layer 436b wiring layer 437 Insulating Layer 440 transistors 505 board 506 Protective insulation layer 507 Gate insulating layer 510 Transistor 511 Gate electrode layer 515a Source electrode layer 515b Drain electrode layer 516 Insulating Layer 530 Oxide semiconductor film 531 Oxide semiconductor layer 601 Display panel 602 Touchpad 603 Case 604 Display device 605 pixels 606 Optical Sensor 607 Liquid crystal element 608 Scanning line driving circuit 609 Signal Line Driver Circuit 610 Optical sensor driver circuit 2201 Main unit 2202 Case 2203 Display section 2204 keyboard 2211 Main unit 2212 Stylus 2213 Display section 2214 Operation button 2215 External Interface 2220 e-books 2221 Case 2223 Case 2225 Display section 2227 Display section 2231 Power supply 2233 Operation key 2235 Speaker 2237 Shaft 2240 chassis 2241 Case 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lenses 2248 External connection terminal 2249 Solar Cells 2250 external memory slot

Claims

[Claim 1] A display device that displays an image by controlling input of an image signal to a pixel portion by a driver circuit, an input device that outputs an image manipulation signal; a signal detection circuit that detects the image operation signal and outputs a detection signal; a signal generating circuit for generating a reference image signal; a signal extraction circuit that receives the reference image signal and outputs an extracted image signal that is a signal obtained by extracting a portion of the reference image signal; a first relay circuit and a second relay circuit to which the detection signal is input, When the image manipulation signal is detected by the signal detection circuit, the reference image signal input via the first relay circuit is selected as the image signal; When the image operation signal is not detected by the signal detection circuit, the extracted image signal input via the second relay circuit is selected as the image signal.

Images