Comparison circuit and semiconductor device

Abstract

To easily and accurately adjust a threshold voltage while suppressing an increase of a circuit area.SOLUTION: A comparison circuit 10 includes: a comparator CMP for comparing a first voltage V1 with a second voltage V2 so as to generate a comparison signal CMPO; a current generation circuit CGNR for generating a first current I1 and a second current I2; a first current / voltage conversion circuit R1 connected between an application end of a first monitoring object voltage V12 and an application end of the first voltage V1 so as to convert the first current I1 into the first voltage V1; a second current / voltage conversion circuit R2 connected between an application end of a second monitoring object voltage VDD and an application end of the second voltage V2 so as to convert the second current I2 into the second voltage V2; and an adjustment circuit TRIM for adjusting a difference value (I1-I2) between the first current I1 and the second current I2.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a comparison circuit and a semiconductor device. [Background technology]

[0002] A voltage comparison circuit that compares a monitored voltage with a predetermined threshold voltage to determine whether they are larger or smaller can be used in a variety of applications.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-172328

[0005] [overview] In conventional comparator circuits, there is room for further study on the method of adjusting the threshold voltage.

[0006] The comparison circuit according to the present disclosure includes a comparator configured to compare a first voltage and a second voltage to generate a comparison signal; a current generation circuit configured to generate a first current and a second current, respectively; a first current / voltage conversion circuit connected between an application terminal of a first monitored voltage and an application terminal of the first voltage and configured to convert the first current into the first voltage; a second current / voltage conversion circuit connected between an application terminal of a second monitored voltage and an application terminal of the second voltage and configured to convert the second current into the second voltage; and an adjustment circuit configured to adjust a difference value between the first current and the second current. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a semiconductor device. [Figure 2] FIG. 2 is a diagram showing a first modified example of the semiconductor device. [Figure 3] FIG. 3 is a diagram showing a second modified example of the semiconductor device. [Figure 4] FIG. 4 is a diagram showing a first embodiment (comparative example) of a comparison circuit. [Figure 5] FIG. 5 is a diagram showing a second embodiment of the comparator circuit. [Figure 6] FIG. 6 is a diagram illustrating an example of the operation of the comparison circuit in the second embodiment. [Figure 7] FIG. 7 is a diagram showing a third embodiment of the comparison circuit. [Figure 8] FIG. 8 is a diagram showing the relationship between the on / off state of the switch and the threshold voltage. [Figure 9] FIG. 9 is a diagram showing a fourth embodiment of the comparison circuit. [Figure 10] FIG. 10 is a diagram illustrating an example of the operation of the comparison circuit in the fourth embodiment.

[0008] [Detailed explanation] <Semiconductor device> 1 is a diagram showing the overall configuration of a semiconductor device 1. The semiconductor device 1 of this configuration example includes a transistor M1, a diode D1, and a comparison circuit 10. The transistor M1 may be, for example, an N-channel metal oxide semiconductor field effect transistor (MOSFET).

[0009] The drain of transistor M1 and the cathode of diode D1 are connected to node n11. The source and back gate of transistor M1 and the anode of diode D1 are connected to node n12. The gate of transistor M1 is connected to an application terminal of gate voltage G1. Transistor M1 may be understood as a transistor connected between node n11 and node n12. Diode D1 may also be understood as a body diode associated with transistor M1.

[0010] The transistor M1 may be a high-voltage element (for example, a 15V-withstand voltage element) that will not break down even if a voltage VDD is applied between the drain and source.

[0011] The comparison circuit 10 regards the voltage V12 applied to the node n11 as the first voltage to be monitored, and the comparison circuit 10 regards the voltage VDD applied to the node n12 as the second voltage to be monitored. Referring to the figure, the comparison circuit 10 includes a comparator CMP.

[0012] The comparator CMP compares the voltage V12 input to its inverting input terminal (-) with the voltage VDD input to its non-inverting input terminal (+) to generate a comparison signal CMPO. For example, the comparison signal CMPO goes low when the difference ΔV1 (=V12-VDD) between the voltages V12 and VDD is higher than the threshold voltage Vth. On the other hand, the comparison signal CMPO goes high when the difference ΔV1 is lower than the threshold voltage Vth. The comparator CMP may operate by receiving the supply of the voltage V12.

[0013] The node n11 may be an external terminal to which a first terminal of a capacitor C1 is externally connected. A second terminal of the capacitor C1 may be connected to a ground terminal. The capacitor C1 may be understood as a capacitive load. The capacitance value of the capacitor C1 may be, for example, 100 to 300 μF. A voltage V12 (for example, 12 V typ) may be applied to the node n11. The voltage V12 may be an internal power supply voltage of a driver DRV (power transistor) that rotates a motor M of a hard disk drive (HDD). The node n12 may be an external terminal to which a voltage VDD (for example, 12 V typ) is applied. The voltage VDD may be an external power supply voltage of the HDD.

[0014] Referring to this figure, the driver DRV includes transistors MH and ML as power transistors forming a half-bridge output stage. The transistors MH and ML may be, for example, N-channel MOSFETs. The drain of the transistor MH and the cathode of the diode DH are connected to a node n11. The source and backgate of the transistor ML and the anode of the diode DL are connected to the ground terminal. The source and backgate of the transistor MH, the drain of the transistor ML, the anode of the diode DH, and the cathode of the diode DL are connected to a node n13. The node n13 is connected to the motor M. The diodes DH and DL may be understood as body diodes associated with the transistors MH and ML, respectively. Note that the motor M may be a three-phase brushless motor. In this case, the transistors MH and ML may be understood as an example of one phase of the half-bridge output stage.

[0015] When the motor M is driven and the transistor MH is in the off state, a current flows from the node n13 to the node n11 via the diode DH, and the capacitor C1 can be charged. At this time, the voltage V12 can be boosted to a voltage higher than the voltage VDD. As a result, if the semiconductor device 1 is not provided with a protection circuit, a voltage higher than the voltage VDD may be applied to the internal circuit (not shown), which may exceed the withstand voltage of the internal circuit (not shown).

[0016] Therefore, the comparator circuit 10 monitors the difference ΔV1 between the voltage V12 and the voltage VDD, and controls the on / off of the transistor M1 based on the monitoring result. Specifically, the comparator circuit 10 sets the comparison signal CMPO to a low level when the difference ΔV1 is higher than the threshold voltage Vth (e.g., 4 mV). When the comparison signal CMPO is at a low level, the gate voltage G1 is forcibly pulled down to a low level. As a result, the transistor M1 is forcibly turned off. In this way, the transistor M1 functions as a backflow prevention element (a so-called e-fuse) to protect the internal circuit (not shown).

[0017] The semiconductor device 1 is not limited to HDDs, but can be installed in various applications such as server systems or chargers.

[0018] Fig. 2 is a diagram showing a first modified example of the semiconductor device 1. The semiconductor device 1 of this modified example is based on the semiconductor device 1 shown in Fig. 1, and a transistor M1 and a diode D1 are connected between a node n21 and a node n22.

[0019] Referring to this figure, the drain of transistor M1 and the cathode of diode D1 are connected to node n21. The source and back gate of transistor M1 and the anode of diode D1 are connected to node n22. The gate of transistor M1 is connected to an application terminal of gate voltage G1. Transistor M1 can be understood as a transistor connected between nodes n21 and n22.

[0020] The comparison circuit 10 regards the voltage V5 applied to the node n21 as the first voltage to be monitored, and the comparison circuit 10 regards the voltage VCC applied to the node n22 as the second voltage to be monitored. Referring to the figure, the comparison circuit 10 includes a comparator CMP.

[0021] The comparator CMP compares the voltage V5 input to the inverting input terminal (-) with the voltage VCC input to the non-inverting input terminal (+) to generate a comparison signal CMPO. For example, the comparison signal CMPO goes low when the difference ΔV2 (=V5-VCC) between the voltages V5 and VCC is higher than the threshold voltage Vth. On the other hand, the comparison signal CMPO goes high when the difference ΔV2 is lower than the threshold voltage Vth. The comparator CMP may operate by receiving the supply of the voltage V5.

[0022] The node n21 may be an external terminal to which a first terminal of the capacitor C2 is externally connected. A second terminal of the capacitor C2 may be connected to a ground terminal. The capacitor C2 may be understood as a capacitive load. The capacitance value of the capacitor C2 may be, for example, 50 μF. A voltage V5 (e.g., typ. 5 V) may be applied to the node n21. The voltage V5 may be the power supply voltage of the microcomputer. A voltage VCC (e.g., typ. 5 V) may be applied to the node n22. The voltage VCC may be the power supply voltage of the semiconductor device 1.

[0023] The comparator circuit 10 monitors the difference ΔV2 between the voltages V5 and VCC, and controls the on / off state of the transistor M1 based on the monitoring result. Specifically, the comparator circuit 10 sets the comparison signal CMPO to a low level when the difference ΔV2 is higher than a threshold voltage Vth (e.g., 5 mV). When the comparison signal CMPO is at a low level, the gate voltage G1 is forcibly pulled down to a low level. As a result, the transistor M1 is forcibly turned off. In this way, the transistor M1 functions as a backflow prevention element (a so-called e-fuse), as in FIG. 1.

[0024] 3 is a diagram showing a second modified example of the semiconductor device 1. The semiconductor device 1 of this modified example includes a resistor Rs.

[0025] A first end of the resistor Rs is connected to the node n31. A second end of the resistor Rs is connected to the node n32. A voltage Vs (=I×Rs) corresponding to the current I flowing through the resistor Rs is generated across the resistor Rs. The resistor Rs can be understood as a sense resistor connected between the node n31 and the node n32.

[0026] The comparison circuit 10 regards the voltage VDD-Vs applied to node n31 as the first voltage to be monitored, and the comparison circuit 10 regards the voltage VDD applied to node n32 as the second voltage to be monitored. Referring to the figure, the comparison circuit 10 includes a comparator CMP.

[0027] The comparator CMP compares the voltage VDD-Vs input to the non-inverting input terminal (+) with the voltage VDD input to the inverting input terminal (-) to generate a comparison signal CMPO. For example, the comparison signal CMPO goes low when the voltage Vs (=I×Rs) appearing across the resistor Rs is higher than the threshold voltage Vth. That is, the comparison signal CMPO goes low when the current I is higher than the overcurrent detection threshold Iocp. On the other hand, the comparison signal CMPO goes high when the voltage Vs is lower than the threshold voltage Vth. That is, the comparison signal CMPO goes high when the current I is lower than the overcurrent detection threshold Iocp. In this way, the comparator circuit 10 may function as an overcurrent protection circuit. The comparator CMP may operate by receiving the voltage VDD.

[0028] <Comparator circuit (first embodiment)> 4 is a diagram showing a first embodiment of a comparison circuit 10 (corresponding to a comparative example to be compared with the second to fourth embodiments described later). The comparison circuit 10 of this embodiment includes resistors R11 to R14 in addition to the comparator CMP described above. Note that this diagram illustrates the comparison circuit 10 applied to the semiconductor device 1 of FIG. 1.

[0029] The first terminal of resistor R11 is connected to the terminal to which voltage V12 is applied. The second terminal of resistor R11 and the first terminal of resistor R12 are connected to the terminal to which voltage V1 is applied. The second terminal of resistor R12 is connected to the ground terminal. Voltage V1 is the divided voltage of voltage V12 (= V12 × R12 / (R11 + R12)).

[0030] The first terminal of resistor R13 is connected to the terminal to which voltage VDD is applied. The second terminal of resistor R13 and the first terminal of resistor R14 are connected to the terminal to which voltage V2 is applied. The second terminal of resistor R14 is connected to the ground terminal. Voltage V2 is the divided voltage of voltage VDD (= VDD × R14 / (R13 + R14)).

[0031] The comparator CMP compares a voltage V1 input to its inverting input terminal (-) with a voltage V2 input to its non-inverting input terminal (+) to generate a comparison signal CMPO. For example, the comparison signal CMPO goes low when the voltage V1 is higher than the voltage V2. On the other hand, the comparison signal CMPO goes high when the voltage V1 is lower than the voltage V2. The comparator CMP may operate by receiving a voltage V12 (e.g., typically 12V) and a voltage V1.5 (e.g., typically 1.5V).

[0032] Now, consider a case where the comparison signal CMPO falls from high to low when the voltage V12 rises from the voltage VDD (=12V) to 12.004V, i.e., when the difference value ΔV1 (=V12-VDD) becomes higher than the threshold voltage Vth (=4mV). In this case, the ratio of the resistors R11 and R12 is set so that V1 = V2 (=11.996V) when V12 = 12.004V. For example, the ratio of the resistors R11 and R12 may be set to R11:R12 = 2:2999. However, if the resistance values ​​of the resistors R11 and R12 are designed to be R11 = 2Ω and R12 = 2999Ω, it may be difficult to design the relative resistances of the resistors R11 and R12.

[0033] Note that MOS switches are required to adjust the resistance values ​​of the resistors R11 and R12 by trimming. However, if the voltage V12 is a high voltage (e.g., 12 V), a high-voltage MOS switch is required. Furthermore, to turn the high-voltage MOS switch on and off, a level shifter is also required to convert a low-voltage drive control signal (e.g., 0 V to 1.5 V drive) output from a logic circuit (not shown) into a high-voltage drive control signal (e.g., 0 V to 12 V drive). Furthermore, if the threshold voltage Vth can be switched from multiple candidate values ​​(e.g., 4 mV, 6 mV, 8 mV, and 10 mV), the resistance values ​​of the resistors R11 and R12 must be adjusted by trimming for each of the multiple candidate values. Therefore, the comparison circuit 10 of the first embodiment is prone to increasing its circuit area.

[0034] In view of the above considerations, a new embodiment is proposed below that can easily and accurately adjust the threshold voltage Vth of the comparator circuit 10 while suppressing an increase in the circuit area.

[0035] <Comparator circuit (second embodiment)> 5 is a diagram illustrating a second embodiment of the comparator circuit 10. In addition to the comparator CMP, the comparator circuit 10 of this embodiment includes resistors R1 and R2, a current generator circuit CGNR, and an adjustment circuit TRIM. This diagram illustrates the comparator circuit 10 applied to the semiconductor device 1 of FIG. 1.

[0036] A first end of resistor R1 is connected to the end to which voltage V12 is applied. A second end of resistor R1 is connected to the end to which voltage V1 is applied. Resistor R1 can be understood as a first current / voltage conversion circuit that is connected between the end to which voltage V12 is applied and the end to which voltage V1 is applied, and converts current I1 into voltage V1. Voltage V1 has a voltage value (=V12-I1×R1) obtained by subtracting the voltage across resistor R1 (=I1×R1) from voltage V12.

[0037] A first terminal of resistor R2 is connected to the terminal to which voltage VDD is applied. A second terminal of resistor R2 is connected to the terminal to which voltage V2 is applied. Resistor R2 can be understood as a second current / voltage conversion circuit connected between the terminal to which voltage VDD is applied and the terminal to which voltage V2 is applied, and converts current I2 into voltage V2. Voltage V2 has a voltage value (= VDD - I2 × R2) obtained by subtracting the voltage across resistor R2 (= I2 × R2) from voltage VDD.

[0038] The current generating circuit CGNR generates currents I1 and I2, respectively. Referring to the figure, the current generating circuit CGNR includes current sources CS1 and CS2. The current source CS1 is connected between the application terminal of voltage V1 and the ground terminal to generate the current I1. The current source CS2 is connected between the application terminal of voltage V2 and the ground terminal to generate the current I2.

[0039] The adjustment circuit TRIM adjusts the difference value ΔI (=I1−I2) between the current I1 and the current I2 by trimming. For example, the adjustment circuit TRIM may adjust at least one of the currents I1 and I2.

[0040] The comparator CMP compares a voltage V1 input to its inverting input terminal (-) with a voltage V2 input to its non-inverting input terminal (+) to generate a comparison signal CMPO. For example, the comparison signal CMPO goes low when the voltage V1 is higher than the voltage V2. That is, the comparison signal CMPO goes low when the difference ΔV1 (=V12-VDD) between the voltages V12 and VDD is higher than the threshold voltage Vth (=I1×R1-I2×R2).

[0041] On the other hand, the comparison signal CMPO goes high when the voltage V1 is lower than the voltage V2. That is, the comparison signal CMPO goes high when the difference ΔV1 (=V12−VDD) between the voltages V12 and VDD is lower than the threshold voltage Vth (=I1×R1−I2×R2).

[0042] When the resistors R1 and R2 have the same resistance value R, the threshold voltage Vth is a voltage value (=R×ΔI) according to the difference value ΔI between the current I1 and the current I2.

[0043] The comparator CMP may operate by receiving the voltage V12 (for example, 12 V typ.) and the voltage V1.5 (for example, 1.5 V typ.), as in the first embodiment (FIG. 4).

[0044] In this way, in the comparator circuit 10 of this embodiment, the difference ΔI between the currents I1 and I2 is adjusted when setting the threshold voltage Vth. The relative design of the currents I1 and I2 is easier than the relative design of the resistors R11 and R12 in the first embodiment (FIG. 4). Therefore, a minute threshold voltage Vth (e.g., on the order of mV) can be adjusted with high precision.

[0045] Furthermore, unlike the first embodiment (FIG. 4), this configuration does not require high-voltage MOS switches or level shifters. Therefore, an increase in the circuit area is suppressed. When voltages V12 and VDD are high, high-voltage voltage clamp elements may be provided between the application terminal of voltage V1 and current source CS1, and between the application terminal of voltage V2 and current source CS2. With this configuration, current sources CS1 and CS2 are formed using low-voltage elements. Therefore, a reduction in the area of ​​the current generating circuit CGNR can be achieved.

[0046] The comparison circuit 10 of this embodiment can also be applied to the semiconductor device 1 of the first modification (FIG. 2) or the second modification (FIG. 3). For example, when the comparison circuit 10 of this embodiment is applied to the semiconductor device 1 of the first modification (FIG. 2), the voltages V12 and VDD may be replaced with the voltages V5 and VCC, respectively.

[0047] 6 is a diagram showing an example of the operation of the comparison circuit 10 in the second embodiment. The upper part of the diagram depicts the voltage V12 (solid line) and the voltage VDD (dashed line). The lower part of the diagram depicts the comparison signal CMPO.

[0048] As shown in the figure, when the voltage V12 exceeds the voltage VDD and further rises by the threshold voltage Vth, the comparison signal CMPO falls from high level to low level.

[0049] For example, consider the case where R1=R2=0.5 kΩ. In this case, to set Vth=4 mV, the difference ΔI between current I1 and current I2 should be adjusted so that 0.5 kΩ×ΔI=4 mV. At least one of currents I1 and I2 should be trimmed so that ΔI=8 μA (for example, I1=16 μA, I2=8 μA).

[0050] If the threshold voltage Vth can be switched from multiple candidate values, the difference value ΔI can be adjusted to match the multiple candidate values. For example, when R1=R2=0.5V, to set Vth=4mV, 5mV, 6mV, 7mV, 8mV, and 9mV, it is sufficient to adjust ΔI to 8μA, 10μA, 12μA, 14μA, 16μA, and 18μA.

[0051] <Comparator circuit (third embodiment)> 7 is a diagram showing a third embodiment of the comparator circuit 10. The comparator circuit 10 of this embodiment is based on the second embodiment (FIG. 5) described above, with a modification made to the configuration of the current generator circuit CGNR. Referring to this diagram, the current generator circuit CGNR includes current sources CS10 and CS20, current mirrors CM1 and CM2, and switches SW1 to SW6.

[0052] Current sources CS10 and CS20 generate reference currents I10 and I20, respectively. The adjustment circuit TRIM may adjust at least one of the reference currents I10 and I20 by trimming. Referring to the figure, the adjustment circuit TRIM adjusts the reference current I10. With this configuration, it is possible to keep the variation in the threshold voltage Vth within a desired specification (e.g., ±3 mV).

[0053] The current mirror CM1 mirrors the reference current I10 to generate a current I1. Referring to the figure, the current mirror CM1 generates three mirror currents I11-I13 from the reference current I10. The switches SW1-SW3 are connected between the application terminal of the voltage V1 and the output terminal of each of the mirror currents I11-I13. Therefore, the mirror currents I11-I13 are selectively added together in response to the on / off control of the switches SW1-SW3, and output as the current I1. The mirror ratio of the current mirror CM1 may be, for example, I10:I11:I12:I13=4:1:2:4.

[0054] The current mirror CM2 mirrors the reference current I20 to generate a current I2. Referring to the figure, the current mirror CM2 generates three mirror currents I21 to I23 from the reference current I20. The switches SW4 to SW6 are connected between the application terminal of the voltage V2 and the output terminals of the mirror currents I21 to I23, respectively. Therefore, the mirror currents I21 to I23 are selectively added together in response to the on / off control of the switches SW4 to SW6, and output as the current I2. The mirror ratio of the current mirror CM2 may be, for example, I20:I21:I22:I23=4:1:2:4.

[0055] The current source CS10, the current mirror CM1, and the switches SW1 to SW3 may be understood as circuit elements constituting the aforementioned current source CS1 (FIG. 5), and the current source CS20, the current mirror CM2, and the switches SW4 to SW6 may be understood as circuit elements constituting the aforementioned current source CS2 (FIG. 5).

[0056] FIG. 8 is a diagram showing the relationship between the on / off state of each of the switches SW1 to SW6 and the threshold voltage Vth. In this diagram, it is assumed that I10=32 μA and I20=8 μA. It is also assumed that I10:I11:I12:I13=4:1:2:4 and I20:I21:I22:I23=4:1:2:4. That is, it is assumed that I11=8 μA, I12=16 μA, I13=32 μA, I21=2 μA, I22=4 μA, I23=8 μA. It is also assumed that R1=R2=0.5 kΩ.

[0057] For example, as shown in the second row of the figure, consider the case where switches SW2 and SW6 are on and switches SW1, SW3 to SW5 are off. In this case, I1 = I12 = 16 μA, and I2 = I23 = 8 μA. Therefore, ΔI = I1 - I2 = 8 μA, and Vth is set to 4 mV. In this case, the mirror ratio of current mirror CM1 can be understood as being switched to I10:I1 = 4:2. Similarly, the mirror ratio of current mirror CM2 can be understood as being switched to I20:I2 = 4:4.

[0058] Also, for example, as shown in the fourth row of the figure, consider the case where switches SW1, SW2, SW5, and SW6 are on and switches SW3 and SW4 are off. In this case, I1 = I11 + I12 = 24 μA, and I2 = I22 + I23 = 12 μA. Therefore, ΔI = 12 μA, and Vth is set to 6 mV. In this case, the mirror ratio of current mirror CM1 can be understood as being switched to I10:I1 = 4:3. Similarly, the mirror ratio of current mirror CM2 can be understood as being switched to I20:I2 = 4:6.

[0059] Also, for example, as shown in the sixth row of the figure, consider the case where switches SW1, SW2, and SW6 are on and switches SW3 to SW5 are off. In this case, I1 = I11 + I12 = 24 μA, and I2 = I23 = 8 μA. Therefore, ΔI = 16 μA, and Vth is set to 8 mV. In this case, the mirror ratio of current mirror CM1 can be understood as being switched to I10:I1 = 4:3. Similarly, the mirror ratio of current mirror CM2 can be understood as being switched to I20:I2 = 4:4.

[0060] Also, for example, as shown in the eighth row of the figure, consider the case where switches SW3, SW5, and SW6 are on and switches SW1, SW2, and SW4 are off. In this case, I1 = I13 = 32 μA, and I2 = I22 + I23 = 12 μA. Therefore, ΔI = 20 μA, and Vth is set to 10 mV. In this case, the mirror ratio of current mirror CM1 can be understood as being switched to I10:I1 = 4:4. Similarly, the mirror ratio of current mirror CM2 can be understood as being switched to I20:I2 = 4:6.

[0061] The same applies to the first, third, fifth, seventh, and ninth to eighteenth stages of this diagram. That is, the mirror ratio of each of the current mirrors CM1 and CM2 can be switched from a plurality of candidate values. With this configuration, the difference value ΔI between the currents I1 and I2, and therefore the threshold voltage Vth, can be arbitrarily switched according to the on / off control of the switches SW1 to SW6. Furthermore, with this configuration, the relative design of the currents I1 and I2 is easy, and the pairing of the currents I1 and I2 can be improved. Therefore, even if the threshold voltage Vth can be switched from a plurality of candidate values, trimming can be easily performed with high precision for all candidate values.

[0062] The threshold voltage Vth can also be arbitrarily switched by adjusting the resistance values ​​of the resistors R1 and R2 or by increasing the number of outputs of each of the current mirrors CM1 and CM2.

[0063] <Comparator circuit (fourth embodiment)> 9 is a diagram showing a fourth embodiment of the comparator circuit 10. The comparator circuit 10 of this embodiment is based on the third embodiment (FIG. 7) described above, but has a modified configuration of the current generator circuit CGNR. Referring to this diagram, the current generator circuit CGNR further includes a hysteresis applying circuit HYS.

[0064] The hysteresis applying circuit HYS applies hysteresis to the difference value ΔI between the current I1 and the current I2. Referring to this figure, the hysteresis applying circuit HYS includes a current source CS13, a current mirror CM3, and switches SW7 and SW8.

[0065] A current source CS30 generates a reference current I30. A current mirror CM3 generates two mirror currents I31 and I32 from the reference current I30. A switch SW7 is connected between an application terminal of a voltage V1 and an output terminal of the mirror current I31. Therefore, the mirror currents I11 to I13 and I31 are selectively added together in response to on / off control of the switches SW1 to SW3 and SW7, and the resulting current is output as current I1. On the other hand, a switch SW8 is connected between an application terminal of a voltage V2 and an output terminal of the mirror current I32. Therefore, the mirror currents I21 to I23 and I32 are selectively added together in response to on / off control of the switches SW4 to SW6 and SW8, and the resulting current is output as current I2. The mirror ratio of the current mirror CM3 may be, for example, I30:I31:I32=1:1:2. Trimming of the reference current I30 is not essential. Furthermore, the reference currents I10, I20, and I30 may be generated from a common reference current (not shown) by a current mirror (not shown).

[0066] In the comparison circuit 10 of this embodiment, the first voltage / current conversion circuit that converts the current I1 to the voltage V1 includes a resistor R3 and a switch SW9 in addition to the resistor R1 described above, and the second voltage / current conversion circuit that converts the current I2 to the voltage V2 includes a resistor R4 and a switch SW10 in addition to the resistor R2 described above.

[0067] Resistor R3 and switch SW9 are connected in parallel between the second terminal of resistor R1 and the terminal to which voltage V1 is applied. Therefore, when switch SW9 is in the on state, if the combined resistance value of the first voltage / current conversion circuit is Rx, then Rx = R1. On the other hand, when switch SW9 is in the off state, then Rx = R1 + R3. That is, the first current / voltage conversion circuit includes a variable resistance circuit (resistors R1, R3 and switch SW9) having a combined resistance value Rx.

[0068] Resistor R4 and switch SW10 are connected in parallel between the second terminal of resistor R2 and the terminal to which voltage V2 is applied. When switch SW10 is in the on state, if the combined resistance of the second voltage / current conversion circuit is Ry, then Ry = R2. On the other hand, when switch SW10 is in the off state, then Ry = R2 + R4. That is, the second current / voltage conversion circuit includes a variable resistance circuit (resistors R2, R4 and switch SW10) having a combined resistance Ry.

[0069] In this figure, the comparison circuit 10 applied to the semiconductor device 1 of the first modified example (FIG. 2) is illustrated. That is, the voltage V12 and the voltage VDD of the third embodiment (FIG. 7) are replaced with the voltage V5 and the voltage VCC, respectively. However, the comparison circuit 10 of this embodiment may also be applied to the semiconductor device 1 of FIG. 1.

[0070] 10 is a diagram showing an example of the operation of the comparison circuit 10 in the fourth embodiment. The upper part of the diagram depicts a voltage V5 (solid line) and a voltage VCC (dashed line). The lower part of the diagram depicts a comparison signal CMPO.

[0071] As shown in this figure, when voltage V5 exceeds voltage VCC and then rises by the threshold voltage VthH, comparison signal CMPO falls from high to low. Also, when voltage V5 falls below voltage VCC and then falls by the threshold voltage VthL, comparison signal CMPO rises from low to high. Thus, hysteresis is imparted to threshold voltage Vth (Vth → VthH, VthL).

[0072] In the following, it is assumed that I10 = 32 μA, I20 = 8 μA, and I30 = 4 μA. It is also assumed that I10:I11:I12:I13 = 4:1:2:4, I20:I21:I22:I23 = 4:1:2:4, and I30:I31:I32 = 1:1:2. That is, it is assumed that I11 = 8 μA, I12 = 16 μA, I13 = 32 μA, I21 = 2 μA, I22 = 4 μA, I23 = 8 μA, I31 = 4 μA, and I32 = 8 μA. It is also assumed that R1 = R2 = 0.5 kΩ, and R3 = R4 = 19.5 kΩ. It is also assumed that Rx = Ry = R.

[0073] In this case, to set VthH=4mV, the resistance value R and the difference value ΔI should be adjusted so that R×ΔI=4mV. For example, by turning on switches SW2 and SW6 and turning off switches SW1 to SW5, SW7, and SW8, I1=16μA and I2=8μA. Therefore, ΔI=8μA. Furthermore, by turning on switches SW9 and SW10, R=0.5kΩ. As a result, VthH is set to 4mV (=0.5kΩ×8μA).

[0074] On the other hand, to set VthL=-80mV, the resistance value R and the difference value ΔI should be adjusted so that R×ΔI=-80mV. For example, by turning on switches SW7 and SW8 and turning off switches SW1 to SW6, I1=4μA and I2=8μA. Therefore, ΔI=-4μA. Furthermore, by turning off switches SW9 and SW10, R=20kΩ (=0.5kΩ+19.5kΩ). As a result, VthL is set to -80mV (=20kΩ×(-4μA)).

[0075] Even if switch SW6 is turned on and switch SW8 is turned off, I2 = I23 = 8 μA. However, the pairing between mirror current I31 and mirror current I32 is generally stronger than the pairing between mirror current I31 and mirror current I23. Therefore, it is preferable to turn switch SW6 off and switch SW8 on.

[0076] <Additional Notes> The comparison circuit according to the present disclosure makes it possible to easily and accurately adjust the threshold voltage while suppressing an increase in the circuit area.

[0077] [Appendix 1] a comparator (CMP) configured to compare a first voltage (V1) and a second voltage (V2) to generate a comparison signal (CMPO); a current generating circuit (CGNR) configured to generate a first current (I1) and a second current (I2), respectively; a first current / voltage conversion circuit (R1) connected between an application terminal of a first monitored voltage (V12 / V5 / VDD-Vs) and an application terminal of the first voltage (V1) and configured to convert the first current (I1) into the first voltage (V1); a second current / voltage conversion circuit (R2) connected between an application terminal of a second monitored voltage (VDD / VCC) and an application terminal of the second voltage (V2) and configured to convert the second current (I2) into the second voltage (V2); a trimming circuit (TRIM) configured to adjust a difference (I1-I2) between the first current (I1) and the second current (I2); A comparison circuit (10) comprising:

[0078] [Appendix 2] 2. The comparison circuit (10) of claim 1, wherein the current generation circuit (CGNR) includes a first current mirror (CM1) configured to mirror a first reference current (I10) to generate the first current (I1), and a second current mirror (CM2) configured to mirror a second reference current (I20) to generate the second current (I2).

[0079] [Appendix 3] 3. The comparison circuit (10) according to claim 2, wherein the adjustment circuit (TRIM) adjusts at least one of the first reference current (I10) and the second reference current (I20).

[0080] [Appendix 4] 4. The comparison circuit (10) according to claim 2 or 3, wherein the first current mirror (CM1) and the second current mirror (CM2) each have a mirror ratio that can be switched from a plurality of options.

[0081] [Appendix 5] The comparison circuit (10) according to any one of appendices 2 to 4, wherein the current generating circuit (CGNR) further includes a hysteresis imparting circuit (HYS) configured to impart hysteresis to a difference value (I1-I2) between the first current (I1) and the second current (I2).

[0082] [Appendix 6] 6. The comparison circuit (10) of claim 5, wherein the hysteresis imparting circuit (HYS) includes a third current mirror (CM3) configured to mirror a third reference current (I13) to generate the first current (I1) and the second current (I2).

[0083] [Appendix 7] The comparison circuit (10) according to any one of appendices 1 to 6, wherein the first current / voltage conversion circuit (R1, R3, R9) and the second current / voltage conversion circuit (R2, R4, R9) each include a variable resistance circuit (R3, R4, SW9, SW10).

[0084] [Appendix 8] a transistor (M1) connected between a first node (n11, n21) and a second node (n12, n22); A comparison circuit (10) according to any one of appendices 1 to 7, in which a voltage (V12, V5) applied to the first node (n11, n21) is the first voltage to be monitored, and a voltage (VDD, VCC) applied to the second node (n11, n22) is the second voltage to be monitored; A semiconductor device (1) comprising:

[0085] [Appendix 9] a sense resistor (Rs) connected between the first node (n31) and the second node (n32); a comparison circuit (10) according to any one of appendices 1 to 7, in which a voltage (VDD-Vs) applied to the first node (n31) is the first voltage to be monitored and a voltage (VDD) applied to the second node (n32) is the second voltage to be monitored; A semiconductor device (1) comprising:

[0086] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0087] 1. Semiconductor device 10 Comparison circuit C1, C2 capacitors CGNR current generation circuit CM1~CM3 current mirror CMP Comparator CS1, CS2, CS10, CS20, CS30 current sources D1, DH, DL diode DRV driver HYS Hysteresis circuit Medium motor M1, MH, ML transistors (N-channel MOSFETs) n11, n12, n13, n21, n22, n31, n32 nodes R1~R4, R11~R14, Rs resistance SW1 to SW10 switches TRIM adjustment circuit

Claims

1. a comparator configured to compare the first voltage and the second voltage to generate a comparison signal; a current generating circuit configured to generate a first current and a second current, respectively; a first current / voltage conversion circuit connected between an application terminal of a first monitored voltage and an application terminal of the first voltage, and configured to convert the first current into the first voltage; a second current / voltage conversion circuit connected between an application terminal of a second monitored voltage and an application terminal of the second voltage, and configured to convert the second current into the second voltage; an adjustment circuit configured to adjust a difference between the first current and the second current; A comparison circuit comprising:

2. 2. The comparison circuit of claim 1, wherein the current generation circuit includes: a first current mirror configured to mirror a first reference current to generate the first current; and a second current mirror configured to mirror a second reference current to generate the second current.

3. The comparison circuit according to claim 2 , wherein the adjustment circuit adjusts at least one of the first reference current and the second reference current.

4. 3. The comparison circuit according to claim 2, wherein the mirror ratios of the first current mirror and the second current mirror are switchable from a plurality of options.

5. 3. The comparison circuit according to claim 2, wherein the current generation circuit further comprises a hysteresis applying circuit configured to apply hysteresis to a difference value between the first current and the second current.

6. 6. The comparison circuit of claim 5, wherein the hysteresis providing circuit includes a third current mirror configured to mirror a third reference current to generate an offset current for each of the first current and the second current.

7. 2. The comparison circuit according to claim 1, wherein said first current / voltage conversion circuit and said second current / voltage conversion circuit each include a variable resistance circuit.

8. a transistor connected between a first node and a second node; a comparison circuit according to any one of claims 1 to 7, wherein a voltage applied to the first node is the first voltage to be monitored and a voltage applied to the second node is the second voltage to be monitored; A semiconductor device comprising:

9. a sense resistor connected between the first node and the second node; a comparison circuit according to any one of claims 1 to 7, wherein a voltage applied to the first node is the first voltage to be monitored and a voltage applied to the second node is the second voltage to be monitored; A semiconductor device comprising:

Images