Display device and method for manufacturing the same

Abstract

To improve yield of a display device.SOLUTION: A display device according to an embodiment comprises a substrate, an organic insulating layer disposed above the substrate over a display region for displaying images and a peripheral region, a lower electrode disposed above the organic insulating layer in the display region, a rib layer disposed above the organic insulating layer and the lower electrode and having a pixel opening overlapping the lower electrode, an organic layer that covers the lower electrode through the pixel opening, an upper electrode that covers the organic layer, and a first partition wall that includes a first lower portion disposed above the rib layer and a first upper portion having an end protruding from a side surface of the first lower portion and surrounds the pixel opening. The peripheral region includes a first region which is formed along the outer edge of the substrate and in which the organic insulating layer is not disposed, and a second region which is formed along the outer edge, and overlaps a part of the first region, and in which the rib layer is not disposed.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a manufacturing method thereof that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes a substrate, an organic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area around the display area, a lower electrode disposed above the organic insulating layer in the display area, a rib layer disposed above the organic insulating layer and the lower electrode and having pixel openings overlapping the lower electrode, an organic layer covering the lower electrode through the pixel openings and emitting light in response to application of a voltage, an upper electrode covering the organic layer, a first partition wall including a first lower portion disposed above the rib layer and a first upper portion having an end portion protruding from a side surface of the first lower portion, and surrounding the pixel openings. The peripheral area includes a first area formed along an outer edge of the substrate and not covered by the organic insulating layer, and a second area formed along the outer edge, overlapping a portion of the first area, not covered by the rib layer.

[0006] Moreover, according to an embodiment, a method for manufacturing a display device includes forming an organic insulating layer having a first groove surrounding a display area above a substrate, forming a lower electrode above the organic insulating layer in the display area, forming a rib layer above the organic insulating layer and the lower electrode, forming a first partition in the display area, the first partition including a first lower portion disposed above the rib layer and a first upper portion having an end portion protruding from a side surface of the first lower portion, forming a pixel opening in the rib layer that overlaps with the lower electrode, forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage, forming an upper electrode that covers the organic layer, etching the rib layer to form a second groove in the rib layer that overlaps with a portion of the first groove, and cutting the substrate along a cut line that overlaps with the first groove and the second groove. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display panel taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the motherboard according to the first embodiment. [Figure 5] FIG. 5 is a schematic plan view of the panel unit according to the first embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an enlarged view of the vicinity of the cut line in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the panel portion PP taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing an example of the structure of a portion where the dam structure shown in FIG. 5 intersects with a cut line. [Figure 9] FIG. 9 is a schematic cross-sectional view showing another example of the structure of the portion where the dam structure shown in FIG. 5 intersects with the cut line. [Figure 10] FIG. 10 is a schematic cross-sectional view showing an example of the structure of a portion where the wiring and the cut line shown in FIG. 5 intersect. [Figure 11] FIG. 11 is a flowchart showing an example of a method for manufacturing the display device according to the first embodiment. [Figure 12A] FIG. 12A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 12B] FIG. 12B is a schematic cross-sectional view showing a step subsequent to FIG. 12A. [Figure 12C] FIG. 12C is a schematic cross-sectional view showing a step subsequent to FIG. 12B. [Figure 12D] FIG. 12D is a schematic cross-sectional view showing a step subsequent to FIG. 12C. [Figure 12E] FIG. 12E is a schematic cross-sectional view showing a step subsequent to FIG. 12D. [Figure 12F] FIG. 12F is a schematic cross-sectional view showing a step subsequent to FIG. 12E. [Figure 12G] FIG. 12G is a schematic cross-sectional view showing a step subsequent to FIG. 12F. [Figure 12H] FIG. 12H is a schematic cross-sectional view showing a step subsequent to FIG. 12G. [Figure 12I]FIG. 12I is a schematic cross-sectional view showing a step subsequent to FIG. 12H. [Figure 12J] FIG. 12J is a schematic cross-sectional view showing a step subsequent to FIG. 12I. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the vicinity of the outer edge of the substrate in the display device according to the first embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view of the vicinity of the cut line in the panel portion according to the second embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view of the vicinity of the cut line in the panel portion according to the third embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of the vicinity of the cut line in the panel portion according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1 and AP3 are quadrangles with the same area. On the other hand, the pixel opening AP2 is a rectangle that is longer in the Y direction than the pixel openings AP1 and AP3. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] Conductive partition walls 6A (first partition walls) are disposed above the rib layer 5. The partition walls 6A serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition walls 6A entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5. The partition walls 6A surround each of the pixel openings AP1, AP2, and AP3.

[0025] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0026] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0027] The partition wall 6A includes a conductive lower portion 61 (first lower portion) disposed on the rib layer 5, and an upper portion 62 (first upper portion) disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. That is, the partition wall 6A has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0028] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0029] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0030] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6A.

[0031] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0032] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0033] Sealing layers SE11, SE12, and SE13 (first to third sealing layers) are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6A around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6A around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6A around it.

[0034] 3, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6A. Also, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6A. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6A.

[0035] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6A. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0036] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1 (first resin layer). The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2 (second resin layer). The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0037] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0038] The electrodes constituting the touch panel may be disposed on the sealing layer SE2. Also, color filters corresponding to the colors of the subpixels SP1, SP2, SP3 may be disposed above the display elements DE1, DE2, DE3, respectively.

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0042] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0045] The first top layer 65 of the partition wall 6A is formed of, for example, a metal material. The second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] When manufacturing the display device DSP, a large motherboard is fabricated on which a plurality of regions (panel sections) each corresponding to a display device DSP are formed. The following describes a configuration that can be applied to this motherboard.

[0050] 4 is a schematic plan view of the mother substrate MB (mother substrate for a display device) according to this embodiment. The mother substrate MB has a rectangular shape as shown in the figure, but may have other shapes such as a circle.

[0051] The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA surrounding the panel portions PP. In the example of Fig. 4, the panel portions PP are lined up in the X and Y directions with blank areas BA between them. However, the arrangement of the plurality of panel portions PP on the mother substrate MB is not limited to this example. As another example, some panel portions PP may be lined up without blank areas BA between them.

[0052] 5 is a schematic plan view of the panel portion PP. The outer shape of the panel portion PP corresponds to the cutting lines CL1 for cutting out each panel portion PP from the motherboard MB.

[0053] The panel unit PP has the above-mentioned display area DA and peripheral area SA. The peripheral area SA in the panel unit PP corresponds to the area between the display area DA and the cut line CL1.

[0054] The peripheral area SA further has a cut line CL2 that defines the outline of the substrate 10 of the display device DSP. The peripheral area SA includes an inspection area TA between the cut lines CL1 and CL2. In the inspection area TA, a plurality of inspection pads TD are arranged for inspecting the operation of the display panel PNL. Each inspection pad TD is connected to a terminal section T via a wiring WL.

[0055] The cut line CL2 passes between the terminal portion T and each test pad TD near the terminal portion T. That is, the cut line CL2 crosses each wiring WL.

[0056] When manufacturing the display device DSP, a panel portion PP is cut out from a mother substrate MB along a cut line CL1. Further, the cut-out panel portion PP is inspected using the inspection pads TD. After this inspection, an inspection area TA is cut out from the panel portion PP along a cut line CL2.

[0057] The panel portion PP has dam structures DS1 and DS2. The dam structure DS1 is located between the cut line CL2 and the display area DA and surrounds the display area DA. The dam structure DS2 is located in the inspection area TA and surrounds the cut line CL2. In the example of Figure 5, the dam structures DS1 and DS2 meet near the terminal portion T, and this joined portion passes between the terminal portion T and the display area DA.

[0058] Most of the cut line CL2 is located between the dam structures DS1 and DS2. However, in the example of Fig. 5, the cut line CL2 is located outside the dam structures DS1 and DS2 near the terminal portion T. In other words, the cut line CL2 crosses the dam structure DS2 near the terminal portion T.

[0059] Fig. 6 is a schematic plan view enlarging the vicinity of the cut line CL2, and Fig. 7 is a schematic cross-sectional view of the panel portion PP taken along line VII-VII in Fig. 6.

[0060] 6, the dam structure DS1 has two dam portions DM1 and DM2. The dam structure DS2 has two dam portions DM3 and DM4. The number of dam portions provided in the dam structures DS1 and DS2 is not limited to two, and may be one, or three or more.

[0061] A large number of partition walls 6B (second partition walls) are arranged in the peripheral area SA. For example, these partition walls 6B are spaced apart from one another and extend longitudinally along the dam portions DM1, DM2, DM3, and DM4 and the cut line CL2.

[0062] 7, like the partition wall 6A, the partition wall 6B has a lower part 61 (second lower part) including a bottom layer 63 and an axis layer 64, and an upper part 62 (second upper part) including a first top layer 65 and a second top layer 66. In the partition wall 6B as well, both ends of the upper part 62 protrude from the side surfaces of the lower part 61 (side surfaces of the axis layer 64).

[0063] As shown in FIG. 7, the circuit layer 11 includes inorganic insulating layers 31, 32, 33, and 34 and an organic insulating layer 35, which are sequentially arranged on the substrate 10. Although not shown in FIG. 7, the circuit layer 11 also includes metal layers and semiconductor layers arranged between these insulating layers. The inorganic insulating layers 31, 32, 33, and 34 are formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. In one example, the inorganic insulating layer 33 is formed of silicon oxide, and the inorganic insulating layer 34 is formed of silicon nitride. The organic insulating layer 35 is formed of an organic insulating material such as polyimide.

[0064] For example, each of the dam portions DM1, DM2, DM3, and DM4 is formed of an organic insulating layer 35 and an organic insulating layer 12 covering the organic insulating layer 35. Each of the dam portions DM1, DM2, DM3, and DM4 is disposed on the inorganic insulating layer 34 and covered with the rib layer 5. Each of the partition walls 6B is disposed on the rib layer 5.

[0065] The dam portions DM1 and DM2 serve to hold back the resin layer RS1 before it hardens. The dam portions DM3 and DM4 serve to hold back the resin layer RS2 before it hardens. In the example of FIG. 7, the end portion Er1 of the resin layer RS1 is located above the dam portion DM1. The end portion Er2 of the resin layer RS2 is located above the dam portion DM4. However, the positions of the ends Er1 and Er2 are not limited to this example.

[0066] The sealing layer SE2 covers the end portion Er1 of the resin layer RS1. Furthermore, the sealing layer SE2 covers the rib layer 5 and the partition wall 6B in the region between the end portion Er1 and the cut line CL2 and in the region outside the cut line CL2 (to the right in the figure).

[0067] The cut line CL2 overlaps with the substrate 10, the inorganic insulating layers 31, 32, 33, and 34, and the resin layer RS2. After the panel portion PP is cut along the cut line CL2, the portion of the substrate 10 that overlaps with the cut line CL2 becomes the outer edge E10 of the substrate 10. That is, in the display device DSP after cutting along the cut line CL2, the sealing layer SE2 covers the rib layer 5 in the region between the end Er1 of the resin layer RS1 and the outer edge E10 of the substrate 10.

[0068] The organic insulating layer 12 is not disposed between the dam portions DM2 and DM3. From another perspective, the organic insulating layer 12 has a first groove GR1 between the dam portions DM2 and DM3. The first groove GR1 surrounds the display area DA as shown in FIG. 5. The majority of the cut line CL2 is located in the first groove GR1.

[0069] The rib layer 5 has second grooves GR2 that overlap with the cut lines CL2. In the examples of Figures 6 and 7, the second grooves GR2 overlap with parts of the first grooves GR1. That is, the first grooves GR1 have parts that overlap with the second grooves GR2 and parts that do not overlap with them.

[0070] 7, the first groove GR1 has a width W1. The second groove GR2 has a width W2 that is smaller than the width W1 (W1>W2). For example, the width W2 is 100 μm or more, but is not limited to this example.

[0071] 7, the sealing layer SE2 is removed in the second grooves GR2. As a result, the inorganic insulating layer 34 is exposed from the rib layer 5 and the sealing layer SE2 through the second grooves GR2. The second grooves GR2 are covered with the resin layer RS2.

[0072] 7, the sealing layer SE2 is also removed near the dam portion DM2. The area from which the sealing layer SE2 has been removed may surround the display area DA together with the dam portion DM2.

[0073] Fig. 8 is a schematic cross-sectional view showing an example of the structure of the portion where the dam structure DS2 intersects with the cut line CL2. Fig. 9 is a schematic cross-sectional view showing another example of the structure of the portion where the dam structure DS2 intersects with the cut line CL2. While these figures focus on the dam portion DM3, a similar structure can also be applied to the dam portion DM4. Note that the resin layer RS2 is omitted in these figures.

[0074] 8, the second groove GR2 is also formed in the rib layer 5 above the dam portion DM3. The sealing layer SE2 is also removed from the second groove GR2, so that the upper surface of the dam portion DM3 is exposed from the rib layer 5 and the sealing layer SE2.

[0075] 9, the second groove GR2 is not formed on the dam portion DM3. That is, the dam portion DM3 is covered with the rib layer 5 and the sealing layer SE2 at the portion where it intersects with the cut line CL2.

[0076] 6 to 9, the partition walls 6B are not provided at positions that overlap with the cut lines CL2, which prevents the partition walls 6B from interfering with cutting along the cut lines CL2.

[0077] Fig. 10 is a schematic cross-sectional view showing an example of the structure of the portion where the wiring WL and the cut line CL2 shown in Fig. 5 intersect. In the example shown in this figure, the wiring WL is disposed between the inorganic insulating layers 33 and 34. However, the position of the wiring WL is not limited to this example.

[0078] The wiring WL is made of a metal material. If a moisture path to the wiring WL is formed, the wiring WL may corrode. In the example of FIG. 10, the second groove GR2 is not formed in the rib layer 5 at the portion where the wiring WL intersects with the cut line CL2. The wiring WL is entirely covered with the inorganic insulating layer 34, the rib layer 5, and the sealing layer SE2. This makes it possible to prevent the formation of the moisture path to the wiring WL.

[0079] 7 may be provided not only with respect to the cut line CL2 but also with respect to the cut line CL1. Furthermore, the sealing layer SE2 may be removed in the second groove GR2 provided with respect to the cut line CL1.

[0080] Next, an example of a manufacturing method of the display device DSP will be described. Fig. 11 is a flowchart showing an example of a manufacturing method of the display device DSP. Figs. 12A to 12J are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figs. 12A to 12J mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0081] In forming the panel portion PP, first, the circuit layer 11 including the inorganic insulating layers 31, 32, 33, and 34, the organic insulating layer 35, and a plurality of metal layers and semiconductor layers is formed above the substrate 10 of the motherboard MB (step PR1 in FIG. 11). Further, the organic insulating layer 12 having the first groove GR1 is formed (step PR2 in FIG. 11).

[0082] After step PR2, as shown in FIG. 12A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in FIG. 11).

[0083] 12B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB (step PR4 in FIG. 11). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0084] After the rib layer 5 is formed, a step for forming the partition walls 6A and 6B is performed (step PR5 in FIG. 11). In step PR5, as shown in FIG. 12C, a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first top layer 65, and a fourth layer L4 to be processed into the second top layer 66 are sequentially formed over the entire mother substrate MB. Furthermore, a resist R1 is disposed on the fourth layer L4. The resist R1 is patterned into the shape of the partition walls 6A and 6B. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed by, for example, sputtering.

[0085] Then, using the resist R1 as a mask, the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are patterned. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove portions of the fourth layer L4 exposed by the resist R1, dry etching to remove portions of the first layer L1, the second layer L2, and the third layer L3 exposed by the resist R1, and wet etching to reduce the width of the second layer L2.

[0086] 12D, partition walls 6A are formed in the display area DA. Also, partition walls 6B are formed in the peripheral area SA. After the partition walls 6A and 6B are formed, the resist R1 is removed (peeled off).

[0087] Next, a step for providing pixel openings AP1, AP2, and AP3 is performed (step PR6 in FIG. 11). In this step PR6, a resist R2 is formed to cover the partition wall 6A, as shown in FIG. 12E. Furthermore, using the resist R2 as a mask, dry etching is performed on the rib layer 5. As a result, pixel openings AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5, as shown in FIG. 12F. After the dry etching, the resist R2 is removed (peeled off). Note that the pixel openings AP1, AP2, and AP3 may be formed before the partition walls 6A and 6B.

[0088] After step PR6, a step is performed to remove the rib layer 5 in the test pad TD shown in Fig. 5 (step PR7 in Fig. 11). In step PR7, a resist having an opening in the test pad TD is placed on the rib layer 5, and the rib layer 5 is dry-etched.

[0089] After step PR7, a step for forming display element DE1 is performed (step PR8 in FIG. 11). To form display element DE1, first, as shown in FIG. 12G, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0090] The laminated film FL1 and sealing layer SE11 are formed over the entire mother substrate MB, including the display area DA of each panel unit PP, the peripheral area SA, and the margin area BA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6A. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6A.

[0091] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R3 is disposed on the sealing layer SE11, as shown in FIG. 12G. The resist R3 covers the subpixel SP1 and part of the partition wall 6A around it.

[0092] Then, an etching process is performed using the resist R3 as a mask. As a result, as shown in FIG. 12H, the portions of the stacked film FL1 and the sealing layer SE11 exposed by the resist R3 are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, in the peripheral region SA and the marginal region BA, the stacked film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R3 is removed (peeled off).

[0093] After step PR8, a step for forming display element DE2 is performed (step PR9 in FIG. 11). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0094] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 12I. For example, in the peripheral region SA and the marginal region BA, the stacked film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0095] After step PR9, a step for forming display element DE3 is performed (step PR10 in FIG. 11). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0096] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 12J. For example, in the peripheral region SA and the marginal region BA, the stacked film FL3 and the sealing layer SE13 are removed by etching during the patterning process.

[0097] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0098] The laminated films FL1, FL2, and FL3 formed by vapor deposition in steps PR8 to PR10 may have poor adhesion to the substrate, which may cause the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them to peel off from the substrate during the manufacture of the display device DSP.

[0099] The peeling is likely to occur when the stacked films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA, the stacked films FL1, FL2, and FL3 are finely divided by the partition walls 6A, which prevents the peeling.

[0100] In this embodiment, a plurality of partition walls 6B are arranged in the peripheral area SA, whereby the stacked films FL1, FL2, and FL3 are divided by the partition walls 6B also in the peripheral area SA, thereby suppressing the peeling.

[0101] After step PR10, a resin layer RS1 is formed (step PR11 in FIG. 11). The resin layer RS1 can be formed inside the dam structure DS1 by, for example, an inkjet method. After step PR11, a sealing layer SE2 is formed over the entire mother substrate MB by, for example, CVD (step PR12 in FIG. 11).

[0102] After step PR12, etching is performed to remove the rib layer 5 and the sealing layer SE2 covering the terminal portion T (step PR13 in FIG. 11). The etching is, for example, dry etching. The second groove GR2 described above is formed by this etching. In this embodiment, the etching removes the sealing layer SE2 together with the rib layer 5 at the position where the second groove GR2 is to be formed.

[0103] After step PR13, a resin layer RS2 is formed (step PR14 in FIG. 11). The resin layer RS2 can be formed inside the dam structure DS2 by, for example, an inkjet method. The dam structure DS2 serves to block the resin layer RS2 before it hardens.

[0104] The resin layer RS2 may be formed by a photolithography process. In this case, a photosensitive resin to be processed into the resin layer RS2 is first formed over the entire mother substrate MB. Then, the photosensitive resin is subjected to pre-baking, exposure, development, and firing processes, whereby the resin layer RS2 is formed in each panel portion PP.

[0105] After step PR14, the mother substrate MB is cut along the cut lines CL1 (step PR15 in FIG. 11). After that, an inspection step using inspection pads TD is performed, and then inspection areas TA are cut along the cut lines CL2 (step PR16 in FIG. 11). This completes the display device DSP. For example, laser cutting, in which an infrared laser is irradiated along the cut lines CL1 and CL2, can be used for cutting in steps PR14 and PR15. However, cutting in steps PR14 and PR15 may also be performed by other methods, such as scribe cutting.

[0106] 13 is a schematic cross-sectional view showing the vicinity of an outer edge E10 of the substrate 10 in the display device DSP manufactured by the above-mentioned manufacturing method. In the display device DSP, a first region A1 where the organic insulating layer 12 is not arranged and a second region A2 where the rib layer 5 is not arranged are formed along the outer edge E10.

[0107] The first region A1 corresponds to a portion of the first groove GR1 closer to the display area DA than the cut line CL2, and the second region A2 corresponds to a portion of the second groove GR2 closer to the display area DA than the cut line CL2.

[0108] The second region A2 is covered with a resin layer RS2. The second region A2 overlaps a part of the first region A1. That is, the first region A1 has a part that overlaps with the second region A2 and a part that does not overlap with the second region A2.

[0109] The first region A1 is formed within a range of a first distance D1 from the outer edge E10. The second region A2 is formed within a range of a second distance D2 from the outer edge E10. As is clear from the relationship between the widths W1 and W2 shown in FIG. 7, the second distance D2 is smaller than the first distance D1 (D1>D2).

[0110] In this embodiment, the sealing layer SE2 is removed in the second region A2, so that the inorganic insulating layer 34 is exposed from the rib layer 5 and the sealing layer SE2 in the second region A2.

[0111] For example, the display device DSP may have the first region A1 and the second region A2 all around the periphery of the display region DA, but at least one of the first region A1 and the second region A2 may not be formed near the terminal portion T shown in FIG.

[0112] According to this embodiment, the yield of the display device DSP can be improved as will be described below. If the panel portion PP of the display device DSP in the middle of manufacturing does not have the second region A2, the rib layer 5 and the sealing layer SE2 made of an inorganic insulating material may be partially damaged near the cut line CL2 when the panel portion PP is cut along the cut line CL2. In this case, cracks may occur in the rib layer 5 and the sealing layer SE2 starting from the damaged portions of the rib layer 5 and the sealing layer SE2.

[0113] In contrast to this, when the second grooves GR2 are provided along the cut lines CL2 as in this embodiment, the rib layer 5 is less likely to be damaged when cut, and therefore the above-mentioned cracks can be suppressed.

[0114] Furthermore, in this embodiment, the sealing layer SE2 is removed from the second groove GR2, which makes the sealing layer SE2 less susceptible to damage and makes it possible to more effectively suppress the above-mentioned cracks.

[0115] 7, the resin layer RS2 overlaps with the cut line CL2. Therefore, when cutting along the cut line CL2, the thick resin layer RS2 must be cut along with the substrate 10. The above-described laser cutting can cut the portion including the resin layer RS2 more effectively than mechanical methods such as scribe cutting.

[0116] However, when laser cutting is used, the rib layer 5 and the sealing layer SE2 are likely to be damaged. Therefore, the configuration in which the second grooves GR2 are provided as in this embodiment is effective when laser cutting is used.

[0117] As another embodiment of the first grooves GR1 and the second grooves GR2, it is possible to form both of them with approximately the same width. However, in this case, the rib layer 5 underlying the partition walls 6B is not present in the first grooves GR1, and therefore the partition walls 6B cannot be disposed in the first grooves GR1.

[0118] As described above, the partition wall 6B has a role of suppressing peeling of the stacked films FL1, FL2, and FL3 formed in the peripheral area SA and the sealing layers SE11, SE12, and SE13 covering them during the manufacturing process of the display device DSP. Therefore, if the partition wall 6B cannot be disposed in the first groove GR1, the possibility of the above-mentioned peeling occurring in the first groove GR1 increases.

[0119] Therefore, as in this embodiment, it is preferable to provide the second grooves GR2 so as to overlap part of the first grooves GR1, which makes it possible to arrange the partition walls 6B in the regions of the first grooves GR1 where the rib layers 5 are present. In addition to the above, various other advantageous effects can be obtained from this embodiment.

[0120] Second to fourth embodiments are disclosed below. In these embodiments, the configurations of the second groove GR2 and the second region A2 are different from those of the first embodiment. The configurations of the display device DSP, motherboard MB, panel unit PP, and manufacturing method not specifically mentioned can be the same as those of the first embodiment.

[0121] [Second embodiment] 14 is a schematic cross-sectional view of the panel portion PP according to the second embodiment, in the vicinity of the cut line CL2, in which the resin layer RS2 is omitted.

[0122] 14, in addition to the sealing layer SE2, the inorganic insulating layer 34 (first base layer) is removed in the second groove GR2. When such a panel portion PP is cut along the cut line CL2, a display device DSP can be obtained in which the rib layer 5, the sealing layer SE2, and the inorganic insulating layer 34 are removed in the second region A2.

[0123] 11, the inorganic insulating layer 34 is formed, and then the inorganic insulating layer 34 is removed by etching at the positions where the second grooves GR2 are to be formed. Then, as in the first embodiment, the rib layer 5 and the sealing layer SE2 are removed by etching in step PR13 to form the second grooves GR2. As another example, when the second grooves GR2 are formed by etching in step PR13, the inorganic insulating layer 34 overlapping the second grooves GR2 may be removed.

[0124] If the inorganic insulating layer 34 is removed in the second groove GR2 as in this embodiment, it is possible to suppress damage to the inorganic insulating layer 34 when cutting the panel portion PP along the cut line CL2. This makes it possible to suppress cracks originating from damaged portions of the inorganic insulating layer 34, and further improve the yield of the display device DSP.

[0125] [Third embodiment] 15 is a schematic cross-sectional view of the panel portion PP according to the third embodiment, in the vicinity of the cut line CL2, in which the resin layer RS2 is omitted.

[0126] 15, the inorganic insulating layer 33 (second base layer) is removed in the second groove GR2 in addition to the sealing layer SE2 and the inorganic insulating layer 34. When such a panel portion PP is cut along the cut line CL2, a display device DSP can be obtained in which the rib layer 5, the sealing layer SE2, and the inorganic insulating layers 33 and 34 are removed in the second region A2.

[0127] 11, the inorganic insulating layers 33, 34 are formed, and then the inorganic insulating layers 33, 34 are removed by etching at the positions where the second grooves GR2 are to be formed. Then, as in the first embodiment, the rib layer 5 and the sealing layer SE2 are removed by etching in step PR13 to form the second grooves GR2. As another example, when the second grooves GR2 are formed by etching in step PR13, the inorganic insulating layers 33, 34 that overlap the second grooves GR2 may be removed.

[0128] If the inorganic insulating layers 33, 34 are removed in the second groove GR2 as in this embodiment, it is possible to suppress damage to the inorganic insulating layers 33, 34 when cutting the panel portion PP along the cut line CL2. This makes it possible to suppress cracks originating from damaged portions of the inorganic insulating layers 33, 34, and further improve the yield of the display device DSP.

[0129] [Fourth embodiment] 16 is a schematic cross-sectional view of the panel portion PP according to the fourth embodiment, in the vicinity of the cut line CL2, in which the resin layer RS2 is omitted.

[0130] 16, the sealing layer SE2 and the inorganic insulating layers 33 and 34 are not removed at the second groove GR2. When such a panel portion PP is cut along the cut line CL2, a display device DSP in which the second region A2 is covered with the sealing layer SE2 can be obtained.

[0131] 16, before forming the sealing layer SE2, it is necessary to form the second grooves GR2 in the rib layer 5. For example, the second grooves GR2 can be formed by etching the rib layer 5 in step PR7 of FIG.

[0132] Even in the case where the sealing layer SE2 is not removed in the second groove GR2 as in the present embodiment, it is still possible to suppress damage to the rib layer 5 when cutting the panel portion PP along the cut line CL2. Therefore, it is possible to improve the yield of the display device DSP, as in the first embodiment.

[0133] In addition to the configurations disclosed in the first to fourth embodiments, various configurations can be applied to the second groove GR2 and the second region A2. For example, in the configurations of the second and third embodiments, the second groove GR2 (second region A2) may be covered with the sealing layer SE2, as in the fourth embodiment.

[0134] Furthermore, in the configurations of the first to fourth embodiments, at least one of the inorganic insulating layers 31 and 32 may be removed in the second groove GR2 (second region A2). If all of the inorganic insulating layers 31, 32, 33, and 34 are removed, the substrate 10 will be exposed in the second groove GR2 during the manufacturing process of the display device DSP. In this case, depending on the material of the substrate 10, there is a possibility that undesired substances will be precipitated from the substrate 10. From this perspective, it is preferable that the substrate 10 be covered with at least one of the inorganic insulating layers 31, 32, 33, and 34 in the second groove GR2.

[0135] All display devices and manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0136] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0137] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0138] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, MB...motherboard, PP...panel portion, GR1...first groove, GR2...second groove, A1...first region, A2...second region, 31-34...inorganic insulating layer, 5...rib layer, 6A, 6B...partition wall, 61...lower portion, 62...upper portion, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. A substrate; an organic insulating layer disposed above the substrate over a display area for displaying an image and a peripheral area around the display area; a lower electrode disposed above the organic insulating layer in the display area; a rib layer disposed above the organic insulating layer and the lower electrode, the rib layer having a pixel opening overlapping the lower electrode; an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer; a first partition wall including a first lower portion disposed above the rib layer and a first upper portion having an end portion protruding from a side surface of the first lower portion, the first partition wall surrounding the pixel opening; Equipped with The peripheral region is a first region formed along an outer edge of the substrate, where the organic insulating layer is not disposed; a second region formed along the outer edge, overlapping a part of the first region, and in which the rib layer is not disposed; The display device has:

2. the first region is formed within a range of a first distance from the outer edge, the second region is formed within a range of a second distance from the outer edge that is smaller than the first distance, The display device according to claim 1 .

3. a first resin layer covering the display area; a sealing layer formed of an inorganic insulating material and covering the first resin layer; Furthermore, an end portion of the first resin layer is located in the peripheral region; the sealing layer covers the rib layer in a region between the end of the first resin layer and the outer edge of the substrate; The display device according to claim 1 .

4. a plurality of second partition walls each including a second lower portion disposed above the rib layer in the peripheral region and a second upper portion having an end portion protruding from a side surface of the second lower portion; the sealing layer covers the second partition wall. The display device according to claim 3 .

5. The sealing layer is removed in the second region. The display device according to claim 3 .

6. The sealing layer covers the second region. The display device according to claim 3 .

7. a second resin layer covering the sealing layer in the display area and the peripheral area; The display device according to claim 3 .

8. the second resin layer covers the second region; The display device according to claim 7 .

9. a first base layer formed of an inorganic insulating material and disposed below the rib layer; the first underlayer is removed in the second region; 9. The display device according to claim 1.

10. a second underlayer formed of an inorganic insulating material and disposed below the first underlayer; the second underlayer is removed in the second region; The display device according to claim 9 .

11. forming an organic insulating layer above the substrate, the organic insulating layer having a first groove surrounding a display area; forming a lower electrode above the organic insulating layer in the display area; forming a rib layer above the organic insulating layer and the lower electrode; forming a first partition wall in the display area, the first partition wall including a first lower portion disposed above the rib layer and a first upper portion having an end portion protruding from a side surface of the first lower portion; forming a pixel opening in the rib layer so as to overlap the lower electrode; forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; forming an upper electrode covering the organic layer; forming a second groove in the rib layer by etching the rib layer, the second groove overlapping a portion of the first groove; cutting the substrate along a cutting line overlapping the first groove and the second groove; A method for manufacturing a display device, comprising:

12. the first groove has a first width; The second groove has a second width that is smaller than the first width. The method for manufacturing a display device according to claim 11 .

13. After forming the upper electrode and before cutting the substrate, forming a first resin layer covering the display area; forming a sealing layer made of an inorganic insulating material to cover the first resin layer; It further includes: an end portion of the first resin layer is located between the display area and the cut line; the sealing layer covers the rib layer in a region between the end of the first resin layer and the cut line; The method for manufacturing a display device according to claim 11 .

14. and forming a plurality of second partitions in a peripheral region around the display area before forming the sealing layer, each of the second partitions including a second lower portion disposed above the rib layer and a second upper portion having an end portion protruding from a side surface of the second lower portion; the sealing layer is formed to cover the second partition wall. The method for manufacturing a display device according to claim 13 .

15. the etching for forming the second groove is performed after the formation of the sealing layer; the etching removes the sealing layer together with the rib layer at a position where the second groove is to be formed; The method for manufacturing a display device according to claim 13 .

16. further comprising forming a second resin layer covering the sealing layer in the display area and a peripheral area around the display area. The method for manufacturing a display device according to claim 13 .

17. the second resin layer covers the second groove, When the substrate is cut, the second resin layer is cut together with the substrate. The method for manufacturing a display device according to claim 16.

18. forming a first underlayer of an inorganic insulating material over the substrate before forming the organic insulating layer; removing the first underlayer at a position where the second groove is to be formed; The method for manufacturing a display device according to claim 11 , further comprising:

19. forming a second underlayer made of an inorganic insulating material above the substrate before forming the first underlayer; removing the second underlayer at a position where the second groove is to be formed; The method for manufacturing a display device according to claim 18 , further comprising:

20. The cutting of the substrate is performed by a laser. A method for manufacturing a display device according to any one of claims 11 to 19.

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