Transistor and display device

Abstract

To provide a transistor with excellent electric characteristics and high reliability, and a display device including the transistor.SOLUTION: A transistor is a bottom-gate transistor formed by using an oxide semiconductor for a channel region, uses an oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment as an active layer. The active layer comprises a first region of a micro-crystallized surface layer part and a second region of the rest part. By using the oxide semiconductor layer having such structure, change to an n-type, which is due to reentry of moisture from the surface layer part or detachment of oxygen, and generation of a parasitic channel, can be suppressed. Contact resistance with a source electrode and a drain electrode can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a transistor including an oxide semiconductor and a display device including the transistor. [Background technology]

[0002] In recent years, semiconductor thin films (thicknesses ranging from several nm to several hundred nm) formed on substrates with insulating surfaces have become popular. The technology of constructing transistors using this technique is attracting attention. It is widely used in electronic devices such as optical devices, and is particularly used as a switching element in image display devices. There are many different types of metal oxides and they are used for a variety of purposes. Indium oxide is a well-known material that has the optical transparency required for LCD displays. It is used as an electrode material.

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors using metal oxides that exhibit such semiconducting properties in the channel formation region are already known. (Patent Document 1 and Patent Document 2).

[0004] In addition, a transistor using an oxide semiconductor has a relatively low field-effect mobility as an amorphous material. Therefore, the transistor can be used to configure a driver circuit of a display device or the like. can. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] In display devices, the pixel section (also called the pixel circuit) and the driver circuit section are formed on the same substrate. In this case, the transistors used in the pixel section must have excellent switching characteristics, for example, a high on-off ratio. The transistors used in the driver circuits are required to operate at high speed.

[0007] In particular, the higher the pixel density of the display device, the shorter the time it takes to write a display image. It is preferable that the transistors used in the semiconductor device operate at high speed.

[0008] One embodiment of the present invention disclosed in this specification relates to a transistor and a display device that solve the above problems. Regarding. [Means for solving the problem]

[0009] One embodiment of the present invention disclosed in this specification is to provide an oxide semiconductor layer in which a channel region is formed. The surface layer has a crystalline region made up of a microcrystalline layer, and the other parts are amorphous. A mixture of amorphous and microcrystalline with microcrystalline scattered throughout the region, or the entire material is made up of microcrystalline clusters A transistor formed by the above. The display device has a display section and a pixel section formed on the same substrate.

[0010] One aspect of the present invention disclosed in this specification is a gate electrode layer and a gate insulating layer formed on the gate electrode layer. an oxide semiconductor layer over the gate insulating layer; and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed of a first region in a surface layer portion and a second region in the other portion. The transistor is characterized by:

[0011] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate

[0012] Another embodiment of the present invention disclosed in this specification is a gate electrode layer and a gate insulating film formed on the gate electrode layer. a gate insulating layer, a source electrode layer and a drain electrode layer on the gate insulating layer, and a gate insulating layer on the an oxide semiconductor layer overlapping with a part of the source electrode layer and the drain electrode layer; and an oxide insulating layer formed on the surface of the oxide semiconductor layer. The transistor is characterized in that it is formed in the second region.

[0013] The first region of the oxide semiconductor layer is formed of microcrystals whose c-axes are oriented in a direction perpendicular to the film surface. It has been completed.

[0014] The second region of the oxide semiconductor layer may be an amorphous region in which microcrystals are scattered. It is a mixture of crystalline and microcrystalline or is formed entirely of microcrystalline.

[0015] The oxide semiconductor layer is made by dehydration or dehydrogenation treatment at high temperature for a short time using RTA method or the like. This heating step allows the surface of the oxide semiconductor layer to have a crystalline region made up of microcrystals. The other parts are amorphous, and the amorphous and microcrystalline regions are amorphous and microcrystalline. It is a mixture of crystals or the whole is a group of microcrystals.

[0016] By using an oxide semiconductor layer having such a structure, it is possible to prevent re-penetration of moisture from the surface layer and oxidation. This prevents the deterioration of electrical characteristics due to n-type formation caused by the desorption of atoms. The surface layer of the body layer is on the back channel side and has a crystalline region made up of microcrystals. The generation of a parasitic channel can be suppressed. In addition, in the channel-etched structure, The surface layer, which has improved conductivity due to the presence of a crystalline region, is in contact with the source and drain electrodes. Resistance can be reduced.

[0017] Further, a driver circuit portion and a pixel portion can be formed over the same substrate using a transistor which is one embodiment of the present invention. and a display device can be manufactured using a liquid crystal element, a light emitting element, an electrophoretic element, or the like. This can be done.

[0018] Another embodiment of the present invention disclosed in this specification is a pixel circuit having a transistor over the same substrate. The transistor has a gate electrode layer and a gate insulator on the gate electrode layer. an insulating layer; an oxide semiconductor layer on the gate insulating layer; and a portion of the oxide semiconductor layer on the gate insulating layer. an oxide insulating layer in contact with the source electrode layer and the drain electrode layer that overlap with each other; The oxide semiconductor layer is formed in a first region in a surface portion and a second region in the other portion. The display device is characterized by the above.

[0019] Another embodiment of the present invention disclosed in this specification is a pixel circuit having a transistor over the same substrate. The transistor has a gate electrode layer and a gate insulator on the gate electrode layer. a source electrode layer and a drain electrode layer on the gate insulating layer; The oxide semiconductor layer overlaps with a part of the electrode layer and the drain electrode layer, and the oxide semiconductor layer is in contact with the oxide semiconductor layer. and an oxide semiconductor insulating layer, the oxide semiconductor layer having a first region in a surface layer portion and a second region in the other portion. The display device is characterized in that it is formed in the region of

[0020] The first region of the oxide semiconductor layer is formed of microcrystals whose c-axes are oriented in a direction perpendicular to the film surface. The second region is composed of amorphous and amorphous regions with microcrystals scattered in the amorphous region. or is entirely formed of microcrystals. [Effects of the Invention]

[0021] In a transistor using an oxide semiconductor layer, a surface portion of the oxide semiconductor layer has a crystalline region. The remaining part is amorphous, a mixture of amorphous and microcrystalline, or the whole is microcrystalline. By using a crystalline structure, it is possible to provide a transistor and a display device with excellent electrical characteristics and high reliability. A device can be fabricated. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 2] Cross-sectional process diagram of a transistor. [Figure 3] Cross-sectional process diagram of a transistor. [Figure 4] FIG. 1 is a plan view illustrating a transistor. [Figure 5] FIG. 1 is a plan view illustrating a transistor. [Figure 6] FIG. 1 is a plan view illustrating a transistor. [Figure 7] FIG. 1 is a plan view illustrating a transistor. [Figure 8] 3A and 3B are a plan view and a cross-sectional view of a gate line terminal portion. [Figure 9] FIG. 1 is a plan view illustrating a transistor. [Figure 10] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 11]1A to 1C are diagrams illustrating examples of usage of a display device. [Figure 12] FIG. 1 is an external view showing an example of a display device. [Figure 13] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 14] FIG. 1 is a block diagram illustrating a display device. [Figure 15] 2A to 2C are diagrams illustrating a configuration and a timing chart of a signal line driver circuit. [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 1A and 1B are a circuit diagram showing a configuration of a shift register and a timing chart explaining the operation of the shift register; [Figure 18] FIG. 2 is a diagram illustrating a pixel equivalent circuit of a display device. [Figure 19] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 20] 1A and 1B are a cross-sectional view and a plan view illustrating a display device. [Figure 21] FIG. 1 is a cross-sectional view illustrating a display device. [Figure 22] 1A and 1B are a cross-sectional view and a plan view illustrating a display device. [Figure 23] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 24] FIG. 1 is an external view showing an example of a gaming machine. [Figure 25] FIG. 1 is an external view showing an example of a mobile phone. [Figure 26] Cross-sectional TEM image of an oxide semiconductor layer. [Figure 27] Cross-sectional TEM image of an oxide semiconductor layer. [Figure 28] Cross-sectional TEM image of an oxide semiconductor layer. [Figure 29] Cross-sectional TEM photograph and electron diffraction pattern of an oxide semiconductor layer. [Figure 30] EDX analysis spectrum of oxide semiconductor layer. [Figure 31] X-ray diffraction chart of oxide semiconductor layer. [Figure 32] SIMS analysis depth profile of oxide semiconductor layer. [Figure 33]A diagram explaining the overview of scientific computing. [Figure 34] A diagram explaining the overview of scientific computing. [Figure 35] A diagram explaining the results of scientific calculations. [Figure 36] 1A to 1C illustrate the crystal structure of an oxide semiconductor. [Figure 37] -IV characteristics of the transistor before and after BT test. [Figure 38] SIMS analysis depth profile of oxide semiconductor layer. [Figure 39] SIMS analysis depth profile of oxide semiconductor layer. DETAILED DESCRIPTION OF THE INVENTION

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents of the description. The same reference numerals are used in different drawings to designate the same parts or parts having similar functions. , and a repeated explanation thereof will be omitted.

[0024] (Embodiment 1) In this embodiment, a structure of a transistor will be described with reference to FIGS.

[0025] FIG. 1(A) is a cross-sectional view of a channel-etched transistor, and its plan view is shown in FIG. 4(A). ) FIG. 1(A) is a cross-sectional view taken along line A1-A2 in FIG. 4(A).

[0026] The transistor shown in FIG. 1 includes a gate electrode layer 101, a gate insulating layer 102, and a The oxide semiconductor layer 103 having the crystalline region 106 in the surface layer portion, the source electrode layer 105a, and the drain electrode layer 105b are The oxide semiconductor layer 10 includes an oxide electrode layer 105b having a crystalline region 106 in the surface layer portion. 3. An oxide insulating layer 107 is provided over the source electrode layer 105a and the drain electrode layer 105b. It is being done.

[0027] In FIG. 1A, a source electrode layer 10 is used as a normal channel etch type transistor. The oxide semiconductor layer is partly etched between the drain electrode layer 105a and the drain electrode layer 105b. However, as shown in FIG. 1B, the oxide semiconductor layer is not etched and the crystalline region in the surface layer remains. It is also possible to have a structure in which the area is left.

[0028] The gate electrode layer 101 may be made of aluminum, copper, molybdenum, titanium, chromium, tantalum, or titanium. Metallic materials such as tungsten, neodymium, scandium, etc., or materials containing these metallic materials as the main components Single layer or multilayered laminated ... When a low-resistance metal material such as aluminum or copper is used for the electrode layer, It is recommended to use in combination with high melting point metal materials due to heat resistance and corrosion issues. Materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and Indium and the like can be used.

[0029] In order to improve the aperture ratio of the pixel portion, the gate electrode layer 101 is made of indium oxide, Indium oxide tin oxide alloy, indium oxide zinc oxide alloy, zinc oxide, zinc aluminum oxide A transparent oxide conductive material such as zinc aluminum oxynitride or zinc gallium oxide is used. A conductive layer may also be used.

[0030] The gate insulating layer 102 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. A single layer or a laminated film of tantalum oxide, aluminum oxide, or the like can be used. These can be formed by CVD or sputtering.

[0031] The oxide semiconductor film is InMO3(ZnO) m Use a thin film expressed as (m>0) Here, M is one or more selected from Ga, Al, Mn and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and and Co. InMO3(ZnO) m Oxide semiconductor with a structure represented by (m>0) Among the films, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O oxide semiconductors. The thin film is also called an In-Ga-Zn-O film.

[0032] The oxide semiconductor layer 103 is formed by a sputtering method. The thickness is preferably 20 nm or more and 100 nm or less. In the case where a part of the nitride semiconductor layer 103 is etched, when the device is completed, The film will have a region thinner than the above-mentioned film thickness.

[0033] The oxide semiconductor layer 103 is subjected to dehydration or dehydrogenation treatment at high temperature for a short time by an RTA method or the like. The dehydration or dehydrogenation process is carried out using a high-temperature gas (nitrogen or an inert gas such as a rare gas). Using gas or light, the temperature is between 500℃ and 750℃ (or below the distortion point of the glass substrate). ) for 1 minute or more and 10 minutes or less, preferably 650°C for 3 minutes or more and 6 minutes or less R This can be done using TA (Rapid Thermal Anneal) processing. By using this method, dehydration or dehydrogenation can be achieved in a short time, and the temperature can be increased to a level above the strain point of the glass substrate. It can be processed at any time.

[0034] The oxide semiconductor layer 103 is an amorphous layer having many dangling bonds when it is deposited. However, by carrying out the heating step as the dehydration or dehydrogenation treatment, the unbonded bonds in close proximity are The bonds between the hands can form an ordered amorphous structure. Then, it is either a mixture of amorphous and microcrystalline regions with microcrystalline regions scattered throughout the amorphous region, or The entire structure is made up of microcrystals. The particle size of the microcrystals is 1 nm or more and 20 nm or less. These are so-called nanocrystals with a size of less than 100 nm, and are generally called microcrystals. It is smaller than a child.

[0035] The surface portion of the oxide semiconductor layer 103, which is the crystalline region 106, is It is preferable to form a microcrystalline layer having a c-axis orientation. In this case, the long axis of the crystal is oriented in the c-axis direction. and the minor axis direction is 1 nm or more and 20 nm or less.

[0036] The surface of the oxide semiconductor layer with this structure has a dense crystalline region made up of microcrystals. To prevent this, the deterioration of electrical characteristics due to re-penetration of moisture from the surface and conversion to n-type due to desorption of oxygen is prevented. In addition, the surface portion of the oxide semiconductor layer is on the back channel side, and Preventing the crystallization is also effective in suppressing parasitic channels. The contact resistance between the surface layer portion having improved contact resistance and the source electrode layer 105a or the drain electrode layer 105b is It can be lowered.

[0037] Here, the In-Ga-Zn-O based film can be formed in the following manner depending on the oxide semiconductor film formation target used: The crystal structure that is easy to grow is different. For example, the molar ratio is In2O3:Ga2O3:ZnO= Using an oxide semiconductor film deposition target containing In, Ga, and Zn in a ratio of 1:1:1, When an n-Ga-Zn-O film is formed and crystallized through a heating process, the In oxide layer is It is a hexagonal layered compound crystal with one or two oxide layers containing Ga and Zn. In addition, the molar ratio of In2O3:Ga2O3:ZnO=1:1:2 When a film is formed using a target and crystallized through a heating process, the film is sandwiched between In oxide layers. The oxide layer containing Ga and Zn tends to be two layers. The stable crystal structure is the latter one containing Ga and Zn. The oxide layer is two-layered, and crystal growth is easy to occur. The molar ratio is In2O3:Ga The film was formed using a target of 2O3:ZnO = 1:1:2, and then crystallized through a heating process. In this case, crystals may be formed that are connected from the surface layer to the gate insulating film interface. The molar ratio may be rephrased as the atomic ratio.

[0038] As shown in FIG. 10A, depending on the order of steps, the side surface of the oxide semiconductor layer 103 may be damaged. The crystalline region 106 is formed only in the upper layer portion excluding the side surface portion. However, the area ratio of the side surface portion is small, and the above-mentioned effect is maintained even in this case.

[0039] The source electrode layer 105a and the drain electrode layer 105b are formed by the first conductive layers 112a and 112b. , a three-layer structure consisting of second conductive layers 113a and 113b, and third conductive layers 114a and 114b. The materials used for these layers are the same as those for the gate electrode layer 101 described above. It is possible.

[0040] Similarly to the gate electrode layer 101, the above-described light-transmitting oxide conductive layer is formed on the source electrode layer 1 By using the same for the drain electrode layer 105a and the drain electrode layer 105b, the light-transmitting property of the pixel portion can be improved, and the aperture ratio can be increased. It can also be made higher.

[0041] In addition, the above-mentioned metal film and oxide semiconductor film that will become the source electrode layer 105a and the drain electrode layer 105b are The aforementioned oxide conductive layer is formed between each of the conductive layers 103 to reduce contact resistance. It is also possible.

[0042] A channel electrode layer was formed over the oxide semiconductor layer 103, the source electrode layer 105a, and the drain electrode layer 105b. The oxide insulating layer 107 functions as a protective layer for the panel. An inorganic insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. Alternatively, an aluminum oxynitride film or the like is used.

[0043] The constituent materials of each part are the same, and the transistor has a bottom contact structure as shown in FIG. 10(B). A transistor can also be formed.

[0044] The transistor shown in FIG. 10B includes a gate electrode layer 101 and a gate insulating layer 102 formed on a substrate 100. 102, a source electrode layer 105a, a drain electrode layer 105b, and a crystalline region 106 in the surface layer portion. The oxide semiconductor layer 103 includes a gate insulating layer 102 and a source electrode layer 105a. The drain electrode layer 105b and the oxide semiconductor layer 103 are provided with an oxide insulating layer 107. are.

[0045] In this structure, the oxide semiconductor layer 103 is amorphous and has microcrystals scattered in the amorphous region. It is a mixture of amorphous and microcrystalline, or the entire material is made up of microcrystalline, with only the surface layer The crystalline region 106 is made of a microcrystalline layer. As a result, the re-intrusion of moisture from the surface and the desorption of oxygen occur, similar to the channel etch type. In addition, the surface layer of the oxide semiconductor layer can be prevented from deteriorating in electrical characteristics due to the n-type structure. The back channel side has a crystalline region made of a microcrystalline layer, which prevents parasitic channels. This can prevent the occurrence of bubbles.

[0046] By adopting the above-described structure, a transistor with high reliability and improved electrical characteristics can be provided. It can be provided.

[0047] Although an example of a channel-etched transistor is shown in this embodiment, a channel-protected transistor may be used. A protection transistor can also be used. A bottom-contact transistor having an overlapping oxide semiconductor layer can also be used. .

[0048] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0049] (Embodiment 2) In this embodiment, a display device including the channel-etch transistor described in Embodiment 1 The manufacturing process will be described with reference to FIGS. 2 to 9. FIGS. 2 and 3 are cross-sectional views, and FIGS. 4 to 7 are plan views, and the lines A1-A2 and B1-B2 in FIGS. 4 to 7 correspond to the lines A1-A2 and B1-B2 in FIGS. 2 and 3. These correspond to the cross-sectional views A1-A2 and B1-B2.

[0050] First, a substrate 100 is prepared. The substrate 100 is made of barium borosilicate glass, aluminophore, Silica glass or aluminosilicate glass, fusion or float process In addition to alkali-free glass substrates and ceramic substrates manufactured by this method, A plastic substrate or the like having sufficient heat resistance can be used. Any metal substrate having an insulating film formed on its surface may be used.

[0051] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used.

[0052] An insulating film may be formed as a base film on the substrate 100. The base film may be formed of silicon oxide. a single layer or a stack of a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film; These can be formed by CVD, sputtering, etc. When a substrate containing mobile ions such as a glass substrate is used as the plate 100, By using a film containing nitrogen such as silicon nitride film or silicon nitride oxide film, the mobile ions This can prevent ions from penetrating into the semiconductor layer.

[0053] Next, the gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 are A conductive film for forming the conductive layer is formed on the entire surface of the substrate 100 by sputtering or vacuum deposition. A first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching. The wiring and electrodes (gate wiring including the gate electrode layer 101, capacitance wiring 108) are removed. , and the first terminal 121). At this time, a film is formed above the gate electrode layer 101. To prevent the film from being cut off, the edge of the gate electrode layer 101 is etched to have a tapered shape. It is preferable to perform this step. The cross section at this stage is shown in FIG. 2(A). The plan view corresponds to FIG. 4(B).

[0054] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, Metallic materials such as scandium, or alloy materials whose main components are these metallic materials, or It can be formed as a single layer or a multilayer using nitrides containing these metal materials. When using low-resistance metal materials such as aluminum or copper for the electrode layer, problems of heat resistance and corrosion arise. Therefore, it is recommended to use it in combination with a high melting point metal material. Use of titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be done.

[0055] For example, the gate electrode layer 101 has a laminated structure in which molybdenum is laminated on aluminum. two-layer laminated structure with molybdenum on copper; two-layer structure with titanium nitride or Two-layer structure with tantalum nitride laminated or two-layer structure with titanium nitride and molybdenum laminated The three-layer laminated structure is preferably made of aluminum, an alloy of aluminum and silicon, or aluminum. The intermediate layer is an alloy of aluminum and titanium or an alloy of aluminum and neodymium, and the tungsten A laminated structure of upper and lower layers of tungsten, tungsten nitride, titanium nitride or titanium is preferred. It's nice.

[0056] At this time, a light-transmitting oxide conductive layer is used for a part of the electrode layer and the wiring layer to improve the aperture ratio. For example, the oxide conductive layer may be formed of indium oxide, indium oxide tin oxide, or the like. Alloys, indium oxide zinc oxide alloys, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride For example, aluminum, zinc oxide, or zinc gallium oxide can be used.

[0057] Next, a gate insulating layer 102 is formed on the gate electrode layer 101. The gate insulating layer 102 is The film thickness is set to 50 nm or more and 250 nm or less, and is formed by a CVD method, a sputtering method, or the like.

[0058] For example, a silicon oxide film having a thickness of 100 nm is formed as the gate insulating layer 102 by sputtering. Of course, the gate insulating layer 102 is not limited to a silicon oxide film, but may be an oxynitride film. Silicon film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, tantalum oxide It may be formed as a single layer or a laminated structure made of these materials using an insulating film such as a film. .

[0059] The gate insulating layer 102 is formed by depositing silicon oxide by a CVD method using organic silane gas. It is also possible to form a layer. The organic silane gas includes ethyl silicate (TEOS), tetrahydrofuran (TEOS), and tetrahydrofuran (TEOS). Tetramethylsilane (TMS), tetramethylcyclotetrasiloxane (TMCTS), Hexamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMDS) ), triethoxysilane (TRIES), trisdimethylaminosilane (TDMAS), etc. The following silicon-containing compounds can be used:

[0060] The gate insulating layer 102 may be made of an oxide of aluminum, yttrium, or hafnium. The compound may be a nitride, an oxynitride, or a nitride oxide. A compound containing at least two or more substances may also be used.

[0061] In this specification, an oxynitride is a compound having a composition in which the number of oxygen atoms is greater than the number of nitrogen atoms. Nitrided oxide refers to a substance in which the number of nitrogen atoms exceeds the number of oxygen atoms. For example, a silicon oxynitride film has a composition that contains more than nitrogen atoms. The number of oxygen atoms is larger than that of the ion-doped fluoride, and the Rutherford B Backscattering Spectrometry and Hydrogen Forward Scattering Spectrometry (HFS) When measured using Hydrogen Forward Scattering (Hydrogen Forward Scattering) The concentration range is 50 atomic % or more and 70 atomic % or less for oxygen, and 0.5 atomic % or more and 15 atomic % or less for nitrogen. % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 0.1 atomic % or more and 10 atomic % or less % or less. The silicon nitride oxide film has the following composition: There are more nitrogen atoms than oxygen atoms, and when measured using RBS and HFS, the concentration range As the oxygen content, 5 atomic % or more and 30 atomic % or less, nitrogen content, 20 atomic % or more and 55 atomic % or less, silicon content, The content of carbon is between 25 atomic % and 35 atomic % and the content of hydrogen is between 10 atomic % and 30 atomic %. However, the total number of atoms constituting silicon oxynitride or silicon nitride oxide is When the atomic percentage of silicon is 100, the content ratios of nitrogen, oxygen, silicon and hydrogen are within the above ranges. shall be included.

[0062] Before forming an oxide semiconductor film for forming the oxide semiconductor layer 103, an argon gas was Reverse sputtering is performed by introducing gas to generate plasma, and the It is preferable to remove the dust that is present on the substrate. This method involves applying voltage using a power supply to generate plasma near the substrate, thereby modifying the surface. Instead of the argon atmosphere, nitrogen, helium, etc. may be used. It may be carried out in an atmosphere containing oxygen, N2O, etc., or in an argon atmosphere containing Cl2, It may be performed in an atmosphere containing CF4, etc. After the reverse sputtering process, oxidation is performed without exposing to the atmosphere. By forming an oxide semiconductor film, the interface between the gate insulating layer 102 and the oxide semiconductor layer 103 This can prevent dust and moisture from adhering to the surface.

[0063] Next, a film having a thickness of 5 nm to 200 nm, preferably 10 nm, is formed on the gate insulating layer 102. An oxide semiconductor film having a thickness of 40 nm or less is formed.

[0064] Examples of oxide semiconductor films include quaternary metal oxide films such as In-Sn-Ga-Zn-O films, Ternary metal oxide films: In-Ga-Zn-O film, In-Sn-Zn-O film, In-A l-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn -O system, and binary metal oxide films such as In-Zn-O film, Sn-Zn-O film, and Al-Zn -O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, In-O film, Sn An oxide semiconductor film such as a Zn-O film or a Zn-O film can be used. The body film may contain SiO2.

[0065] Here, a target for forming an oxide semiconductor film containing In, Ga, and Zn (the molar ratio of In 2O3:Ga2O3:ZnO=1:1:1, or In2O3:Ga2O3:ZnO= 1:1:2), the distance between the substrate and the target was 100 mm, the pressure was 0.6 Pa, The film is formed in an oxygen atmosphere (oxygen flow rate 100%) with a direct current (DC) power supply of 0.5 kW. By using a pulsed direct current (DC) power supply, dust can be reduced and the film thickness distribution can be made uniform. In the embodiment, an oxide semiconductor film is formed using a substrate for forming an In-Ga-Zn-O-based oxide semiconductor film. A 30 nm thick In-Ga-Zn-O film is formed by sputtering using a target. .

[0066] The sputtering method uses RF sputtering, which uses a high frequency power supply, and DC sputtering. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which applies a bias pulse. The sputtering method is mainly used to form insulating films, while the DC sputtering method is mainly used to form conductive films such as metal films. It is used when forming a film having electrical conductivity.

[0067] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films of similar materials simultaneously.

[0068] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0069] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and the other method is to use a base compound during film formation. There is also a bias sputtering method in which voltage is applied to the plate.

[0070] Next, a second photolithography process is performed to form a resist mask, and an In-Ga-Z The etching is performed on the nO-based film using organic acids such as citric acid and oxalic acid. It can be used as a chant. Here, ITO07N (manufactured by Kanto Chemical Co., Ltd.) was used. Unnecessary parts are removed by wet etching to form islands of the In-Ga-Zn-O film. Then, an oxide semiconductor layer 103 is formed. The edge of the oxide semiconductor layer 103 is etched to have a tapered shape. By doing this, it is possible to prevent the wiring from being cut off due to the step shape. The etching is not limited to wet etching, and dry etching may also be used.

[0071] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The first heat treatment is performed using high-temperature gas (nitrogen or inert gas such as rare gas) and light. 00℃ to 750℃ (or a temperature below the distortion point of the glass substrate) for 1 minute to 10 minutes Preferably, the RTA (Rapid Thermal Annealing) is performed at 650°C for 3 to 6 minutes. The RTA method can be used to remove the Since hydration or dehydrogenation can be performed, processing can be performed even at temperatures exceeding the strain point of the glass substrate. The cross section at this stage is shown in Figure 2(B) and the plan view is shown in Figure 5. Regardless of the timing, the process may be performed multiple times before and after the photolithography process or the film formation process. stomach.

[0072] Here, the surface portion of the oxide semiconductor layer 103 is crystallized by the first heat treatment and has a microcrystalline structure. The oxide semiconductor layer 103 has a crystalline region 106 formed therein. The regions are either amorphous, a mixture of amorphous and microcrystalline with microcrystalline interspersed among the amorphous regions, or The crystalline region 106 is a part of the oxide semiconductor layer 103. Hereinafter, the term "oxide semiconductor layer 103" will include the crystalline region 106.

[0073] In this specification, the heat treatment under an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This is also called heat treatment for dehydrogenation. Dehydrogenation does not only mean that H, OH, etc. are eliminated. For convenience, this process will be referred to as dehydration or dehydrogenation.

[0074] The dehydrated or dehydrogenated oxide semiconductor layer is not exposed to the air, and is then cooled to room temperature. It is important not to reconstitute the oxide semiconductor layer by dehydration or dehydrogenation. n-type (n - , n + etc.), that is, oxides that are made low-resistance and then made i-type to make them high-resistance. The transistor using the semiconductor layer has a positive threshold voltage (Vth), which is called a nodal The transistors used in display devices have a turn-off characteristic. In an active matrix display device, it is preferable that the threshold voltage is positive and close to the threshold voltage. In this case, the electrical characteristics of the transistors that make up the circuit are important, and these electrical characteristics are The threshold voltage of a transistor is particularly important. If the threshold voltage is negative, a current flows between the source and drain electrodes even when the gate voltage is 0V. This results in a so-called normally-on characteristic, and the circuit configured with this transistor can be controlled. In addition, even if the threshold voltage is positive, it is difficult to obtain a transistor with a high absolute value. In this case, the driving voltage may be insufficient and the switching operation itself may not be possible. In the case of a channel type transistor, the channel is first generated when a positive voltage is applied as the gate voltage. It is desirable that the transistor has a gate current and a drain current. There are transistors in which a channel does not form unless the voltage is high, and transistors in which a channel forms even under negative voltage conditions. A transistor in which a drain current flows is not suitable for use in a circuit. It is.

[0075] The atmosphere when lowering the temperature from the temperature at which dehydration or dehydrogenation was performed is the same as that when raising the temperature or when performing heat treatment. For example, the atmosphere may be changed to a different atmosphere from that used when dehydration or dehydrogenation was performed. In the same furnace, high-purity oxygen gas, N2O gas, or ultra-high-purity gas are used without exposing the furnace to the atmosphere. Cooling can be achieved by filling with dry air (dew point below -40°C, preferably below -60°C). can.

[0076] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device should be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably 0.1 ppm or less.

[0077] When the heat treatment is performed in an inert gas atmosphere, the oxide semiconductor layer Oxygen deficiency and n-type (n - , n + After that, the oxide semiconductor By forming an oxide insulating layer in contact with the semiconductor layer, the oxide semiconductor layer is made into an oxygen-excess state. This makes the material i-type, i.e., highly resistive. This results in good electrical properties and reliability. This makes it possible to fabricate highly reliable transistors.

[0078] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer After the first heat treatment, the oxide becomes oxygen-deficient and has low resistance. The oxide semiconductor layer 103 is formed after the first heat treatment. The carrier concentration is increased, preferably to 1×10 18 / cm 3 The carrier concentration is becomes.

[0079] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. It can also be applied to a semiconductor film. In that case, the second photolithography is performed after the first heat treatment. In this case, a crystalline region is not formed in part of the island-shaped oxide semiconductor layer 103. The crystalline region 106 is formed only in the upper layer portion excluding the side surface portion (see FIG. 10(A)). .)

[0080] Next, a third photolithography step is performed to form a resist mask and then to perform etching. By removing unnecessary portions, contacts reaching the wiring and electrode layer made of the same material as the gate electrode layer 101 are formed. This contact hole will connect the conductive film to be formed later and the wiring etc. This is established to continue.

[0081] Next, a first conductive layer was formed on the oxide semiconductor layer 103 and the gate insulating layer 102 as a conductive layer. 112, a second conductive layer 113, and a third conductive layer 114 are formed by sputtering or vacuum deposition. The cross section at this stage is shown in Figure 2(C).

[0082] The materials for the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 are the same as those described above. The same material as that of the gate electrode layer 101 can be used.

[0083] Here, the first conductive layer 112 and the third conductive layer 114 are made of titanium, which is a heat-resistant conductive material. and the second conductive layer 113 is made of an aluminum alloy containing neodymium. By doing so, it is possible to reduce the occurrence of hillocks while taking advantage of the low resistivity of aluminum. In this embodiment, the conductive layer has a three-layer structure, but the present invention is not limited to this. For example, a single layer structure of titanium may be used. Alternatively, a laminated structure with aluminum containing silicon may be used.

[0084] Next, a fourth photolithography step is performed to form a resist mask 131, and etching is performed. The unnecessary portions are removed by etching, and the source electrode layer 105a and the drain electrode layer 105b are oxidized. The compound semiconductor layer 103 and the connection electrode 120 are formed. For example, the first conductive layer 112 and the third conductive layer 113 are removed by hot etching or dry etching. The conductive layer 114 is made of titanium, and the second conductive layer 113 is made of an aluminum alloy containing neodymium. In this case, wet etching is performed using hydrogen peroxide or heated hydrochloric acid as an etchant. In this etching step, part of the oxide semiconductor layer 103 is etched. and has a thin region between the source electrode layer 105a and the drain electrode layer 105b. This results in an oxide semiconductor layer 103. A cross-sectional view at this stage is shown in FIG. 3A, and a plan view is shown in FIG.

[0085] At this time, the first conductive layer 112, the third conductive layer 114, and the oxide semiconductor layer 103 are etched. If etching is performed under conditions where the etching selectivity is sufficient, the surface shown in Figure 1(B) will be The resulting transistor structure is one in which the crystalline region of the layer remains.

[0086] In addition, the first conductive layer 112, the second conductive layer 113, the third conductive layer 114, the oxide semiconductor layer Etching of 103 is performed entirely using hydrogen peroxide or heated hydrochloric acid. Therefore, the source electrode layer 105a or the drain electrode layer 105b and the oxide No steps or the like are generated at the edge of the semiconductor layer 103. In addition, wet etching is not used. In order to do this, etching is performed isotropically, and the source electrode layer 105a and the drain electrode layer 10 The end portion of the oxide semiconductor layer 103 is recessed from the resist mask 131. In addition, a transistor 170 can be manufactured in which the crystalline region 106 serves as a channel formation region.

[0087] Here, similarly to the gate electrode layer 101, the above-described light-transmitting oxide conductive layer is used as the source electrode layer. By using the transparent conductive layer 105a and the drain electrode layer 105b, the light transmittance of the pixel portion can be improved, and the aperture ratio can be increased. can also be made higher.

[0088] In addition, the above-mentioned metal film and oxide semiconductor film that will become the source electrode layer 105a and the drain electrode layer 105b are The aforementioned oxide conductive layer can be formed between each of the conductive layers to reduce contact resistance. do.

[0089] In this fourth photolithography step, the source electrode layer 105a and the drain electrode layer 105b are formed. The second terminal 122 made of the same material as the electrode layer 105b is left in the terminal portion. 22 is a source wiring (a source wiring including a source electrode layer 105a or a drain electrode layer 105b). The power supply is electrically connected to the power supply line.

[0090] In addition, in the terminal portion, the connection electrode 120 is connected to a contact formed in the gate insulating layer 102. It is directly connected to the first terminal 121 of the terminal portion through a hole. However, the source wiring or drain wiring of the transistor of the driving circuit is formed through the same process as described above. The gate electrode is directly connected to the gate wiring.

[0091] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a resist mask, the number of resist masks can be reduced, which simplifies the process and This also reduces costs.

[0092] Next, the resist mask 131 is removed, and the oxide insulating layer 107 covering the transistor 170 is removed. The oxide insulating layer 107 can be formed using a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like. For example, a tantalum oxide film or a tantalum oxide film can be used.

[0093] In this embodiment, a silicon oxide film is deposited as the oxide insulating layer by a sputtering method. The substrate temperature during the heating process may be set to a temperature between room temperature and 300° C., and is set to 100° C. in this embodiment. Here, as a method to prevent impurities such as water and hydrogen from being mixed in during film formation, Pre-bake at a temperature between 50°C and 350°C for between 2 and 10 minutes, and do not expose to air. It is desirable to form an oxide insulating layer without causing any damage. The film is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically The target can be formed under a mixed atmosphere of argon and oxygen. A silicon oxide target or a silicon target can be used. For example, a silicon target Silicon oxide can be formed by sputtering under an oxygen and rare gas atmosphere using a silicon dioxide nozzle. The oxide insulating layer formed in contact with the oxide semiconductor layer with reduced resistance is free from moisture and hydrogen. ions and OH - It does not contain impurities such as lactic acid bacteria and blocks them from entering from the outside. It is preferable to use an inorganic insulating film.

[0094] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0095] Next, a second heat treatment is performed in an inert gas atmosphere (preferably at a temperature of 200°C or higher and 400°C or lower, For example, the heating temperature is 250°C or higher and 350°C or lower. For example, the heating temperature is 250°C for 1 hour in a nitrogen atmosphere. A second heat treatment is carried out. Alternatively, a high-temperature, short-time RTA treatment is carried out in the same manner as the first heat treatment. In the second heat treatment, the oxide insulating layer 107 is in contact with the oxide semiconductor layer 103. Since the oxide semiconductor layer 10 is heated in the n-type state by the first heat treatment, the oxide semiconductor layer 10 is turned into an n-type oxide semiconductor layer and is made low in resistance. Oxygen is supplied from the oxide insulating layer 107 to the oxide semiconductor layer 1 03 can be made i-type (high resistance).

[0096] In this embodiment, the second heat treatment is performed after the silicon oxide film is formed. There is no problem if the silicon oxide film is formed afterwards, and it is not limited to the time immediately after the silicon oxide film is formed. stomach.

[0097] In addition, when a heat-resistant material is used for the source electrode layer 105a and the drain electrode layer 105b, In this case, a step using the first heat treatment conditions can be performed at the timing of the second heat treatment. In this case, the heat treatment may be performed only once after the silicon oxide film is formed.

[0098] Next, a fifth photolithography step is performed to form a resist mask, and an oxide insulating layer 1 A contact hole 125 reaching the drain electrode layer 105b is formed by etching in step 07. In addition, the etching here forms a contact hole 122 that reaches the second terminal 122. 7. A contact hole 126 reaching the connection electrode 120 is also formed. Shown in Figure 3(B).

[0099] Next, after removing the resist mask, a light-transmitting conductive film is formed. Indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, hereafter Materials such as ITO can be used, and they are formed by sputtering or vacuum deposition. The etching process for such materials is carried out using a hydrochloric acid solution. However, ITO is not suitable for etching. In order to improve the etching processability, indium oxide oxide is used. A zinc oxide alloy (In2O3-ZnO, hereinafter abbreviated as IZO) may also be used.

[0100] Next, a sixth photolithography step is performed to form a resist mask, and then etching is performed. Then, unnecessary portions of the transparent conductive film are removed to form the pixel electrode layer 110. The gate insulating layer 102 and the oxide insulating layer 107 are used as dielectrics, and the capacitance wiring 108 and the A storage capacitor is formed together with the electrode layer 110 .

[0101] In the sixth photolithography and etching process, the first terminal 12 Light-transmitting conductive layers 128 and 129 are formed above the first and second terminals 122, respectively. The photoconductive layers 128 and 129 serve as electrodes or wiring used for connection with the FPC. The transparent conductive layer 128 connected to the terminal 121 functions as an input terminal of the gate wiring. The transparent conductive layer 129 formed on the second terminal 122 serves as a terminal electrode for connection. , which serves as a connection terminal electrode that functions as an input terminal of the source wiring.

[0102] Next, the resist mask is removed. The cross section at this stage is shown in FIG. 3(C), and the plan view is shown in FIG. 7. show.

[0103] 8(A1) and 8(A2) are a plan view and a cross section of the gate wiring terminal portion at this stage. 8(A1) is a cross-sectional view taken along line C1-C2 in FIG. 8(A2). In FIG. 8(A1), a protective insulating film 154 and a connecting electrode 153 are formed on the protective insulating film 154 and the connecting electrode 153. The transparent conductive layer 155 is a terminal electrode for connection that functions as an input terminal. In FIG. 8(A1), the first terminal 151 and the source terminal 152 are made of the same material as the gate wiring. The connection electrode 153, which is made of the same material as the wiring, overlaps the gate insulating layer 152 via the gate insulating layer 152. The connection electrode 153 and the transparent conductive layer 155 are in direct contact with each other and are electrically conductive. The film 154 is in direct contact with the contact hole for electrical continuity.

[0104] FIG. 8(B1) and FIG. 8(B2) are a plan view and a cross-sectional view of the source wiring terminal portion, respectively. FIG. 8(B1) is a cross section taken along the line D1-D2 in FIG. 8(B2). 8(B1), a protective insulating film 154 and a connection electrode 150 are formed on the protective insulating film 154. The transparent conductive layer 155 is a connection terminal electrode that functions as an input terminal. In FIG. 8(B1), the second terminal 156 made of the same material as the gate wiring is connected to the source It overlaps with a connection electrode 150 electrically connected to the wiring via a gate insulating layer 152 . The second terminal 156 is not electrically connected to the connection electrode 150. If the potential is set to a different potential from the connection electrode 150, for example, floating, GND, 0V, etc., It is possible to form a capacitance for noise countermeasures or static electricity countermeasures. The connection electrode 150 is formed on the transparent conductive layer 15 through a contact hole provided in the protective insulating film 154 . 5 is electrically connected.

[0105] A plurality of gate lines, source lines, and capacitance lines are provided depending on the pixel density. In the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and a A plurality of second terminals, a third terminal having the same potential as the capacitance wiring, etc. are arranged side by side. The number of terminals may be any number and may be determined by the implementer. .

[0106] In this way, a channel-etched transistor 17 was fabricated using six photolithography processes. These are arranged in a matrix to form a pixel section. By configuring the above, one substrate for manufacturing an active matrix type display device In this specification, for convenience, such a substrate is referred to as an active matrix substrate. It is called.

[0107] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0108] Furthermore, this embodiment is not limited to the pixel configuration shown in Fig. 7. A plan view of another example of pixel configuration is shown in Fig. 9. In FIG. 9, no capacitance wiring is provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel and the protective insulating film. and a gate insulating layer are placed on top of each other to form a storage capacitor. In this case, the capacitor wiring and The third terminal connected to the capacitance wiring can be omitted. The same symbols are used for the same parts.

[0109] In an active matrix liquid crystal display device, liquid crystal elements arranged in a matrix are An image is formed by driving the liquid crystal elements. When a voltage is applied between the pixel electrode and the counter electrode, the liquid crystal layer undergoes optical modulation. This optical modulation is perceived by the observer as an image.

[0110] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause image retention. In order to reduce this kind of image retention, a so-called full black display is performed every other frame. There is a driving technique called black insertion.

[0111] In addition, the response speed can be improved by increasing the normal vertical sync frequency by 1.5 times, preferably by more than 2 times. and selects the gradation to be written for each of the divided fields in each frame. There is also a driving technology called double speed driving.

[0112] In addition, multiple LED (light emitting diode) light sources or multiple EL light sources are used as backlights. Each light source constituting the surface light source is independently controlled within one frame period. There is also a driving technology for intermittent lighting. For example, when using LEDs, a single white LED It is also possible to use LEDs with three or more colors. Therefore, the timing of LED light emission can be synchronized with the timing of switching the optical modulation of the liquid crystal layer. This driving technique allows LEDs to be partially turned off, so they can be synchronized. In particular, in the case of video displays where the proportion of black display areas occupying the entire screen is high, the power consumption reduction effect is The results can be seen.

[0113] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0114] In addition, when a light-emitting display device is manufactured, an electrode (also called a cathode) on the low power supply potential side of a light-emitting element is ) is set to, for example, GND, 0V, etc., so the cathode is connected to the terminal at a low power supply potential, e.g. For example, a fourth terminal is provided for setting the voltage to GND, 0V, etc. When manufacturing a device using a MOSFET, a power supply line is provided in addition to the source and gate lines. The slave part is provided with a fifth terminal for electrical connection to the power supply line.

[0115] In this embodiment mode, a manufacturing method will be described using a channel-etched transistor as an example. However, by changing the order of the steps, a transistor with a bottom contact structure was fabricated. It is also possible to do this.

[0116] In addition, since transistors are easily damaged by static electricity, etc., On the other hand, it is preferable to provide a protection circuit for protecting the transistor in the pixel portion on the same substrate. The protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer.

[0117] By the above steps, a transistor having good electrical characteristics and high reliability and a method for manufacturing a semiconductor device using the transistor can be obtained. It is possible to provide a display device that

[0118] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0119] (Embodiment 3) In this embodiment, a part of a driver circuit and a transistor formed on the same substrate are An example of operating the pixel portion will be described.

[0120] In this embodiment mode, a transistor is manufactured on the same substrate by the manufacturing method according to Embodiment Mode 1. A pixel portion and a driver circuit portion are formed in the transistor described in Embodiment 1. The driving circuit section is composed of only n-channel transistors. This is limited to some circuits that can

[0121] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. A driving circuit 5303 and a signal line driving circuit 5304 are arranged in the pixel portion 5301. A plurality of signal lines are arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning direction. The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersecting regions of the scanning lines and the signal lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is also mounted on a flexible printed circuit board (FPC). The timing control circuit 5305 (controller 5306) is connected to the timing control circuit 5305 via a connection part such as a timing control circuit (controller 5306). The power supply is connected to the power supply (also called a controller or control IC).

[0122] The first scanning line driver circuit 5302, the second scanning line driver circuit 5303, and The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. Therefore, the number of external components such as drive circuits can be reduced, leading to cost reduction. In addition, the number of connecting parts (FPC, etc.) between the substrate 5300 and the external drive circuit can be reduced. This allows for improved reliability and yield.

[0123] The timing control circuit 5305 controls the first scanning line driver circuit 5302 to Start signal for scanning line driver circuit (GSP1) (start signal is also called start pulse) , a clock signal (GCK1) for the scanning line driving circuit, etc. Also, the second scanning line driving circuit The line 5303 is connected to a second scanning line driver circuit start signal (GSP2), a scanning line driver It supplies the circuit clock signal (GCK2) etc.

[0124] A signal line driver circuit start signal (SSP) is sent to the signal line driver circuit 5304. Clock signal for signal line driver circuit (SCK), data for video signal (DATA) (simply video The clock signal (CLK) is also called a clock signal, and the latch signal (LAT) is also called a clock signal. may be multiple clock signals with different periods, or an inverted clock signal (CK B) may be supplied together with the first scanning line driver circuit 5302. Either the first or second scanning line driver circuit 5303 can be omitted.

[0125] In FIG. 14B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Depending on the configuration, even if a transistor with a relatively low field effect mobility is used, it is possible to use the same substrate as the pixel portion. Therefore, it is possible to reduce costs and improve yields. This can be achieved by:

[0126] Next, an example of the configuration and operation of a signal line driver circuit configured with n-channel transistors will be described. This will be explained with reference to FIGS. 15(A) and 15(B).

[0127] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N are each configured as a transistor. It consists of transistors 5603_1 to 5603_k (k is a natural number). The transistors 5603_1 to 5603_k are n-channel transistors.

[0128] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The second terminals of the transistors 5603_1 to 5603_k are connected to , and are connected to signal lines S1 to Sk. The gates of the transistors 5603_1 to 5603_k are , and is connected to the wiring 5605_1.

[0129] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0130] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function for controlling the conduction state between the wirings S1 to Sk, that is, the wirings 5604_1 to 5604_k. The transistor 5603_1 has a function of supplying a voltage to the signal lines S1 to Sk. .about.5603_k each function as a switch.

[0131] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. Often a logged signal.

[0132] Next, the operation of the signal line driver circuit of FIG. 15(A) will be explained with reference to the timing chart of FIG. 15(B). 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0133] In the drawings of this embodiment, the distortion of the signal waveform is exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0134] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 603_1 to 5603_k are turned on, and the wiring 5604_1 to 5604_k and the signal line S 1 to Sk are in a conductive state. (S1)~Data(Sk) are input. Data(S1)~Data(Sk) are input. The pixels belonging to the selected row are individually connected to the transistors 5603_1 to 5603_k. That is, the signals are written to the pixels in the first to kth columns. Video signal data (DATA) is written to the pixels belonging to the selected row in order of k columns. .

[0135] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0136] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. Alternatively, a circuit configured with the transistors shown in 2 can be used. All the transistors in the soft resistor 5601 are made up of unipolar transistors. This can be done.

[0137] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register. In some cases, a level shifter or a buffer may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S) are input to the shift register. P) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line, and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. Since all of these must be turned on at the same time, the buffer must be able to pass a large current. is used.

[0138] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 16 and 17.

[0139] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number equal to or greater than 3 (see FIG. 16(A)). The pulse output circuits 10_1 to 10_N are connected to the first wiring 11. A clock signal CK1 is transmitted from the second wiring 12, a second clock signal CK2 is transmitted from the third wiring 13, and a A third clock signal CK3 is supplied through the first wiring 13, and a fourth clock signal CK4 is supplied through the fourth wiring 14. do.

[0140] In addition, in the first pulse output circuit 10_1, a start pulse SP1 from the fifth wiring 15 (first start pulse) is input. n (n is a natural number between 2 and N) is the signal from the previous stage pulse output circuit (previous stage signal) The number OUT(n-1) is input.

[0141] The first pulse output circuit 10_1 is connected to a third pulse output circuit 10_3 located two stages later. Similarly, the n-th pulse output circuit 10_n in the second stage or later receives the signal , the signal from the (n+2)th pulse output circuit 10_(n+2) two stages later (the later stage signal OU T(n+2)) is input.

[0142] Therefore, the pulse output circuit of each stage outputs a signal to be input to the pulse output circuit of the subsequent stage and / or the preceding stage. a first output signal (OUT(1)(SR) to OUT(N)(SR)) for outputting a second signal to another circuit, etc. The second output signals (OUT(1) to OUT(N)) input to the As shown in 6(A), the last two stages of the shift register are connected to the next stage signal OUT(n+ 2) is not input, so for example, the second start pulse SP2 and the third start pulse SP3 are input separately. The configuration may be such that the output pulse SP3 is input to each of the input terminals.

[0143] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0144] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. In the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is is electrically connected to the third wiring 13. In the second pulse output circuit 10_2, The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14. It is being done.

[0145] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 16B, the input terminal 25, the first output terminal 26, and the second output terminal 27. (see).

[0146] In the first pulse output circuit 10_1, a first clock signal CK is input to a first input terminal 21. 1 is input to the second input terminal 22, the second clock signal CK2 is input to the third input terminal 30, A third clock signal CK3 is input to a terminal 23, and a start pulse is input to the fifth input terminal 25, the subsequent signal OUT(3) is input to the first output terminal 2 The first output signal OUT(1)(SR) is output from the first output terminal 6, and the second output signal OUT(2)(SR) is output from the second output terminal 27. The output signal OUT(1) is output.

[0147] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are provided with a three-terminal transistor. In addition to the transistor, a four-terminal transistor 28 (see FIG. 16(C)) can be used. In this specification, a transistor having two gate electrodes via a semiconductor layer is referred to as a In this case, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. The gate electrode of the transistor 28 is also called the upper gate electrode. A first control signal G1 is input to the gate electrode and a second control signal G2 is input to the upper gate electrode. It is an element that can perform electrical control between the In terminal and the Out terminal.

[0148] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a transistor, As a result, the threshold voltage may shift to the negative or positive side. In a transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, A structure capable of controlling the voltage is preferable. In the case of the MOSFET, gate electrodes are provided above and below the channel forming region via gate insulating layers. and / or by controlling the potential of the underlying gate electrode, the threshold voltage can be adjusted to a desired value. It can be controlled.

[0149] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. 16(D). do.

[0150] The pulse output circuit shown in FIG. 16(D) includes the first transistor 31 to the thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a voltage source to which a first high power supply potential VDD is supplied is also provided. a power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. The power supply lines 53 are connected to the first to thirteenth transistors 31 to 33, respectively. A signal or a power supply potential is supplied to the transistor 43 .

[0151] Here, the magnitude relationship of the power supply potentials of the power supply lines in FIG. 16(D) is as follows: the first power supply potential VDD is The second power supply potential VCC is set to a potential equal to or higher than the third power supply potential VSS. The first clock signal (CK1) to the fourth clock signal (CK4) are , is a signal that alternates between H level and L level at regular intervals. For example, when it is H level, it is V DD, and VSS when at L level.

[0152] By making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, The potential applied to the gate electrode of the transistor can be kept low without affecting the operation. This makes it possible to reduce the shift in the threshold voltage of the transistor and suppress degradation.

[0153] Also, as shown in FIG. 16(D), the first transistor 31 to the thirteenth transistor 43, the first transistor 31, the sixth transistor 36 to the ninth transistor It is preferable to use the four-terminal transistor 28 shown in FIG. 16(C) for 39.

[0154] The first transistor 31 and the sixth to ninth transistors 36 to 39 are source The potential of the node to which either the source or drain electrode is connected is controlled by the control signal of the gate electrode. Therefore, it is necessary to switch the gate electrode. Fast response (steep rise of on-current) reduces malfunction of pulse output circuits Therefore, it is preferable to use a four-terminal transistor. By doing so, the threshold voltage can be controlled, and the pulse output circuit can further reduce malfunctions. In FIG. 16(D), the first control signal G1 and the second control signal Although the same control signal is input to G2, a different control signal may be input.

[0155] In FIG. 16(D), the first terminal of the first transistor 31 is electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. There are.

[0156] The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the ninth the first terminal of the fourth transistor 39, and the gate electrode of the fourth transistor 3 The gate electrode of the transistor 4 is electrically connected to the transistor 4.

[0157] The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal The terminal is electrically connected to the first output terminal 26.

[0158] The fourth transistor 34 has a first terminal electrically connected to the power supply line 53 and a second terminal The output terminal 26 is electrically connected to the

[0159] The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the first transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The gate electrode is electrically connected to the fourth input terminal 24 .

[0160] The sixth transistor 36 has a first terminal electrically connected to the power supply line 52 and a second terminal The gate electrode of the first transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The gate electrodes (lower gate electrode and upper gate electrode) are connected to the fifth input terminal 25. are electrically connected.

[0161] The seventh transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth and a gate electrode (lower gate electrode and The upper gate electrode is electrically connected to the third input terminal 23 .

[0162] The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a fourth terminal connected to the gate electrode of the fourth transistor 33. The gate electrode of the transistor 34 is electrically connected to the gate electrode of the gate electrode (the lower gate electrode and The upper gate electrode is electrically connected to a second input terminal 22 .

[0163] The ninth transistor 39 has a first terminal connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The second terminal of the third transistor 32 is electrically connected to the gate of the third transistor 33. The gate electrode of the tenth transistor 40 is electrically connected to the gate electrode of the tenth transistor 40. The lower gate electrode and the upper gate electrode are electrically connected to a power supply line 52 .

[0164] The tenth transistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal The terminal is electrically connected to the second output terminal 27, and the gate electrode of the ninth transistor 39 It is electrically connected to the second terminal.

[0165] The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the second transistor 32 is electrically connected to the output terminal 27 of the second transistor 32. and the gate electrode of the fourth transistor 34 .

[0166] The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the seventh transistor 37 is electrically connected to the output terminal 27 of the second transistor. The gate electrodes are electrically connected to the electrodes (lower gate electrode and upper gate electrode).

[0167] The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 53 and a second terminal The gate electrode of the seventh transistor 37 is electrically connected to the output terminal 26 of the first transistor. The gate electrodes are electrically connected to the electrodes (lower gate electrode and upper gate electrode).

[0168] In FIG. 16(D), the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 17(A)).

[0169] FIG. 17(A) shows the pulse output circuit described in FIG. 16(D) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the signal input to or output from the second output terminal 27.

[0170] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse (SP1) is input to the fourth input terminal 24, and a signal CK3 is input to the fifth input terminal 25. The next stage signal OUT(3) is input to the input terminal 25 of the The signal OUT(1)(SR) is output, and the second output signal OUT( 1) is output.

[0171] A transistor has at least three terminals including a gate, a drain, and a source. The element has a channel region between a drain region and a source region, and the drain A current can flow through the source region, the channel region, and the source region. The drain and source are different depending on the transistor structure and operating conditions. Therefore, it is difficult to determine whether the source or drain is the In some cases, the functional region is not called a source or a drain. These may be referred to as the first terminal and the second terminal, respectively.

[0172] In FIG. 17(A), the node A is set in a floating state, and the bootstrap operation is performed. A capacitor may be provided separately to maintain the potential of the node B. A capacitor having one electrode electrically connected to the node B may be provided separately.

[0173] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. The shift register is a scanning line driver circuit. In FIG. 17(B), period 61 is a vertical blanking period, and period 62 corresponds to a gate selection period. .

[0174] As shown in FIG. 17A, the ninth power supply voltage Vcc is applied to the gate electrode. By providing the transistor 39, the following occurs before and after the bootstrap operation: The advantages are as follows:

[0175] If the ninth transistor 39, to whose gate electrode the second power supply potential VCC is applied, is not present, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and source, the gate and drain In both cases, a large bias voltage is applied, which causes a large stress on the transistor. This can be a factor in deterioration.

[0176] Therefore, a ninth transistor 39 is provided to the gate electrode of which the second power supply potential VCC is applied. By setting the voltage at node A to 0 V, the voltage at node A rises due to the bootstrap operation, but the voltage at node A rises due to the first This can prevent the potential of the second terminal of the transistor 31 from increasing. By providing the ninth transistor 39, the gate and source of the first transistor 31 are connected Therefore, the value of the negative bias voltage applied between the electrodes can be reduced. By using this circuit configuration, a voltage applied between the gate and source of the first transistor 31 is Since the negative bias voltage applied to the first transistor 31 can be reduced, the Deterioration can be suppressed.

[0177] The ninth transistor 39 is connected to the second terminal of the first transistor 31 and the third transistor 32. The first terminal and the second terminal may be connected between the gate of the transistor 33 and the transistor 34. In the case of a shift register having a plurality of pulse output circuits in this embodiment, the scanning line driving In a signal line driver circuit having more stages than the circuit, the ninth transistor 39 may be omitted. This has the advantage of reducing the number of transistors.

[0178] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide. By using a semiconductor, the off-state current of a transistor can be reduced, and the on-state current and the Therefore, the degree of degradation can be reduced. Therefore, malfunctions in the circuit can be reduced. Compared to transistors using silicon, a high potential is applied to the gate electrode. The degree of deterioration of the transistor is small. Therefore, the power supply line that supplies the second power supply potential VCC The same operation can be obtained by supplying the first power supply potential VDD to the Since the number of lines can be reduced, the circuit can be made smaller.

[0179] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 the clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38 The input electrodes (lower gate electrode and upper gate electrode) are supplied with a voltage by a second input terminal 22. The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). a clock signal provided by the second input terminal 22 to the gate electrode of the eighth transistor; The gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode 38 are connected to the third input terminal 23. Therefore, the same effect can be achieved by rearranging the wiring so that the clock signal is supplied. do.

[0180] In the shift register shown in FIG. 17A, the seventh transistor 37 and the eighth transistor The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. 8 is turned off, the potentials of the second input terminal 22 and the third input terminal 23 The voltage drop at node B is caused by the voltage drop at node B. and the potential of the gate electrode of the eighth transistor 38 decreases. This will be the case.

[0181] On the other hand, in the shift register shown in FIG. 17A, the seventh transistor 37 and the eighth transistor The seventh transistor 37 is turned on, and the eighth transistor 38 is turned on. Then the seventh transistor 37 is off, and the eighth transistor 38 is off. By turning off the input terminal 38, the voltages of the second input terminal 22 and the third input terminal 23 are The drop in the potential of the node B caused by the drop in the potential is absorbed by the gate electrode of the eighth transistor 38. This can be reduced to a single time by reducing the potential.

[0182] Therefore, the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) A clock signal CK3 is supplied to the third input terminal 23, and the eighth transistor 38 The gate electrodes (lower gate electrode and upper gate electrode) are connected to the second input terminal 22. It is preferable to have a wiring relationship in which the clock signal CK2 is supplied. This is because the number of fluctuations in position is reduced, and noise can be reduced.

[0183] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0184] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0185] (Fourth embodiment) In this embodiment, the transistors described in Embodiments 1 and 2 are used in a pixel portion and a driver circuit. A display device having a display function formed by the above method will be described.

[0186] Display devices include display elements, such as liquid crystal elements (also called liquid crystal display elements). A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by pressure, specifically inorganic EL (Electroluminescent) Electro Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. It is also possible to use a display medium whose contrast changes due to an electrical effect.

[0187] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon A module with a TAB tape attached, a printed wiring board is attached to the end of the TAB tape. The display element is a COG (Chip On Glass) type. This also includes all modules on which ICs (integrated circuits) are directly mounted.

[0188] In this embodiment, the appearance and cross section of a liquid crystal display panel, which is one mode of a display device, will be described. This will be explained with reference to FIG. 20. FIGS. 20(A1) and 20(A2) are top views of a liquid crystal display panel. Therefore, FIG. 20(B) corresponds to a cross-sectional view taken along line MN in FIGS. 20(A1) and 20(A2). The liquid crystal display panel includes transistors 4010 and 4011 including oxide semiconductor layers. A liquid crystal element 4013 is formed between a first substrate 4001 and a second substrate 4006 by a sealant 4005. The structure is sealed.

[0189] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the substrate 4004. The driver circuit 4004 includes a first substrate 4001, a sealing material 4005, a second substrate 4006, and a The first substrate 4001 is sealed together with the liquid crystal layer 4008 by the sealing material. A single crystal semiconductor or a polycrystalline semiconductor is formed in a region different from the region surrounded by 4005. A signal line driver circuit 4003 formed by the above is mounted.

[0190] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. This is an example of mounting a signal line driver circuit 4003 by the OG method. This is an example in which the signal line driver circuit 4003 is mounted by the method.

[0191] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 20B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4011 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided on the transistor 4010. An insulating layer 4020 is provided on the O11.

[0192] The transistors 4010 and 4011 each include the oxide semiconductor layer described in Embodiments 1 and 2. In this embodiment, a highly reliable transistor including The transistors 4010 and 4011 are n-channel transistors.

[0193] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4044. A conductive layer 4040 is provided in a position overlapping the panel formation region. By placing the gate electrode at a position overlapping the channel formation region of the semiconductor layer, the The amount of change in the threshold voltage of the transistor 4011 can be reduced. The second gate electrode 4040 is set to the same potential as the gate electrode layer of the transistor 4011. The conductive layer 4040 can function as a gate electrode of the transistor 4011. The potential of the conductive layer 4040 may be different from that of the ground electrode layer. It may be 0V or may be in a floating state.

[0194] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 400. 6. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films. Although not shown, the color filter is formed on the first substrate 4001 or the second substrate 4002. The electrodes may be provided on either side of the substrate 4006.

[0195] The first substrate 4001 and the second substrate 4006 may be made of glass, ceramics, plastic, or the like. As for plastic, FRP (Fiberglass -Reinforced Plastics) plate, PVF (Polyvinyl Fluoride) Film, polyester film, or acrylic resin film can be used. Also, a sheet with a structure in which aluminum foil is sandwiched between PVF film or polyester film. can also be used.

[0196] In addition, columnar spacers 4035 are provided to control the thickness (cell gap) of the liquid crystal layer 4008. The spacers 4035 are obtained by selectively etching the insulating film. The shape of the spacer is not limited to a columnar shape, and for example, a spherical spacer may be used. It's okay to be there.

[0197] The counter electrode layer 4031 is connected to a common potential The conductive particles disposed between the pair of substrates are electrically connected to the wiring by using the common connection part. The counter electrode layer 4031 and the common potential line can be electrically connected via the conductive layer. The particles are contained in the sealing material 4005 .

[0198] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the blue phase liquid crystal and the chiral agent has a response speed of 10 μsec or more. It is optically isotropic, requiring no alignment treatment, and has no viewing angle dependency. When a blue phase is used, the configuration is not limited to that shown in FIG. The electrode layer corresponding to the pixel electrode layer 4030 is formed on the same substrate side as the pixel electrode layer 4030. A code configuration may also be used.

[0199] Although the present embodiment is an example of a transmissive liquid crystal display device, a reflective liquid crystal display device or a semi-transmissive liquid crystal display device may also be used. It can also be applied to a liquid crystal display device.

[0200] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0201] In addition, in this embodiment, surface irregularities caused by transistors are reduced and reliability is improved. Therefore, the transistor is covered with an insulating layer (insulating layer 4020, insulating The protective film is made of a protective material that protects the surface from organic matter and metals floating in the air. It is intended to prevent the intrusion of contaminating impurities such as metals and water vapor, and a dense membrane is preferable. The protective film is made by sputtering silicon oxide film, silicon nitride film, silicon oxynitride film, and nitride film. silicon oxide film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, Alternatively, an aluminum nitride oxide film may be formed as a single layer or a stacked layer. Although an example in which the protective film is formed by sputtering is shown, there is no particular limitation and other methods may also be used.

[0202] In this embodiment, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the layer 4020, a silicon oxide film is formed by sputtering. When a silicon oxide film is used as the source electrode layer and the drain electrode layer, the aluminum It is effective in preventing hillocks on rubber films.

[0203] In addition, a silicon nitride film is formed as the second layer of the protective film by using a sputtering method. When a silicon nitride film is used, mobile ions such as sodium penetrate into the semiconductor region, Changes in the electrical characteristics of the transistor can be suppressed.

[0204] After forming the protective film, the oxide semiconductor layer is annealed (at 300°C or higher and 400°C or lower). may be performed.

[0205] An insulating layer 4021 is formed as a planarizing insulating film. The insulating layer 4021 is made of an acrylic resin. Heat resistance of resins such as grease, polyimide, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (boron phosphorus glass) ) can be used. It is possible to laminate a plurality of insulating films made of these materials. The insulating layer 4021 may be formed in this manner.

[0206] The siloxane resin is a Si—O— compound formed using a siloxane material as a starting material. It is a resin containing Si bonds. The substituents of siloxane resins include organic groups (e.g., alkyl groups and An aryl group or a fluoro group may be used. The organic group may also have a fluoro group. stomach.

[0207] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a liquid material, a baking The oxide semiconductor layer can be annealed (at 300°C or higher and 400°C or lower) at the same time. The baking process of the insulating layer 4021 and the annealing process of the oxide semiconductor layer are combined, thereby reducing the number of steps. can be reduced.

[0208] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide , indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, Use a transparent conductive material such as indium tin oxide doped with silicon oxide. can be done.

[0209] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (also known as a conductive polymer). The conductive composition may be used to form the conductive layer. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 7.0 at a wavelength of 550 nm. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0% or more. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0210] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0211] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are supplied to 002 via FPC4018.

[0212] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed of the same conductive film as that of the transistors 4010 and 4011. The source electrode layer and the drain electrode layer are formed using the same conductive film.

[0213] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0214] In addition, in FIG. 20, a signal line driver circuit 4003 is mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Only a part of the paths or only a part of the scanning line driver circuit may be implemented.

[0215] FIG. 21 shows a liquid crystal display device using a substrate 2600 on which the transistors shown in Embodiments 1 and 2 are formed. 1 shows an example of a liquid crystal display module.

[0216] FIG. 21 shows an example of a liquid crystal display module, in which a substrate 2600 and an opposing substrate 2601 are made of a sealing material. 2602, and a pixel portion 2603 including a transistor and the like and a liquid crystal layer are provided between them. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. The light source is a cold cathode fluorescent lamp (CFL). 2610 and a reflector 2611, and the circuit board 2612 is a flexible wiring board. 2609 is connected to the wiring circuit section 2608 of the substrate 2600, and the control circuit and the power supply It also has a retardation film between the polarizer and the liquid crystal layer. The layers may be laminated in this state.

[0217] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated) Birefringence mode, FLC (Ferroelectric Liquid Crystal uid Crystal) mode, AFLC(AntiFerroelectric L You can use modes such as IQID Crystal.

[0218] As a result, a highly reliable liquid crystal display panel can be constructed.

[0219] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0220] (Embodiment 5) In this embodiment, a display device using the transistors described in Embodiments 1 and 2 is An example of a child paper is shown below.

[0221] FIG. 13 shows an active matrix electronic paper as an example of a display device. The transistor 581 used in the above embodiment may be the transistor described in Embodiments 1 and 2. It can be used.

[0222] The electronic paper in Figure 13 is an example of a display device that uses the twisting ball display method. The spherical display method uses black and white spherical particles on the first electrode layer and the second electrode layer. The spherical particles are placed between the first and second electrode layers, and a potential difference is generated between the first and second electrode layers to change their orientation. This is a method of displaying by controlling the above.

[0223] The transistor 581 is a bottom-gate transistor, and the source electrode layer or The insulating layers 585, 584, and 583 are formed with openings to expose the first electrode. The first electrode layer 587 and the second electrode layer 588 are electrically connected to each other. , black area 590a, white area 590b, and liquid-filled cavity 594. The spherical particles 589 are surrounded by a filler 595 such as a resin. In this embodiment, the first electrode layer 587 is a pixel electrode. The second electrode layer 588 corresponds to the transistor electrode, and the second electrode layer 588 corresponds to the common electrode. The resistor 581 is electrically connected to a common potential line provided on the same substrate.

[0224] Also, instead of the twist ball, an electrophoretic element can be used. and a 20 μm diameter or larger particle containing positively charged white particles and negatively charged black particles. Microcapsules with a size of approximately 0 μm or less are used. When an electric field is applied to the microcapsules by the first and second electrode layers, The white particles and the black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, and The device is generally called electronic paper. Electrophoretic display elements are liquid crystal display elements. It has a higher reflectivity than other light sources, so auxiliary lights are not required, and it consumes less power and is suitable for use in dimly lit areas. The display can be recognized even when there is no power supply to the display. Even if the image is displayed, it can be retained, so it can be easily transmitted from the radio wave source to the display function. When a display device (also referred to as a semiconductor device or a semiconductor device including a display device) is placed far away Even if the image is displayed, it is possible to store the displayed image.

[0225] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0226] (Sixth embodiment) In this embodiment, a display device using the transistors described in Embodiments 1 and 2 is used. An example of a display device is shown below. Here, an electroluminescent display element is used as a display element of the display device. A light-emitting element using electroluminescence is shown. are distinguished by whether the luminescent material is an organic compound or an inorganic compound, and generally, The former is called an organic EL element, and the latter is called an inorganic EL element.

[0227] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0228] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. It is a localized emission that uses

[0229] In this example, an organic EL element is used as the light-emitting element. FIG. 10 is a diagram showing an example of a pixel configuration to which half-tone driving can be applied.

[0230] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The n-channel semiconductor device shown in Embodiments 1 and 2 in which an oxide semiconductor layer is used for a channel formation region An example in which two capacitor-type transistors are used in one pixel is shown.

[0231] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (a source electrode and a drain electrode) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405. It is connected to the gate of the driving transistor 6402. The driving transistor 6402 , the gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 64 07, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on one substrate.

[0232] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is determined based on the high power supply potential set to the power supply line 6407. The low power supply potential may be set to, for example, GND or 0V. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404, In order to make the light emitting element 6404 emit light by passing a current through the transistor 404, a high power supply potential and a low power supply potential are applied. The potentials are set so that the potential difference is equal to or greater than the voltage required for the light emitting element 6404 to emit light. do.

[0233] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is A capacitance may be formed between the region and the gate electrode.

[0234] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0235] Also, when analog grayscale driving is used instead of digital time grayscale driving, the signal input is different. By using the same pixel configuration as in FIG. 18, it is possible to use the same pixel configuration as in FIG.

[0236] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0237] Note that the pixel configuration shown in Fig. 18 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, or a logic circuit may be added to .

[0238] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be explained using an example in which the capacitor is n-type. The transistors 7001, 7011, and 7021 used in the display device of (C) are The transistors described in the first and second aspects can be used.

[0239] The light-emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. For example, a top-emission structure in which light is extracted from the surface opposite to the substrate on which the transistor is formed, or a substrate side There is also a bottom-emission structure that extracts light from the top surface. There are also light-emitting elements, and the pixel configuration of the present invention can be used for light-emitting elements of any emission structure.

[0240] A light emitting element with a bottom emission structure will be described with reference to FIG.

[0241] The transistor 7011 is an n-type transistor, and light emitted from the light-emitting element 7012 is incident on the first electrode 701 19A shows a cross-sectional view of a pixel in the case where light is emitted to the side 3 of the transistor 7011. The first conductive layer 7017 of the light-emitting element 7012 is electrically connected to the drain electrode layer. A first electrode 7013 is formed on the first electrode 7013, an EL layer 7014 is formed on the first electrode 7013, and a second electrode 7015 is formed on the second electrode 7015. The poles 7015 are stacked in order.

[0242] The light-transmitting conductive layer 7017 may be formed of indium oxide containing tungsten oxide, tungsten oxide, or the like. Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, titanium oxide Indium tin oxide, indium tin oxide, indium zinc oxide, silicon oxide A light-transmitting conductive film such as a doped indium tin oxide film can be used.

[0243] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the first electrode 7013 is used as a cathode, a material having a relatively small work function, for example, Alkali metals (Li, Cs, etc.), alkaline earth metals (Mg, Ca, Sr, etc.), alkali Metals and alloys containing alkaline earth metals (Mg:Ag, Al:Li, etc.), or Yb and Er In FIG. 19A, the thickness of the first electrode 7013 is set to a value that allows light to pass through. For example, the thickness of an aluminum film having a film thickness of 20 nm is set to a thickness of about 5 nm to 30 nm. The aluminum film is used as the first electrode 7013 .

[0244] After laminating the light-transmitting conductive film and the aluminum film, the light-transmitting conductive film is selectively etched. The conductive layer 7017 and the first electrode 7013 may be formed. It can be etched using a etch.

[0245] The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane When a photosensitive resin material is used for the partition wall 7019, a resist The step of forming a mask can be omitted.

[0246] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is made of at least The EL layer 7 may be a single layer or a laminate of multiple layers, as long as it includes a light-emitting layer. When the electrode 7014 is made up of multiple layers, an electrode is formed on the first electrode 7013 which functions as a cathode. The electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer are laminated in this order. Of these, it is not necessary to provide all of the layers other than the light-emitting layer.

[0247] The stacking order is not limited to the above, and the first electrode 7013 may function as an anode. Layers of hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked on top of 7013 in this order. However, the first electrode 7013 may function as a cathode. It is better to stack the electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order. This can suppress a voltage rise in the drive circuit section, thereby reducing power consumption.

[0248] In addition, various materials can be used for the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, the work function is relatively Large materials such as ZrN, Ti, W, Ni, Pt, Cr, etc., ITO, IZO, Zn A transparent conductive material such as O is preferable. Therefore, a metal that blocks light or a metal that reflects light is used. An ITO film is used as the electrode 7015 and a Ti film is used as the shielding film 7016 .

[0249] The region where the first electrode 7013, the EL layer 7014, and the second electrode 7015 are stacked is This corresponds to the light-emitting element 7012. In the case of the element structure shown in FIG. Light emitted from the first electrode 7013 is emitted to the first electrode 7013 side as shown by the arrow.

[0250] In FIG. 19A, the light emitted from the light emitting element 7012 is reflected by the color filter layer. 7033, and passes through the insulating layer 7032, the oxide insulating layer 7031, the gate insulating layer 7030, and The light is then emitted through the substrate 7010.

[0251] The color filter layer 7033 can be formed by a droplet discharge method such as an ink jet method, a printing method, a photolithography method, or the like. It can be formed by an etching method using lithography technology.

[0252] The color filter layer 7033 is formed by an overcoat layer 7034 and a protective insulating layer 7035. In FIG. 19(A), the overcoat layer 7034 is illustrated as being thin. However, it also has the function of flattening the unevenness caused by the color filter layer 7033. The overcoat layer 7034 can be formed from a resin material such as an acrylic resin.

[0253] Also, a protective insulating layer 7035, an overcoat layer 7034, a color filter layer 7033, an insulating layer A contact extending to the drain electrode layer formed in the edge layer 7032 and the oxide insulating layer 7031. The holes are arranged at positions overlapping with the partition walls 7019 .

[0254] Next, a light emitting element with a dual emission structure will be described with reference to FIG. 19(B).

[0255] In FIG. 19B, a light-transmitting A first electrode 7023 and an EL layer 7024 included in a light-emitting element 7022 are formed on the conductive layer 7027. , and a second electrode 7025 are laminated in this order.

[0256] The light-transmitting conductive layer 7027 is made of indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide containing titanium oxide, Indium oxide containing titanium oxide Indium tin oxide, Indium tin oxide, Indium zinc oxide, Silicon oxide added A light-transmitting conductive film such as an indium tin oxide film can be used.

[0257] In addition, various materials can be used for the first electrode 7023. For example, When O23 is used as the cathode, a material with a relatively small work function, such as alkali gold, is used. metals (Li, Cs, etc.), alkaline earth metals (Mg, Ca, Sr, etc.), alkali metals and alkali Alloys containing alkaline earth metals (Mg:Ag, Al:Li, etc.) or rare earths such as Yb and Er In this embodiment, the first electrode 7023 is used as a cathode, and the film The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). An aluminum film of 1 nm is used as the first electrode 7023 .

[0258] After laminating the light-transmitting conductive film and the aluminum film, the light-transmitting conductive film is selectively etched. The conductive layer 7027 and the first electrode 7023 may be formed using the same resist mask. can be etched using

[0259] The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane When a photosensitive resin material is used for the partition wall 7029, a resist mask is used. The step of forming a mask can be omitted.

[0260] The EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 is at least The EL layer 7 may be a single layer or a laminate of multiple layers, as long as it includes a light-emitting layer. When the electrode 7024 is made up of multiple layers, an electrode is formed on the first electrode 7023 which functions as a cathode. The electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer are laminated in this order. Of these, it is not necessary to provide all of the layers other than the light-emitting layer.

[0261] The stacking order is not limited to the above, and the first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer may be laminated in this order. The first electrode 7023 functions as a cathode, and an electron injection layer and an electron The voltage of the drive circuit section is lower when the transport layer, light-emitting layer, hole transport layer, and hole injection layer are stacked in this order. This can suppress the rise in temperature and reduce power consumption.

[0262] In addition, various materials can be used for the second electrode 7025 formed on the EL layer 7024. For example, when the second electrode 7025 is used as an anode, the work function is relatively It is preferable to use a transparent conductive material such as ITO, IZO, or ZnO. In this embodiment, the second electrode 7025 is used as an anode, and a thin film containing silicon oxide is used. An ITO film is formed.

[0263] The region where the first electrode 7023, the EL layer 7024, and the second electrode 7025 are stacked is This corresponds to the light-emitting element 7022. In the case of the element structure shown in FIG. 19(B), The light emitted from the second electrode 7025 side and the first electrode 7023 side is Shoots in both directions.

[0264] In FIG. 19B, light emitted from the light-emitting element 7022 toward the first electrode 7023 One light passes through the color filter layer 7043 and enters the insulating layer 7042 and the oxide insulating layer 704 1. The light is emitted through the first gate insulating layer 7040 and the substrate 7020.

[0265] The color filter layer 7043 can be formed by a droplet discharge method such as an ink jet method, a printing method, a photolithography method, or the like. It can be formed by an etching method using lithography technology.

[0266] The color filter layer 7043 is formed by an overcoat layer 7044 and a protective insulating layer 7045. is covered with

[0267] Also, a protective insulating layer 7045, an overcoat layer 7044, a color filter layer 7043, an insulating layer A contact extending to the drain electrode layer formed in the edge layer 7042 and the oxide insulating layer 7041. The holes are arranged at positions overlapping with the partition walls 7029 .

[0268] However, if a light-emitting element with a dual-side emission structure is used and both display surfaces are full color, Since light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is required. It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0269] Next, a light emitting element with a top emission structure will be described with reference to FIG.

[0270] In FIG. 19C, a light-emitting element electrically connected to the drain electrode layer of the transistor 7001 is A first electrode 7003 of the transistor 7002 is formed, and an EL layer 70 is formed on the first electrode 7003. 04 and a second electrode 7005 are laminated in this order.

[0271] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a relatively small work function, such as an alkali metal (L i, Cs, etc.), alkaline earth metals (Mg, Ca, Sr, etc.), alkali metals and alkalis Alloys containing earth metals (Mg:Ag, Al:Li, etc.) or rare earth metals such as Yb and Er etc. are preferred.

[0272] The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane When a photosensitive resin material is used for the partition wall 7009, a resist mask is used. The step of forming a mask can be omitted.

[0273] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is The EL layer 7 may be a single layer or a laminate of multiple layers, as long as it includes a light-emitting layer. When the electrode 7004 is made up of multiple layers, an electrode is placed on the first electrode 7003 which functions as a cathode. The electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer are laminated in this order. Of these, it is not necessary to provide all of the layers other than the light-emitting layer.

[0274] The stacking order is not limited to the above, and the hole injection layer may be formed on the first electrode 7003 used as an anode. Alternatively, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order.

[0275] In this embodiment, a titanium film, an aluminum film, and a titanium film are laminated in this order, and a hole is formed on the laminated film. The hole injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are stacked in this order, and M g: A laminate of Ag alloy thin film and ITO is formed.

[0276] However, when the transistor 7001 is an n-type, an electron injection layer and an electron The order of stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer is advantageous in terms of the drive circuit. This makes it possible to suppress voltage rise and reduce power consumption.

[0277] The second electrode 7005 is formed using a light-transmitting conductive material, for example. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide, indium zinc oxide, indium tin oxide with silicon oxide added, etc. A light-transmitting conductive film may also be used.

[0278] The region where the first electrode 7003, the EL layer 7004, and the second electrode 7005 are stacked is In the case of the pixel shown in FIG. 19C, the light emitting element 7002 The emitted light is emitted to the second electrode 7005 side as shown by the arrow.

[0279] The drain electrode layer of the transistor 7001 is formed by an oxide insulating layer 7051 and a protective insulating layer 7052. 7052 and the insulating layer 7055 through a contact hole. Make an electrical connection.

[0280] The planarization insulating layer 7053 is made of polyimide, acrylic, benzocyclobutene, polyamide, ethylene In addition to the above resin materials, low dielectric constant materials ( low-k materials), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron gas) In addition, a plurality of insulating films made of these materials can be stacked. The planarization insulating layer 7053 may be formed by the following method. There is no particular limitation, and depending on the material, methods such as sputtering, SOG, spin coating, dipping, Spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), Doctor knife, roll coater, curtain coater, knife coater, etc. can be used. can.

[0281] In addition, a partition wall 7009 is provided to insulate the first electrode 7003 from the first electrode of an adjacent pixel. The partition wall 7009 is made of an organic resin such as polyimide, acrylic, polyamide, or epoxy. The partition wall 7009 is formed using a photosensitive film, an inorganic insulating film, or an organic polysiloxane. When the resin material is used, the step of forming a resist mask can be omitted.

[0282] In addition, when full color display is performed in the structure of FIG. 19(C), for example, the light emitting element 70 02 is a green light emitting element, one of the adjacent light emitting elements is a red light emitting element, and the other adjacent light emitting element is a red light emitting element. The light emitting element on one side is a blue light emitting element. In addition to these three color light emitting elements, a white element is also used. A light-emitting display device capable of full-color display may be manufactured by adding four types of light-emitting elements.

[0283] In addition, all the light emitting elements to be arranged are white light emitting elements, and a color A sealing substrate having a filter or the like is arranged, and a light-emitting display capable of full color display is provided. A material that emits a single color such as white light may be formed, and a color filter or a color By combining conversion layers, full color display is possible.

[0284] Of course, a single-color display may be performed. For example, a lighting device may be formed using white light. Alternatively, a monochromatic light emitting device may be used to form an area color type light emitting device.

[0285] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0286] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0287] In addition, an example in which a transistor for controlling the driving of a light-emitting element is electrically connected to a light-emitting element is shown. As shown in the figure, a current control transistor is connected between the transistor and the light emitting element. It may be configured as follows.

[0288] Note that the display device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the invention are possible.

[0289] Next, a display device corresponding to one mode of a display device to which the transistor described in Embodiments 1 and 2 is applied will be described. The appearance and cross section of the optical display panel (also called a light-emitting panel) will be explained with reference to FIG. 22. FIG. 22 shows a structure in which a transistor and a light-emitting element formed on a first substrate are sandwiched between the first substrate and the second substrate. 22(B) is a top view of the panel sealed with a sealant, and FIG. 22(A) is a top view of the panel sealed with a sealant. -Equivalent to the cross-sectional view at I.

[0290] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0291] In addition, a pixel portion 4502, a signal line driver circuit 4503a, 4503b and the scanning line driver circuits 4504a and 4504b have a plurality of transistors. 22B, a transistor 4510 included in a pixel portion 4502 and a signal line driver 4 illustrates a transistor 4509 included in a driving circuit 4503a.

[0292] The transistors 4509 and 4510 have an In-Ga-Zn-O based film as an oxide semiconductor layer. The highly reliable transistors described in Embodiments 1 and 2 can be applied to this embodiment. In this embodiment, the transistors 4509 and 4510 are n-channel transistors. do.

[0293] The channel of the oxide semiconductor layer of the transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the panel formation region. By placing it at a position that overlaps with the channel formation region of the semiconductor layer, It is possible to reduce the amount of change in the threshold voltage of the transistor 4509. The second gate electrode 540 is set to the same potential as the gate electrode layer of the transistor 4509. The conductive layer 4540 can also function as a gate electrode of the transistor 4509. The potential of the conductive layer 4540 may be different from that of the ground electrode layer. Alternatively, it may be in a floating state.

[0294] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The electrode layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light-emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0295] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. The partition wall 4520 is made of a photosensitive material and has an opening whose side wall is a curved inclined surface. It is preferably formed on the first electrode layer 4517 .

[0296] The electroluminescent layer 4512 is not limited to a single layer, and may be formed by stacking a plurality of layers.

[0297] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon nitride oxide film, a DLC film, etc.

[0298] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0299] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the transistors 4509 and 451 The source electrode layer and the drain electrode layer of the transistor 10 are formed from the same conductive film as the source electrode layer and the drain electrode layer of the transistor 10.

[0300] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0301] The substrate positioned in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, glass plates, plastic plates, polyester films or acrylic A light-transmitting material such as a film is used.

[0302] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used. do.

[0303] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. It is possible to apply an anti-glare treatment that can diffuse reflected light and reduce glare.

[0304] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed by a separately formed single crystal semiconductor or polycrystalline semiconductor is mounted. Alternatively, only the signal line driver circuit, only the scanning line driver circuit, or both of them may be used. The portion may be separately formed and mounted, and the present embodiment is not limited to the configuration of FIG.

[0305] Through the above steps, a highly reliable light-emitting display device (display panel) can be formed.

[0306] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0307] (Embodiment 7) The display device to which the transistor described in Embodiments 1 and 2 is applied can be used for electronic paper. Electronic paper can be used in all kinds of electronic devices that display information. For example, electronic books, postal mail, etc. can be displayed using electronic paper. Used for advertisements on trains and other vehicles, and for display on various cards such as credit cards. An example of an electronic device is shown in Figures 11 and 12.

[0308] FIG. 11(A) shows a poster 2631 made of electronic paper. When printed materials are used, the advertisements are replaced manually, but when electronic paper is used, The advertisement display can be changed in a short time. It may be configured to be capable of transmitting and receiving.

[0309] FIG. 11(B) shows an advertisement 2632 inside a vehicle such as a train. When using printed paper, advertisements are exchanged manually, but with electronic paper, This allows you to change the display of your advertisements in a short time without requiring a lot of manpower. It is possible to obtain a stable image without any distortion. It may also be possible to use the following.

[0310] 12 shows an example of an electronic book. For example, an electronic book 2700 has a housing 27 It consists of two housings, housing 2701 and housing 2703. 3 is integrated with a shaft portion 2711, and performs opening and closing operations around the shaft portion 2711. This configuration allows the user to operate the device in a manner similar to browsing a paper book. It becomes Noh.

[0311] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 12) and An image can be displayed on the display unit 2707 in FIG.

[0312] 12 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0313] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0314] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0315] (Embodiment 8) The display devices using the transistors described in Embodiments 1 and 2 can be used in a variety of electronic devices (games, The electronic device can be applied to, for example, a television set (including a television (also called TV receivers), computer monitors, digital cameras, etc. digital cameras, digital video cameras, digital photo frames, mobile phones (mobile phones, mobile phones) (also called "talking device"), portable game consoles, personal digital assistants, audio playback devices, pachinko machines, and other large Examples include game consoles.

[0316] FIG. 23A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this case, the housing 9601 is supported by a stand 9605. The figure shows the configuration.

[0317] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The display 9609 allows you to change channels and control the volume. In addition, the remote control operation device 9610 can be used to operate the video displayed on the remote control device. A display unit 9607 for displaying information output from the computer operating device 9610 may be provided. stomach.

[0318] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0319] FIG. 23B shows an example of a digital photo frame. The frame 9700 has a display unit 9703 built into a housing 9701. 3 is capable of displaying various images, for example, images taken with a digital camera. By displaying data, it can function like a regular photo frame.

[0320] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0321] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0322] FIG. 24(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 24(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient that the display device according to the present invention is included, and other auxiliary equipment is provided as appropriate. The portable gaming machine shown in FIG. 24(A) can play the program recorded on the recording medium. It has the function of reading RAM or data and displaying it on the display, and wireless communication with other portable gaming machines. The portable gaming machine shown in FIG. 24(A) has a function of sharing information. The function is not limited to this and can have various functions.

[0323] FIG. 24(B) shows an example of a slot machine, which is a large gaming machine. 900 has a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, it is not limited to this, and it is sufficient if the display device according to the present invention is included. can be appropriately provided.

[0324] 25A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002 incorporated in the It is equipped with a speaker 1005, a microphone 1006, etc.

[0325] The mobile phone 1000 shown in FIG. 25A displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making calls and sending and receiving emails can be performed using the display unit 1002. This can be done by touching with a finger or the like.

[0326] The screen of the display unit 1002 has three main modes. The first is a mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines the display mode and the input mode.

[0327] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and the input operation of characters displayed on the screen can be performed.

[0328] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0329] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. The type of image displayed on the display unit 1002 can be selected by operating the operation button 1003. For example, the image signal to be displayed on the display unit can be switched by If the data is text data, the mode switches to display mode, and if the data is text data, the mode switches to input mode.

[0330] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0331] The display unit 1002 can also function as an image sensor. By touching the 02 with your palm or fingers, your palm print, fingerprint, etc. can be captured and your identity can be authenticated. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0332] FIG. 25B is also an example of a mobile phone. The mobile phone in FIG. 25B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the display device 9410 is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can communicate with each other wirelessly. Alternatively, images or input information can be sent and received via wired communication, and each can be recharged using a battery. It has Lee.

[0333] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiment modes. It is possible to do so.

[0334] (Embodiment 9) When an oxide semiconductor layer comes into contact with a metal layer or an oxide insulating layer, oxygen transfer occurs. In this embodiment, the difference between the case where the oxide semiconductor layer is amorphous and the case where the oxide semiconductor layer is crystalline will be described. Explain the results of scientific calculations on the phenomenon.

[0335] FIG. 33 shows a structure of a transistor according to one embodiment of the present invention, in which an oxide semiconductor layer and a source The metal layer that will become the electrode and drain electrode, and the oxide semiconductor layer and oxide insulating layer are in contact with each other. The arrows in the figure indicate the direction of the contact or heating state. Each shows the direction of oxygen movement.

[0336] When oxygen vacancies occur in an i-type oxide semiconductor layer, it exhibits n-type conductivity. An oxide semiconductor layer that is n-type due to defects becomes i-type when oxygen is supplied in excess. In actual device processes, this effect is utilized to form the metals that become the source and drain electrodes. In the oxide semiconductor layer in contact with the metal layer, oxygen is attracted to the metal side, and a part of the contact area (film If the thickness is too thin, oxygen deficiency occurs in the entire film thickness, making the film n-type, and good contact with the metal layer is not obtained. In addition, the oxide semiconductor layer in contact with the oxide insulating layer can be formed by transferring the oxide from the oxide insulating layer. When oxygen is supplied, a part of the contact area (or the entire film thickness direction if the film thickness is thin) becomes oxygen-excessive. This makes the layer i-type and functions as a channel formation region of the transistor.

[0337] In one embodiment of the present invention, a metal layer to be an oxide semiconductor layer and a source electrode and a drain electrode is formed. A crystalline region of the oxide semiconductor is formed in the region where the oxide semiconductor layer and the oxide insulating layer contact each other. Therefore, the region in contact with the metal layer or the oxide insulating layer is an amorphous oxide semiconductor. The oxygen transport patterns were confirmed by scientific calculations to see the difference between the case of a layer and the case of a layer.

[0338] The model used for the scientific calculations is an In-Ga-Zn-O system amorphous and crystalline structure, with a rectangular parallelepiped. The specimen was designed with 10% oxygen deficiency from one side of the longitudinal direction (see Figure 34). The figure compares the oxygen distribution after 10 ns under the accelerated condition of 650°C. The conditions are shown in Tables 1 and 2.

[0339] [Table 1]

[0340] [Table 2]

[0341] As a result of the calculation, Fig. 35(A) shows the oxygen distribution when an amorphous material is used, and Fig. 35(B) shows the oxygen distribution when a crystalline material is used. The dotted line shows the initial state, and the solid line shows the result (10n The change in distribution indicates that oxygen is moving in both amorphous and crystalline structures. Light.

[0342] The increase in oxygen atoms before and after calculation in the region with oxygen vacancies was 15.9% for the amorphous material, In other words, oxygen is more mobile in the amorphous state than in the crystalline state, and oxygen vacancies are more likely to occur. In other words, oxygen moves more easily in the crystal than in the amorphous state. It will be difficult.

[0343] Therefore, even in the structure in which the oxide semiconductor layer has a crystalline region according to one embodiment of the present invention, It was confirmed that oxygen migration occurs in the same way as when the oxide semiconductor layer is amorphous. Since oxygen is less mobile in the oxide semiconductor layer than in the amorphous state, oxygen is released from the oxide semiconductor layer. It was confirmed that it has the effect of suppressing

[0344] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so. [Example]

[0345] In this example, an oxide semiconductor film was dehydrated or dehydrogenated at high temperature for a short time by RTA. The state of the material was analyzed using TEM analysis, TEM-EDX analysis, X-ray diffraction, and SIMS analysis. The results of the analysis will be explained below.

[0346] The sample used for the analysis was an oxide of In2O3:Ga2O3:ZnO=1:1:1 (molar ratio). Using a compound semiconductor film deposition target, an In-Ga-Zn The sample was heated at 650°C for 6 minutes in a nitrogen gas atmosphere using an RTA device. For comparison, sample A was heated at 450°C in a nitrogen gas atmosphere using an electric furnace. Sample B was heated for 10 min, and sample C was not heated (as-depo). did.

[0347] First, to examine the crystalline state of each sample, a high-resolution transmission electron microscope (Hitachi The cross section was observed using a TEM (H9000-NAR, manufactured by Epson) at an accelerating voltage of 300 kV. Figure 26 shows cross-sectional photographs of sample A, Figure 27 shows cross-sectional photographs of sample B, and Figure 28 shows cross-sectional photographs of sample C. In this figure, (A) is a low-magnification photograph (2 million times), and (B) is a high-magnification photograph (4 million times).

[0348] Specimen A, which was heated at 650°C for 6 minutes by the RTA method shown in Figure 26, has the following characteristics in its cross section: A continuous lattice image was observed in the surface layer. In particular, in the high-magnification photograph of Figure 26(B), the area surrounded by a white frame can be seen. A clear lattice image was observed in the region, suggesting the presence of aligned microcrystals. The surface of the In-Ga-Zn-O system film was heated at 650°C for a short time of about 6 minutes using the RTA method. It was revealed that the layer portion crystallized and had a crystalline region. In other regions, no clear continuous lattice image is observed, and only small amorphous regions are observed. The crystal particles were observed floating. The particle size of the microcrystals was between 2nm and 4nm. These were so-called nanocrystals.

[0349] On the other hand, the cross-sectional photographs of Figure 27 (sample B) and Figure 28 (sample C) show that the thickness of the sample is No clear lattice image was observed, confirming that the material was amorphous.

[0350] 29(A) and (B) show the surface layer of sample A, which was heated at 650°C for 6 minutes by the RTA method. The enlarged photograph of the surface layer (Fig. 29(A)) and the electron diffraction pattern of the crystalline region are shown. ) are shown with arrows 1 to 5 indicating the direction in which the lattice images are aligned, and the direction perpendicular to the film surface. The electron diffraction pattern shown in Figure 29(B) shows that the crystals grow in the direction indicated by the arrows. The observation was made at the position of number 3, and the orientation of the c-axis direction was confirmed. Comparison of the X-ray diffraction pattern with the known lattice constants revealed that the crystal structure was In2Ga2ZnO7. (See Figure 36.)

[0351] Figure 30 shows the results of TEM-EDX (energy dispersive X-ray spectroscopy) analysis of the cross section of the surface layer of sample A. The results are as follows. A raw material target with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:1 was used. In contrast, the composition ratio of the surface layer was 1:1 for In or Ga and 0.3 to 0.4 for Zn. The ratio was as follows, indicating a slight Zn deficiency.

[0352] Next, the crystal state of the same three samples was analyzed by X-ray diffraction, and the results are shown in Figure 31. In the charts of each sample, the peaks seen at 2θ=30~36° are In-G This information is derived from a-Zn-O based materials, and the broadness reflects the amorphous state. However, sample A, which was heated at 650°C for 6 minutes by the RTA method, The peak position is at a lower angle than that of material C, and the strongest diffraction is observed in the In-Ga-Zn-O crystal material. This suggests the presence of diffraction peaks from the (009) and (101) planes, which show high intensity. Therefore, the presence of crystalline regions in sample A was confirmed by X-ray diffraction as well.

[0353] Next, SIM was performed on the hydrogen concentration, carbon concentration, and nitrogen concentration in the film of sample A and sample C. The results of the S (secondary ion mass spectrometry) analysis are shown in Figure 32. The horizontal axis indicates the depth from the sample surface. The position at the depth of 0 nm on the left edge corresponds to the outermost surface of the sample (the outermost surface of the oxide semiconductor layer). The analysis is carried out from the surface side.

[0354] FIG. 32(A) shows the hydrogen concentration profile. From the profile of sample A, sample C It was found that the hydrogen concentration was reduced by more than one order of magnitude compared to the profile of 650 It was confirmed that dehydration or dehydrogenation was effectively achieved by heating at ℃ for 6 minutes. The profiles of sample A and sample C were obtained using the same In-Ga- The quantitative analysis was carried out using a standard sample made of a Zn-O-based oxide semiconductor layer.

[0355] In principle, SIMS analysis can only measure data near the sample surface or near the interface of laminated films made of different materials. It is known that it is difficult to obtain accurate data. In order to obtain accurate data, the profile was taken from a depth of 15 nm to 35 nm within a film thickness of approximately 40 nm. The files were the subject of evaluation.

[0356] From the profile of sample C, it was found that hydrogen was present in the oxide semiconductor layer that had not been dehydrogenated by approximately 3× 10 20 atoms / cm 3 That's about 5 x 10 20 atoms / cm 3 Below, the average hydrogen concentration Approximately 4 x 10 degrees 20 atoms / cm 3 It can be seen that the protons of sample A are included. From the file, it was found that the average hydrogen concentration in the oxide semiconductor layer was reduced to approximately 2 × 10 by dehydrogenation. 19 at oms / cm 3 It can be seen that the noise level has been reduced to .

[0357] Figure 32(B) shows the carbon concentration profile, and Figure 32(C) shows the nitrogen concentration profile. Unlike the hydrogen concentration profile, no clear difference was observed between specimen A and specimen C. The RTA method was used to measure the desorption or incorporation of carbon and nitrogen components by heating at 650°C for 6 minutes. In addition, Fig. 38 shows the secondary ion intensity of "H" + "O", and Fig. 39 shows the The results of detecting the secondary ion intensity of "H2" + "O" are shown. Both samples were treated at high temperatures. The strength of the hydroxyl group is low, and even when heated at 650°C for 6 minutes using the RTA method, there is no desorption of moisture or OH. was found to be carried out efficiently.

[0358] From the above analysis results, it was found that the sample heated to 650℃ for 6 minutes by the RTA method had the following characteristics: It was confirmed that a crystalline region existed in the layer. It was confirmed that the value could be reduced to 10 or less. [Example]

[0359] In this example, the results of a -BT test performed on the transistor manufactured in Embodiment 1 are shown. explain.

[0360] One of the methods for investigating the reliability of transistors is the bias-thermal stress test (hereinafter referred to as The BT test is a type of accelerated test that tests for the effects of long-term use. The change in transistor characteristics before and after the BT test can be evaluated in a short time. The amount of change in the threshold voltage of a transistor during the test is an important index for examining reliability. The smaller the change in threshold voltage before and after the BT test, the more reliable the transistor. It can be said that this is the case.

[0361] Specifically, the temperature of the substrate on which the transistor is formed (substrate temperature) is kept constant, and the transistor The source and drain of the transistor are at the same potential, and the gate is connected to a different potential from the source and drain. The substrate temperature may be set appropriately depending on the purpose of the test. The case where the potential applied to the gate is higher than the potentials of the source and drain is called a +BT test. The case where the potential applied to the gate is lower than the potential of the source and drain is called the -BT test. say.

[0362] The test intensity of the BT test depends on the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength applied to the gate insulating film can be determined by the following equation: The potential difference between the source and drain is divided by the thickness of the gate insulating film. If you want to apply a 2MV / cm electric field to a gate insulating film with a thickness of 1000 nm, you need to set the potential difference to 20V. This can be done as follows.

[0363] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. It refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage" or Voltage may be read as potential.

[0364] The -BT test was performed at a substrate temperature of 150°C and an electric field strength of 2MV / cm applied to the gate insulating film. The application time was set to 1 hour.

[0365] First, to measure the initial characteristics of the transistors to be tested for -BT, the substrate temperature was set to 40°C. and the source-drain voltage (hereinafter referred to as drain voltage or Vd) is 1 V. The source-gate voltage (hereinafter referred to as gate voltage or Vg) can be set from -20V to +20V. The source-drain current (hereinafter referred to as drain current or Id) when The change characteristics, that is, the Vg-Id characteristics when Vd is 1 V, were measured. The temperature is set at 40°C to prevent moisture absorption on the substrate surface, but if there are no particular problems, the substrate temperature can be set at room temperature ( It is acceptable to measure at 25°C.

[0366] Next, the same measurement was performed with Vd set to 10V, and the Vg-Id characteristics were measured when Vd was 10V. did.

[0367] Next, the substrate temperature was raised to 150°C, and then the source and drain voltages of the transistor were Next, the electric field strength applied to the gate insulating film was set to 2 MV / cm. In this case, the thickness of the gate insulating film of the transistor is 100 nm. Therefore, -20V was applied to the gate and kept for 1 hour. Although the time is set to 1 hour, it may be changed depending on the purpose.

[0368] Next, while voltages are still being applied to the gate, source, and drain, the substrate temperature is lowered to 40°C. At this time, if the voltage application is stopped before the substrate temperature has completely dropped, the residual heat - Voltage should not be applied because the damage done to the transistor during the BT test will be repaired. After the substrate temperature reaches 40°C, the voltage application is stopped. Strictly speaking, the temperature drop time must also be added to the application time, but in reality, the temperature rose to 40°C in a few minutes. Since this was considered to be within the error range, the temperature drop time was added to the application time. do not have.

[0369] Next, under the same conditions as the measurement of the initial characteristics, the Vg-Id characteristics were measured when Vd was 1 V and 10 V. The Vg-Id characteristics after the -BT test were obtained.

[0370] Figure 37(A) shows the Vg-Id characteristics of the transistor before and after the -BT test. The horizontal axis of (A) is the gate voltage (Vg), and the vertical axis is the drain current (Id) relative to the gate voltage. is shown on a logarithmic scale.

[0371] FIG. 37(B) is an enlarged view of the portion 900 shown in FIG. 37(A). The initial characteristic 901 is , Vg-Id characteristics of the transistor before the -BT test when Vd is 1V, and the initial characteristics 91 1 shows the Vg-Id characteristics of the transistor before the -BT test when Vd is 10V. -BT902 is the Vg-Id characteristics of the transistor after the -BT test when Vd is 1V. -BT912 is the Vg-Id characteristic of the transistor when Vd is 10V after the -BT test. It is sex.

[0372] From FIG. 37, compared with the initial characteristics 901 and 911, -BT902 and -BT912 It can be seen that the whole is slightly shifted in the positive direction. However, the amount of shift is The transistor fabricated in the first embodiment has a very small resistance of 0.5 V or less. It was confirmed that this transistor has high reliability. [Explanation of symbols]

[0373] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 input terminals 25 Input terminals 26 Output terminal 27 Output terminal 28 transistors 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 42 transistors 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 boards 101 gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 106 Crystal region 107 Oxide insulating layer 108 Capacitance wiring 110 Pixel electrode layer 112 Conductive layer 113 Conductive Layer 114 Conductive layer 120 connecting electrode 121 terminal 122 terminals 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Transparent conductive layer 129 Transparent conductive layer 131 Resist mask 150 connecting electrode 151 terminals 152 Gate insulating layer 153 Connecting electrode 154 Protective insulating film 155 Transparent conductive layer 156 terminals 170 transistors 581 Transistor 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 900 parts 901 Initial Characteristics 902-BT 911 initial characteristics 912-BT 1000 mobile phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 105a Source electrode layer 105b drain electrode layer 112a conductive layer 113a conductive layer 114a conductive layer 2600 board 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4044 Insulation layer 4501 Circuit Board 4502 Pixel section 4505 Sealing material 4506 board 4507 Filling material 4509 Transistor 4510 transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulation layer 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 590a black area 590b White area 6400 pixels 6401 Switching transistor 6402 Drive transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Transistor 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7010 board 7011 Transistor 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Transparent conductive layer 7019 Bulkhead 7020 board 7021 Transistor 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7026 Electrode 7027 Transparent conductive layer 7029 Bulkhead 7030 Gate insulating layer 7031 Oxide insulating layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7040 Gate insulating layer 7041 Oxide insulating layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7051 Oxide insulating layer 7052 Protective insulation layer 7053 Planarization insulating layer 7055 Insulation layer 9400 Communication Equipment 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4518a FPC 4518b FPC

Claims

1. a gate electrode layer; a gate insulating layer on the gate electrode layer; a source electrode layer and a drain electrode layer on the gate insulating layer; an oxide semiconductor layer that is formed on the gate insulating layer and overlaps with a portion of the source electrode layer and the drain electrode layer; an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer is formed of a first region in a surface layer portion and a second region in the other portion, The first region of the oxide semiconductor layer is a transistor formed of microcrystals having a c-axis oriented in a direction perpendicular to a film surface.

2. A pixel portion and a driver circuit portion having transistors on the same substrate, The transistor is a gate electrode layer; a gate insulating layer on the gate electrode layer; a source electrode layer and a drain electrode layer on the gate insulating layer; an oxide semiconductor layer that is formed on the gate insulating layer and overlaps with a portion of the source electrode layer and the drain electrode layer; an oxide insulating layer in contact with the oxide semiconductor layer, the oxide semiconductor layer is formed of a first region in a surface layer portion and a second region in the other portion, The display device, wherein the first region of the oxide semiconductor layer is formed of microcrystals having a c-axis oriented in a direction perpendicular to a film surface.

Images