Controller and electronic apparatus

Abstract

To provide a controller and an electronic apparatus where the number of output-terminals of a processor for outputting the clock signal to respective control units can be reduced.SOLUTION: A controller 10 includes: a CPU 30 that has an output terminal 31 for outputting a clock signal X1 and controls a motor driver 5 and a calculation integrated circuit 6; and a relay circuit 40. The relay circuit 40 generates and outputs a clock signal X2 to be output to the motor driver 5 in response to input of the clock signal X1 whose duty ratio is a first value and generates and outputs a clock signal X3 to be output to the calculation integrated circuit 6 in response to input of the clock signal X1 whose duty ratio is a second value differing from the first value.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a control device and an electronic device. [Background technology]

[0002] Electronic devices such as printers are equipped with processors such as CPUs (see, for example, Patent Document 1). In these electronic devices, the processor inputs clock signals used for drive control and arithmetic processing to drivers (controllers) that drive and control loads such as motors, and integrated circuits (controllers) that process data in storage devices such as memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-046648 Summary of the Invention [Problem to be solved by the invention]

[0004] In the conventional electronic devices, in order to output the clock signal from the processor to each of the control units, it is necessary to provide the processor with individual output terminals corresponding to each of the control units.

[0005] An object of the present invention is to provide a control device and electronic equipment that can reduce the number of output terminals of a processor that outputs the clock signal to each control unit. [Means for solving the problem]

[0006] A control device according to one aspect of the present invention comprises a processor having an output terminal for outputting a clock signal, the processor controlling a first control unit that controls a first load and a second control unit that controls a second load, and a signal output circuit that generates a first clock signal to be output to the first control unit in response to input of the clock signal having a duty ratio of a predetermined first value and outputs the first clock signal to the first control unit, and that generates a second clock signal to be output to the second control unit in response to input of the clock signal having a duty ratio of a second value different from the first value and outputs the second clock signal to the second control unit.

[0007] An electronic device according to another aspect of the present invention includes the control device, the first load and the first control unit, and the second load and the second control unit. [Effects of the Invention]

[0008] According to the present invention, it is possible to reduce the number of output terminals of the processor that outputs the clock signal to each control unit. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view showing the configuration of an image forming apparatus according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing the configuration of the control unit according to the embodiment of the present invention. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of a relay circuit of a control unit according to an embodiment of the present invention. [Figure 4] FIG. 4 is a flowchart showing an example of a clock signal output process executed by the CPU of the control unit according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Note that the following embodiment is an example of a specific embodiment of the present invention and does not limit the technical scope of the present invention.

[0011] [Configuration of image forming apparatus 100] First, the configuration of an image forming apparatus 100 according to an embodiment of the present invention will be described with reference to FIGS.

[0012] The image forming apparatus 100 is a multifunction peripheral that has multiple functions, such as a scanning function for reading an image from a document, a printing function for forming an image based on image data, a facsimile function, and a copy function. The image forming apparatus 100 is an example of an electronic device of the present invention. The present invention may also be applied to electronic devices such as scanners, printers, fax machines, copy machines, personal computers, laptop computers, televisions, microwave ovens, and refrigerators.

[0013] As shown in FIG. 1, image forming apparatus 100 includes an ADF (Auto Document Feeder) 1, an image reading unit 2, an image forming unit 3, and a paper feeding unit 4. Also, image forming apparatus 100 includes a motor driver 5 (hereinafter abbreviated as driver 5) shown in FIG. 2, a motor 50, an arithmetic integrated circuit 6 equipped with a memory unit 60, and a control unit 10. Driver 5 is an example of a first control unit of the present invention, and motor 50 is an example of a first load and an example of a motor of the present invention. Arithmetic integrated circuit 6 is an example of a second control unit and an integrated circuit of the present invention, and memory unit 60 is an example of a second load of the present invention. Also, control unit 10 is an example of a control device of the present invention.

[0014] The ADF 1 transports documents to be scanned by the scanning function, and includes a document setting section, a plurality of document transport rollers, a document presser, and a paper ejection section.

[0015] The image reading unit 2 realizes the scanning function and includes a document table, a light source, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device).

[0016] The image forming unit 3 realizes the printing function. As shown in Fig. 1, the image forming unit 3 includes a photosensitive drum 11, a charging roller 12, an optical scanning device 13, a developing device 14, a toner container 15, a transfer roller 16, a cleaning device 17, a fixing device 18, and a paper output tray 19.

[0017] The photosensitive drum 11 is rotatably mounted. The charging roller 12 is provided in contact with the surface of the photosensitive drum 11 and charges the surface of the photosensitive drum 11.

[0018] The optical scanning device 13 irradiates the surface of the photosensitive drum 11, which has been charged by the charging roller 12, with light based on image data. An electrostatic latent image is formed on the surface of the photosensitive drum 11 by the optical scanning device 13.

[0019] The developing device 14 uses toner to develop the electrostatic latent image formed on the surface of the photosensitive drum 11. The toner container 15 supplies the toner to the developing device 14.

[0020] The transfer roller 16 transfers the electrostatic latent image (toner image) developed by the developing device 14 onto a sheet supplied by the paper feed unit 4. The cleaning device 17 cleans the surface of the photosensitive drum 11 after the toner image has been transferred by the transfer roller 16.

[0021] The fixing device 18 fixes the toner image transferred onto the sheet by the transfer roller 16. The sheet onto which the toner image has been fixed by the fixing device 18 is discharged to a paper discharge tray 19.

[0022] The paper feed unit 4 supplies sheets to the image forming unit 3. As shown in FIG. 1, the paper feed unit 4 includes a paper feed cassette 21, a pickup roller 22, a paper feed roller 23, a plurality of sheet transport rollers 24, and a registration roller 25.

[0023] The paper feed cassette 21 is detachably provided in the housing of the image forming apparatus 100, and holds sheets to be supplied to the image forming unit 3. The pickup roller 22 picks up the top sheet from the paper feed cassette 21 among the multiple sheets stacked in the paper feed cassette 21.

[0024] The paper feed roller 23 conveys the sheet picked up from the paper feed cassette 21 by the pickup roller 22 to a sheet supply path leading to the image forming unit 3. A plurality of sheet conveying rollers 24 are provided in the sheet supply path and convey the sheet to the image forming unit 3.

[0025] The registration rollers 25 are provided at the most downstream portion of the sheet supply path, and supply the sheet to the image forming unit 3 at a predetermined timing.

[0026] The driver 5 drives and controls the motor 50. The motor 50 rotates each of the document transport rollers of the ADF 1. For example, the motor 50 is a stepping motor. The motor 50 may also be used to drive a driven unit such as a roller member provided in the image forming unit 3 or the paper feeding unit 4. The motor 50 may also be a brushless motor, and the first load of the present invention is not limited to a motor but may also be a heater, etc. In this case, the first control unit of the present invention is a heater driver that controls the heating of the heater.

[0027] The driver 5 controls the driving of the motor 50 during a period when the data in the memory unit 60 is not being processed by the arithmetic integrated circuit 6. For example, when the image forming apparatus 100 is powered on, the driver 5 is not driven during an authentication period in which a login ID and password are requested to be input, and a login process or authentication process corresponding to the input operation of the login ID and password is performed. In other words, during this authentication period, the driver 5 does not need a clock signal to control the driving of the motor 50.

[0028] The arithmetic integrated circuit 6 is an integrated circuit that performs predetermined arithmetic processing on various data in the storage unit 60. The arithmetic integrated circuit 6 is, for example, an LSI (Large Scale Integration), an ASIC (Application Specific Integrated Circuit), a DSP (Digital Signal Processor), or an FPGA (Field-Programmable Gate Array).

[0029] The arithmetic integrated circuit 6 is, for example, a security chip. When an ID or password required for operating the image forming apparatus 100 is set, the arithmetic integrated circuit 6 is an IC chip for storing and managing important data such as the password and encryption keys used when encrypting various files in the storage unit 60. The arithmetic integrated circuit 6 operates during a time period when the motor 50 is not controlled by the driver 5. This time period is, for example, the authentication period during which the login process or the authentication process is performed when the image forming apparatus 100 is powered on.

[0030] The arithmetic integrated circuit 6 may be an image processing circuit that executes predetermined image processing on image data to be printed.

[0031] The control unit 10 performs overall control of the image forming apparatus 100. The control unit 10 may be an engine control unit that controls the ADF 1 and the image reading unit 2.

[0032] As shown in FIG. 2, the control unit 10 includes a CPU 30.

[0033] The CPU 30 is a processor that executes various types of arithmetic processing. The CPU 30 controls the driver 5 and the arithmetic integrated circuit 6. The CPU 30 also outputs a clock signal required for drive control by the driver 5 and arithmetic processing by the arithmetic integrated circuit 6.

[0034] In conventional electronic devices, in order to output the clock signal directly from the CPU 30 to the driver 5 and the arithmetic integrated circuit 6, it is necessary to provide the CPU 30 with individual output terminals corresponding to each control unit, such as the driver 5 and the arithmetic integrated circuit 6.

[0035] In contrast, the image forming apparatus 100 according to an embodiment of the present invention is configured as described below, and therefore it is possible to reduce the number of output terminals for outputting the clock signal to each control unit such as the driver 5 and the arithmetic integrated circuit 6.

[0036] Specifically, the CPU 30 includes an output terminal 31 (see FIG. 2) that outputs a square-wave clock signal X1 (see FIG. 2).

[0037] The control unit 10 also includes a relay circuit 40 shown in Figures 2 and 3. The relay circuit 40 is an example of the signal output circuit of the present invention.

[0038] 2, the CPU 30 includes processing units such as an output processing unit 32 and a switching processing unit 33. Specifically, the CPU 30 functions as each of the above-mentioned processing units by executing a control program stored in advance in a ROM (not shown).

[0039] [Configuration of relay circuit 40] Next, the configuration of the relay circuit 40 will be described with reference to FIGS.

[0040] As shown in FIG. 2, relay circuit 40 relays clock signal X1 output from CPU 30, outputs clock signal X2 (an example of a first clock signal of the present invention) to driver 5, and outputs clock signal X3 (an example of a second clock signal of the present invention) to arithmetic integrated circuit 6.

[0041] In this embodiment, the relay circuit 40 generates a clock signal X2 to be output to the driver 5 in response to input of a clock signal X1 having a duty ratio of a predetermined first value, and outputs the generated clock signal to the driver 5. In response to input of a clock signal X1 having a duty ratio of a second value different from the first value, the relay circuit 40 generates a clock signal X3 to be output to the calculation integrated circuit 6.

[0042] As shown in FIG. 3, the relay circuit 40 includes a comparison circuit 41 (an example of a comparison circuit of the present invention), a first clock signal output circuit 42 (an example of a first output circuit of the present invention), and a second clock signal output circuit 43 (an example of a second output circuit of the present invention).

[0043] When a clock signal X1 having a duty ratio of the first value is input, the comparator circuit 41 outputs a first voltage signal (non-clock signal) of a high level having a constant voltage value, and when a clock signal X1 having a duty ratio of the second value lower than the first value is input, the comparator circuit 41 outputs a second voltage signal (non-clock signal) of a low level lower than the constant voltage signal. In this embodiment, the first voltage signal is a voltage signal of the same voltage value as the power supply voltage Vcc input to the relay circuit 40. The second voltage signal is a voltage signal of ground potential.

[0044] When the duty ratio of the clock signal X1 input from the output terminal 31 of the CPU 30 is switched from the first value to the second value, the comparator circuit 41 outputs the second voltage signal in response to the switching. Also, when the duty ratio of the clock signal X1 input from the output terminal 31 of the CPU 30 is switched from the second value to the first value, the comparator circuit 41 outputs the first voltage signal in response to the switching.

[0045] As shown in FIG. 3, the comparison circuit 41 includes resistors R1 to R3, a comparator U1, and capacitors C1 to C2.

[0046] The comparator U1 has a positive input terminal (non-inverting input terminal) V+, a negative input terminal (inverting input terminal) V-, a positive power supply terminal Vs+, a negative power supply terminal Vs-, and an output terminal Vout, and compares the voltages input to each input terminal, and outputs the first voltage signal from the output terminal Vout if the input terminal V+ is greater than the input terminal V-, and outputs the second voltage signal from the output terminal Vout if the input terminal V+ is smaller than the input terminal V-. As the comparator U1, for example, a comparator LT1018 from Analog Devices, Inc. is used.

[0047] Resistors R1 and R2 are so-called voltage dividing resistors. Resistor R1 is provided between a power supply terminal Vin to which a power supply voltage Vcc is input and an input terminal V- of the comparator U1. Resistor R2 is provided between resistor R1 and ground.

[0048] A reference voltage Vref is input to the input terminal V- of the comparator U1. The reference voltage Vref is the voltage obtained by dividing the power supply voltage Vcc by resistor R1. The power supply terminal Vs+ is connected to the power supply terminal Vin, and the power supply voltage Vcc is input to the power supply terminal Vs+. The power supply terminal Vs- is connected to ground. The output terminal Vout is connected to ground via capacitor C2.

[0049] The input terminal V+ of the comparator U1 is connected to the input terminal T1 to which the clock signal X1 is input via a resistor R3, so that the clock signal X1 is input from the output terminal 31 of the CPU 30 (see FIG. 2) to the input terminal V+.

[0050] In the comparison circuit 41, when a clock signal X1 is input to the input terminal V+ of the comparator U1 and the signal level of the clock signal X1 is high, the capacitor C1 is charged and the voltage applied to the input terminal V+ of the comparator U1 increases. When the voltage applied to the input terminal V+ of the comparator U1 exceeds the reference voltage Vref, the first voltage signal (power supply voltage Vcc) is output from the comparator U1.

[0051] In the comparison circuit 41, when the clock signal X1 is input to the input terminal V+ of the comparator U1 and the signal level of the clock signal X1 is low, the capacitor C1 discharges. This reduces the voltage applied to the input terminal V+ of the comparator U1. When the applied voltage to the input terminal V+ of the comparator U1 becomes lower than the reference voltage Vref, the comparator U1 outputs the second voltage signal (ground potential).

[0052] Here, the higher the duty ratio of the clock signal X1, the longer the charging time of the capacitor C1 and the shorter the discharging time of the capacitor C1. In other words, if the duty ratio of the clock signal X1 is sufficiently high, the first voltage signal (power supply voltage Vcc) can be output from the comparator U1 regardless of the switching of the signal level of the clock signal X1.

[0053] Specifically, in the comparison circuit 41, when the duty ratio of the clock signal X1 exceeds 50%, the comparator U1 can output the first voltage signal regardless of whether the signal level of the clock signal X1 is switched. Note that the first value is set within a range exceeding 50%.

[0054] On the other hand, the lower the duty ratio of the clock signal X1, the shorter the charging time of the capacitor C1 and the longer the discharging time of the capacitor C1. In other words, if the duty ratio of the clock signal X1 is sufficiently low, the charge of the capacitor C1 is lost due to discharging while the signal level of the clock signal X1 is at a low level. As a result, the voltage applied to the input terminal V+ of the comparator U1 becomes lower than the reference voltage Vref, causing the comparator U1 to output the second voltage signal (ground potential).

[0055] Specifically, in the comparator circuit 41, when the duty ratio of the clock signal X1 is lower than 50%, the charge of the capacitor C1 is discharged during the period when the signal level of the clock signal X1 is at a low level. Note that the second value is set within a range of less than 50%.

[0056] Therefore, the comparison circuit 41 outputs the first voltage signal (power supply voltage Vcc) while the clock signal X1 having the duty ratio of the first value is input, and outputs the second voltage signal (ground potential) while the clock signal X1 having the duty ratio of the second value is input.

[0057] The first clock signal output circuit 42 generates a clock signal X2 having the same frequency and duty ratio as the clock signal X1 in response to the voltage signal output from the comparison circuit 41, and outputs the generated clock signal X2 to the driver 5. In detail, when the first voltage signal is input, the first clock signal output circuit 42 outputs the clock signal X2 having the duty ratio of the first value, and when the first voltage signal is not input, the first clock signal output circuit 42 does not output the clock signal X2.

[0058] In this embodiment, when the driver 5 controls the drive of the motor 50 and the arithmetic integrated circuit 6 does not control the memory unit 60, the CPU 30 inputs a clock signal X1 having a duty ratio of the first value from the output terminal 31 to the comparison circuit 41, and causes the first clock signal output circuit 42 to output a clock signal X2 to the driver 5.

[0059] As shown in FIG. 3, the first clock signal output circuit 42 includes a comparator U2.

[0060] The comparator U2 is the same as the comparator U1. The output signal of the comparator U1 is input to the input terminal V+ of the comparator U2. The reference voltage Vref is input to the input terminal V- of the comparator U2.

[0061] The power supply terminal Vs+ of the comparator U2 is connected to the input terminal T1 to which the clock signal X1 is input, and the clock signal X1 is input to the power supply terminal Vs+. The power supply terminal Vs- is connected to ground.

[0062] Therefore, when the first voltage signal (power supply voltage Vcc) is input to the input terminal V+ of the comparator U2, the first voltage signal is higher than the reference voltage Vref, and therefore the output terminal Vout of the comparator U2 outputs a clock signal X2 having the same frequency and duty ratio as the clock signal X1 input to the power supply terminal Vs+ of the comparator U3.

[0063] On the other hand, when the second voltage signal (ground potential) is input to the input terminal V- of the comparator U2, the second voltage signal is lower than the reference voltage Vref, and therefore a low-level voltage signal (non-clock signal) dropped to ground potential is output from the output terminal Vout of the comparator U2. In other words, in this case, the clock signal X2 is not output from the comparator U2.

[0064] The second clock signal output circuit 43 generates a clock signal X3 having the same frequency and duty ratio as the clock signal X1 in response to the voltage signal output from the comparison circuit 41, and outputs the clock signal X3 to the arithmetic integrated circuit 6. In detail, when the second voltage signal is input, the second clock signal output circuit 43 outputs the clock signal X3 having the second value of duty ratio, and when the second voltage signal is not input, the second clock signal output circuit 43 does not output the clock signal X3.

[0065] In this embodiment, when the driver 5 does not control the drive of the motor 50 and the arithmetic integrated circuit 6 controls the memory unit 60, the CPU 30 inputs a clock signal X1 having a duty ratio of the second value from the output terminal 31 to the comparison circuit 41, and causes the second clock signal output circuit 43 to output a clock signal X3 to the arithmetic integrated circuit 6.

[0066] As shown in FIG. 3, the second clock signal output circuit 43 includes a comparator U3 and a NOT gate element NG1.

[0067] The comparator U3 is the same as the comparator U1. The output signal of the comparator U1 is input to the input terminal V+ of the comparator U3 via a NOT gate element NG1. The reference voltage Vref is input to the input terminal V- of the comparator U3.

[0068] The power supply terminal Vs+ of the comparator U3 is connected to the input terminal T1 to which the clock signal X1 is input, and the clock signal X1 is input to the power supply terminal Vs+. The power supply terminal Vs- is connected to ground.

[0069] Therefore, when the comparator U1 outputs the first voltage signal (power supply voltage Vcc), a low-level voltage signal obtained by inverting the first voltage signal by the NOT gate element NG1 is input to the input terminal V+ of the comparator U3. In this case, the voltage signal input to the input terminal V+ is lower than the reference voltage Vref, so a low-level voltage signal (non-clock signal) dropped to ground potential is output from the output terminal Vout of the comparator U3. In other words, in this case, the clock signal X3 is not output from the comparator U3.

[0070] On the other hand, when the second voltage signal (ground potential) is output from the comparator U1, a High-level voltage signal obtained by inverting the second voltage signal by the NOT gate element NG1 is input to the input terminal V+ of the comparator U3. In this case, since the voltage signal input to the input terminal V+ is higher than the reference voltage Vref, the output terminal Vout of the comparator U3 outputs a clock signal X3 having the same frequency and duty ratio as the clock signal X1 input to the power supply terminal Vs+ of the comparator U3.

[0071] Because the relay circuit 40 is configured in this manner, the relay circuit 40 outputs a clock signal X2 to the driver 5 while the clock signal X1 having the duty ratio of the first value is input to the relay circuit 40, and outputs a clock signal X3 to the calculation integrated circuit 6 while the clock signal X1 having the duty ratio of the second value is input.

[0072] [Functions of each processing unit included in CPU 30] Next, the function of each processing unit included in the CPU 30 will be described with reference to FIG.

[0073] The output processing unit 32 outputs a clock signal X1 from the output terminal 31 in order to generate a clock signal required for the driver 5 and the arithmetic integrated circuit 6.

[0074] During the authentication period when the arithmetic integrated circuit 6 performs arithmetic processing, the switching processing unit 33 switches the duty ratio of the clock signal X1 output from the output terminal 31 from the first value to the second value. Moreover, during the non-authentication period when the arithmetic integrated circuit 6 does not perform arithmetic processing, the switching processing unit 33 returns the duty ratio of the clock signal X1 from the first value to the second value.

[0075] [Clock signal output processing] 4, a clock signal output method will be described below along with an example of the procedure of the clock signal output process executed by the CPU 30 in the image forming apparatus 100. Here, steps S11, S12, etc. represent the numbers of the processing procedures (steps) executed by the CPU 30.

[0076] <Step S11> First, in step S11, the CPU 30 outputs the clock signal X1 having the duty ratio of the first value from the output terminal 31. The process of step S11 is started, for example, when the image forming apparatus 100 is powered on.

[0077] By executing the process of step S11, the clock signal X1 having the duty ratio of the first value is input to the relay circuit 40 (see FIG. 2). As a result, the first clock signal output circuit 42 outputs a clock signal X2 having the same frequency and duty ratio as the clock signal X1 to the driver 5. At this time, the second clock signal output circuit 43 does not output the clock signal X3 to the arithmetic integrated circuit 6.

[0078] <Step S12> In step S12, the CPU 30 determines whether login authentication is required.

[0079] For example, CPU 30 determines that the authentication is required if a login operation is input from the operation display panel (not shown) of image forming apparatus 100 during the period from the execution of the process of step S11 until a predetermined first time period has elapsed. The period from this determination until the completion of login authentication is the authentication period.

[0080] <Step S13> If the CPU 30 determines in step S12 that the authentication is necessary, then in step S13, the CPU 30 switches the duty ratio of the clock signal X1 output from the output terminal 31 from the first value to the second value in order to cause the calculation integrated circuit 6 to output the clock signal X3 required for calculation processing by the calculation integrated circuit 6. The processing of step S13 is executed by the switching processing unit 33 of the CPU 30.

[0081] By executing the process of step S13, the clock signal X1 having the second duty ratio is input to the relay circuit 40 (see FIG. 2). As a result, the second clock signal output circuit 43 outputs a clock signal X3 having the same frequency and duty ratio as the clock signal X1 to the arithmetic integrated circuit 6. At this time, the first clock signal output circuit 42 does not output the clock signal X2 to the driver 5.

[0082] <Steps S14 and S15> If the CPU 30 determines in step S14 that login authentication has ended, then in the next step S15, the CPU 30 changes the duty ratio of the clock signal X1 output from the output terminal 31 back to the first value from the second value. The processing of step S15 is executed by the switching processing unit 33 of the CPU 30. When the duty ratio of the clock signal X1 is changed back to the first value from the second value, the clock signal X2 is again output from the first clock signal output circuit 42 to the driver 5, and the output of the clock signal X3 from the second clock signal output circuit 43 is stopped.

[0083] This eliminates the need for the CPU 30 to have separate output terminals corresponding to each control unit, such as the driver 5 and the arithmetic integrated circuit 6, and enables the number of output terminals in the CPU 30 for outputting clock signals to each control unit, such as the driver 5 and the arithmetic integrated circuit 6, to be reduced.

[0084] In the above embodiment, the motor 50 is described as an example of the first load and the memory unit 60 is described as an example of the second load, but the first load and the second load of the present invention may be any combination of controlled or driven units that are not controlled simultaneously in the image forming apparatus 100.

[0085] [Notes on the Invention] The following will provide an outline of the invention extracted from the above-described embodiment. Note that the configurations and processing functions described in the following supplementary notes can be selected and combined as desired.

[0086] <Appendix 1> a processor having an output terminal for outputting a clock signal, and controlling a first control unit that controls a first load and a second control unit that controls a second load; a signal output circuit that generates a first clock signal to be output to the first control unit in response to an input of the clock signal having a duty ratio of a predetermined first value, and outputs the first clock signal to the first control unit, and that generates a second clock signal to be output to the second control unit in response to an input of the clock signal having a duty ratio of a second value different from the first value, and outputs the second clock signal to the second control unit; A control device comprising:

[0087] <Appendix 2> The signal output circuit a comparison circuit that outputs a first voltage signal of a high level when the clock signal having the first duty ratio is input, and outputs a second voltage signal of a low level when the clock signal having the second duty ratio is input; a first output circuit that outputs the first clock signal when the first voltage signal is input, and does not output the first clock signal when the first voltage signal is not input; a second output circuit that outputs the second clock signal when the second voltage signal is input, and does not output the second clock signal when the second voltage signal is not input, 10. The control device of claim 1.

[0088] <Appendix 3> The processor: when the first control unit controls the first load and the second control unit does not control the second load, inputting the clock signal having the first duty ratio from the output terminal to the comparison circuit and outputting the first clock signal from the first output circuit; When the first load is not controlled by the first control unit and the second load is controlled by the second control unit, the clock signal having the second duty ratio is input from the output terminal to the comparison circuit, and the second clock signal is output from the second output circuit. 3. The control device according to claim 2.

[0089] <Appendix 4> the first control unit is a motor driver that drives and controls a motor serving as the first load, the second control unit is an integrated circuit that performs arithmetic processing on information stored in the storage unit serving as the second load; 4. The control device according to any one of claims 1 to 3.

[0090] <Appendix 5> A control device according to any one of Supplementary Notes 1 to 4; the first load and the first control unit; the second load and the second control unit; An electronic device comprising: [Explanation of symbols]

[0091] 5: Motor driver 6: Arithmetic integrated circuit 10: Control section 30: CPU 31: Output terminal 32: Output processing section 33: Switching processing section 40: Relay circuit 41: Comparison circuit 42: First clock signal output circuit 43: Second clock signal output circuit 50: Motor 60: Storage section 100: Image forming device

Claims

1. a processor having an output terminal for outputting a clock signal, and controlling a first control unit that controls a first load and a second control unit that controls a second load; a signal output circuit that generates a first clock signal to be output to the first control unit in response to input of the clock signal having a duty ratio of a predetermined first value, and outputs the first clock signal to the first control unit, and that generates a second clock signal to be output to the second control unit in response to input of the clock signal having a duty ratio of a second value different from the first value, and outputs the second clock signal to the second control unit; A control device comprising:

2. The signal output circuit a comparison circuit that outputs a first voltage signal of a high level when the clock signal having the first duty ratio is input, and outputs a second voltage signal of a low level when the clock signal having the second duty ratio is input; a first output circuit that outputs the first clock signal when the first voltage signal is input, and does not output the first clock signal when the first voltage signal is not input; a second output circuit that outputs the second clock signal when the second voltage signal is input, and does not output the second clock signal when the second voltage signal is not input, The control device according to claim 1 .

3. The processor: when the first control unit controls the first load and the second control unit does not control the second load, inputting the clock signal having the first duty ratio from the output terminal to the comparison circuit and outputting the first clock signal from the first output circuit; When the first load is not controlled by the first control unit and the second load is controlled by the second control unit, the clock signal having the second duty ratio is input from the output terminal to the comparison circuit, and the second clock signal is output from the second output circuit. The control device according to claim 2 .

4. the first control unit is a motor driver that drives and controls a motor serving as the first load, the second control unit is an integrated circuit that performs arithmetic processing on information stored in the storage unit serving as the second load; The control device according to claim 3 .

5. A control device according to any one of claims 1 to 4; the first load and the first control unit; the second load and the second control unit; An electronic device comprising:

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