Readout Circuit

Abstract

A readout circuit (110) is proposed. The readout circuit (110) is configured to convert an analog sensor charge (112) into a digital output count (114). The readout circuit (110) comprises at least one integrate and fire (IAF) circuit (116). The IAF circuit (116) is configured to convert the analog sensor charge (112) into a first digital output count (118). An analog voltage residue (120) after the last IAF cycle is further processed. The readout circuit (110) includes at least one analog-to-digital converter (ADC) (122). The ADC (122) is configured to convert the analog voltage residue (120) into a second digital output (124). Furthermore, the input charge to the readout circuit is a photodetector (182), and a method of readout of the analog sensor charge (112) is proposed.

Description

[Technical field]

[0001] The present invention relates to a readout circuit configured to convert an analog sensor charge into a digital output count, a photodetector, and a method for reading out an analog sensor charge. In particular, the readout circuit can be used to read out a photodetector, such as a photodetector used in a spectrometer. More particularly, the readout circuit can be used to determine the digital output count of a photoconductor, such as a lead sulfide photoconductor, or a photodiode, such as Si, InGaAs, SiGe, etc. Other options are also feasible. [Background technology]

[0002] Spectroscopic measurements generally require separating radiation into its spectral wavelength components and measuring the intensity of each component. One approach to spectroscopy is to use an array of sensors that respond to radiation separated into many spectral wavelength components to perform measurements in parallel. Many sensor technologies are available for spectroscopy, including lead sulfide (PbS), lead selenide (PbSe), indium gallium arsenide (InGaAs), and pyroelectric. Most of these sensor technologies require measuring small amounts of charge with high resolution. Electronic circuitry first converts the charge from the sensor array into a voltage in a readout integrated circuit (ROIC). The voltage is then digitized using an analog-to-digital converter (ADC). These two integrated circuits are typically expensive and require large amounts of power. In addition, using separate ROICs and ADCs can require extra circuitry and long connection lengths between the ROIC analog output and the ADC input. These connections can be vulnerable to noise pickup from internal and external sources.

[0003] It is known to use an ROIC and an ADC to convert charge to a voltage and digitize it. Most parallel charge-to-voltage conversion ROICs use a charge amplifier circuit that exploits the linear relationship between the charge stored in a capacitor and the voltage. This type of circuit can be used due to its flexibility in adjusting the output voltage depending on the application requirements and input, its ability to measure and resolve small charges, and the ability to realize the circuit within most existing mixed IC foundry processes. An ROIC is expressed as

number

[0004] The maximum voltage may be limited by the IC technology, so the charge-capacity product must be kept below this limit. The flexibility of the ROIC allows the voltage output to be adjusted for use in many different applications. Regardless of the maximum charge dictated by the sensor and application, the output can be adjusted to utilize most of the maximum voltage dictated by the IC. Two methods can be used to adjust the charge-to-voltage gain to control the charge and maximize the output voltage.

[0005] 1) Adjusting the capacitor value to increase or decrease the voltage to charge conversion ratio, and / or 2) The charge is expressed by the sensor current i(t) as

number

[0006] Multiple capacitance values ​​tend to be implemented within the IC per channel. The user can select the capacitance value and adjust the integration time depending on the application. Capacitors tend to range between tens of femtofarads to tens of picofarads. Smaller capacitors can increase the output voltage for a given charge by increasing the charge-to-voltage gain. The lower limit of capacitance is determined by the IC technology. Larger capacitors may require a larger area on the IC but will increase the dynamic range and decrease the charge-to-voltage gain.

[0007] The noise of the measurement can be limited by three factors.

[0008] 1) sensor current noise; 2) Noise due to ROIC; 3) ADC quantization noise It is.

[0009] In all applications, it may be desirable to have the sensor noise dominate the noise floor. Thus, noise due to ROIC and quantization noise should be kept significantly lower than the sensor noise. In this architecture, the analog voltage output of the charge converter may be connected to an ADC. The ADC may be located within the integrated circuit or it may be a separate integrated circuit. In either case, due to the large number of signals, the channels tend to be multiplexed and transferred serially. The multiplexing may require extra circuitry, and the relatively long length of the connections may make this type of architecture vulnerable to analog noise pickup from other internal or external sources.

[0010] Furthermore, the complexity, size and power of the ADC grow rapidly with the number of bits. To reduce overall power, cost and size, there is a trend towards using a single high-resolution ADC at a high sampling rate as opposed to using multiple high-resolution ADCs at lower sampling rates.

[0011] A different approach has been commercialized in other charge-based sensor array systems. This approach is exemplified in Dei, Michele et al., “Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers.”, IEEE, 2017, presentation at the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), and is known as an integrate-and-fire circuit (IAF circuit). A linear charge-to-voltage conversion using a capacitor may be employed. However, it is modified to convert the analog current directly to a digital signal. The capacitor and maximum voltage may be reduced to allow the charge to saturate the output. The circuit may detect saturation and automatically reset the charge-to-voltage conversion. At the same time, a counter is incremented by one for each saturation event. The saturation and counting may continue for the integration cycle, and the counter value after the integration time is proportional to the input current.

[0012] The digital output may be generated locally by the measurement cell and a separate ADC may not be required. Indeed, all measurement cells may digitize the signal directly as a counter value. The analog signal path may be short and the circuit may operate without a clock, i.e. asynchronously, further reducing noise sources. The integration capacitors can be made smaller to increase the number of saturation events. The area required for the capacitors is therefore significantly smaller and the measurement cells can be made smaller. Some capacitors are generally still included to allow the user to adjust the gain. The integration time may be left out to allow the user full control of the gain and maximize the resolution. The ADC may likewise be replaced by a relatively small counter and Schmitt trigger circuit, along with other logic gates. Such a circuit requires relatively little area and power and can be replicated for all sensor inputs. By its nature, the circuit can be smaller and more energy efficient. With modern CMOS mixed-signal processes, power consumption can be as low as 10 μW per channel. The size of the circuit can be reduced as well, since the size of the capacitors can be reduced and the ADC can be replaced by a counter and Schmitt trigger. [Prior art documents] [Non-patent literature]

[0013] [Non-Patent Document 1] Dei, Michele et al., “Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers.” (2017, IEEE International Symposium on Circuits and Systems (ISCAS)) Summary of the Invention [Problem to be solved by the invention]

[0014] Despite the advantages achieved in the prior art, various technical challenges remain. Specifically, it is necessary to reduce the size, complexity, cost, and power consumption of the parallel charge-to-digital conversion, as well as to reduce the noise of the overall system. Furthermore, in the IAF circuit, the charge must be large enough to generate enough counts during integration to achieve high resolution of the measurement signal. To achieve 16-bit resolution, 65k or more count events are required. As an example, with a minimum capacitance of 25fF and a saturation voltage of 0.5V, a charge of 820pC is required to achieve 16-bit resolution. Thus, for sensors that generate small currents, the IAF circuit generally does not provide sufficient digital resolution.

[0015] Problem to be solved It is therefore desirable to provide a readout circuit, a photodetector and a method for reading out an analog sensor charge that overcomes the above-mentioned drawbacks of known devices and methods of similar type. In particular, the device and method should be suitable for reducing the size, complexity, cost, power consumption and noise of the readout circuit, in particular the photodetector, while ensuring a reliable and accurate readout, in particular of small analog sensor charges. [Means for solving the problem]

[0016] overview This problem is solved by a circuit, a photodetector and a method for reading out an analog sensor charge with the features of the independent claims. Advantageous embodiments, which can be realized independently or in any combination, are set out in the dependent claims and in the entire specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In a first aspect of the present invention, a readout circuit is disclosed.

[0018] The term "readout" as used herein is a broad term and is given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to, but is not limited to, an operation or process of quantifying and / or processing at least one physical property and / or a change in at least one physical property detected by at least one device, specifically at least one measurement device, such as at least one sensor. The measurement device may specifically include at least one photodetector. The photodetector may specifically include at least one light sensitive area. The readout may include an individual readout of one device, such as a sensor. Additionally or alternatively, the readout may include a readout of a group of devices, such as a group of sensors. The term "readout circuitry" as used herein is a broad term and is given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to, but is not limited to, an electrical circuitry configured to quantify and / or process at least one physical property and / or a change in at least one physical property detected by at least one measurement device, such as a sensor. The readout circuitry may be configured to read out the at least one sensor, in particular the readout circuitry may be configured to read out the at least one photodetector or at least one sensor of the photodetector.

[0019] The term "sensor" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically, but not exclusively, denote any element or device configured to detect at least one condition or to measure at least one measurement variable. As an example, the sensor may be a light-sensitive sensor, such as used in a photodetector. However, other options are possible. In particular, the sensor may generate at least one signal, such as a measurement signal that is a qualitative or quantitative indicator of the measurement variable and / or measurement characteristic, such as the illumination of the sensor. The signal may be or may include an electrical signal, such as a current or charge.

[0020] The term "photodetector" as used herein is a broad term and is to be given its usual and customary meaning to those skilled in the art, and is not to be limited to any special or customized meaning. The term may specifically refer to, but is not limited to, a measurement device configured to detect optical radiation, such as for detecting illumination and / or light spots generated by at least one light beam. The photodetector may be and / or include a photoconductor or photodiode. The photodetector may include at least one substrate. The single photodetector may be a substrate having at least one single photosensitive area, which generates a physical response to illumination in a predetermined wavelength range. The photodetector comprises at least one sensor configured to generate an analog sensor charge depending on illumination of the photosensitive area of ​​the sensor.

[0021] The term "photosensitive region" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to an area that is sensitive to illumination, e.g., an incident light beam, but is not limited to such an area. For example, the photosensitive region may be a two-dimensional or three-dimensional area that may preferably, but not necessarily, form a continuous and / or continuous area. The photosensitive region may include at least one photoconductive material selected from the group consisting of lead sulfide (PbS); lead selenide (PbSe); mercury cadmium telluride (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimony (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe), extrinsic semiconductors, and organic semiconductors. Specifically, the photodetector may include a plurality of sensors, and the sensors may be arranged in an array.

[0022] The term "light" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to electromagnetic radiation in one or more of the following ranges: visible spectrum range, ultraviolet spectrum range, and infrared spectrum range. Therein, in accordance with part of the standard ISO-21348, the term visible spectrum range generally refers to the spectral range of 380 nm to 760 nm. The term infrared (IR) spectrum range generally refers to electromagnetic radiation in the range of 760 nm to 1000 μm, with the range of 760 nm to 1.4 μm usually referred to as the near infrared (NIR) spectrum range, and the range of 15 μm to 1000 μm referred to as the far infrared (FIR) spectrum range. The term "ultraviolet spectrum range" generally refers to electromagnetic radiation in the range of 1 nm to 380 nm, preferably in the range of 100 nm to 380 nm. The term "light" may also be written as "illumination". Preferably, the illumination used in the present invention is visible light, ie light in the visible spectral range, and / or infrared light, ie light in the infrared spectral range.

[0023] The photosensitive area may be illuminated by at least one illumination source. The illumination source may be or include, for example, an ambient light source and / or may be or include, an artificial illumination source. By way of example, the illumination source may include at least one infrared emitter and / or at least one emitter for visible light and / or at least one emitter for ultraviolet light. By way of example, the illumination source may include at least one light-emitting diode and / or at least one laser diode. The illumination source may in particular consist of one or more of the following illumination sources: lasers, in particular laser diodes (although in principle, alternatively or additionally, other types of lasers can also be used); light-emitting diodes; incandescent lamps; neon lights; flame sources; organic light sources, in particular organic light-emitting diodes; structured light sources. Alternatively or additionally, other illumination sources can also be used.

[0024] The illumination source may be any light source having at least one emission wavelength overlapping with the sensitivity wavelength of the photodetector. The illumination source may generally be adapted to emit at least one light in the ultraviolet spectral range, the infrared spectral range. Most preferably, the at least one illumination source is adapted to emit light in the NIR and IR range, preferably in the range of 800 nm and 5000 nm, most preferably in the range of 1000 nm and 4000 nm. The illumination source may comprise at least one non-continuous light source. The illumination source may be configured to generate at least one modulated light beam. Alternatively, the illumination source may comprise at least one continuous light source. The light beam generated by the illumination source may be unmodulated and / or modulated by further optical means.

[0025] The readout circuit is configured to convert the analog sensor charge to a digital output count. The readout circuit includes at least one integrate-and-fire (IAF) circuit. The IAF circuit is configured to convert the analog sensor charge to a first digital output count. The readout circuit is further configured to process an analog voltage residual value after a last IAF cycle. The readout circuit includes at least one analog-to-digital converter (ADC). The ADC is configured to convert the analog voltage residual value to a second digital output.

[0026] The term "analog signal" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. This term may refer to, but is not limited to, a continuous progression of a physical quantity. The term "analog sensor charge" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. This term may refer to, but is not limited to, a continuous progression of a charging time. As an example, the analog sensor charge may vary continuously in time, for example, by accumulating due to illumination of a light-sensitive area of ​​a photodetector. Additionally or alternatively, the analog sensor charge may vary continuously in time, for example, by dissipating due to transfer to further electrical components.

[0027] The term "digital" as used herein is a broad term and is given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to, but is not limited to, a finite or at least countable set of quantized or discrete signal values. The term "digital output count" as used herein is a broad term and is given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to, but is not limited to, a digital count or digital census output by a readout circuit. In particular, the digital output count may be a count or census using at least one of natural numbers, whole numbers, and integers. As an example, the digital output count may start at 0 and increase by 1 for each event that triggers a count, for example, a light-sensitive area of ​​a photodetector being illuminated with a certain intensity. The digital output count may be provided in the Boolean domain, such as using binary numbers, also called bits. Other options are possible. The digital output may be provided to at least one processor for further processing, for example for evaluating the at least one sensor signal to generate measurement data that can be displayed to a user.

[0028] The readout circuit includes at least one integrate-and-fire circuit (IAF circuit). The term "integrate-and-fire circuit", also referred to as IAF circuit, as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically, but not exclusively, refer to an electrical circuit configured to integrate an incoming analog sensor charge, for example, by using an integrator, and emit an event signal, for example, by using a comparator, when the output voltage reaches a predefined quantization threshold. The event may be used to reset the integrator to start integrating the incoming analog sensor charge again. The incoming analog sensor charge may be based, for example, on at least one capacitive transimpedance amplifier (CTIA). Different types of IAF circuits are generally known to those skilled in the art, for example, from the publication "Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers" by Dei, Michele et al., IEEE International Symposium on Circuits and Systems (ISCAS), 2017, which is incorporated herein in its entirety. Without limitation, specific embodiments of IAF circuits are also outlined in further detail below.

[0029] The IAF circuit is configured to convert the analog sensor charge to a first digital output count.

[0030] The IAF circuit may include at least one integrator. The term "integrator" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to, but is not limited to, an electrical circuit configured to integrate at least one input signal, particularly over time. In other words, the integrator may be configured to accumulate the input signal over time. Specifically, the integrator may be a current integrator. The integrator may be configured to measure an analog sensor charge. The integrator may include at least one of an operational amplifier and a capacitor. The operational amplifier may be an inverting operational amplifier. The operational amplifier and the capacitor may be connected in parallel. The IAF circuit may specifically include at least one capacitor, and the IAF circuit may be configured to employ the linearity of charge-to-voltage conversion using a capacitor. The integrator may include at least one mixed-signal circuit, particularly at least one mixed-signal circuit for resetting the integrator. The integrator may include at least one charge amplifier. Further options are possible and are commonly known to those skilled in the art.

[0031] The input of the op amp is connected to a known voltage, V ref The integrator may hold the opamp output at V after each saturation event. ref The integrator may be configured to reset to an integrated voltage V int To determine the reference voltage V ref and the comparator voltage V comp Therefore, the output of the operational amplifier V int V ref ≧V int ≧V comp It could be.

[0032] As used herein, the term "integrated voltage" refers to V intAlso referred to as an integrator, this term is a broad term that is to be given its ordinary and customary meaning to those skilled in the art and is not intended to be limited to any special or customized meaning. This term may refer to, but is not limited to, an integrator, and in particular the voltage output generated by an operational amplifier of an integrator.

[0033] As used herein, the term "reference voltage" means V ref Also referred to as a reference voltage, it is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may indicate, but is not limited to, a predetermined voltage supply, particularly for an integrator, and in particular to an integrator. The reference voltage may be applied, in particular to an operational amplifier of the integrator, in particular to a first input of the operational amplifier, typically two inputs. The analog sensor charge may be provided, in particular to a second input of the operational amplifier. The output of the operational amplifier may further be fed back to the second input, in particular via a capacitor to the second input.

[0034] As used herein, the term "comparator voltage" means V comp Also referred to as "reference voltage threshold voltage", this term is a broad term and is given its ordinary and customary meaning to those skilled in the art and is not limited to any special or customized meaning. This term may refer to, but is not limited to, a predetermined voltage supply as a reference or threshold, particularly a predetermined voltage supply as a reference or threshold to a comparator.

[0035] Generally, in this specification, the terms "first", "second", and further numbering, if necessary, are used merely as nomenclature and do not indicate any order or priority. In particular, a first entity may be different from a second entity. However, a first entity and a second entity may also at least partially contain each other or at least be of the same type.

[0036] The IAF circuit may further include at least one comparator configured to determine a saturation event. int and Vcomp Specifically, the comparator may be configured to compare V int V comp The comparator may be configured to detect when V is equal to int V comp The comparator may be configured to generate an event signal, also referred to as an event, whenever the first input voltage exceeds the second input voltage. The term "comparator" as used herein is a broad term and is to be given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to, but is not limited to, an electrical circuit configured to compare at least two input signals, specifically voltages. The comparator may be configured to generate at least one output signal, specifically a digital output signal, indicating the result of the comparison, e.g., which input signal is greater. As an example, the comparator may generate a "HIGH" or "1" as an output when the first input voltage is higher than the second input voltage, and a "LOW" or "0" as an output when the first input voltage is lower than the second input voltage. The output signal may be generated continuously over time, especially for changing input signals.

[0037] The comparator may be and / or include at least one Schmitt trigger. The Schmitt trigger may be an inverting or non-inverting Schmitt trigger. The term "Schmitt trigger" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art and is not limited to any special or customized meaning. The term may specifically, but not exclusively, refer to a comparator circuit in which the switch-on and switch-off thresholds are offset from each other by a switching hysteresis. The Schmitt trigger may be configured to compare an input voltage, specifically a time-varying voltage, with two threshold voltages, an upper threshold voltage and a lower threshold voltage. Specifically, the Schmitt trigger may be configured to output a HIGH or 1 if the input voltage is higher than the upper threshold voltage and a LOW or 0 if the input voltage is lower than the lower threshold voltage, and the Schmitt trigger may further be configured to maintain a leading output between the upper threshold voltage and the lower threshold voltage. In other words, the output of the Schmitt trigger may not change unless the input voltage exceeds one of the two threshold voltages. However, other options for the comparator are also feasible.

[0038] The output of the op amp is reset to a known voltage, V ref The output of the opamp may decrease as charge from the sensor is integrated. The output of the opamp may be connected to a comparator V- input. The comparator output may switch HIGH when the output of the opamp / comparator V- input falls below the comparator V+ terminal. The comparator switching switches the output of the opamp back to the initial voltage state V so that the integration cycle may begin again. ref A change in the comparator output to HIGH may cause the reset circuit to pull back to 0. A change in the comparator output to HIGH may be a saturation event that triggers a reset of the integrator. The change in the comparator output may also, specifically, simultaneously increment the counter value by one. In this way, integration cycles are counted. Each completed integration cycle increments the initial digital output count by one.

[0039] The term "saturation event" as used herein is a broad term and is given its ordinary and customary meaning to those skilled in the art and is not limited to any special or customized meaning. The term may specifically refer to, but is not limited to, the saturation or occurrence of an electrical component, specifically an integrator, and more specifically a capacitor of an integrator.

[0040] The value of the integrating capacitor affects the frequency of saturation events in the system. Thus, a smaller capacitor will generate more saturation events / second than a larger capacitor. Thus, for the same charge, a smaller capacitor will count more events than a larger capacitor. The capacitance of a capacitor can be defined by the size of the capacitor, for example, the ratio of the area of ​​the capacitor plates divided by the distance between the capacitor plates. The occurrence of a saturation event can indicate a completed integration cycle of the integrator.

[0041] The IAF circuit may further include at least one counter configured to determine a first digital output count by counting saturation events. The term "counter" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art and is not limited to any special or customized meaning. The term may specifically, but not limited to, denote an electrical circuit configured to count events. In other words, the counter may be configured to store the number of times a particular event has occurred. Specifically, for each determined saturation event, the counter may be incremented by one. The counter may include at least one output. The counter may be configured to output the count, in other words, the number of times a particular event has occurred, specifically in a binary number system. Other options are possible. The counter may include at least one input. The input of the counter may be connected to the comparator mentioned above. A further input of the counter may be connected to a clock, specifically a global clock of the system, such as the readout circuit. The counter may include multiple flip-flops connected in cascade. The counter may be a synchronous counter. The flip-flops are triggered simultaneously by the clock. However, the counter may be an asynchronous counter. Other options are possible and are generally known to those skilled in the art. The first digital output count, also referred to as the IAF digital output, may be an integer number of saturation events for a given input charge. The first digital output count may be proportional to an integer number of integration cycles. Specifically, the counter of the IAF circuit may be a most significant bit (MSB) counter. The MSB counter may be configured to determine the most significant bit of the output of the readout circuit. The readout circuit may include at least one switch for resetting the MSB counter. For example, the MSB counter may include a reset pin for resetting the count back to 0.

[0042] The IAF circuit reduces the op amp's output, V, after each saturation event. int V refThe IAF circuit may further include at least one mixed signal circuit configured to reset the analog voltage to V after each saturation event. The mixed signal circuit may be connected in parallel with the integrator or the integrator's capacitor and generate a short circuit when closed. The mixed signal circuit may be an electrical switch or an electromechanical switch. Specifically, the mixed signal circuit may include at least one transmission gate. Resetting the output of the op-amp is a key component of the IAF. The IAF circuit may be configured such that the reset occurs quickly and automatically after each saturation event. The analog voltage is consistently V after each event. ref needs to be returned to.

[0043] As outlined above, the comparator is int V comp However, in a completed integration cycle (also called a completed IAF cycle) of integrating the incoming analog sensor charge, the integrated voltage exceeds the quantization threshold V comp Since it has not reached (V int >V comp ), there may be a residual that cannot trigger an event firing and therefore is not counted. The term "analog voltage residual" as used herein is a broad term and is given its ordinary and customary meaning to those skilled in the art and is not limited to any special or customized meaning. In particular, the term may refer to, but is not limited to, the residual, remainder, or residue remaining after complete processing of the analog sensor charge by the IAF circuitry, specifically at the end of the final completed integration cycle. The residual may be one or more characterized, described, or quantified by using at least one analog voltage. The analog voltage residual may refer to the residual of the final uncompleted integration cycle.

[0044] The readout circuit is configured to process the analog voltage remaining amount after the last IAF cycle. The IAF circuit may be configured to digitize the analog sensor charge at least to the analog voltage remaining amount. The term "digitization" as used herein, including grammatical variations thereof, is a broad term and is given its ordinary and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. In particular, the term may refer to, but is not limited to, a process of converting or transferring at least one analog input signal, specifically an analog sensor charge, to at least one digital output signal, specifically a digital output count. Digitization may include detecting and / or quantifying the analog input signal, specifically for subsequent conversion. A non-digitizable remaining amount may be an entity that is not detectable and / or quantifiable by the IAF circuit. An incomplete integration cycle may not be quantifiable, specifically by the IAF circuit, and therefore may not be digitized by the IAF circuit, while a completed integration cycle may be digitized by incrementing a counter of the IAF circuit. As an example, the analog sensor charge may not be high enough to produce a completed integration cycle in the IAF circuit, in which case the analog sensor charge may not be digitizable in its entirety, and therefore the IAF circuit may not be sufficient, especially for small analog sensor charges.

[0045] The readout circuit further includes at least one analog-to-digital converter (ADC) configured to convert the analog voltage remainder to a second digital output. The term "second digital output" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may refer to any digital output generated by the ADC that is proportional to the remainder voltage of the final, uncompleted integration cycle, but is not limited to this. For example, the second digital output may be a digital output count. However, other options are also feasible. The second digital output may be proportional to the remainder voltage of the final, but uncompleted, integration cycle. The ADC may be a least significant bit (LSB) counter, also denoted as LSB counter. The LSB counter may be configured to determine the least significant bit of the output of the readout circuit.

[0046] The readout circuit may be configured to determine a combined digital output count by combining the first digital output count and the second digital output. The combined digital output count may be provided in a binary number system. The IAF circuit may be configured to determine a most significant bit (MSB) and the ADC may be configured to determine a least significant bit. The counter of the IAF circuit may be called an MSB counter and the counter of the ADC may be called an LSB counter. M bits of the MSB counter may represent a number of completed integration cycles and N bits of the LSB counter may represent a binary completion value of the remaining voltage of the IAF. The combined digital value of the concatenation of the MSB and LSB may represent a digital resolution of N+M bits. The readout circuit may include at least one output unit or at least one interface. The output unit may be configured to generate at least one output, in particular at least one digital output voltage signal, such as the combined digital output count. The output unit may be configured to pass the output to at least one external device or element, for example a processor for further evaluation. As an example, the output unit may be configured to identify or mark the most significant bits and / or the least significant bits, for example so that a processor can allocate them correctly. Further options are possible.

[0047] The readout circuit further comprises at least one analog-to-digital converter (ADC). The ADC is configured to convert the analog voltage residue into a second digital output. The term "analog-to-digital converter" as used herein, also referred to as ADC, is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically refer to, without being limited to, an electrical circuit configured to convert or transfer at least one analog input signal, specifically an analog sensor charge, into at least one digital output signal, specifically a digital output count. Any known ADC architecture may be used as the ADC for converting the analog voltage residue into the second digital output. For example, the ADC may include at least one ADC architecture selected from the group consisting of a counter-type ADC, a single-slope ADC, a dual-slope ADC, a pipeline ADC, a successive approximation (SAR) ADC, and a sigma-delta ADC. For implementations of ADCs, see Brian Black, "Analog-to-Digital Converter Architectures and Choices for System Design," Analog Dialogue 33-8 (1999). The ADC may have low resolution, specifically 14 bits or less, more specifically 10 bits or less. It may be possible to use a simple ADC that requires little power and little area.

[0048] For example, the ADC may be a counter-type ADC, also called a counter ADC or a slope ADC or a slope converter. However, as outlined above, other options are possible and generally known to those skilled in the art. The ADC may specifically include at least one of a comparator, in particular a Schmitt trigger, and a counter. The V+ terminal of the comparator is connected to the V+ terminal via a DAC. comp From V int Until 2 N During the increase, V comp Voltage is V intThe remaining voltage of V+ can be exceeded and the comparator output can be triggered. At this point a counter starts and increments for each remaining V+ step from the DAC. The final count on the counter is the voltage remaining V int , which may be a digitized representation of the counter. The readout circuit may include at least one switch for resetting the counter. For example, the counter may include a reset pin for returning the count to 0. The use of a counter-type ADC may allow for sharing of a comparator circuit. The ADC and the IAF circuit may share at least one element, specifically at least one comparator. In particular, the ADC and the IAF circuit may share the Schmitt trigger mentioned above. For example, a Schmitt trigger connected to an integrator of the IAF circuit may also be used as part of the ADC. The input of the counter of the ADC may then be connected to the output of the Schmitt trigger. In particular, a further input of the counter of the ADC may be connected to a clock, specifically to the global clock of the readout circuit.

[0049] The readout circuit may further include at least one event handler. The event handler may be configured to identify an event generated by the comparator. The event handler may be configured to initiate a reset of the integrator, such as by initiating a mixed signal circuit, based on the event. The event handler may be configured to initiate an IAF counter, based on the event. The event handler may be configured to initiate a circuit for digitizing the analog voltage residue, particularly in the case of using a counter ADC, based on the event. The event handler may be pre-connected to the counter of the ADC and / or the counter of the IAF circuit. The event handler may be configured to assign an output of the Schmitt trigger to the counter of the ADC and / or the counter of the IAF circuit.

[0050] When integration in the IAF circuit is complete, the output of the op amp is V ref ≧V int >V comp The analog voltage remaining amount V intThe IAF circuit may be V int V comp , which may automatically trigger an IAF reset if the voltage exceeds the threshold of the voltage V. The residual voltage may be the remaining voltage that did not trigger an IAF reset. The analog voltage residual may be quantized by an ADC to generate a value that represents a binary percentage completion of the opamp output voltage. A binary value of 0 is the voltage V int represents the binary value 2 N -1 is the value V comp where N is the number of bits of resolution for the ADC. N ADC values ​​between -1 and 0 represent the analog voltage remaining.

[0051] The readout circuitry may be configured to read out small analog sensor charges, in particular analog sensor charges below 1 nC, more particularly below 1 pC. As explained, also small analog sensor charges that do not trigger a saturation event in the integrator of the IAF circuitry may be digitized, in particular by using an ADC to determine the LSB. This may be particularly relevant with respect to the readout of individual sensors of photodetectors, more particularly photodetectors that generate only small photocurrents. The readout circuitry may be configured to read out at least one sensor configured to generate an analog sensor charge dependent on illumination of a photosensitive area of ​​the sensor.

[0052] The readout circuitry may be configured to read out a number of sensors configured to generate analog sensor charges depending on illumination of the light-sensitive areas of the sensors. The sensors may be arranged in an array. The term "array" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art and is not limited to any special or customized meaning. The term may refer to a spatial arrangement of elements, such as sensors, without being limited thereto. The array may be a one-dimensional array, e.g., a row of sensors along an axis, or a two-dimensional array, e.g., a matrix of sensors. The array may also be a three-dimensional arrangement. The array may be a regular array, e.g., where the distance between elements is constant. The array may be an irregular array, e.g., where the distance between elements varies. The elements in the array may be of the same type or of different types. As an example, the array may include sensors sensitive to different wavelengths. Further options are possible.

[0053] The readout circuit may be a readout integrated circuit (ROIC). The readout circuit may be an integrated circuit (IC), also called a chip or microchip, or the readout circuit may form at least a part of the IC. As known to those skilled in the art, an IC typically includes at least one electrical circuit fabricated on a substrate, in particular a semiconductor substrate, more particularly a silicon (Si) substrate. The readout circuit may be configured to accumulate at least one sensor current, in particular a photocurrent, and the accumulation of the sensor current may generate an analog sensor charge. As an example, the readout circuit may be configured to accumulate a photocurrent for each sensor of the photodetector, or for a group of sensors of the photodetector. The readout circuit may be configured to accumulate, or at least buffer, an analog sensor charge. The readout circuit may be configured to transfer the analog sensor charge to at least one output, for example an output of the IC, which may in particular be a digital output. The readout circuit may be a digital readout integrated circuit (DROIC). The DROIC may use on-chip analog-to-digital conversion, in particular to digitize at least one accumulated photocurrent. The readout circuit may be a digital pixel readout integrated circuit (DPROIC). DPROIC specifically uses on-chip analog-to-digital conversion within each pixel or group of pixels to digitize at least one accumulated photocurrent, where pixel specifically may refer to a photodetector sensor.

[0054] In a further aspect of the invention, a photodetector is disclosed. The photodetector comprises at least one sensor configured to generate an analog sensor charge depending on the illumination of a photosensitive area of ​​the sensor. The photodetector comprises at least one readout circuit according to any one of the embodiments disclosed above or in further detail below. For further details and embodiments of the photodetector, reference can be made to the description of the readout circuit above.

[0055] In a further aspect of the invention, a method for readout of analog sensor charge is disclosed, the method comprising: a) providing at least one readout circuit according to any one of the embodiments disclosed in more detail above or below referring to a readout circuit; b) converting the analog sensor charge to a first digital output count and an analog voltage residue using an IAF circuit; and c) converting the analog voltage residue using an ADC to a second digital output. Includes.

[0056] The method further comprises: d) determining a combined digital output count by combining the first digital output count and the second digital output count. Includes.

[0057] The method may include additional method steps not recited. Further, one or more of the method steps may be performed once or repeatedly. Further, two or more method steps may be performed simultaneously or with overlapping timing.

[0058] The term "providing" as used herein, including grammatical variations thereof, is a broad term and is to be given its ordinary and customary meaning to those skilled in the art, and is not limited to a special or customized meaning. The term may refer to, but is not limited to, at least one of manufacturing a readout circuit, producing a readout circuit, using an existing readout circuit, applying an existing readout circuit, and modifying an existing readout circuit.

[0059] The readout may include a readout of at least one sensor of at least one photodetector according to any of the embodiments disclosed above or in further detail below that refer to a photodetector. The resolution of the readout may be controlled by varying the resolution of the second digital output in step c). The term "resolution" as used herein is a broad term and is given its usual and customary meaning to those skilled in the art, and is not limited to any special or customized meaning. The term may specifically, but not exclusively, indicate how finely and incrementally an originally analog signal, such as an analog sensor charge or light intensity incident on a photodetector, can be digitized. Specifically, the resolution may indicate how finely and incrementally an analog signal can be digitized. Thus, the higher the resolution, the finer the steps of the digitized signal can be. An "N" bit ADC may increase the resolution of the readout circuit by "N" bits. Thus, the resolution of the readout circuit may include the total number of saturation events and a fractional number related to the final uncompleted integration cycle. The total number of saturation events may be captured using an IAF circuit. The fractional part of the final uncompleted integration cycle can be captured using the ADC. The IAF circuit may be less sensitive to current or charge inputs, especially compared to the ADC. As an example, for high enough currents, the bits from the ADC may be reduced to adjust the resolution. Additionally or alternatively, the gain of the readout, specifically the charge-to-voltage gain, may be controlled by varying the resolution of the second digital output in step c). The gain may be controlled by utilizing more or less bits from the analog voltage residue.

[0060] In a further aspect of the invention, it is disclosed that the use of the readout circuit of the invention is for the purpose of reading out at least one PbS sensor, at least one PbSe sensor, or at least one pixelated sensor array comprising a plurality of pixels, each of said pixels comprising at least one PbS or PbSe sensor. In particular, the readout circuit according to the invention can be used in applications with modest or low bias voltages, such as applications where the device is battery-powered or needs to operate at low power, such as sensor nodes, portable measuring devices, devices in explosive atmospheres, etc., allowing an improved signal-to-noise ratio and therefore a high signal quality. For example, the readout circuit can be used in spectrometers, moisture measuring devices, thickness measuring devices, gas analyzers, or any other type of device using a photoconductor as a sensor element. The readout circuit can be used in optical sensors. For example, it can be used in optical sensors employing the so-called FiP effect, such as those described in WO 2012 / 110924 A1, WO 2014 / 097181 A1 and WO 2016 / 120392 A1.

[0061] In a further aspect of the invention, a non-transitory computer readable medium is disclosed, the non-transitory computer readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method according to any one of the embodiments disclosed in detail above or below that refer to the method.

[0062] Further disclosed and proposed herein is a computer program comprising computer executable instructions for carrying out the method according to the invention in one or more of the embodiments encompassed herein, when the program is executed on a computer or a computer network. In particular, the computer program may be stored on a computer readable data carrier and / or on a computer readable storage medium.

[0063] As used herein, the terms "computer-readable data carrier" and "computer-readable storage medium" may specifically denote a non-transitory data storage means such as a hardware storage medium on which computer-executable instructions are stored. A computer-readable data carrier or storage medium may specifically be or include a storage medium such as a random access memory (RAM) and / or a read-only memory (ROM).

[0064] Thus, in particular, one, more than one or all of the method steps as set out above may be carried out using a computer or a computer network, preferably using a computer program.

[0065] Further disclosed and proposed herein is a computer program product having program code means for carrying out the method according to the invention in one or more of the embodiments encompassed herein when said program is executed on a computer or a computer network. In particular, said program code means may be stored on a computer readable data carrier and / or on a computer readable storage medium.

[0066] Further disclosed and suggested in this specification is a data carrier having a data structure stored thereon, which is capable of performing the methods according to one or more of the embodiments disclosed in this specification after being loaded into a computer or a computer network, such as a working memory or a main memory of the computer or computer network.

[0067] Further disclosed and proposed herein is a computer program product having program code means stored on a machine-readable carrier for performing the method according to one or more of the embodiments disclosed herein when the program is executed on a computer or a computer network. As used herein, a computer program product refers to a program as a tradeable product. The product can be in any form, such as generally on a paper medium or on a computer-readable data carrier and / or on a computer-readable storage medium. In particular, the computer program product may be distributed over a data network.

[0068] Finally, what is disclosed and suggested herein is a modulated data signal containing instructions readable by a computer system or computer network for carrying out a method according to one or more of the embodiments disclosed herein.

[0069] With reference to computer-implemented aspects of the present invention, one or more, or even all, of the method steps of the method according to one or more of the embodiments disclosed herein can be performed using a computer or a computer network. Thus, in general, any of the method steps involving providing and / or manipulating data can be performed using a computer or a computer network. In general, these method steps can include any method steps, except for those that typically require manual labor, such as providing a sample and / or certain aspects of performing the actual measurement.

[0070] Specifically, disclosed herein are a computer or computer network comprising at least one processor, the processor being adapted to execute a method according to one of the embodiments described herein, - a computer-loadable data structure adapted to carry out a method according to one of the embodiments described herein while said data structure is executed on a computer, a computer program adapted to carry out a method according to one of the embodiments described herein while said program is running on a computer, a computer program comprising program means for carrying out a method according to one of the embodiments described herein while said computer program is being run on a computer or on a computer network, a computer program comprising program means according to the embodiment, the program means being stored on a computer readable storage medium; a storage medium, on which a data structure is stored, the data structure being adapted to execute a method according to one of the embodiments described herein after being loaded into a main and / or working storage device of a computer or a computer network, and A computer program product having program code means, which may be stored on a storage medium or is stored on a storage medium, for performing a method according to one of the embodiments described herein when the program code means is executed on a computer or on a computer network. It is.

[0071] The devices and methods according to the invention can offer many advantages over known devices and methods. In particular, they are suitable for reducing the size, complexity, cost, power consumption and noise of readout circuits, especially for photodetectors, while also ensuring a reliable and accurate readout, especially of small analog sensor charges. They can furthermore achieve a wider dynamic range and more flexibility in selecting the charge-to-voltage gain. As an example, a 16-bit resolution can be achieved with a wider charge range.

[0072] As used herein, the terms "have", "comprise", "include" or any grammatical variants thereof are used in a non-exclusive sense. Thus, these terms may refer to the situation where there are no further features in the entity described in this context other than the features introduced by these terms, as well as the situation where there are one or more further features. As an example, the expressions "A has B", "A comprises B" and "A includes B" may refer both to the situation where there are no other elements in A besides B (i.e., A consists only of B) and to the situation where, besides B, one or more further elements are present in the entity A, such as element C, elements C and D, or even other elements.

[0073] Furthermore, it should be noted that the terms "at least one," "one or more," or similar language indicating that a feature or element may be present one or more times, are typically used only once in introducing each feature or element. In most cases, the language "at least one" or "one or more" will not be repeated when referring to each feature or element, regardless of the fact that each feature or element may be present one or more times.

[0074] Furthermore, as used herein, the terms "preferably", "more preferably", "particularly", "more particularly", "particularly", "more particularly" or similar terms are used in combination with any feature without limiting the possibility of substitution. Thus, features introduced by these terms are optional features and are not intended to limit the scope of the claims in any way. The invention can be practiced with alternative features, as the skilled artisan will recognize. Similarly, features introduced by "in an embodiment of the invention" or similar expressions are intended to be optional features, without any limitation on alternative embodiments of the invention, without any limitation on the scope of the invention, and without any limitation on the possibility of combining the feature so introduced with other optional or non-optional features of the invention.

[0075] In summary, without excluding further possible embodiments, the following embodiments are envisaged: Embodiment 1: A readout circuit configured to convert an analog sensor charge to a digital output count, the readout circuit comprising at least one integrate and fire (IAF) circuit, the IAF circuit configured to convert the analog sensor charge to a first digital output count, the readout circuit further configured to process an analog voltage residual value after a last IAF cycle, the readout circuit including at least one analog-to-digital converter (ADC), the ADC configured to convert the analog voltage residual value to a second digital output.

[0076] Embodiment 2: A readout circuit according to the previous embodiment, wherein the readout circuit is configured to read out a small analog sensor charge, in particular an analog sensor charge less than 1 nC, more in particular less than 1 pC.

[0077] Embodiment 3: A readout circuit according to any one of the previous embodiments, configured to read out at least one sensor configured to generate an analog sensor charge depending on illumination of a photosensitive area of ​​the sensor.

[0078] Embodiment 4: A readout circuit according to the previous embodiment, wherein the readout circuit is configured to read out a plurality of sensors configured to generate an analog sensor charge depending on the illumination of a photosensitive area of ​​the sensor, the sensors being arranged in an array.

[0079] Embodiment 5: A readout circuit described in any one of the two preceding embodiments, wherein the photosensitive region comprises at least one photoconductive material selected from the group consisting of lead sulfide (PbS); lead selenide (PbSe); mercury cadmium telluride (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimony (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe), extrinsic semiconductors, and organic semiconductors.

[0080] Embodiment 6: A readout circuit as described in any one of the previous embodiments, wherein the readout circuit is configured to determine a combined digital output count by combining the first digital output count and the second digital output, the first digital output count (118) being proportional to a total number of integration cycles and the second digital output (124) being proportional to a remaining voltage of a final uncompleted integration cycle.

[0081] Embodiment 7: A readout circuit according to any one of the previous embodiments, wherein the IAF circuit is configured to digitize the analog sensor charge at least up to an analog voltage remainder, the analog voltage remainder being a non-digitizable remainder of the IAF circuit.

[0082] Embodiment 8: A readout circuit according to any one of the preceding embodiments, wherein the IAF circuit is: at least one integrator, the integrator comprising at least one operational amplifier and at least one capacitor, the input of the operational amplifier being connected to a known voltage V ref The integrator holds the op amp output at V after each saturation event. refand the integrator is configured to reset to the integral voltage V int To determine the reference voltage V ref and the comparator voltage V comp an integrator configured to integrate an output of the operational amplifier between - at least one comparator, in particular at least one Schmitt trigger, configured to determine a saturation event; at least one counter configured to determine a first digital output count by counting saturation events; and - V after each saturation event int V ref at least one mixed signal circuit configured to reset to a read circuit including:

[0083] Embodiment 9: A readout circuit as described in the previous embodiment, wherein the analog voltage remaining amount is the remaining voltage after the last IAF cycle that did not trigger a saturation event.

[0084] Embodiment 10: A readout circuit as described in any one of the preceding embodiments, wherein the ADC comprises at least one ADC architecture selected from the group consisting of a counter-type ADC, a single-slope ADC, a dual-slope ADC, a pipeline ADC, a successive approximation (SAR) ADC, and a sigma-delta ADC.

[0085] Embodiment 11: A readout circuit according to any one of the preceding embodiments, wherein the ADC includes a counter-type ADC, and the ADC and the IAF circuit share at least one component, specifically at least one comparator.

[0086] Embodiment 12: A readout circuit according to any one of the preceding embodiments, wherein the ADC has a low resolution, specifically a resolution of 14 bits or less, more specifically a resolution of 10 bits or less.

[0087] Embodiment 13: A photodetector comprising: - at least one sensor configured to generate an analog sensor charge depending on the illumination of a photosensitive area of ​​said sensor; and At least one read-out circuit according to any one of the preceding embodiments. a photodetector including:

[0088] Embodiment 14: The photodetector according to the previous embodiment, wherein the photodetector comprises a plurality of sensors, the sensors being arranged in an array.

[0089] Embodiment 15: A photodetector according to any one of the preceding embodiments referring to a photodetector, wherein the photosensitive region comprises at least one photoconductive material selected from the group consisting of lead sulfide (PbS); lead selenide (PbSe); mercury cadmium telluride (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimony (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe), extrinsic semiconductors, and organic semiconductors.

[0090] Embodiment 16: A method for reading out an analog sensor charge, the method comprising: a) providing at least one readout circuit according to any one of the preceding embodiments referring to a readout circuit; b) converting the analog sensor charge to a first digital output count and an analog voltage residue using an IAF circuit; and c) converting the analog voltage residue using an ADC to a second digital output. A method comprising:

[0091] Embodiment 17: Further d) determining a combined digital output count by combining the first digital output count and the second digital output. The method according to the previous embodiment, comprising:

[0092] Embodiment 18: A method according to any one of the preceding method embodiments, wherein the readout comprises readout of at least one sensor of at least one photodetector as described in any of the preceding embodiments referring to a photodetector.

[0093] Embodiment 19: A method according to any one of the embodiments of the preceding method, wherein the resolution of the readout is controlled by varying the resolution of the second digital output in step c).

[0094] Embodiment 20: A method according to any one of the embodiments of the preceding method, wherein the readout gain, in particular the charge-to-voltage gain, is controlled by varying the resolution of the second digital count in step c).

[0095] Embodiment 21: A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method as described in any one of the preceding embodiments referring to a method.

[0096] Embodiment 22: A method of using a readout circuit described in any one of the preceding embodiments referring to a readout circuit for one or more readouts of at least one PbS sensor, at least one PbSe sensor, or at least one pixelated sensor array including a plurality of pixels, each of the pixels including at least one PbS or PbSe sensor. Brief explanation of the figure Further optional features and embodiments are disclosed in more detail in the description of the following embodiments, preferably in conjunction with the dependent claims, where each optional feature may be realized in any possible combination as well as in an independent manner as understood by a person skilled in the art. The scope of the present invention is not limited by the preferred embodiments. The embodiments are illustrated diagrammatically in the figures, where the same reference numbers in these figures refer to the same or functionally equivalent elements. [Brief description of the drawings]

[0097] [Figure 1] 1 illustrates an exemplary embodiment of a schematic circuit diagram of a readout circuit. [Figure 2A] 4 shows a further exemplary embodiment of a schematic circuit diagram of a readout circuit and corresponding voltage diagrams; [Figure 2B] 4 shows a further exemplary embodiment of a schematic circuit diagram of a readout circuit and corresponding voltage diagrams; [Figure 3A] 4 shows experimental results of measurements of an exemplary embodiment of a readout circuit. [Figure 3B] 4 shows experimental results of measurements of an exemplary embodiment of a readout circuit. [Figure 4] The experimental results of the photodetector are shown. [Diagram 5] 1 shows a flow chart of an exemplary embodiment of a method for reading out an analog sensor charge.

[0098] Detailed Description of the Embodiments FIG. 1 shows an exemplary embodiment of a schematic circuit diagram of a readout circuit 110. The readout circuit 110 is configured to convert an analog sensor charge 112 into a digital output count 114. The readout circuit 110 includes at least one integrate and fire (IAF) circuit 116. The IAF circuit 116 is configured to convert the analog sensor charge into a first digital output count 118. The readout circuit 110 is further configured to process an analog voltage residue 120 after the last IAF cycle. The readout circuit 110 includes at least one analog-to-digital converter (ADC) 122. The ADC 122 is configured to convert the analog voltage residue into a second digital output 124. The readout circuit 110 may be an electrical circuit configured to quantify and / or process at least one physical property and / or a change in at least one physical property detected by at least one measurement device.

[0099] As shown in FIG. 1, the IAF circuit 116 and the ADC 122 may be separate entities. However, as outlined in more detail below, the IAF circuit 116 and the ADC 122 may also share components, at least in part. At a minimum, the IAF circuit 116 and the ADC 122 may be connected to each other, and more specifically, their components may be connected to each other. The ADC 122 may be an extension of the IAF circuit 116. In the following, the components of the IAF circuit 116 and the ADC 122 are described with reference to FIG. 1.

[0100] The IAF circuit 116 may be an electrical circuit configured to integrate the incoming analog sensor charge 112 and fire an event 126 when the output voltage reaches a predefined quantization threshold. The event 126 can be used to reset the integrator 128 to start integrating the incoming analog sensor charge 112 again. Different types of IAF circuits are generally known to those skilled in the art, for example, from the publication by Dei, Michele et al., “Highly linear integrate-and-fire modulators with soft reset for low-power high-speed imagers,” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), which is incorporated herein in its entirety. The IAF circuit 116 may include at least one integrator 128. The integrator 128 may be an electrical circuit configured to integrate at least one input signal, specifically over time. The integrator 128 may be configured to accumulate the input signal over time. Specifically, the integrator 128 may be a current integrator 128. The integrator 128 may be configured to measure the analog sensor charge 112. The integrator 128 may include at least one of an operational amplifier 130 and a capacitor 132. The operational amplifier 130 may be an inverting operational amplifier 130. The operational amplifier 130 and the capacitor 132 may be connected in parallel. The IAF circuit 116 may specifically include at least one capacitor 132, and the IAF circuit 116 may be configured to employ linearity of charge-to-voltage conversion using the capacitor 132. The integrator 128 may include at least one mixed signal circuit 134, specifically at least one mixed signal circuit 134 for resetting the integrator 128. Thus, the IAF circuit 116 resets V after each saturation event 126. intThe mixed signal circuit 134 may include at least one mixed signal circuit 134 configured to reset the integrator 128. The mixed signal circuit 134 may be connected in parallel with the integrator 128 or the capacitor 132 of the integrator 128 to create a short circuit when closed. The mixed signal circuit 134 may be an electrical switch or an electromechanical switch. The mixed signal circuit 134 may include at least one transistor, such as a field effect transistor or a bipolar junction transistor. Specifically, the mixed signal circuit 134 may include at least one transmission gate. Resetting the output of the operational amplifier 130 may be a critical component of the IAF circuit 116. The IAF circuit 116 may be configured to ensure that the reset occurs quickly and automatically after each saturation event 126. The analog voltage is consistently V after each event 126. ref needs to be returned to.

[0101] The input of op amp 130 is connected to a known voltage V ref The integrator 128 may hold the output of the op-amp 130 at V after each saturation event 126. ref The integrator 128 may be configured to reset the integrated voltage V int To determine the reference voltage V ref and the comparator voltage V comp Therefore, the output of the operational amplifier 130, V int V ref ≧V int ≧V comp It could be.

[0102] The IAF circuit 116 is V int V comp The input signal may further include at least one comparator 136 configured to determine a saturation event 126 when V is reached. The comparator 136 may be configured to fire the event 126. The comparator 136 is configured to detect at least two input signals, specifically V int and V compThe comparator 136 may be an electrical circuit configured to compare voltages such as V and V. The comparator 136 may be configured to generate at least one output signal, in particular a digital output signal, as a result of the comparison, indicative of, for example, which input signal is greater. As an example, the comparator 136 may generate an output of "HIGH" or "1" if the first input voltage is greater than the second input voltage, and an output of "LOW" or "0" if the first input voltage is less than the second input voltage. The output signal may be generated continuously over time, in particular for a changing input signal. The comparator 136 may be configured to generate at least one output signal, in particular a digital output signal, indicative of, for example, which input signal is greater. As an example, the comparator 136 may generate an output of "HIGH" or "1" if the first input voltage is greater than the second input voltage, and a output of "LOW" or "0" if the first input voltage is less than the second input voltage. The output signal may be generated continuously over time, in particular for a changing input signal. int and V comp Specifically, the comparator 136 may be configured to compare V int V comp The comparator 136 may be configured to detect when V int V comp may be configured to generate an event signal, also denoted as an event, each time the threshold Vcc exceeds the threshold Vcc.

[0103] The comparator 136 may be and / or include at least one Schmitt trigger 138. The Schmitt trigger 138 may be an inverting or a non-inverting Schmitt trigger 138. The Schmitt trigger 138 may be a comparator circuit in which a switch-on threshold and a switch-off threshold are offset from each other by a switching hysteresis. The Schmitt trigger 138 may be configured to compare an input voltage, specifically a time-varying voltage, with two threshold voltages, an upper threshold voltage and a lower threshold voltage. Specifically, the Schmitt trigger 138 may be configured to output a HIGH or 1 if the input voltage is higher than the upper threshold voltage and to output a LOW or 0 if the input voltage is lower than the lower threshold voltage, and the Schmitt trigger 138 may further be configured to maintain a leading output between the upper threshold voltage and the lower threshold voltage. The output of the Schmitt trigger 138 may not be changed unless the input voltage exceeds one of the two threshold voltages. However, other options for the comparator 136 are feasible. The comparator 136 may be connected to the output of the integrator 128, specifically to the output of the operational amplifier 130 of the integrator 128. The comparator 136, specifically the output of the comparator 136, may further be connected to at least one switch control 140. The switch control 140 may be configured to control the mixed signal circuit 134 to reset the integrator 128. The readout circuit 110, specifically the ADC 122, may include at least one switch 141. The switch control 140 may be configured to control the switch 141.

[0104] The IAF circuit 116 may further include at least one counter 142 configured to determine the first digital output count 118 by counting the saturation events 126. The counter 142 may be an electrical circuit configured to count the events 126. The counter 142 may be configured to store the number of times that a particular event 126 has occurred. Specifically, for each determined saturation event 126, the counter 142 may increment by one. The counter 142 may be configured to output the count. The counter 142 may be configured to output the number of times that a particular event 126 has occurred, specifically in a binary number. The counter 142 may include multiple cascaded flip-flops. The counter 142 may be a synchronous counter or an asynchronous counter 142. The counter 142 may include at least one input. The input of the counter 142 may be connected to the comparator 136 described above. The readout circuit 110 may include multiple counters 142. Specifically, the counter 142 of the IAF circuit 116 may be an MSB counter 144. The MSB counter 144 may be configured to determine a most significant bit (MSB) of the output of the readout circuit 110. The MSB counter 144 may be configured to determine the first digital output count 118. A further input of the MSB counter 144 may be connected to a shutter 146, specifically a global shutter 146, such as a global shutter 146 shared with the ADC 122 of the readout circuit 110. The global shutter 146 may be configured to transfer at least one signal, specifically a voltage, from the IAF circuit 116 to the ADC 122.

[0105] The ADC 122 may be an electrical circuit configured to convert or transfer at least one analog input signal, specifically the analog sensor charge 112, to at least one digital output signal, specifically the digital output count 114. For example, the ADC 122 may be a counter-type ADC 122. However, in principle, any known ADC architecture may be used for the ADC 122 to convert the analog voltage residue to a second digital output. For example, the ADC may include at least one ADC architecture selected from the group consisting of a counter-type ADC, a single-slope ADC, a dual-slope ADC, a pipeline ADC, a successive approximation (SAR) ADC, and a sigma-delta ADC. For an embodiment of the ADC 122, see Brian Black, "Analog-to-Digital Converter Architectures and Choices for System Design," Analog Dialogue 33-8 (1999). The ADC 122 may have a low resolution, specifically 14 bits or less, more specifically 10 bits or less. It may be possible to use a simple ADC that requires little power supply and little area. The ADC 122 may specifically include a comparator 136, specifically a Schmitt trigger 138, and / or a counter 142. The V+ terminal of the comparator 136 is coupled to a V comp From V int Until, 2 N During the ramp, V comp Voltage is V int The residual voltage may be exceeded and the comparator output may be triggered. At this point, counter 142 is started and increments for each remaining V+ step from the DAC. The final count of counter 142 is the voltage residual V intThe readout circuit 110 may include at least one switch 141 for resetting the counter 142. For example, the counter 142 may include a reset pin for resetting the count back to 0. The use of a counter-type ADC allows for sharing of comparator circuits.

[0106] As already indicated, in principle, the ADC 122 and the IAF circuit 116 can share at least one component, in particular at least one comparator 136. In particular, the ADC 122 and the IAF circuit 116 may share a Schmitt trigger 138. For example, the Schmitt trigger 138 connected to the integrator 128 of the IAF circuit 116 may be used as part of the ADC 122. However, as previously mentioned and as shown in FIG. 1, the ADC 122 and the IAF circuit 116 may be separate entities, which may be connected to each other, in particular by using a shutter 146. In particular, the ADC 122 may be an extension of the IAF circuit 116. An input of the comparator 136 of the ADC 122 may be connected to the output of the comparator 136 of the IAF circuit 116, in particular by using a shutter 146. A further input of the comparator 136 of the ADC 122 may be connected to the integrated voltage V int is the V of ADC122 ramp As compared with the lamp voltage V ramp may be connected to

[0107] As mentioned above, the ADC 122 may further include at least one counter 142. An input of the counter 142 of the ADC 122 may be connected to an output of the Schmitt trigger 138 of the ADC 122. The counter 142 of the ADC 122 may be an LSB counter 148. The LSB counter 148 may be configured to determine a least significant bit (LSB) of the output of the readout circuit 110. As mentioned above, an input of the LSB counter 148 may be connected to an output of the comparator 136 of the ADC 122. In particular, a further input of the LSB counter 148 may be connected to a clock 150, in particular to the global clock 150 of the readout circuit 110. The LSB counter 148 may be a synchronous counter 142 triggered by the clock 150. The LSB counter 148 may be configured to determine a second digital output 124. The second digital output 124 may be any digital output generated by the ADC 122 that is proportional to a remaining voltage of the final uncompleted integration cycle. For example, the second digital output 124 may be a digital output count. However, other options are possible. The second digital output 124 may be proportional to a remaining voltage of a final but uncompleted integration cycle. The ADC 122 may be a least significant bit (LSB) counter 142, such as an LSB counter 148. The LSB counter 148 may be configured to determine the least significant bit of the output of the readout circuit 110.

[0108] The readout circuit 110 may be configured to determine a combined digital output count 114 by combining the first digital output count 118 and the second digital output 124. The combined digital output count 114 may be output in a binary number system. As mentioned above, the IAF circuit 116 may be configured to determine the most significant bit (MSB) and the ADC 122 may be configured to determine the least significant bit (LSB). The M bits of the MSB counter 144 may represent the number of integration cycles completed and the N bits of the LSB counter 148 may represent a binary completion value of the remaining voltage on the IAF. The combined digital value concatenated with the LSB of the MSB may represent a digital resolution of N+M bits. The readout circuit 110 may include at least one output unit 152 and / or at least one interface, for example, to at least one further device for further evaluation. The output unit 152 may be configured to generate at least one output, in particular at least one digital output voltage signal, such as the combined digital output count 114. The output unit 152 may be configured to pass the output to at least one external device or element, such as a processor for further evaluation. As an example, the output unit 152 may be configured to identify or mark the most significant bit and / or the least significant bit, such as for a processor to correctly assign them. The MSB counter 144 and / or the LSB counter 148 may at least partially form the output unit 152. A processor receiving the first digital output count 118 from the MSB counter 144 and the second digital output 124 from the LSB counter 148 may be configured to use the first digital output count 118 from the MSB counter 144 as the most significant bit and the second digital output 124 from the LSB counter 148 as the least significant bit for the combined digital output count 114.

[0109] The operation of the readout circuit 110 will now be described with reference to Figure 1. Initially, the analog sensor charge 112 may arrive at the IAF circuit 116, and specifically, the integrator 128 of the IAF circuit 116. The integrator 128 is coupled to a reference voltage V ref and the comparator voltage V comp By integrating the analog sensor charge 112 between int The integral voltage V int may be the voltage output generated by the integrator 128, specifically the operational amplifier 130. ref may be a predefined voltage supply as a reference, specifically a predefined voltage supply as a reference to the integrator 128. The reference voltage may specifically be applied to an operational amplifier 130, specifically a first of the typically two inputs of the operational amplifier 130. The analog sensor charge 112 may specifically be supplied to a second input of the operational amplifier 130. The output of the operational amplifier 130 may further be fed back to the second input, specifically via a capacitor 132. The integration and resetting of the charge results in an integrated voltage V int can be a triangular signal over time, as shown in FIG. 1. As the analog sensor charge 112 is directed to the integrator 128, the integrated voltage V int may increase over time until the integrator 128 is reset using the mixed signal circuit 134 of the integrator 128. int Such a process in which V is accumulated and reset may be referred to as a completed integration cycle. As previously mentioned, a completed integration cycle may indicate a countable saturation event 126 for the IAF circuit 116. However, the presence of an integrated voltage V int is not large enough to trigger a saturation event 126, such as the final uncompleted integration cycle, the integration voltage V int may remain as analog voltage remainder 120 without being reset. Thus, as an example, and as shown in FIG. 1, the integrated voltage V remaining at the output of opamp 130 in the final uncompleted integration cycle may be int may be the analog voltage residue 120.

[0110] The saturation event 126 may be the saturation or occurrence of satiation of an electrical component, specifically the integrator 128, more specifically the capacitor 132 of the integrator 128. The saturation event 126 may refer to an event of maximum charge on the capacitor 132. The saturation may depend on at least one geometric characteristic of the capacitor 132, specifically the size. The smaller the capacitor 132, the faster the saturation may occur and the more saturation events 126 may occur over time. The capacitance of the capacitor 132 may be defined by the size of the capacitor 132, for example, the ratio of the area of ​​the capacitor plates divided by the distance between the capacitor plates. The occurrence of the saturation event 126 may indicate a completed integration cycle of the integrator 128. As outlined above, when the saturation event 126 occurs, the integrated voltage V int is a predefined quantization threshold V comp When integration cycle 118 is reached, comparator 136 of IAF circuit 116 may fire an event signal that may be counted. Specifically, IAF circuit 116 may be configured to convert analog sensor charge 112 to a first digital output count 118 by counting integration cycles. Each completed integration cycle may increment first digital output count 118.

[0111] The saturation event 126 is detected by the comparator 136 of the IAF circuit 116 and the comparator voltage V comp It can be determined using V int may be provided to a first of typically two inputs of the comparator 136 of the IAF circuit 116. comp may be provided to the second of typically two inputs of the comparator 136 of the IAF circuit 116. comp may be a predefined voltage supply as a reference or threshold, specifically a predefined voltage supply as a reference or threshold for the comparator 136 of the IAF circuit 116. The comparator 136 of the IAF circuit 116 is int and V compSpecifically, the comparator 136 of the IAF circuit 116 may be configured to compare V int V comp This condition may be configured to detect when a saturation event occurs, specifically when V comp When a saturation event 126 is detected, the comparator 136 may fire an event signal that may be counted, specifically by the MSB counter 144. The comparator 136 may be configured to detect a saturation event when V int V comp However, in the final integration cycle, also called the last IAF cycle, which integrates the incoming analog sensor charge 112, the integrated voltage reaches the quantization threshold V comp (V int <V comp ), there may be a remainder that cannot trigger an event firing and therefore is not counted. The analog voltage remainder 120 may be a remainder or a remainder or a remainder left after full processing of the analog sensor charge 112 by the IAF circuit 116, specifically upon completion of the final integration cycle. The remainder may be one or more characterized, described, or quantified by using at least one analog voltage. The analog voltage remainder 120 may refer to a remainder of the final uncompleted integration cycle. The IAF circuit 116 may be configured to digitize the analog sensor charge 112 at least up to the analog voltage remainder 120.

[0112] The event signal fired by the comparator 136 of the IAF circuit 116 may be directed to an MSB counter 144, which may be configured to count the saturation events 126 and increment the first digital output count 118 accordingly. The event signal fired by the comparator 136 of the IAF circuit 116 may be further directed to a switch control 140 to reset the integrator 128. The analog voltage residue 120 may be directed to the ADC 122 by using a shutter 146 and / or a switch 141 of the ADC 122. The comparator 136 of the ADC 122 detects the V int is the lamp voltage V ramp V ramp can increase and / or decrease. ramp V int When the integration in the IAF circuit 116 is completed, a signal may be passed to the LSB counter 148. The LSB counter 148 may then begin counting by using a clock 150 to generate the second digital output 124. Specifically, when the integration in the IAF circuit 116 is completed, V ref ≧V int >V comp The remaining analog voltage V int may be present at the output of the operational amplifier 130. The IAF circuit 116 int V comp , an IAF reset may be automatically triggered when the voltage exceeds the threshold voltage V. The remainder voltage may be a remainder voltage that did not trigger an IAF reset. The analog voltage remainder 120 may be quantized by the ADC 122 to obtain a value that represents a binary percentage completion of the opamp 130 output voltage. A binary value of 0 represents the voltage V int and has the binary value 2 N -1 is the value V comp represents 0 and 2 N An ADC value between -1 can represent an analog voltage residue 120.

[0113] The first digital output count 118 and the second digital output 124 may then be passed to a processor, for example, for further evaluation of the analog sensor charge 112. The readout circuit 110 may be configured to read out small analog sensor charges 112, specifically less than 1 nC, more specifically less than 1 pC. As described, small analog sensor charges 112 that do not trigger a saturation event 126 in the integrator 128 of the IAF circuit 116 may also be digitized, specifically by using the ADC 122 to determine the least significant bits.

[0114] 2A-2B show further exemplary embodiments of a schematic circuit diagram and corresponding voltage signal state diagrams of the readout circuit 110. For the description of FIG. 2A, the description of FIG. 1 above can generally be referred to. FIG. 2A shows an exemplary embodiment of the readout circuit 110, in which the IAF circuit 116 and the ADC 122 can share the comparator 136. Thus, there may no longer be a clear separation between the IAF circuit 116 and the ADC 122 in the readout circuit 110, but both may be integrated into one common electrical circuit. The analog sensor charge 112 may be directed to at least one transmission gate 154. The transmission gate 154 may be configured to direct the analog sensor charge 112 to at least one of the integrator 128 and a dummy integrator. Thus, from the transmission gate 154, the analog sensor charge 112 may be directed to the integrator 128. The integrator 128 may include an operational amplifier 130, which may specifically be a capacitive transimpedance amplifier 156, and a capacitor 132. The integrator 128 outputs an integrated voltage V int The integral voltage V int may be directed to a comparator 136, which may specifically be a Schmitt trigger 138. The comparator 136 is int V compmay generate an event signal whenever the comparator 126 exceeds the integrator 128. The readout circuit 110 may include at least one event handler 158. The event handler 158 may be configured to identify a comparator event 126. The event handler 158 may then initiate a reset of the integrator 128, such as using the switch control 140, based on the comparator event 126. Additionally or alternatively, the event handler 158 may initiate at least one of the counters 142. Additionally or alternatively, the event handler 158 may initiate a digitization of the analog voltage residue 120, such as by configuring the comparator 136 to digitize the analog voltage residue 120. The event handler 158 may set appropriate counter inputs based on the comparator output, which is clocked via a system clock 150. The MSB counter 144 and / or the LSB counter 148 may be coupled to at least one clock 150. The MSB counter 144 may be coupled to an integrate and fire clock (IAF clock) 160. The LSB counter 148 may be connected to an analog-to-digital converter clock (ADC clock) 162 .

[0115] The event handler 158 may further be connected to the switch control 140. The switch control 140 may be configured to control at least one switch 141 of the readout circuit 110. In particular, the switch control 140 may be configured to control the mixed signal circuit 134 of the readout circuit 110. The readout circuit 110 may include at least one mixed signal circuit 134 for resetting the integrator 128. The readout circuit 110 may include at least one switch 141 configured to reset at least one of the MSB counter 144 and the LSB counter 148, such as to initialize a new readout. The readout circuit 110 may comprise at least one switch 141 for selectively assigning at least one voltage to at least one component of the readout circuit 110. The readout circuit 110 is connected to a comparator voltage V comp , and / or the lamp voltage V rampThe switch control unit 140 may include at least one switch 141 for selectively allocating the comparator voltage V comp and / or lamp voltage V ramp to the comparator 136. Specifically, the switch control section 140 may be configured to assign a comparator voltage V comp to the comparator 136. Specifically, the switch control unit 140 may be configured to assign the ramp voltage V ramp to the comparator 136. In general, other embodiments of the read circuit 110, such as other interconnections of the components of the read circuit 110 or further components of the read circuit 110, are also possible.

[0116] FIG. 2B is a voltage diagram during reading using the readout circuit 110 shown in FIG. 2A. The top row of the diagram shows the current control state of the readout circuit 110. First, an initialization of the readout circuit 110 can be performed. The initialization state is indicated by reference numeral 164 in FIG. 2B. In the initialization state 162, the MSB counter 144 and the LSB counter 148 may be reset and the IAF clock 162 may be switched on, as shown in the second row of the diagram. The reset of the MSB counter 144 and the LSB counter 148 is indicated by reference numeral 166 in FIG. 2B. The first sub-integrator clock 168 and the second sub-integrator clock 170 may be started along with the IAF clock 162. The initialization state 164 may be followed by an integrate and fire state (IAF state) 172 and an end state 174. The IAF state 172 and the end state 174 are used to reset the integration time T of the readout circuit 110. int, i.e., may cover the time during which an integration cycle or, correspondingly, a saturation event 126 may be counted, specifically by using the IAF clock 160. In the end state 174, the analog voltage remainder 120 may remain in the integrator 128. Previously, the end of the IAF state 172 may be represented by the first sub-integrator clock 160. The end of the end state 174 may be represented by the second sub-integrator clock 170. The end state 174 may be followed by a stop state 176, in which the IAF clock 160 may be switched off. Up to and including the stop state 176, the comparator voltage V comp may be applied to the comparator 136. Thus, the analog sensor charge 112 is proportional to the reference voltage V ref and V comp The integrated voltage V int Each integration cycle may produce a countable saturation event 126, and in the final uncompleted integration cycle, the analog voltage remainder 120 may remain in the integrator 128 as outlined above. The stop state 178 may be followed by an analog-to-digital converter state (ADC state) 178. In the ADC state 178, the ramp voltage V ramp may be applied to the comparator 136. V ramp may be increased over time until it equals the analog voltage remainder 120, which may again trigger an event signal. However, this time the ADC counter 162 may be used to digitize the signal. Finally, a read state 180 may follow to output the determined digital output count 114, where V comp is again applied to comparator 136, and V int As in the original case, V ref will be reset to.

[0117] 3A-3B show experimental results of measurements on an exemplary embodiment of the readout circuit 110. The experiments were performed using a prototype system implementing the described readout circuit 110. An exemplary experiment is shown to illustrate the described readout circuit 110 and its advantages. The prototype system uses an IAF circuit 116 followed by an 8-bit counter-type ADC 122. FIG. 3A shows 1600 measurements M at a sample frequency of 1600 Hz, each measurement M resulting in a measured ADC count N. An average ADC output μ of 9830 counts implies 38 IAF counts, i.e. effectively 5.25 bits of resolution. The experiment showed a standard deviation σ of 9.9 counts. The implied signal-to-noise ratio (SNR) based on the mean and standard deviation is 992, i.e. effectively 9.96 bits. The effective gain of 4.7 bits of resolution is due to the measurement of the analog voltage residue 120 utilizing an 8-bit counter-type ADC 122. The IAF circuit 116 used a 50 fF capacitor 132 to integrate the charge over 500 μs. The measured charge Q was calculated to be 0.9 pC per sample, as shown in FIG. 3B. A discrete Fourier transform (DFT) analysis of the measurements is shown in FIG. 3C. The root mean square (RMS) charge noise at 16 Hz was measured to be 58 aC. At a frequency f of 160 Hz, the RMS charge noise was measured to be 43 aC, and at 620 Hz, the RMS charge noise was measured to be 40 aC. These noise densities indicate a SNR in a 1 Hz bandwidth of the FFT of 15.392 / √Hz at 16 Hz, 20.999 / √Hz at 160 Hz, and 22.449 / √Hz at 620 Hz. The effective number of bits is therefore 13.9 at 16 Hz, 14.4 at 160 Hz, and 14.5 at 620 Hz, respectively.

[0118] The readout circuit 110 has been shown to increase the SNR from 5.25 bits to 9.96 bits of effective resolution based on full bandwidth analysis of the ADC output. Analysis of the input analog sensor charge 112 shows a noise measurement floor of 40 aCrms up to 58 aCrms of charge per square root Hertz of bandwidth. A measurement charge of 0.9 pC is sufficient for infrared sensors such as PbS and InGaAs, whose small dimensions make them suitable for array or matrix type structures. FFT 1 Hz SNR measurements show a measurement of about 15 effective bits. The readout circuit 110 was implemented with 64 independent ADC measurement channels for parallel readout of 64 sensor elements, using an average power of 62 μW per channel. ADC resolution of 8 bits up to 24 bits showed INL and DNL linearity of <1-LSB. The resolution of the readout circuit 110 was significantly improved by utilizing an 8-bit counter-type ADC 120 instead of a simple IAF current counter approach. Compared to the classical approach using a ROIC and an ADC, the power requirements of the readout circuit 110 were less than 100 times lower than state-of-the-art analog front-ends (AFEs) from Texas Instruments Inc. and Analog Devices Inc.

[0119] FIG. 4 shows an exemplary embodiment of a photodetector 182. The photodetector may be and / or include a photoconductor or a photodiode. The photodetector 182 comprises at least one sensor 184 configured to generate an analog sensor charge 112 depending on the illumination of a light-sensitive area 186 of the sensor 184. The photodetector 182 comprises at least one readout circuit 110 according to any one of the embodiments disclosed above or below, with further reference to the readout circuit 110 in detail. The photodetector 182 may be a measurement device configured to detect light radiation, such as to detect illumination and / or light spots generated by at least one light beam 188. The photodetector 182 may include at least one substrate. The single photodetector 182 may be a substrate having at least one single light-sensitive area 186, which generates a physical response to illumination in a predetermined wavelength range. The photodetector 182 may include at least one housing 190 that encloses at least one component of the photodetector 182, such as the at least one sensor 184 and the readout circuitry 110. The housing 190 may include at least one window 192 for transmitting optical radiation, such as the light beam 188, specifically to the at least one sensor 184.

[0120] The sensor 184 may be any element or device configured to detect at least one condition or to measure at least one measurement variable. The sensor 184 may be a light-sensitive sensor 184, for example as used in the photodetector 182. In particular, the sensor 184 may generate at least one signal, such as a measurement signal, which is a qualitative or quantitative indication of a measurement variable and / or a measurement characteristic, for example of illumination of the sensor 184. The signal may be or may include an electrical signal, such as a current or charge. The light-sensitive area 186 may be an area that is sensitive to illumination, for example by an incident light beam 188. For example, the light-sensitive area 186 may be a two-dimensional or three-dimensional area that may preferably, but not necessarily, be continuous and / or form a continuous area. The photosensitive region may include at least one photoconductive material selected from the group consisting of lead sulfide (PbS), lead selenide (PbSe), mercury cadmium telluride (HgCdTe), cadmium sulfide (CdS), cadmium selenide (CdSe), indium antimony (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), silicon (Si), silicon germanium (SiGe), extrinsic semiconductors, and organic semiconductors. Specifically, the photodetector 182 may include a plurality of sensors 184, and the sensors 184 may be arranged in an array.

[0121] As mentioned above, the readout circuit 110 may be configured to read out, in particular, a small analog sensor charge 112. This may be particularly relevant with regard to the readout of a photodetector 182, more particularly an individual sensor 184 of the photodetector 182 that may generate only a small photocurrent. The readout circuit 110 may be configured to read out at least one sensor 182 configured to generate an analog sensor charge 112 depending on the illumination of a light-sensitive area 186 of the sensor 184. The readout circuit 110 may be configured to read out a plurality of sensors 184 configured to generate an analog sensor charge 112 depending on the illumination of a light-sensitive area 186 of the sensor 184. The sensor 184 may be arranged in an array. An array may be a spatial arrangement of elements such as the sensor 184. The array may be a one-dimensional array, for example a row of sensors along an axis, or a two-dimensional array, for example a matrix of sensors. The array may also be a three-dimensional array. The array may be a regular array, for example with a constant distance between the elements. The array may also be an irregular array, for example with different distances between elements. The elements in the array may be of the same type or of different types. As an example, the array may include sensors 184 that are sensitive to different wavelengths.

[0122] The readout circuit 110 may be a readout integrated circuit (ROIC). The readout circuit 110 may be an integrated circuit (IC), also called a chip or microchip, or the readout circuit 110 may form at least a part of the IC. As a person skilled in the art will appreciate, an IC typically includes at least one electrical circuit fabricated on a substrate, in particular a semiconductor substrate, more particularly a silicon (Si) substrate. The readout circuit 110 may be configured to accumulate at least one sensor current, in particular a photocurrent, the accumulation of the sensor current may generate an analog sensor charge 112. The readout circuit 110 may be configured to accumulate a photocurrent for each sensor 184 of the photodetector 182, or for a group of sensors 184 of the photodetector 182. The readout circuit 110 may be configured to accumulate, or at least buffer, the analog sensor charge 112. The readout circuit 110 may be configured to transfer the analog sensor charge 112 to at least one output, for example an output of the IC, in particular a digital output. The readout circuit 110 may be a digital readout integrated circuit (DROIC). The DROIC may use on-chip analog-to-digital conversion to digitize at least one accumulated photocurrent, in particular. The readout circuit 110 may be a digital pixel readout integrated circuit (DPROIC). The DPROIC may use on-chip analog-to-digital conversion to digitize at least one accumulated photocurrent, in particular within each pixel or group of pixels, which may represent a sensor 184 of a photodetector 182.

[0123] 5 shows a flow chart of an exemplary embodiment of a method for reading out the analog sensor charge 112. The method includes: a) (denoted by reference numeral 194) providing at least one readout circuit according to any one of the embodiments disclosed above or in detail below, referring to readout circuit 110; b) converting the analog sensor charge 112 to a first digital output count 118 and an analog voltage residue 120 using an IAF circuit 116 (designated by reference numeral 196); and c) converting the analog voltage residue 120 to a second digital output 124 using an ADC 122 (designated with reference numeral 198).

[0124] The method further comprises: d) determining a combined digital output count 118 by combining the first digital output count 118 and the second digital output 124 (designated with reference numeral 200).

[0125] The method may include further method steps not listed. Furthermore, one or more method steps may be performed once or repeatedly. Furthermore, two or more method steps may be performed simultaneously or overlapping in time. The readout may include a readout of at least one sensor 184 of at least one photodetector 182 according to any of the embodiments disclosed above or in further detail below, referring to the photodetector 182. The resolution of the readout may be controlled by varying the resolution of the second digital output 124 of step c). The gain of the readout, in particular the charge-to-voltage gain, may be controlled by varying the resolution of the second digital output 124 of step c). [Explanation of symbols]

[0126] 110 Readout circuit 112 Analog Sensor Charge 114 Digital Output Counts 116 Integrate and fire circuit (IAF circuit) 118 First Digital Output Count 120 Analog voltage remaining 122 Analog-to-Digital Converter (ADC) 124 Second Digital Output 126 Events 128 Integrator 130 Operational Amplifiers 132 Capacitor 134 Mixed Signal Circuit 136 Comparator 138 Schmitt Trigger 140 Switch control section 141 Switch 142 Counter 144 Most Significant Bit Counter (MSB Counter) 146 Shutter 148 Least Significant Bit Counter (LSB Counter) 150 Clock 152 Output Unit 154 Transmission Gate 156 Capacitive Transimpedance Amplifier (CTIA) 158 Event Handlers 160 Integrate-and-fire clock (IAF clock) 162 Analog-to-Digital Converter Clock (ADC Clock) 164 Initialization state 166 Reset 168 1st Lower Integrator Clock 170 Second Lower Integrator Clock 172 Integrate-and-fire state (IAF state) 174 End Status 176 Stopped 178 Analog-to-Digital Converter Status (ADC Status) 180 Read state 182 Photodetector 184 Sensors 186 Photosensitive area 188 Light Beam 190 Housing 192 Windows 194 Process a) 196 Process b) 198 Process c) 200 process d)

Claims

1. A readout circuit (110) configured to convert an analog sensor charge (112) into a digital output count (114), The readout circuit (110) comprises at least one integral firing (IAF) circuit (116), the IAF circuit (116) is configured to convert the analog sensor charge (112) into a first digital output count (118), The readout circuit (110) is further configured to process the remaining analog voltage (120) after the last IAF cycle. The readout circuit (110) includes at least one analog-to-digital converter (ADC) (122), the ADC (122) configured to convert the remaining analog voltage (120) to a second digital output (124).

2. The readout circuit (110) according to claim 1, wherein the readout circuit (110) is configured to read out a small analog sensor charge (112).

3. The readout circuit (110) according to claim 1 or 2, wherein the readout circuit (110) is configured to read out the sensor (184) which is configured to generate an analog sensor charge (112) depending on the illumination of the photosensitive area (186) of at least one sensor (184).

4. The readout circuit (110) is configured to determine a combined digital output (114) by combining the first digital output count (118) and the second digital output (124). The readout circuit (110) according to claim 1 or 2, wherein the first digital output count (118) is proportional to the total number of integration cycles, and the second digital output (124) is proportional to the remaining voltage of the final incomplete integration cycle.

5. A readout circuit (110) according to claim 1 or 2, wherein the IAF circuit (116) is - At least one integrator (128), the integrator (128) comprises at least one operational amplifier and at least one capacitor, the input to the operational amplifier is a known voltage V ｒｅｆ The integrator (128) holds the output of the operational amplifier to V after each saturation event (126). ｒｅｆ The integrator (128) is configured to reset to the integral voltage V ｉｎｔ To determine the reference voltage V, ｒｅｆ Comparator voltage V ｃｏｍｐ An integrator (128) configured to integrate the output of the operational amplifier between the two; - At least one comparator (136) configured to determine a saturation event (126); - At least one counter (142) configured to determine the first digital output count (118) by counting the saturation events (126); and - After each saturation event (126) V ｉｎｔ V ｒｅｆ At least one mixed signal circuit (134) configured to be reset A readout circuit (110) including the readout circuit.

6. The readout circuit (110) according to claim 5, wherein the remaining analog voltage is the remaining voltage after the last IAF cycle that did not trigger a saturation event (126).

7. The readout circuit (110) according to claim 1 or 2, wherein the ADC (122) comprises at least one ADC architecture selected from the group consisting of a counter-type ADC, a single-slope ADC, a dual-slope ADC, a pipeline ADC, a successive approximation (SAR) ADC, and a sigma-delta ADC.

8. The readout circuit (110) according to claim 1 or 2, wherein the ADC (122) includes a counter-type ADC, and the ADC and the IAF circuit share at least one component.

9. - The sensor (184) is configured to generate an analog sensor charge (112) depending on the illumination of the photosensitive area (186) of at least one sensor (184); and - At least one readout circuit (110) according to claim 1 or 2 A photodetector (182) equipped with the following features.

10. The photodetector (182) according to claim 9, wherein the photosensitive region (186) comprises at least one photoconductive material selected from the group consisting of lead sulfide (PbS); lead selenide (PbSe); mercury cadmium telluride (HgCdTe); cadmium sulfide (CdS); cadmium selenide (CdSe); indium antimony (InSb); indium arsenide (InAs); indium gallium arsenide (InGaAs); silicon (Si); silicon germanium (SiGe); external semiconductors; and organic semiconductors.

11. A method for reading an analog sensor charge (112), wherein the method is a) A step of providing at least one read circuit (110) according to claim 1 or 2, referring to a read circuit (110); b) A step of using the IAF circuit (116) to convert the analog sensor charge (112) into a first digital output count (118) and an analog voltage remaining amount (120); and c) A step of using the ADC (122) to convert the remaining analog voltage (120) into a second digital output (124) count. Methods that include...

12. d) A step of determining a combined digital output count (114) by combining the first digital output count (118) and the second digital output (124). The method according to claim 11, further comprising:

13. A non-temporary computer-readable medium, which, when executed by one or more processors, includes instructions causing the one or more processors to perform the method described in claim 11, which refers to the method.

14. A method of using a readout circuit (110) according to claim 1 or 2, relating to a readout circuit (110) for reading one or more of at least one PbS sensor, at least one PbSe sensor, or at least one pixelated sensor ray including a plurality of pixels, A method of use in which each of the aforementioned pixels includes at least one PbS sensor or PbSe sensor.

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