Receiver synchronization for optical communications.

Abstract

An optical communication system, receiver, and method for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver are provided, the method including receiving a data input stream at the receiver, the data input stream having a first data rate set based on a transmitter clock rate, generating a wave, obtaining a phase error between the data input stream and the generated wave, determining a synchronized clock rate by using the phase error to adjust a frequency of the generated wave to match the frequency of the generated wave to the transmitter clock rate of the data input stream, and using the synchronized clock rate to decode the data input stream to obtain data encoded in the data input stream.

Description

[Technical field]

[0001] Technical Field The present disclosure relates to methods and systems for synchronizing a receiver for purposes of decoding communications transmitted using an optical communication system, such as synchronizing the receiver's clock to a received data input stream. [Background technology]

[0002] background Optical or light communication systems in which light is modulated to encode data or information for communication between optical communication nodes are useful for a variety of applications such as establishing ad-hoc networks between peers; for example, in certain vehicular applications, such optical communication systems can be used for vehicular communication as described in U.S. Pat. No. 11,245,469. However, such systems may include or rely on external synchronization to synchronize a receiver with a transmitter so that encoded data can be properly decoded. Such external synchronization refers to a synchronization process in which a receiver is synchronized with a transmitter using communication separate (different) from the optical communication system with which the receiver is to be synchronized. For example, external synchronization may include informing a receiver of the data or clock rate of an input stream to be transmitted by use of a cellular network or dedicated short range communication (DSRC). It has been found that there is a need for systems and methods for enabling internal synchronization for ad-hoc optical communication networks, i.e., synchronization that does not rely on external communication, such as using DSRC or cellular communication, or on providing a configuration to a vehicle during manufacture, such as by setting all of the clock rates of the optical communication nodes the same.

[0003] U.S. Patent No. 11,245,469 teaches a vehicular line-of-sight optical communication system for use in ad-hoc networks formed by vehicles during their travel along a road. As discussed in the patent, vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) networks provide the ability to significantly reduce vehicle collisions by allowing vehicles to exchange messages such as "change lanes," "hard brakes," "ice patch," and the like with other vehicles. Active and passive sensor-based vehicular object detection systems that do not include V2V and V2I communications rely on the interpretation of signals to determine the behavior of nearby vehicles and other objects. Signals can be corrupted or jammed, leading to erroneous interpretations. Sensors can also fail, resulting in loss of functionality. V2V networks, on the other hand, rely on explicit information exchanged between vehicles in the form of data packets. These packets, if received without error, provide precise and unambiguous information about the current status (e.g., location, speed, and heading) and intentions (e.g., lane change, hard braking, right turn) from nearby vehicles. This information can be fused with information from existing sensors (e.g., cameras, radar, lidar) to improve driving.

[0004] In realistic traffic situations (e.g., on busy main roads), the number of vehicles, the speeds at which they are moving, and their continuously changing positions and headings relative to each other make achieving a low-latency and reliable V2V and / or V2I network extremely challenging.

[0005] V2V networks that rely on radio frequency (RF) communications, such as those using DSRC, have been widely envisioned to address this issue. However, these RF networks have inherent drawbacks due to the propagation characteristics of RF signals. RF signals tend to propagate in a plane in an omnidirectional pattern. As a result, more vehicles than the desired vehicle will receive the RF signal transmitted from the host vehicle. Therefore, network architectures based on DSRC may require additional processing and hardware overhead to determine which vehicles form a subnetwork, manage orthogonal channel assignments (e.g., time, frequency, code, and space) to those subnetworks, and then route packets between the vehicles in the subnetwork. Moreover, because the positions and orientations of the vehicles relative to each other are constantly changing, these networks must be able to perform these tasks very quickly.

[0006] In some implementations, synchronization of a transmitter, such as one or more light sources, and a receiver may be performed using external communications such as Wi-Fi™, Bluetooth™, or other DSRC. Nevertheless, as noted above, it has been found that there is a need for systems and methods for enabling internal synchronization for ad-hoc optical communications networks, i.e., synchronization for ad-hoc optical communications networks that does not rely on external communications such as any of the DSRCs described above, or by constraining the system to certain characteristics or parameters. Summary of the Invention [Means for solving the problem]

[0007] overview According to one aspect of the disclosure, a method is provided for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver, the method including receiving a data input stream at the receiver, the data input stream having a first data rate set based on a transmitter clock rate, generating a wave, obtaining a phase error between the data input stream and the generated wave, determining a synchronized clock rate by using the phase error to adjust a frequency of the generated wave to match the frequency of the generated wave to the transmitter clock rate of the data input stream, and using the synchronized clock rate to decode the data input stream to obtain data encoded in the data input stream.

[0008] According to various embodiments, the method may further comprise any one of the following features or any technically feasible combination of some or all of these features:

[0009] The method further comprises inputting the phase error into a proportional integral (PI) controller, the PI controller being connected to a wave generator used to generate the generated wave. The wave generator includes a phase generator and a direct digital synthesizer (DDS), the PI controller outputs a phase step that is input to a phase generator, the phase generator being operatively connected to the DDS; The generated wave output by the DDS is mixed or multiplied with the data input stream to generate a phase error; the synchronization clock rate is determined based on a feedback process that modifies the frequency and / or phase of the generated wave until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match; The obtaining of the phase error is performed recursively or iteratively until the phase error between the data input stream and the generated wave falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match, -The generated wave is a sine wave, the method is performed by an optical communication node having a receiving device configured to perform the method, and / or An initial frequency is used to initially generate the wave, the initial frequency being predetermined.

[0010] According to another aspect of the present disclosure, an optical communication receiver is provided. The optical communication receiver includes a photodetector for receiving a data input stream, a phase generator, a direct digital synthesizer (DDS) operably connected to an output of the phase generator, and a clock extraction module having a proportional-integral (PI) controller whose output is operably connected to the phase generator. The output of the DDS is used to obtain a phase error that is input to the PI controller. The clock extraction module is configured to perform a feedback process that includes adjusting the frequency of the generated wave based on the obtained phase error until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are deemed to match. The optical communication receiver is configured to decode the data input stream using a synchronized clock rate determined based on the feedback process to obtain data.

[0011] According to various embodiments, the automatic topology determination system may further include any one of the following features or any technically feasible combination of some or all of these features:

[0012] The synchronization clock rate is determined based on the adjusted frequency of the generated wave when the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

[0013] the PI controller is used to generate a phase step as an output operatively connected to the phase generator, the phase step being generated based on a phase error; The phase error is obtained by mixing or multiplying the data input stream with the generated wave, - The synchronization clock rate is synchronized internally to the data input stream without the use of external communication; the clock extraction module is configured to provide a synchronized clock rate to the finite state machine; and / or - the finite state machine is operatively connected to the processor to provide data to the processor;

[0014] BRIEF DESCRIPTION OF THE DRAWINGS Preferred exemplary embodiments are described below in conjunction with the accompanying drawings, in which like reference numbers refer to like elements and in which: [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 illustrates an optical communication system including a transmitting device and a receiving device, according to one embodiment. [Diagram 2] 2 is a schematic diagram of exemplary components of a transmitter of the transmitting device of FIG. 1 according to one embodiment. [Diagram 3] FIG. 2 illustrates an example of encoding bytes using an exemplary four-cycle encoding scheme, according to one embodiment. [Figure 4] 2 is a schematic diagram of exemplary components of a receiver of the receiving device of FIG. 1 according to one embodiment. [Diagram 5] 5 is a schematic diagram of exemplary components of a clock extraction module of the receiver of FIG. 4 in accordance with one embodiment. [Figure 6] 6 is a schematic diagram of exemplary components of a proportional-integral (PI) controller of the clock extraction module of FIG. 5 in accordance with one embodiment. [Figure 7]4 is a flow diagram of a method for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver, according to one embodiment. [Figure 8] 4 is a flow diagram of a method for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver, according to one embodiment. [Figure 9] 1 is a graph of an example of generated square wave input data according to one embodiment. [Figure 10] 1 is a graph of an example of a sine wave generated by a direct digital synthesizer (DDS) of a clock extraction module, in accordance with one embodiment. [Figure 11] 11 is a graph of the product of the two signals of FIGS. 9 and 10 according to one embodiment. [Figure 12] 12 is a graph of a filtered signal based on filtering the signal of FIG. 11 according to one embodiment. [Figure 13] 1 is a graph of the phase step (ΔΦ) of a PI controller, according to one embodiment. [Figure 14] FIG. 1 is a diagram of a unit circle showing values ​​located around it and used by the DDS, according to one embodiment. [Figure 15] FIG. 4 is a diagram of a sawtooth function representing the phase of a signal being generated, according to one embodiment. [Figure 16] 1 is a diagram of a vehicle communication system including a host vehicle and other vehicles that communicate using an optical communication system, according to one embodiment. [Figure 17] FIG. 17 is a diagram of the host vehicle of FIG. 16 including multiple optical communication modules, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Detailed Description The systems and methods described herein, according to at least some embodiments, enable synchronization of communications between two electronic devices performed using optical or light communications, and in particular, the systems and methods enable internal ad-hoc synchronization of such communications. Such electronic devices having optical or light communications capabilities, such as line-of-sight optical communications capabilities, are each referred to as optical communications nodes and may include one or more transmitters for transmitting light to transmit data to another node and / or one or more receivers for receiving light to obtain data transmitted by another node. "Light" or "optical" communications as described herein refers to visible light as well as light invisible to the human eye having wavelengths suitable for use in line-of-sight communications, including at least portions of the infrared (IR), visible, and ultraviolet (UV) light spectrums. The transmitter encodes or modulates data using light at or according to a transmitter clock rate and transmits such encoded data as a data input stream, which is then received at the receiver. In at least some embodiments, to properly decode and / or interpret the data input stream to obtain the data being communicated by the transmitter, the receiver synchronizes a clock that matches the clock used by the transmitter to encode the data input stream, in this embodiment, the synchronized clock is then used to decode the data input stream to obtain the data.

[0017] According to at least some embodiments, a method is provided for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver. According to embodiments, the method includes receiving a data input stream at the receiver, the data input stream having a first data rate set based on a transmitter clock rate, generating a wave, obtaining a phase error between the data input stream and the generated wave, determining a synchronized clock rate by using the phase error to adjust the frequency of the generated wave to match a phase and / or frequency of the generated wave to the transmitter clock rate of the data input stream, and using the synchronized clock rate to decode the data input stream to obtain data encoded in the data input stream.

[0018] According to some embodiments, an optical communication receiver is provided that includes a photodetector for receiving a data input stream, a clock extraction module having a phase generator, a direct digital synthesizer (DDS) operatively connected to an output of the phase generator, and a proportional-integral (PI) controller whose output is operatively connected to the phase generator. In this embodiment, the output of the DDS is used to obtain a phase error that is input to the PI controller and to obtain a synchronized clock rate at the time when the frequency of the generated wave and the transmitter data rate of the data input stream match. According to this embodiment, the clock extraction module is configured to implement a feedback process that includes adjusting the frequency of the generated wave based on the obtained phase error until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are deemed to match. The optical communication receiver is configured to decode the data input stream using the synchronized clock rate determined based on the feedback process, at least according to this embodiment.

[0019] Referring to FIG. 1, an optical communication system 10 having a transmitting device 12 and a receiving device 14 is shown. The transmitting device 12 has a transmitter 16 used to communicate data with a receiver 18 of the receiving device 14. In one embodiment, the transmitting device 12 is a first vehicle, such as a first automobile, and the receiving device 14 is a second vehicle, such as a second automobile. The transmitter 16, which may be comprised of one or more light sources and a transmission processing circuit, transmits data by modulating or encoding the data using the emitted light, and this emission of light with the encoded data is referred to as a data input stream. The data input stream is received at the receiver 18, which may be comprised of a receiving processing circuit having a photodetector 19, and in some embodiments, the receiver 18 may include certain components or circuits of a receiving processing circuit 78 or a dedicated receiving processing circuit 78' described in U.S. Pat. No. 11,245,469, which is incorporated herein by reference.

[0020] The transmitter 16 may be comprised of one or more light sources, such as one or more light emitting diodes (LEDs), and other transmit processing circuitry, such as an integrated driver circuit 76 and / or a dedicated driver circuit 76', as described in U.S. Pat. No. 11,245,469, incorporated herein by reference. According to at least some embodiments, to transmit a message, the light emitted by the transmitter 16, such as one or more LEDs, may be encoded or modulated (pulsed) by the transmit processing circuitry (or other transmitter control) using a transmit signal that is modulated according to the message to be transmitted. In this manner, the light source (e.g., LEDs) is effective to optically communicate the message from the transmitter 16. Various encoding techniques may be used, such as time, frequency, or digital encoding, e.g., digitally transmitting the message as binary data using frequency shift keying (FSK). The message may be transmitted in data packets, with error checking, encryption, and other data messaging techniques used as needed or desired for the particular application.

[0021] 2, there is shown a transmitter 16 including a power source 20, an electronic controller 22 shown as a field programmable gate array (FPGA), and a light source 24. It should be understood that other types of processors or controllers may be used instead of or in addition to an FPGA for the electronic controller 22. The electronic controller 22 may obtain data to be transmitted in digital form, which may be encoded such that a clock signal (or transmitter clock rate) may be derivable or extractable using the receiver 18. In one embodiment, each bit is transmitted using four clock cycles or phases, which allows for consistent extraction of the clock signal through the use of the internal synchronization methods described herein. For example, with reference to FIG. 3, there is shown an example of encoding the binary data byte 11000010 (as shown at 25a-h) using this four-cycle encoding scheme. In other embodiments, an N-cycle encoding scheme may be used, where N is a number other than four. According to at least some embodiments, the data is encoded in a way that only a clock signal is transmitted, thereby ensuring that all pulses are in phase with one another and that there is no secondary data frequency for the receiver 18 (specifically, the clock extraction module 30 of the receiver 18, as described above with respect to FIG. 4) to lock onto. This is accomplished by transmitting a clock signal and allocating four clock cycles for each bit. When a zero bit is transmitted, a single clock cycle goes low, as shown in FIG. 3.

[0022] The receiver 18 may be comprised of a receiver processing circuit that may include components and / or circuits of the receiver processing circuit 78 and / or dedicated receiver processing circuit 78' described in U.S. Pat. No. 11,245,469, which is incorporated herein by reference. With reference to FIGS. 1 and 4, the receiver 18 is shown to include a photodetector 19 (FIG. 1), a clock extraction module 30, a finite-state machine (FSM) 32, a system clock 34, a processor 36, and a memory 37. The photodetector 19 may include one or more photodiodes (e.g., pn photodiodes, pin photodiodes, avalanche photodiodes) and / or other photodetector elements such as metal-semiconductor-metal (MSM) photodetectors. The receiver 18 is also shown to have an analog-to-digital converter (ADC) 38 that may convert the data input stream from an analog format (designated 51) to a digital format (designated 52) before the data is provided to the clock extraction module 30, as shown in FIG. 4.

[0023] 5, the clock extraction module 30 is shown to include a mixer / multiplier 42, a proportional-integral (PI) controller 44, a phase generator 46, and a direct digital synthesizer (DDS) 48. The clock extraction module 30 receives a digital data input stream as an input, as shown at 52, and provides a synchronized clock output (indicating a synchronized clock rate) 66 that is synchronized to the data input stream. In at least some embodiments, the purpose of the clock extraction module (or clock-data recovery (CDR) module) 30 is to extract the clock rate of the data input stream (the transmitter clock rate) and replicate a clock with a matching frequency (the synchronized clock rate) at the receiver 18. This allows the data input stream to be properly decoded at the receiver through the use of the synchronized clock rate. As shown in FIG. 5, the mixer / multiplier 42 is used to obtain a phase error, as shown at 54, which is then fed to the PI controller 44.

[0024] Referring to FIG. 6, the PI controller 44 is shown taking as inputs the obtained phase error 54 and the clock being adjusted (referred to as the "synchronous running clock"), as shown at 56, and provides a phase step (ΔΦ) (used as clock control feedback) used to control the frequency of the wave generated by the DDS 48, as shown at 60. In at least some embodiments, the DDS 48 operates as a wave generator to generate a starting or base wave at an initial frequency. The phase generator 46 is used to control the frequency of the DDS 48. The DDS 48 uses a 12-bit lookup table that corresponds to values ​​around a unit circle. The phase generator 46 outputs a sawtooth function that represents the phase of the signal being generated. As the PI controller 44 corrects by increasing or decreasing the frequency, the phase step (ΔΦ) of the sawtooth function increases or decreases to match, as shown at 60. The phase generator 46 and the DDS 48 are used as a wave generator to generate a wave that is provided as an input to the clock extraction module 30, as shown at 62. As shown, the phase step 60 is determined by the PI controller 44 via feedback from the DDS 48 as shown at 62, which allows correction until the phase and frequency (i.e., clock or data rate) of the data input stream and the generated wave match, and determines an extracted or synchronized clock rate as shown at 66, which allows the data input stream to be decoded to obtain the data. As shown in Figure 5, the phase step 60 is then used by the phase generator 46 to generate a phase input 61, which is fed to the DDS 48 and used to generate the wave.

[0025] The PI controller 44 includes an accumulator 70 that has as inputs the phase error 54 and the synchronous running clock 56, which then outputs a phase step (ΔΦ) 60 that is used to adjust the generated wave. The accumulator 70 is used to provide an input to an integral gain component 72 of the PI controller 44, which is then used with a proportional gain component 74 to provide the phase step (ΔΦ) 60.

[0026] 7, one embodiment of a method 200 for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver is shown. According to at least some embodiments, the method 200 is performed by the receiver 18 of the receiving device 14, and thus the method 200 may include the use of one or more components of the receiving device 14, as will be understood by those skilled in the art in light of the following description. It will also be understood that although steps 210-250 are described as being performed in a particular order, the steps may be performed in any suitable and technically feasible order.

[0027] Method 200 begins by step 210, where a data input stream is received at a receiver, and the data input stream is being transmitted at a first data rate that is set based on a transmitter clock rate. As used herein, the term "transmitter clock rate" refers to the rate of a clock used by a transmitter as part of the encoded data of the data input stream transmitted to a receiver. Also, as used herein, the term "data rate" refers to the rate at which bits of data are provided over time, such as the rate at which bits of data are transmitted by a transmitter. According to at least some embodiments and implementations, such as when method 200 is used for certain vehicle-to-everything (V2X) communications, the data rate at which the data input stream is transmitted is assumed to be the same as the data input stream received at the receiver, since such actual differences are negligible. Method 200 continues to step 220.

[0028] In step 220, a wave is generated, the wave having an initial frequency. In at least some embodiments, the wave is a sine wave generated by the DDS 48. The initial frequency may be predetermined and may be stored in a memory, such as the memory 37 of the receiver 18. The wave may be generated by a wave generator, such as the DDS 48, which may generate the wave based on a phase input 61, for example, of FIG. 5. The phase input 61 may be generated by the phase generator 46. As shown in FIG. 5, the clock extraction module 30 implements a feedback loop in which the frequency and / or phase of the generated wave is adjusted. The method 200 continues to step 230.

[0029] In step 230, a phase error between the data input stream and the generated wave is obtained. As shown in FIG. 5, in one embodiment, the mixer / multiplier 42 of the clock extraction module 30 is used to generate a phase error 54 based on the data input stream 52 and the generated wave 62. The sine wave of the generated wave 62 is multiplied with the data input stream, and the resulting product is similar to the trigonometric identity sin(x)×sin(y)=1 / 2[cos(xy)−cos(x+y)]. In this identity, the cos(xy) term represents the phase difference between the two signals. After using a low-pass filter to remove cos(x+y), the resulting signal is used as the phase error 54.

[0030] In the example shown in Figures 9-12, square wave input data 400 (Figure 9) is being transmitted at 10 kHz while DDS sine wave 420 is generating a 10.5 kHz sine wave (Figure 10). The product 440 (Figure 11) of these two signals is the 20.5 kHz signal plus the 0.5 kHz signal. After filtering the 20.5 kHz signal, only the 0.5 kHz signal remains, which represents the phase difference 460 (Figure 12). Method 200 continues at step 240.

[0031] In step 240, a synchronized clock rate is determined by using the phase error to adjust the frequency of the generated wave to match the transmitter clock rate of the data input stream. The synchronized clock rate may also be referred to as the extracted clock rate since it is extracted from the data input stream. In at least some embodiments, the phase error is provided as an input to the PI controller 44, which controls the frequency of the sine wave generated by the DDS 48, meaning that as the phase error 54 approaches zero, the frequency of the sine wave converges to the value of the received data input stream 52. For example, as shown in FIG. 13, the phase step (ΔΦ) 60 of the PI controller 44 is shown as converging over time, as shown at 480. The phase generator 46 is used to control the frequency of the DDS 48. In the illustrated embodiment, the DDS 48 is a 12-bit lookup table that corresponds to values ​​around a unit circle 500 as shown in FIG. 14. The phase generator 46 outputs a sawtooth function that represents the phase of the signal being generated, as represented at 520 in Figure 15. As the PI controller 44 corrects by increasing or decreasing the frequency, the phase step (ΔΦ) 60 of the sawtooth function increases or decreases to match the transmitter clock rate. Method 200 continues at step 250.

[0032] In step 250, the data input stream is decoded using the synchronized clock rate to obtain data encoded within the data input stream. The transmitter clock rate of the data input stream is extracted as the synchronized clock rate so that the data input stream can be interpreted by a receiver. For example, receiver 18 can demodulate or otherwise decode the data using the synchronized clock rate by dividing the data input stream into segments each represented by four periods, e.g., as shown in FIG. 3. Method 200 then ends.

[0033] 8, one embodiment of a method 300 for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver is shown. According to at least some embodiments, the method 300 is performed by the receiver 18 of the receiving device 14. The method 300 may include the use of one or more components of the receiving device 14, as will be understood by those skilled in the art in light of the following description. In step 310, a data input stream is received, which is similar to step 210 of the method 200, and the discussion of which is attributed to this step 310. The method 300 continues with step 320.

[0034] In step 320, the clock rate is extracted through a feedback clock rate matching process 322. In at least one embodiment, the feedback clock rate matching process includes steps 210-240 of method 200 described above. In some embodiments, the feedback clock rate matching process includes tuning or adjusting the frequency of a generated wave, such as a sine wave, until the frequency matches the transmitter clock rate, which is the clock rate used to encode the data being transmitted by the transmitter. In some embodiments, using an encoding in which each bit is represented by four periods of the transmitter clock rate, it is possible to extract the transmitter clock rate at the receiver through the use of a feedback clock rate matching process. The feedback clock rate matching process is a process of up-mixing the generated wave in the DDS 48 with the data input stream, as described above, and then adjusting the frequency of the generated wave using the PI controller 44, phase generator 46 and DDS 48 until the frequency matches the transmitter clock rate. Method 300 continues at step 330.

[0035] In step 330, the data input stream is decoded using the extracted clock rate to obtain the data encoded in the data input stream. This step is similar to step 250 of method 200, and the discussion therein refers to this step 330. Method 300 then ends.

[0036] In some embodiments, the extracted / synchronized clock rate of a particular transmitting device may be stored in a memory of the receiving device 14, such as memory 37 of the receiver 18, and used to communicate with that particular transmitting device. For example, a device ID of the transmitting device may be communicated using the data input stream or may be generated by the receiving device 14, which may assign the generated device ID to each unique device detected. The generated ID may be stored in memory 37 along with the extracted clock rate and used to communicate with that device.

[0037] In at least some embodiments, method 200 and / or method 300 enable ad-hoc data communication synchronization such that, for each data input stream transmitted or received at receiver 18, receiver 18 or receiving device 14 can determine a synchronization or extraction clock rate for that data input stream. Thus, in such embodiments, the synchronization or extraction clock rate does not need to be stored, as it may be readily determined using steps 220-240 of method 200 or step 320 of method 300.

[0038] As will now be appreciated by those skilled in the art, method 200, method 300, and / or optical communication system 10 may be adapted to extract a clock rate from a data input stream such that the data input stream can be decoded to obtain data being communicated between a transmitting device and a receiving device, such as for purposes of communicating information between transmitting device 12 and receiving device 14. A variety of specific vehicle applications will be apparent to those skilled in the art.

[0039] FIG. 16 provides one such example directed to a vehicular application in which components and / or features of the system 10 and methods 200, 300 described above may be used. In particular, FIG. 16 illustrates a vehicular communication system 600 including a first or host vehicle 610, a second vehicle 611, a third vehicle 612, a fourth vehicle 613, a fifth vehicle 614, a sixth vehicle 615, and a roadside equipment (RSE) 617. Each of the vehicles 610-616 and the RSE 617 may include one or more optical communication modules including transmitting devices and / or receiving devices, and thus may be referred to as optical communication nodes 612-617 that communicate with each other in the ad-hoc optical communication network 601. For example, each of the optical communication nodes 612-617 may include one or more transmitting devices and one or more receiving devices for purposes such as performing bidirectional communication with other optical communication nodes 612-617 in the ad-hoc optical communication network 601. One or more of the transmitting devices of optical communications nodes 612-617 may each be a transmitting device characterized above as transmitting device 12. One or more of the receiving devices of optical communications nodes 612-617 may each be a transmitting device characterized above as receiving device 14. The description of the ad-hoc line-of-sight optical communications network set forth in U.S. Pat. No. 11,245,469 is incorporated herein by reference and is attributable to vehicular communications system 600.

[0040] FIG. 17 illustrates a host vehicle 610 that is shown as including vehicle electronics 611 having a left headlight communication module 621, a right headlight communication module 622, a left taillight communication module 623, a right taillight communication module 624, a center taillight communication module 625, a left side mirror communication module 626, and a right side mirror communication module 627. Each of these optical communication modules 621-627 includes a transmitting device and a receiving device for two-way optical communication and is integrated into an existing headlight or taillight of the host vehicle 610 as described in U.S. Pat. No. 11,245,469, which is incorporated herein by reference and assigned to the host vehicle 610 unless inconsistent with an express discussion of the host vehicle 610 herein. Moreover, it should be understood that in other embodiments, the transmitting and / or receiving devices of the optical communication modules 621-627 may be integrated into other components of the host vehicle 610 (instead of the headlights or other external vehicle lights / lamp modules) and / or may be of different configurations and numbers.

[0041] Each of the transmitting devices of each of the communication modules 621-627 may be a transmitting device characterized above as transmitting device 12. Each of the receiving devices of each of the communication modules 621-627 may be a transmitting device characterized above as receiving device 14. Each of the other optical communication nodes 612-617 may similarly have optical communication modules similar to the optical communication modules 621-627 of the host vehicle 610 and may use these optical communication modules for bidirectional communication in the ad-hoc optical communication network 601. In at least some embodiments, the optical communication in such embodiments is line-of-sight optical or optical communication, such that the ad-hoc optical communication network 601 is a line-of-sight ad-hoc optical communication network. Each of the optical communication modules described above may implement method 200 and / or method 300 for purposes of synchronizing communication between optical communication modules in the ad-hoc optical communication network 601.

[0042] It should be understood that the foregoing description is of one or more embodiments of the present invention. The present invention is not limited to the specific embodiments disclosed herein, but rather is defined only by the appended claims. Furthermore, statements contained in the foregoing description should not be construed as limitations on the scope of the present invention or the definition of terms used in the claims, unless the terms or phrases are specifically defined above in relation to the disclosed embodiments. Various other embodiments and various changes and modifications to the disclosed embodiments will become apparent to those skilled in the art.

[0043] As used in this specification and claims, the terms "for example," "for instance," "such as," and "such as," as well as the verbs "comprise," "have," "include," and other verb forms thereof, when used in conjunction with a list of one or more components or other items, should each be construed as open-ended, meaning that the list should not be considered to exclude other additional components or items. Other terms should be construed using their broadest reasonable meaning, unless used in a context requiring a different interpretation. Additionally, the term "and / or" should be construed as a disjunction. Thus, for example, the phrase "A, B, and / or C" should be construed to cover all of "A," "B," "C," "A and B," "A and C," "B and C," and "A, B, and C."

Claims

1. 1. A method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received at the receiver, comprising: receiving a data input stream at a receiver, the data input stream having a first data rate set based on a transmitter clock rate; Generating waves; obtaining a phase error between the data input stream and the generated wave; determining a synchronized clock rate by using the phase error to adjust the frequency of the generated wave to match the frequency of the generated wave to the transmitter clock rate of the data input stream; using the synchronized clock rate to decode the data input stream to obtain data encoded in the data input stream; A method comprising:

2. 2. The method of claim 1, further comprising inputting the phase error into a proportional integral (PI) controller, the PI controller being connected to a wave generator used to generate the generated wave.

3. The method of claim 2 , wherein the wave generator includes a phase generator and a direct digital synthesizer (DDS).

4. 4. The method of claim 3, wherein the PI controller outputs a phase step that is input to the phase generator, the phase generator being operatively connected to the DDS.

5. 5. The method of claim 4, wherein the product wave output by the DDS is mixed or multiplied with the data input stream to generate the phase error.

6. 2. The method of claim 1, wherein the synchronized clock rate is determined based on a feedback process that modifies the frequency and / or phase of the generated wave until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

7. 7. The method of claim 6, wherein the obtaining of the phase error is performed recursively or iteratively until the phase error between the data input stream and the generated wave falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

8. The method of claim 1 , wherein the generated wave is a sine wave.

9. The method of claim 1 , wherein the method is performed by an optical communications node having a receiving device configured to perform the method.

10. The method of claim 1 , wherein an initial frequency is used to initially generate the wave, the initial frequency being predetermined.

11. 1. An optical communications receiver, comprising: a photodetector for receiving a data input stream; a clock extraction module having a phase generator, a direct digital synthesizer (DDS) operably connected to an output of the phase generator, and a proportional integral (PI) controller whose output is operably connected to the phase generator, the output of the DDS being used to obtain a phase error that is input to the PI controller; Equipped with the clock extraction module is configured to implement a feedback process that includes adjusting the frequency of the generated wave based on the obtained phase error until the phase error falls below a predetermined threshold at which a transmitter clock rate of the data input stream and a frequency of the generated wave are considered to match; The optical communications receiver is configured to decode the data input stream using a synchronized clock rate determined based on the feedback process to obtain data.

12. 12. The optical communications receiver of claim 11, wherein the synchronized clock rate is determined based on the adjusted frequency of the generated wave when the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

13. 12. The optical communications receiver of claim 11, wherein the PI controller is used to generate a phase step as the output operatively connected to the phase generator, the phase step being generated based on the phase error.

14. 12. The optical communications receiver of claim 11, wherein the phase error is obtained by mixing or multiplying the data input stream with the generated wave.

15. 12. The optical communications receiver of claim 11, wherein the synchronization clock rate is internally synchronized to the data input stream without the use of external communication.

16. The optical communications receiver of claim 11 , wherein the clock extraction module is configured to provide the synchronized clock rate to a finite state machine.

17. 16. The optical communications receiver of claim 15, wherein the finite state machine is operatively connected to a processor to provide the data to the processor.

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