Piezoelectric-on-insulator (POI) substrate and method for manufacturing a piezoelectric-on-insulator (POI) substrate
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-03-30
- Publication Date
- 2026-03-10
AI Technical Summary
The accumulation of metal elements like lithium from the piezoelectric layer in piezoelectric on insulator (POI) substrates can diffuse through the dielectric layer and trap structure, reducing the performance of the trap structure and increasing parasitic currents.
Incorporating a second trap layer made of silicon carbide, which is thinner than the first polycrystalline silicon-based trap layer, to increase the number of traps without significantly increasing the total thickness of the trap structure, thereby reducing parasitic effects.
The use of a silicon carbide-based second trap layer effectively increases the number of traps while maintaining a thin trap structure, thereby reducing parasitic currents and maintaining device performance.
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Abstract
Description
[Technical field]
[0001] The present invention relates to a piezoelectric-on-insulator (POI) substrate comprising, in that order, a support substrate, a trapping structure, a dielectric layer, and a piezoelectric layer, and a method for manufacturing such a POI substrate.
[0002]
[0002] Such substrates are known in the prior art and are, for example, monocrystalline silicon substrates, polycrystalline silicon trap structures, POI substrates with a silicon oxide layer and a piezoelectric layer, in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer. The trap structure makes it possible to reduce the losses associated with the parasitic conduction effects at the interface between the support substrate and the dielectric layer. In particular, the trap layer inserted between the support substrate and the dielectric layer serves to reduce the lifetime of the charges in this region.
[0003]
[0003] However, it has been found that during heat treatments associated with the manufacture of the POI substrate or subsequent thereto, metallic elements of the piezoelectric layer, such as lithium, can diffuse through the dielectric layer and the trapping structure to the interface with the supporting substrate. The accumulation of these metallic elements reduces the performance quality of the trapping structure, thus adversely affecting the suppression of parasitic currents.
[0004]
[0004] It is possible to increase the thickness of the trapping layer to increase the number of available traps, but in this case parasitic modes are found in filters, sensors and other devices that use the POI substrate.
[0005]
[0005] Therefore, the object of the present invention is to increase the number of traps with less risk of parasitic effects. Summary of the Invention
[0006]
[0006] The object of the invention is achieved by a Piezoelectric-on-insulator (POI) substrate comprising a support substrate, in particular a silicon-based substrate, a piezoelectric layer, in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO), a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate, and a trapping structure sandwiched between the dielectric layer and the support substrate and comprising a first trapping layer based on polycrystalline silicon or amorphous silicon or porous silicon, preferably based on polycrystalline silicon, The POI substrate is characterized in that the trapping structure comprises a second trapping layer based on a different material.
[0007]
[0007] By adding a second trap layer having a different material within the trap structure, it is possible to increase the number of traps without having to increase the total thickness of the trap structure to the same extent as would be required with a single material trap structure.
[0008] According to one embodiment, the second trapping layer may be based on silicon carbide. A second layer based on silicon carbide allows for an efficient reduction of parasitic currents.
[0009] According to one embodiment, the second trapping layer based on silicon carbide may be thinner than the first layer, thus making it possible to increase the number of traps while at the same time limiting the appearance of parasitic modes due to the presence of the trapping structure, in particular compared to a monomaterial silicon-based trapping layer containing the same number of traps.
[0010] According to one embodiment, the second trapping layer based on silicon carbide may have a thickness of less than or equal to 500 nm, in particular less than or equal to 200 nm, more particularly less than or equal to 50 nm. Even at such a small thickness, the number of traps is sufficiently increased.
[0011] According to one embodiment, the first silicon-based trapping layer may have a thickness of 2 μm or less, in particular 1 μm or less. The use of the second trapping layer makes it possible to keep the thickness of the first trapping layer sufficiently small, so that parasitic modes due to this layer cannot occur or at least their contribution remains negligible.
[0012] According to one embodiment, the second trapping layer may be formed directly on the first trapping layer, thus maintaining a compact structure.
[0013] According to one embodiment, the first trapping layer is disposed between the support substrate and the second trapping layer, which allows the silicon carbide layer to be deposited at a lower temperature than the silicon layer, making it easier to form the trapping structure.
[0014] According to one embodiment, the trapping structure comprises only the first trapping layer and the second trapping layer.
[0015] According to one embodiment, the trapping structure is disposed directly on the substrate and the dielectric layer is disposed directly on the trapping structure.
[0016]
[0016] The object of the present invention is also achieved by a method for manufacturing the above-mentioned piezoelectric-on-insulator (POI) substrate, comprising the steps of providing a support substrate, in particular a silicon-based substrate, providing a substrate with a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), forming a trap structure above the support substrate, forming a dielectric layer, in particular a silicon oxide layer, above the substrate with the piezoelectric layer and / or above the trap structure, and assembling the piezoelectric substrate with the support substrate such that the dielectric layer and the trap structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the step of forming the trap structure comprises a step of forming a first layer based on polycrystalline silicon or amorphous silicon or porous silicon, preferably based on polycrystalline silicon, and a step of forming a second trap layer based on a different material.
[0017] According to an embodiment, the method for manufacturing a piezoelectric substrate may further comprise the steps of forming a weakened zone in the piezoelectric layer, in particular before the assembly step, and of fracturing along the weakened zone after the assembly step to separate a portion of the piezoelectric layer from the remaining portion of the substrate comprising the piezoelectric layer, in order to transfer the portion of the piezoelectric layer onto a support substrate, which method allows the industrial production of a POI substrate according to the invention.
[0018] The invention and its advantages will be described in more detail below by way of preferred and exemplary embodiments and with particular reference to the following accompanying drawings, in which reference numerals identify features of the invention, and in which: [Brief description of the drawings]
[0019] [Figure 1] 1 illustrates a schematic representation of a Piezoelectric-on-Insulator (POI) substrate according to a first embodiment of the present invention. [Diagram 2]
[0020] 5 illustrates diagrammatically a method for manufacturing a Piezoelectric-on-Insulator (POI) substrate according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0020]
[0021] It should be noted that the described embodiments are merely possible configurations, and that individual features as described above may be provided independently of one another or may be omitted entirely during the implementation of the present invention.
[0021]
[0022] FIG. 1 illustrates a schematic diagram of a piezoelectric-on-insulator (POI) substrate 100 according to a first embodiment of the present invention.
[0022]
[0023] The piezoelectric-on-insulator substrate 100 comprises a supporting substrate 102. In this first embodiment, the supporting substrate 102 is a silicon-based substrate, in particular a single crystal silicon wafer.
[0023]
[0024] The trapping structure 104 is disposed above the supporting substrate 102. The trapping structure 104 may be in direct contact with the supporting substrate 102. The trapping structure 104 has a thickness of 2 μm or less, preferably 1 μm or less, and even more preferably 600 nm or less.
[0024]
[0025] According to a first embodiment, the trapping structure 104 comprises two layers: a first trapping layer 104a and a second trapping layer 104b having a material different from that of the first trapping layer 104a.
[0025]
[0026] According to one variant, the trapping structure 104 comprises only a first trapping layer 104a and a second trapping layer 104b.
[0026]
[0027] The first trapping layer 104a is based on polycrystalline silicon, amorphous silicon or porous silicon. The second trapping layer 104b is based on silicon carbide (SiC). Preferably, these layers are deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP-CVD).
[0027]
[0028] In this embodiment, the two trapping layers 104a, 104b have different thicknesses. Preferably, the silicon-based trapping layer 104a has a thickness of 2 μm or less, in particular a thickness of 1 μm or less. The silicon carbide-based trapping layer 104b has a thickness of preferably 500 nm or less, in particular a thickness of 200 nm or less, more particularly a thickness of 50 nm or less. According to one embodiment of the invention, the first trapping layer 104a has a thickness of 500 nm and the second trapping layer 104b has a thickness of 50 nm.
[0028]
[0029] The dielectric layer 106 is arranged above, in particular directly above, the trapping structure 104. The dielectric layer 106 is preferably a silicon oxide based layer. The dielectric layer 106 preferably has a thickness of 100 nm to 1 μm, in particular 200 nm to 700 nm. The dielectric layer 106 can be formed by CVD deposition or any other suitable deposition process.
[0029]
[0030] The piezoelectric layer 108 is disposed above, and in particular directly above, the dielectric layer 106. The piezoelectric layer is preferably a layer of lithium tantalate (LTO) or lithium niobate (LNO). The piezoelectric layer 108 typically has a thickness of 200 nm to 1 μm.
[0030]
[0031] By using a trapping structure 104 having two trapping layers 104a, 104b of different materials, the number of traps can be increased without increasing the thickness of the trapping structure 104 excessively.
[0031]
[0032] Adding a second trapping layer 104b of a different, and in particular thinner, material allows the number of traps to be increased while keeping the thickness of the trapping structure small enough to limit the appearance of parasitic modes in the final device, such as a sensor, filter, etc.
[0032]
[0033] According to one variant, the order of the first trapping layer 104a and the second trapping layer 104b may be reversed: in this case, the second trapping layer based on silicon carbide is placed between the support substrate 102 and the first trapping layer 104a based on polycrystalline, amorphous or porous silicon.
[0033]
[0034] Fig. 2 shows a schematic diagram of a method for manufacturing a piezoelectric-on-insulator (POI) substrate according to a second embodiment of the invention, to obtain a POI substrate 100 according to the first embodiment described above in relation to Fig. 1. The reference numbers already used with reference to Fig. 1 in the context of the description of the POI substrate 100 are reused to describe the method of the second embodiment.
[0034]
[0035] The method for manufacturing a piezoelectric-on-insulator (POI) substrate 100 begins with step I) of providing a support substrate 102, in particular a silicon-based substrate, in particular a single crystal silicon wafer.
[0035]
[0036] According to this second embodiment of the invention, step II) comprises forming a trapping structure 104 on the free surface 120 of the support substrate 102 .
[0036]
[0037] The formation of the trapping structure 104 begins with the formation of a first trapping layer 104a produced by low pressure chemical vapor deposition (LPCVD). According to a variant, the first trapping layer 104a in step II) can be formed by thermal growth methods or by physical vapor deposition (PVD).
[0037]
[0038] The trapping layer 104a formed on the supporting substrate 102 is a layer based on polycrystalline silicon, amorphous silicon or porous silicon.
[0038]
[0039] The trap layer 104a has a thickness of 2 μm or less, and in particular 1 μm or less.
[0039]
[0040] Thereafter, a second trapping layer 104b is formed on the first trapping layer 104a. This second trapping layer 104b is based on silicon carbide. The second trapping layer 104b is formed to a thickness less than that of the first trapping layer, preferably less than 500 nm, in particular less than 200 nm, and more in particular less than 50 nm.
[0040]
[0041] The second trapping layer 104b is fabricated by low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP-CVD). According to a variant, the second trapping layer 104b can be formed during step II) by thermal growth or physical vapor deposition (PVD). Typically, the second trapping layer 104b is formed at a lower temperature than the first trapping layer 104a.
[0041]
[0042] Before the formation of the second trapping layer, one or more treatments of the surface of the first trapping layer 104a may be performed, such as polishing, in particular CMP type polishing, or activation of the surface by plasma or ozone treatment.
[0042]
[0043] During step III), a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104b. The dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).
[0043]
[0044] The dielectric layer 106a preferably has a thickness of 1 μm or less, and in particular a thickness of 700 nm or less.
[0044]
[0045] After depositing the dielectric layer 106a, a heat treatment may be performed to densify the dielectric layer 106a.
[0045]
[0046] During step IV), a substrate 124 is provided with a piezoelectric layer 126, in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO). The piezoelectric layer 124 is arranged above a base substrate 126 in this embodiment. In an alternative, the piezoelectric layer 126 is a bulk layer and forms the entire substrate 124.
[0046]
[0047] During step V), a second dielectric layer 106b, in particular a silicon oxide layer, is fabricated on the free surface 130 of the piezoelectric layer 126. This layer is fabricated in the same way as the dielectric layer 106a formed during step III). The thickness is chosen such that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 100 nm and 1 μm, in particular between 200 nm and 700 nm.
[0047]
[0048] According to a variant, one or more steps of surface treatment of the free surface 130 of the substrate 124 comprising the piezoelectric layer can be carried out before the formation of the dielectric layer 106b. For example, a surface activation treatment such as a plasma treatment and / or an ozone-based treatment can be carried out.
[0048]
[0049] During step VI), the substrate 124 obtained after step V) is assembled with the support substrate 102 obtained in step III) to form an assembly 132 of support substrate-substrate with piezoelectric layer.
[0049]
[0050] The assembly is performed so that the dielectric layers 106a and 106b are in direct contact with each other. The assembly is preferably performed by molecular adhesion.
[0050]
[0051] Once the two substrates are assembled, step VII) of thinning the assembly 132 is performed to obtain the POI substrate 100 with a thinner piezoelectric layer 108 as shown in FIG.
[0051]
[0052] For example, the thinning step can be performed by milling or by a step of forming a weakened zone in the piezoelectric layer 126 followed by fracturing before assembly step VI) so as to define the boundary of the piezoelectric layer 108 to be transferred onto the support substrate 102. This step of forming the weakened zone is performed by implanting atomic or ionic species in the piezoelectric layer 126. Atomic or ionic implantation can be performed so that the weakened zone is located inside the piezoelectric layer 126 and defines the boundary of the piezoelectric layer 108 to be transferred from the remaining part of the piezoelectric layer 126. Then, a step of fracturing the assembly 132 is subsequently performed by supplying thermal and / or mechanical energy to the weakened zone of the piezoelectric layer 126 in order to obtain a piezoelectric-on-insulator (POI) substrate 100.
[0052]
[0053] According to a variant, the bond between the support substrate 102 and the substrate 124 can also be performed between the trapping structure 104 and the dielectric layer 106b, i.e. without performing step III), or between the dielectric layer 106a and the piezoelectric layer 126.
[0053]
[0054] Prior to fabricating one or more of the above-mentioned layers, one or more steps of cleaning, brushing or polishing the underlying surface may be carried out to remove the presence of particles and dust.
Claims
1. a supporting substrate (102), in particular a silicon-based substrate; a piezoelectric layer (108), in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO), a dielectric layer (106), particularly a silicon oxide layer, sandwiched between the piezoelectric layer (108) and the support substrate (102); a trapping structure (104) sandwiched between said dielectric layer (106) and said support substrate (102) and comprising a first trapping layer (104a) based on polycrystalline silicon or amorphous silicon or porous silicon, preferably based on polycrystalline silicon, a Piezoelectric-on-Insulator (POI) substrate, the trapping structure (104) comprising a second trapping layer (104b) based on silicon carbide, A piezoelectric-on-insulator (POI) substrate, characterized in that the first trapping layer (104a) is disposed between the support substrate (102) and the second trapping layer (104b).
2. The piezoelectric-on-insulator (POI) substrate of claim 1 , wherein the second trapping layer (104b) is thinner than the first trapping layer (104a).
3. 3. A piezoelectric-on-insulator (POI) substrate according to claim 1 or 2, wherein the second trapping layer (104b) has a thickness of 500 nm or less, in particular a thickness of 200 nm or less, in particular a thickness of 50 nm or less.
4. 3. A piezoelectric-on-insulator (POI) substrate according to claim 1 or 2, wherein the first trapping layer has a thickness of 2 μm or less, in particular a thickness of 1 μm or less.
5. 3. The piezoelectric-on-insulator (POI) substrate of claim 1, wherein the second trapping layer (104b) is formed directly on the first trapping layer (104a).
6. The piezoelectric-on-insulator (POI) substrate of claim 1 or 2, wherein the trapping structure (104) comprises only the first trapping layer (104a) and the second trapping layer (104b).
7. providing a support substrate, in particular a silicon-based substrate; providing a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO); forming a trapping structure above the support substrate; forming a dielectric layer, in particular a silicon oxide layer, above the piezoelectric substrate and / or above the trapping structure; assembling the substrate comprising the piezoelectric layer with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate; 3. A method for manufacturing a piezoelectric-on-insulator (POI) substrate according to claim 1 or 2, wherein the step of forming the trapping structure comprises forming a first layer based on polycrystalline silicon or amorphous silicon or porous silicon, preferably based on polycrystalline silicon, on the support substrate, followed by forming a second trapping layer based on silicon carbide.
8. forming a weakened zone within the piezoelectric layer; 8. The method for manufacturing a piezoelectric substrate according to claim 7, further comprising the step of fracturing along the weakened zone to separate the portion of the piezoelectric layer from the remainder of the substrate comprising the piezoelectric layer after the assembling step, in order to transfer the portion of the piezoelectric layer onto the support substrate.