Display substrate, display panel and display device

Abstract

An embodiment of the present invention provides a display substrate, a display panel, and a display device, the display substrate including a base substrate, a plurality of first pixel circuits, a plurality of first light-emitting elements disposed on a side of the first pixel circuits away from the base substrate, at least one planar layer and at least one conductive layer located between the first pixel circuits and the first light-emitting elements, and a pixel definition layer disposed on a side of the first electrodes away from the base substrate, the first light-emitting elements including a first electrode, at least one of the first pixel circuits being electrically connected to the first electrodes of at least one of the first light-emitting elements through the conductive layer via a via hole penetrating the planar layer, the via hole including a first via hole contacting the first electrode, the pixel definition layer including an opening exposing the first electrode, and an orthogonal projection of the opening on the base substrate and an orthogonal projection of the first via hole on the base substrate do not overlap.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display substrate, a display panel and a display device. [Background technology]

[0002] With the rapid development of smartphones, mobile phones not only need to be beautiful in appearance, but also need to provide mobile phone users with a better visual experience. Major manufacturers have begun to increase the screen occupancy rate of smartphones, and full screen has become a new competitive point for smartphones. With the development of full screen, the requirements for improved performance and functionality are also increasing day by day. Under-screen cameras can have a certain impact on the visual and user experience without affecting the high screen occupancy rate. Summary of the Invention

[0003] An embodiment of the present invention provides a display substrate, a display panel, and a display device, the display substrate comprising: A base substrate; a plurality of first pixel circuits disposed on one side of the base substrate; A plurality of first light-emitting elements arranged on a side of a first pixel circuit away from the base substrate; at least one planar layer and at least one conductive layer disposed between the first pixel circuit and the first light emitting element; a pixel defining layer disposed on a side of the first electrode away from the base substrate; the first light emitting element includes a first electrode; the flat layer and the conductive layer are alternately arranged, and at least one of the first pixel circuits is electrically connected to the first electrode of at least one of the first light-emitting elements through the conductive layer via a via hole penetrating the flat layer, the via hole including a first via hole in contact with the first electrode; The pixel definition layer includes an opening exposing the first electrode, and an orthogonal projection of the opening on the base substrate and an orthogonal projection of the first via hole on the base substrate do not overlap.

[0004] In a possible implementation, the at least one planar layer includes a first planar layer and a second planar layer disposed on a side of the first planar layer facing the first pixel circuit, and the via holes include the first via hole penetrating the first planar layer and the second via hole penetrating the second planar layer; An orthogonal projection of the first via hole on the base substrate and an orthogonal projection of the second via hole on the base substrate have an overlapping area, and the first via hole and the second via hole form a first hole group.

[0005] In a possible implementation, the at least one planar layer further includes a third planar layer disposed between the first planar layer and the second planar layer, and a fourth planar layer disposed on a side of the second planar layer away from the third planar layer, and the via holes further include a third via hole penetrating the third planar layer and a fourth via hole penetrating the fourth planar layer; The orthogonal projection of the third via hole on the base substrate and the orthogonal projection of the fourth via hole on the base substrate have an overlapping area, the third via hole and the fourth via hole form a second hole group, and the first pixel circuit is electrically connected to the first electrode via the first hole group and the second hole group.

[0006] In a possible implementation, the at least one planar layer further includes a fifth planar layer disposed on a side of the fourth planar layer away from the second planar layer, and the via holes further include a fifth via hole penetrating the fifth planar layer; The orthogonal projection of the fifth via hole on the base substrate and the orthogonal projection of the first via hole on the base substrate have an overlapping area, and the first hole group further includes the fifth via hole.

[0007] In a possible implementation, the orthogonal projections of the second group of holes on the base substrate and the orthogonal projections of the first group of holes on the base substrate do not overlap.

[0008] In a possible implementation, the plurality of first light-emitting elements include element row groups sequentially arranged along a first direction, each of the element row groups including a first element row, a second element row, a third element row, and a fourth element row sequentially arranged along the first direction; the first element row and the third element row include first sub light-emitting elements and second sub light-emitting elements arranged alternately in a second direction, and the lights emitted by the first sub light-emitting elements and the second sub light-emitting elements are of different colors; the second element row and the fourth element row include third sub light-emitting elements and fourth sub light-emitting elements arranged alternately in a second direction, and the lights emitted by the third sub light-emitting elements and the fourth sub light-emitting elements are of the same color; In the same element row group, there is a first row gap between the first element row and the second element row, and a second row gap between the third element row and the fourth element row, the first hole group and the second hole group used for connecting each of the first light-emitting elements of the first element row, and the first hole group and the second hole group used for connecting each of the first light-emitting elements of the second element row are all located in the first row gap and are arranged along a direction parallel to the second direction, and the first hole group and the second hole group used for connecting each of the first light-emitting elements of the third element row, and the first hole group and the second hole group used for connecting each of the first light-emitting elements of the fourth element row are all located in the second row gap and are arranged along a direction parallel to the second direction.

[0009] In a possible implementation, in the first row gap, the spacing between the centers of at least two adjacent first hole groups in each of the first hole groups used to connect the first electrodes is different; In the second row gap, the spacing between the centers of at least two adjacent first holes in each of the first holes used to connect the first electrodes is different.

[0010] In a possible implementation, in the first row gap, a center-to-center spacing ratio of at least two adjacent second hole groups in each of the second hole groups used to connect the first electrodes is in the range of 0.8 to 1.2; In the second row gap, a center-to-center spacing ratio of at least two adjacent second hole groups in each of the second hole groups used to connect the first electrodes is in the range of 0.8 to 1.2.

[0011] In a possible implementation, the spacing between the centers of at least two adjacent first groups of holes in the first row gap is different from the spacing between the centers of at least two adjacent first groups of holes in the second row gap.

[0012] In a possible implementation, in the first row gap, the first group of holes used to connect the third sub-light-emitting element, the first group of holes used to connect the first sub-light-emitting element, the first group of holes used to connect the fourth sub-light-emitting element, and the first group of holes used to connect the second sub-light-emitting element are sequentially and periodically arranged along the second direction.

[0013] In a possible implementation, in one arrangement period of the first row gap, the second hole group of the third sub light emitting element is located on a side of the first hole group of the third sub light emitting element that is away from the first hole group of the first sub light emitting element, the second hole group of the first sub light emitting element is located between the first hole group of the first sub light emitting element and the first hole group of the third sub light emitting element; the second hole group of the fourth sub light emitting element is located between the first hole group of the first sub light emitting element and the first hole group of the fourth sub light emitting element; The second group of holes of the second sub light-emitting element are located on a side of the first group of holes of the second sub light-emitting element that is away from the first group of holes of the fourth sub light-emitting element.

[0014] In a possible implementation, in the second row gap, the first group of holes used to connect the third sub-light-emitting element, the first group of holes used to connect the first sub-light-emitting element, the first group of holes used to connect the fourth sub-light-emitting element, and the first group of holes used to connect the second sub-light-emitting element are sequentially and periodically arranged along the second direction.

[0015] In a possible implementation, in one arrangement period of the second row gap, the second hole group of the third sub light emitting element is located on a side of the first hole group of the third sub light emitting element that is away from the first hole group of the first sub light emitting element, the second hole group of the first sub light emitting element is located between the first hole group of the third sub light emitting element and the first hole group of the first sub light emitting element; the second hole group of the fourth sub light emitting element is located between the first hole group of the first sub light emitting element and the first hole group of the fourth sub light emitting element; The second group of holes of the second sub-light-emitting element are located between the first group of holes of the fourth sub-light-emitting element and the first group of holes of the second sub-light-emitting element.

[0016] In a possible implementation, the first electrodes of the first light-emitting elements include a first electrode unit row and a second electrode unit row arranged sequentially along the first direction, the first electrode unit row includes a plurality of first electrode units arranged sequentially along the second direction, and the second electrode unit row includes a plurality of second electrode units arranged sequentially along the second direction; Each of the first electrode unit and the second electrode unit includes the first sub-electrode, the second sub-electrode arranged along the first direction, and the third sub-electrode and the fourth sub-electrode arranged along the second direction.

[0017] In a possible implementation, the first electrode unit includes a first side parallel to a long side of the third sub-electrode and a second side parallel to a long side of the fourth sub-electrode; In the first electrode unit, the third sub-electrode includes a third sub-electrode body and a third sub-electrode transfer portion perpendicular to the first side extending from a side of the third sub-electrode body away from the second sub-electrode, and the orthogonal projection of the first hole group on the base substrate for connecting the third sub-light-emitting element and the orthogonal projection of the third sub-electrode transfer portion on the base substrate have an overlapping area.

[0018] In a possible implementation, in the first electrode unit, the fourth sub-electrode includes a fourth sub-electrode body and a fourth sub-electrode transfer portion extending from a side of the fourth sub-electrode body away from the second sub-electrode and perpendicular to the second side; The orthogonal projection of the first hole group on the base substrate for connecting the fourth sub light emitting element and the orthogonal projection of the fourth sub electrode transfer portion on the base substrate have an overlapping area.

[0019] In a possible implementation, the second electrode unit includes a third side parallel to a long side of the third sub-electrode and a fourth side parallel to a long side of the fourth sub-electrode; In the second electrode unit, the third sub-electrode includes a third sub-electrode main body and a third sub-electrode transfer portion perpendicular to the third side extending from a side of the third sub-electrode main body away from the second sub-electrode, and the orthogonal projection of the first hole group on the base substrate for connecting the third sub-light-emitting element and the orthogonal projection of the third sub-electrode transfer portion on the base substrate have an overlapping area.

[0020] In a possible implementation, in the second electrode unit, the first electrode of the fourth sub-electrode includes a fourth sub-electrode body and a fourth sub-electrode transfer portion extending from a side of the fourth sub-electrode body closer to the first sub-electrode and parallel to the fourth side; The orthogonal projection of the first hole group on the base substrate for connecting the fourth sub light emitting element and the orthogonal projection of the fourth sub electrode transfer portion on the base substrate have an overlapping area.

[0021] The display panel in the embodiment of the present invention includes a display substrate provided by an embodiment of the present invention.

[0022] A display device in an embodiment of the present invention includes a display panel provided by an embodiment of the present disclosure.

[0023] In a possible implementation, the display device further includes an optical module disposed in the first display area. [Brief description of the drawings]

[0024] [Figure 1] 1 is a plan view of a display substrate provided according to an embodiment of the present invention; [Diagram 2] 1 is a schematic cross-sectional view of a display substrate provided according to an embodiment of the present invention; [Diagram 3] 4 is a schematic cross-sectional view of another display substrate provided by an embodiment of the present invention. [Figure 4] 1 is a schematic diagram of a hole arrangement method of a light-emitting device provided by an embodiment of the present invention; [Diagram 5]5 is a partially enlarged schematic diagram of a first row gap in FIG. 4. FIG. [Figure 6] FIG. 2 is a schematic diagram of a hole arrangement method of a light-emitting device provided by an embodiment of the present invention. [Figure 7] 7 is a partially enlarged schematic view of a first electrode unit in FIG. 6. FIG. [Figure 8] 7 is a partially enlarged schematic view of the second electrode unit in FIG. 6. FIG. [Figure 9] FIG. 2 is a schematic structural diagram of a display device provided by an embodiment of the present invention; [Figure 10] FIG. 1 is a schematic diagram illustrating a configuration of a conventional display device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention are described below clearly and completely in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part, not all, of the embodiments of the present invention. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present invention.

[0026] Unless otherwise defined, technical or scientific terms used in the present invention shall have the ordinary meaning understood by those skilled in the art to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate order, quantity, or importance, but are used only to distinguish different components. Words such as "comprise" or "contain" mean that the element or thing appearing before the word includes the elements or things listed after the word and their equivalents, without excluding other elements or things. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. "Top", "bottom", "left", "right", etc. are only used to express relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may change accordingly.

[0027] As used herein, "about" or "substantially the same" means that the stated value is understood to be within an acceptable range of error (i.e., the limits of the measurement system) associated with the measurement in question and the measurement of the particular quantity. The meaning of the measurement is determined by one of ordinary skill in the art and is within the acceptable deviation range of the particular value determined. For example, "substantially the same" may mean that the difference from the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0028] In the drawings, thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments. Thus, deviations from the shapes of the illustrations are expected as a result, for example, of manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions depicted herein but are intended to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may typically have rough and / or non-linear features. Additionally, sharp corners as illustrated may be rounded. Thus, the regions depicted in the figures are schematic in nature and the shapes are not intended to illustrate the exact shape of the illustrated regions, and are not intended to limit the scope of the claims.

[0029] To keep the following description of the embodiments of the present invention clear and concise, the present invention omits detailed descriptions of well-known functions and components.

[0030] With the continuous development of full screen, following notch screen and waterdrop screen, blind hole screen and through hole screen have appeared in the past two years, which further improves the screen-to-body ratio. However, even through hole screen cannot realize true full screen because the image is not displayed above the camera. As shown in Figure 10, the first display area AA1 is used to set the camera, and the second display area AA2 is used to set the light emitting element P and the pixel circuit Q that drives the light emitting element P. However, the first display area AA1 is not provided with the light emitting element P and the pixel circuit Q. Currently, the most popular full screen technology is the under-screen camera, which uses a special driver design to display the image in the camera area and achieve high transmittance for the camera to take pictures.

[0031] Figure 1 shows the current under-screen camera technology. Only the light-emitting element is kept in the camera area, and the corresponding pixel circuit is placed outside the camera area. By compressing the size of the pixel circuit laterally to be smaller than the size of the light-emitting element, more additional pixel circuits can be placed outside the camera area to drive the light-emitting element in the camera area to realize display. To realize the electrical connection between the pixel circuit outside the camera area and the light-emitting element in the camera area and to ensure the photography effect by increasing the transmittance, it is preferable to use a transparent ITO layer.

[0032] Limited by process limitations of transparent trace size (pitch), currently three transparent conductive layers (e.g., indium tin oxide, ITO) are used to route the transparent traces, so three planar layer (PLN) holes are added to the pixel design. The compression of the pixel circuit and the addition of three PLN holes narrows the layout space, and if the PLN holes are placed in the area where the anode of the light-emitting element is located, the planarity of the anode will be deteriorated, causing problems. Issues such as color shift on line substrates and full-screen display substrates with under-screen cameras require special design considerations.

[0033] One embodiment of the present invention provides a display substrate as shown in Figures 1, 2, 3, and 4, where Figure 2 may be a partial cross-sectional schematic diagram of a second display area AA2 including a base substrate 1, a plurality of first pixel circuits Q1, a plurality of first light-emitting elements P1, and a pixel definition layer 4.

[0034] The base substrate 1 includes a first display area AA1 and a second display area AA2 located on at least one side of the first display area AA1. Here, the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2. Specifically, the first display area AA1 may be an area used to set an image acquisition component.

[0035] The plurality of first pixel circuits Q1 are located on one side of a base substrate 1, and specifically, the display substrate includes a driving circuit layer 2, and the driving circuit layer 2 includes a plurality of first pixel circuits Q1. The plurality of first pixel circuits Q1 may be arranged in a second display area AA2.

[0036] The plurality of first light-emitting elements P1 are located on a side of the first pixel circuit Q1 away from the base substrate 1, and the first light-emitting element P1 includes a first electrode Ano. The first electrode Ano can be an anode of the first light-emitting element P1. Specifically, the first light-emitting element P1 further includes a light-emitting layer (not shown) located on a side of the first electrode Ano away from the drive circuit layer 2, and a second electrode layer (not shown) located on a side of the light-emitting layer away from the drive circuit layer 2. The second electrode layer can be specifically a cathode layer. Specifically, the display substrate includes a light-emitting element layer 5 located on a side of the drive circuit layer 2 away from the base substrate. The plurality of first light-emitting elements P1 are located on the light-emitting element layer 5, and the light-emitting element layer 5 may include a plurality of second light-emitting elements P2 located in the first display area AA1, and a second pixel circuit Q2 located in the second display area AA2 and driving the second light-emitting element P2.

[0037] At least one flat layer 31 and at least one conductive layer 32 are located between the first pixel circuit Q1 and the first light-emitting element P1, and the flat layer 31 and the conductive layer 32 are alternately arranged. At least one first pixel circuit Q1 is electrically connected to the first electrode Ano of the at least one first light-emitting element P1 through the conductive layer 32 via a via hole penetrating the flat layer 31. The via hole includes a first via hole K1 that contacts the first electrode Ano. Specifically, the display substrate may further include at least one conductive structure layer 30. Each conductive structure layer 30 is located between the driving circuit layer 2 and the light-emitting element layer 5. Each conductive structure layer 30 further includes a flat layer 31 and a conductive layer 32 located on the side of the flat layer 31 away from the driving circuit layer.

[0038] The pixel definition layer 4 is located on the side of the first electrode Ano away from the base substrate 1, specifically, between the conductive structure layer 30 and the light emitting element layer 5. The pixel definition layer 4 includes an opening K3 that exposes the first electrode Ano. The orthogonal projection of the opening K3 on the base substrate 1 and the orthogonal projection of the first via hole K11 on the base substrate 1 do not overlap.

[0039] In the embodiment of the present invention, in the full-screen display substrate equipped with an optical module, the orthogonal projection of the opening K3 on the base substrate 1 exposing the first electrode Ano does not overlap with the orthogonal projection of the first via hole K11 on the base substrate 1 in contact with the first electrode Ano, so that it is prioritized to prevent the first via hole K11 in contact with the first electrode Ano from entering the region of the opening K3 of the pixel definition layer 4. In addition, the flatness of the first electrode Ano is ensured, and color shift is prevented.

[0040] In a particular embodiment, at least one conductive layer 32 may include a plurality of conductive lines L, and at least one second pixel circuit Q2 and at least one second light-emitting element P2 are electrically connected through the conductive lines L.

[0041] Optionally, the conductive line L may be a transparent conductive line. For example, the conductive line L may be formed of a transparent material such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO). Assuming that the conductive line L is made of an ITO material, the conductive line L can also be called an ITO trace. In the following embodiment, the conductive line L is taken as an ITO trace as an example for illustration.

[0042] In a specific embodiment, the second display area AA2 is provided with a plurality of first light-emitting elements P1 and a first pixel circuit Q1 for driving the first light-emitting elements P1. In a conventional display substrate, the pixel circuits (including the first pixel circuit Q1 and the second pixel circuit Q2) and the first light-emitting elements P1 have the same size (pitch). For example, the width is generally about 30 μm to 32 μm, and the length is generally about 60 μm to 65 μm. In the embodiment of the present invention, in order to secure a sufficient space for arranging the second pixel circuits Q2 without reducing the number of pixels in the first display area AA1, each pixel circuit is compressed along the pixel row direction, so that the width of the pixel circuit in the pixel row direction is smaller than the width of the first light-emitting element P1. In this way, on the condition that the size of the base substrate 1 is the same, more areas can be present in the second display area AA2, and accordingly, the second pixel circuits Q2 dedicated to driving the second light-emitting elements P2 arranged in the first display area AA1 can be provided in the more areas.

[0043] For example, the width of each pixel circuit and the width of the first light-emitting element P1 may differ by about 4 μm. Taking a compressed pixel circuit with a width difference of 4 μm as an example, specifically, for example, the size of the pixel circuit and the light-emitting element before compression is 1 to 100 μm in width parallel to the pixel row direction and 2 to 200 μm in height perpendicular to the pixel row direction, and after compression, the size of the light-emitting element does not change, the height of the pixel circuit does not change, but the width decreases by 1 to 20 μm. Therefore, compression is performed by compressing the pixel circuits every few columns, and one or more columns of compressed pixel circuits are added, and the entire screen uses this design to achieve full-screen compression. Here, these added multiple columns can be selected to drive the second light-emitting element P2 in the first display area AA1 and control the emission of the second light-emitting element P2. In some embodiments, it is preferable that the pixel circuits of the added columns close to the periphery of the first display area AA1 are connected to the second light-emitting element P2 as the second pixel circuit Q2. This makes it possible to ensure normal display without changing the resolution of the display panel. In other words, it is possible to maximize the use of the existing space of the display panel to achieve normal display. Specifically, the width of the pixel circuit refers to the length of the layout of the pixel circuit on the base substrate 1 when projected in a direction parallel to the pixel row. The width of the second light-emitting element P2 refers to the length of the anode of the first light-emitting element P1 when projected in a direction parallel to the pixel row on the base substrate 1.

[0044] In a possible implementation, as shown in FIG. 2, the at least one flat layer 31 may include a first flat layer 311 and a second flat layer 312 located on the side of the first flat layer 311 facing the first pixel circuit Q1 (i.e., the driving circuit layer 2). The via holes include a first via K11 penetrating the first flat layer 311 and a second via K12 penetrating the second flat layer 312. The orthogonal projection of the first via hole K11 on the base substrate 1 and the orthogonal projection of the second via hole K12 on the base substrate 1 have an overlapping area. The first via hole K11 and the second via hole K12 form a first hole group K1. Specifically, the center of the orthogonal projection of the first via hole K11 on the base substrate 1 overlaps with the center of the orthogonal projection of the second via hole K12 on the base substrate 1. The first hole group K1 may be a set hole. Specifically, the size of the orthogonal projection of the first via hole K11 on the base substrate 1 is substantially the same as the size of the orthogonal projection of the second via hole K12 on the base substrate 1, and the ratio between the two is 0.8 to 1.2. The length of the orthogonal projection of the first via hole K11 on the base substrate 1 in a direction parallel to the first light-emitting element P1 row is 3.0 μm to 3.5 μm, and specifically, for example, can be 3.3 μm. The width in a direction perpendicular to the first light-emitting element P1 row is 2.5 μm to 3.0 μm, and specifically, for example, can be 2.8 μm. Specifically, the length of the orthogonal projection of the second via hole K12 on the base substrate 1 in a direction parallel to the first light-emitting element P1 row can be 3.0 μm to 3.5 μm, and specifically, for example, can be 3.3 μm. The width in the direction perpendicular to the row of the first light-emitting element P1 can be 2.5 μm to 3.0 μm, and specifically, for example, 2.8 μm. Specifically, the inclination angle of the first via hole K11 may be substantially the same as or different from the inclination angle of the second via hole K12. Specifically, the inclination angle α1 of the first via hole K11 is 40 o ~70 o Specifically, the range can be, for example, 50 o The inclination angle α2 of the second via hole K12 may be 40 o ~70 o Specifically, the range can be, for example, 50 omay be also possible.

[0045] In a possible implementation, as shown in FIG. 2, the at least one planar layer 31 further includes a third planar layer 313 located between the first planar layer 311 and the second planar layer 312, and a fourth planar layer 314 located on the side of the second planar layer 312 away from the third planar layer 313. The via holes further include a third via hole K21 penetrating the third planar layer 313 and a fourth via hole K22 penetrating the fourth planar layer 314. The orthogonal projection of the third via hole K21 on the base substrate 1 and the orthogonal projection of the fourth via hole K22 on the base substrate 1 have an overlapping area. The third via hole K21 and the fourth via hole K22 form a second hole group K2. The first pixel circuit Q1 and the first electrode Ano are specifically electrically connected via the first hole group K1 and the second hole group K2. Specifically, the center of the orthogonal projection of the third via hole K21 on the base substrate 1 overlaps with the center of the orthogonal projection of the fourth via hole K22 on the base substrate 1. The second hole group K2 may be a set hole. Specifically, the size of the orthogonal projection of the third via hole K21 on the base substrate 1 may be smaller than the size of the orthogonal projection of the fourth via hole K22 on the base substrate 1. The length of the orthogonal projection of the third via hole K21 on the base substrate 1 in a direction parallel to the first light-emitting element P1 row is 3.0 μm to 3.5 μm, and specifically, for example, can be 3.3 μm. The width in a direction perpendicular to the first light-emitting element P1 row can be 2.5 μm to 3.0 μm, and specifically, for example, can be 2.8 μm. Specifically, the length of the orthogonal projection of the fourth via hole K22 on the base substrate 1 in a direction parallel to the first light-emitting element P1 row can be 3.5 μm to 4.0 μm, specifically, for example, 3.8 μm. The width in a direction perpendicular to the first light-emitting element P1 row can be 2.5 μm to 3.0 μm, specifically, for example, 2.8 μm. Specifically, the inclination angle of the third via hole K21 may be substantially the same as or different from the inclination angle of the fourth via hole K22. Specifically, the inclination angle α3 of the third via hole K21 is 40 o ~70 oSpecifically, the range can be, for example, 50 o The inclination angle α4 of the fourth via hole K22 is 40 o ~70 o Specifically, the range can be, for example, 50 o It can be said that:

[0046] In a possible implementation, as shown in FIG. 3, the at least one flat layer 31 further includes a fifth flat layer 315 located on the side of the fourth flat layer 314 away from the second flat layer 312. The via holes further include a fifth via hole K13 penetrating the fifth flat layer 315. The orthogonal projection of the fifth via hole K13 on the base substrate 1 and the orthogonal projection of the first via hole K11 on the base substrate 1 have an overlapping area. The first hole group K1 further includes a fifth via hole K13. Specifically, the center of the orthogonal projection of the fifth via hole K13 on the base substrate 1 overlaps with the center of the orthogonal projection of the first via hole K11 on the base substrate 1. Specifically, the size of the orthogonal projection of the second via hole K12 on the base substrate 1 may be smaller than the size of the orthogonal projection of the fifth via hole K13 on the base substrate 1. The length of the fifth via hole K13 on the base substrate 1 in the direction parallel to the first light emitting element P1 row may be 3.5 μm to 4.0 μm, specifically, for example, 3.8 μm. The width in the direction perpendicular to the first light emitting element P1 row may be 2.5 μm to 3.0 μm, specifically, for example, 2.8 μm. In the embodiment of the present invention, when the display substrate further includes a fifth flat layer 315, the fifth conductive layer 325 between the fifth flat layer 315 and the fourth flat layer 314 may be a metal layer. The fifth conductive layer 325 may specifically be a second source drain layer SD2 in the driving circuit layer. Specifically, the driving circuit layer 2 further includes a first source drain layer SD1 located on the side of the second source drain layer SD2 facing the base substrate 1.

[0047] In a possible implementation, the orthogonal projection of the second group of holes K2 on the base substrate 1 does not overlap with the orthogonal projection of the first group of holes K1 on the base substrate 1, as shown in FIGS.

[0048] In a possible implementation, as shown in FIG. 4, the plurality of first light-emitting elements P1 include a group of element rows S arranged in sequence along a first direction X. Each group of element rows includes a first element row S1, a second element row S2, a third element row S3, and a fourth element row S4 arranged in sequence along the first direction. The first element row S1 and the third element row S3 include a first sub-light-emitting element P11 and a second sub-light-emitting element P12 arranged in sequence and alternating along a second direction Y. The first sub-light-emitting element P11 and the second sub-light-emitting element P12 have different emission colors. The second element row S2 and the fourth element row S4 include a third sub-light-emitting element P13 and a fourth sub-light-emitting element P14 arranged in sequence and alternating along the second direction Y, and the emission colors of the third sub-light-emitting element P13 and the fourth sub-light-emitting element P14 are the same. Specifically, the first sub-light emitting element P11 may be a red light emitting element that emits red light, and the second sub-light emitting element P12 may be a blue light emitting element that emits blue light. The third sub-light emitting element P13 and the fourth sub-light emitting element P14 are green light emitting elements that emit green light. In the same element row group S, there is a first row gap H1 between the first element row S1 and the second element row S2, and there is a second row gap H2 between the third element row S3 and the fourth element row S4. The first hole group K1 and the second hole group K2 used to connect each first light emitting element P1 in the first element row S1, and the first hole group K1 and the second hole group K2 used to connect each first light emitting element P1 in the second element row S2 are all located in the first row gap H1 and are arranged parallel to the second direction Y. The first hole group K1 and the second hole group K2 used to connect each of the first light-emitting elements P1 in the third element row S3, and the first hole group K1 and the second hole group K2 used to connect each of the first light-emitting elements P1 in the fourth element row S4 are all located in the second row gap H2 and are arranged parallel to the second direction Y.

[0049] The light-emitting area of ​​the first light-emitting element P1 generally coincides with the area where the first electrode Ano is exposed by the pixel definition layer opening K3, so in FIG. 4 and FIG. 5, the first electrode Ano is exposed by the pixel definition layer opening K3. Although these areas indicate the corresponding light-emitting element, the embodiment of the present invention is not limited thereto in a specific implementation, and the light-emitting element can also include multiple other film layers. For example, it may include a light-emitting layer, a second electrode layer, etc. All the following embodiments are described by taking the area where the first electrode Ano is located to display the corresponding light-emitting element as an example.

[0050] As shown in relation to FIG. 4 and FIG. 5, FIG. 5 is a partial enlarged view of the first row gap H1 in FIG. 4. In each first hole group K1 used to connect the first electrode Ano, the interval between the centers of at least two adjacent first hole groups K1 is different. In the second row gap H2, in each first hole group K1 used to connect the first electrode Ano, the interval between the centers of at least two adjacent first hole groups K1 is different. Specifically, for example, referring to FIG. 5, in the first row gap H1, the interval between the center of the first hole group K1 of the third sub light-emitting element P13 and the center of the first hole group K1 of the first sub light-emitting element P11 is d5, which is different from the interval d6 between the center of the first hole group K1 of the first sub light-emitting element P11 and the center of the first hole group K1 of the fourth sub light-emitting element P14. The distance d6 between the center of the first hole group K1 of the first sub light-emitting element P11 and the center of the first hole group K1 of the fourth sub light-emitting element P14 is different from the distance d7 between the center of the first hole group K1 of the fourth sub light-emitting element P14 and the center of the first hole group K1 of the second sub light-emitting element P12. The distance d7 between the center of the first hole group K1 of the fourth sub light-emitting element P14 and the center of the first hole group K1 of the second sub light-emitting element P12 is different from the distance d8 between the center of the first hole group K1 of the second sub light-emitting element P12 and the center of the first hole group K1 of the third sub light-emitting element P13. In an embodiment of the present invention, the distance between the centers of at least two adjacent first hole groups K1 in each first hole group K1 used to connect the first electrode Ano is different. In the second row gap H2, the distance between the centers of at least two adjacent first hole groups K1 in each first hole group K1 used to connect the first electrode Ano is different. It is preferable to ensure that the first via hole K11 in contact with the first electrode Ano does not enter the area of ​​the opening K3 of the pixel definition layer 4.

[0051] Of course, in certain embodiments, in each first hole group K1 used to connect the first electrodes Ano in the first row gap H1, the spacing between the centers of some or all of the two adjacent first hole groups K1 may be the same. In each first hole group K1 used to connect the first electrodes Ano in the second row gap H2, the spacing between the centers of some or all of the two adjacent first hole groups K1 may be the same. That is, d5, d6, d7, d8 may be partially or completely the same.

[0052] In a possible implementation, in the first row gap H1, the range of the center-to-center spacing ratio of at least two adjacent second hole groups K2 in each second hole group K2 used to connect the first electrode Ano may be 0.8-1.2. The two may be substantially the same. In the second row gap H2, the range of the center-to-center spacing ratio of at least two adjacent second hole groups K2 in each second hole group K2 used to connect the first electrode Ano may be 0.8-1.2. The two may be substantially the same. Specifically, for example, in the first row gap H1, the spacing d1 between the center of the second hole group K2 of the third sub-light-emitting element P13 and the center of the second hole group K2 of the first sub-light-emitting element P11 is substantially the same as the spacing d3 between the center of the second hole group K2 of the fourth sub-light-emitting element P14 and the center of the second hole group K2 of the second sub-light-emitting element P12. The distance d3 between the center of the second hole group K2 of the fourth sub-light-emitting element P14 and the center of the second hole group K2 of the second sub-light-emitting element P12 is substantially the same as the distance d4 between the center of the second hole group K2 of the second sub-light-emitting element P12 and the center of the second hole group K2 of the third sub-light-emitting element P13. In an embodiment of the present invention, in the first row gap H1, the distance between the centers of at least two adjacent second hole groups K2 in each second hole group K2 used to connect the first electrode Ano is substantially the same. In the second row gap H2, the distance between the centers of at least two adjacent second hole groups K2 in each second hole group K2 used to connect the first electrode Ano is substantially the same, which may be advantageous for horizontal signal traces and / or vertical signal traces conductive lines L, gate lines, data lines, etc. In addition, since the flat layer 31 is provided on the side of the second hole group K2 away from the drive circuit layer 2, even if the second hole group K2 is placed in the region of the opening K3 of the pixel definition layer 4, it does not significantly affect the flatness of the first electrode Ano and does not cause the problem of color shift.

[0053] Of course, in certain embodiments, in each second hole group K2 used to connect the first electrodes Ano in the first row gap H1, the spacing between the centers of some or all of the two adjacent second hole groups K2 may also be different. In each second hole group K2 used to connect the first electrodes Ano in the second row gap H2, the spacing between the centers of some or all of the two adjacent second hole groups K2 may also be different. That is, d1, d2, d3, d4 may not be the same.

[0054] In a possible implementation, the spacing between the centers of at least two adjacent first hole groups K1 in the first row gap H1 is different from the spacing between the centers of at least two adjacent first hole groups K1 in the second row gap H2, as shown in Figure 4 or Figure 5. Specifically, for example, as shown in Figure 4, it is preferable that d7, d8, d9, d10, d11, d12, d13, d14 are not identical, ensuring that the first hole groups K1 do not enter the area where the openings K3 of the pixel definition layer 4 are located.

[0055] In a possible implementation form, as shown in FIG. 4, in the first row gap H1, a first hole group K1 for connecting the third sub-light-emitting element P13, a first hole group K1 for connecting the first sub-light-emitting element P11, a first hole group K1 for connecting the fourth sub-light-emitting element P14, and a first hole group K2 for connecting the second sub-light-emitting element P12 are arranged sequentially and periodically along the second direction Y.

[0056] In a possible implementation, as shown in FIGS. 4 and 5, in one arrangement period of the first row gap H1, The second hole group K2 of the third sub-light-emitting element P13 (i.e., the second hole group K2 on the left side of the third sub-light-emitting element P13 in Figure 4 or Figure 5) is located on the side of the first hole group K1 of the third sub-light-emitting element P13 (i.e., the first hole group K1 located in the area where the anode of the third sub-light-emitting element P13 is located in Figure 4 or Figure 5) away from the first hole group K1 of the first sub-light-emitting element P11 (i.e., the first hole group K1 located in the area where the anode of the first sub-light-emitting element P11 is located in Figure 4 or Figure 5).

[0057] The second hole group K2 of the first sub-light-emitting element P11 (i.e., the second hole group K2 closest to the left side of the first hole group K1 of the first sub-light-emitting element P11 in Figure 4 or Figure 5) is located between the first hole group K1 of the first sub-light-emitting element P11 and the first hole group K1 of the third sub-light-emitting element P13 (i.e., the first hole group K1 located in the area where the anode of the third sub-light-emitting element P13 is located in Figure 4 or Figure 5).

[0058] The second hole group K2 of the fourth sub-light-emitting element P14 (i.e., the second hole group K2 closest to the left side of the first hole group K1 of the fourth sub-light-emitting element P14 in Figure 4 or Figure 5) is located between the first hole group K1 of the first sub-light-emitting element P11 and the first hole group K1 of the fourth sub-light-emitting element P14 (i.e., the first hole group K1 located in the area where the anode of the fourth sub-light-emitting element P14 is located in Figure 4 or Figure 5).

[0059] The second hole group K2 of the second sub-light-emitting element P12 (i.e., the second hole group K2 closest to the right side of the first hole group K1 of the second sub-light-emitting element P12 in Figure 4 or Figure 5) is located on the side of the first hole group K1 of the second sub-light-emitting element P12 (i.e., the first hole group K1 located in the area where the anode of the second sub-light-emitting element P12 is located in Figure 4 or Figure 5) away from the first hole group K1 of the fourth sub-light-emitting element P14.

[0060] In a possible implementation form, as shown in FIG. 4, in the second row gap H2, the first hole group K1 for connecting the third sub-light-emitting element P13, the first hole group K1 for connecting the first sub-light-emitting element P11, the first hole group K1 for connecting the fourth sub-light-emitting element P14, and the first hole group K1 for connecting the second sub-light-emitting element P12 are arranged sequentially and periodically along the second direction Y.

[0061] In a possible implementation, as shown in FIG. 4, in one arrangement period of the second row gap H2, the second hole group K2 of the third sub-light-emitting element P13 is located on the side of the first hole group K1 of the third sub-light-emitting element P13 away from the first hole group K1 of the first sub-light-emitting element P11.

[0062] The second hole group K2 of the first sub-light-emitting element P11 is located between the first hole group K1 of the third sub-light-emitting element P13 and the first hole group K1 of the first sub-light-emitting element P11.

[0063] The second hole group K2 of the fourth sub-light-emitting element P14 is located between the first hole group K1 of the first sub-light-emitting element P11 and the first hole group K1 of the fourth sub-light-emitting element P14.

[0064] The second hole group K2 of the second sub-light-emitting element P12 is located between the first hole group K1 of the fourth sub-light-emitting element P14 and the first hole group K1 of the second sub-light-emitting element P12.

[0065] In a possible implementation, the first row gap H1 and / or the second row gap H2 further includes a third hole group K4, which is used to connect the second light-emitting element P2 arranged in the first display area AA1 to the second display area AA2 via the conductive line L and connect the conductive line L to the source-drain layer of the second pixel circuit Q2.

[0066] In a possible implementation, as shown in relation to Figures 6-8, where Figure 7 is an enlarged schematic view of the first electrode unit of Figure 6; Figure 8 is an enlarged schematic view of the second electrode unit of Figure 6; The light-emitting element layer includes a first electrode unit row and a second electrode unit row arranged sequentially along a first direction; The first electrode unit row includes a plurality of first electrode units F1 arranged sequentially along a second direction Y, and the second electrode unit row includes a plurality of second electrode units F2 arranged sequentially along the second direction Y; The first electrode units F1 of the adjacent first electrode unit row and the second electrode units F2 of the adjacent second electrode unit row are arranged side by side in a staggered manner.

[0067] The first electrode unit F1 and the second electrode unit F2 each include a first sub-electrode Ano1, a second sub-electrode Ano2, and a third sub-electrode Ano3 and a fourth sub-electrode Ano4 arranged along a first direction X, and a second direction Y, respectively.

[0068] Specifically, the orthogonal projection shape of the third sub-electrode Ano3 on the base substrate 1 is rectangular, and the orthogonal projection shape of the fourth sub-electrode Ano4 on the base substrate 1 is rectangular. In a possible implementation, as shown in FIG. 6 and FIG. 7, the first electrode unit F1 includes a first side F11 parallel to the long side of the third sub-electrode Ano3 and a second side F12 parallel to the long side of the fourth sub-electrode Ano3. In the first electrode unit F1, the third sub-electrode Ano3 includes a third sub-electrode body A31 and a third sub-electrode transfer portion A32 perpendicular to the first side F11, which extends from the side of the third sub-electrode body A31 away from the second sub-electrode Ano2. The orthogonal projection of the first hole group K1 for connecting the third sub light-emitting element P13 onto the base substrate 1 and the orthogonal projection of the third sub-electrode transfer portion A32 onto the base substrate 1 have an overlapping region.

[0069] 6 and 7, in the first electrode unit F1, the fourth sub-electrode Ano4 includes a fourth sub-electrode body A41 and a fourth sub-electrode transfer portion A42 extending from the side of the fourth sub-electrode body A41 away from the second sub-electrode Ano2 and perpendicular to the second side F12. The orthogonal projection onto the base substrate 1 of the first hole group K1 for connecting the fourth sub light-emitting element P14 and the orthogonal projection onto the base substrate 1 of the fourth sub-electrode transfer portion A42 have an overlapping region.

[0070] In a possible implementation, as shown in Figures 6 and 8, the second electrode unit F2 includes a third side F21 parallel to the long side of the third sub-electrode Ano3 and a fourth side F22 parallel to the long side of the fourth sub-electrode Ano3. In the second electrode unit F2, the third sub-electrode Ano3 includes a third sub-electrode body B31 and a third sub-electrode transfer portion B32 perpendicular to the third side F21, which extends from the side of the third sub-electrode body B31 away from the second sub-electrode Ano2. The orthogonal projection of the first hole group K1 for connecting the third sub light-emitting element P13 onto the base substrate 1 and the orthogonal projection of the third sub-electrode transfer portion B32 onto the base substrate 1 have an overlapping region.

[0071] 6 and 8, in the second electrode unit F2, the fourth sub-electrode Ano4 includes a fourth sub-electrode body B41 and a fourth sub-electrode transfer portion B42 extending from a side of the fourth sub-electrode body B41 closer to the first sub-electrode Ano1 and parallel to the fourth side F22. The orthogonal projection of the first hole group K1 for connecting the fourth sub light-emitting element P14 onto the base substrate 1 and the orthogonal projection of the base substrate 1 onto the fourth sub-electrode transfer portion B42 have an overlapping region.

[0072] In a possible implementation, as shown in Figures 4 to 8, some of the via holes corresponding to first electrodes Ano adjacent in the row direction are provided between the two first electrodes Ano, and some of the via holes corresponding to first electrodes Ano adjacent in the row direction are provided on the same side of the two first electrodes Ano, and some of them are on the opposite side.

[0073] In a possible implementation, as shown in FIG. 4 to FIG. 8, the distance between a part of a via hole corresponding to a first electrode Ano and an opening of a pixel definition layer of a subpixel in which the first electrode Ano is located is greater than the distance between the via hole and an adjacent opening. The distance between a part of a via hole corresponding to a first electrode Ano and an opening of a pixel definition layer of a subpixel in which the first electrode Ano is located is smaller than the distance between the via hole and an adjacent opening. In a possible implementation, each of the first hole groups K1 and the second hole groups K2 can be aligned in the row direction. In another possible implementation, each of the first hole groups K1 and the second hole groups K2 may not be aligned in the row direction. In another possible implementation, each of the first hole groups K1 and the second hole groups K2 may be partially aligned and partially not aligned in the row direction.

[0074] In one possible implementation, holes on the same layer may be aligned but via holes on different layers may not be aligned, and conversely, in another possible implementation, holes on the same layer may not be aligned and via holes on different layers may not be aligned.

[0075] In a possible implementation, the opening is provided with at least one via hole on the left and right side parallel to the row direction of the first light emitting element to prevent the sides from being too tilted.

[0076] In a specific embodiment, in a possible implementation form, each first light-emitting element P1 located in the same row as the second light-emitting element P2 in the second display area AA2 may have a hole arrangement as shown in Figures 2 to 8.

[0077] Based on the same inventive idea, an embodiment of the present invention also provides a display panel, which includes the display substrate provided in the embodiment of the present invention.

[0078] Based on the same inventive idea, the embodiment of the present invention also provides a display device including the display panel provided in the embodiment of the present invention. The display panel may be an organic electroluminescent display panel (OLED), a quantum dot light-emitting display panel (QLED), or a microluminescent diode display panel (Micro LED). The principle by which the display panel solves the problem is similar to the principle by which the above-mentioned display substrate solves the problem, so the implementation of the display panel provided by the embodiment of the present invention can refer to the implementation of the above-mentioned display substrate, and detailed description will not be repeated.

[0079] In a possible implementation, as shown in Fig. 9, the display device further includes an optical module disposed in the first display area AA1. Specifically, the optical module may be a camera module C or another optical module, etc. The principle by which the display device solves the problem is similar to the principle by which the display substrate solves the problem described above, so that the implementation of the display device provided by the implementation of the present invention can refer to the implementation of the display substrate described above, and detailed description will not be repeated.

[0080] Specifically, the camera module C can be directly disposed in the first display area AA1, without needing to dig additional holes in the display panel, which provides a solid foundation for realizing a full-screen display panel.

[0081] Optionally, the first display area AA1 may be rectangular, and the area of ​​the orthogonal projection of the camera module C on the base substrate 1 may be equal to or smaller than the area of ​​the inscribed circle of the first display area AA1. That is, the size of the area where the camera module C is located may be equal to or smaller than the size of the inscribed circle of the first display area AA1. For example, referring to FIG. 9, in the display device shown in the figure, the size of the area where the camera module C is located is equal to the size of the inscribed circle of the first display area AA1. That is, the shape of the area where the camera module C is located may be circular, and accordingly, the area where the camera module C is located may also be called a light-transmitting hole. Of course, in some embodiments, the first display area AA1 may be a shape other than a rectangle, such as a circle or an ellipse.

[0082] In some embodiments, the display device may be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or other products or components with a display function. The display device may include, but is not limited to, a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, a power supply, and other components. Those skilled in the art can understand that the above-mentioned structure of the display device does not limit the display device, and the display device may include more or less of the above components, may combine certain components, or may have different components arranged.

[0083] Although the preferred embodiments of the present invention have been described, those skilled in the art can make further changes and modifications to these embodiments when the basic inventive concept is obvious. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiments and all changes and modifications within the scope of the present invention.

[0084] It is obvious that a person skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and modifications in the embodiments of the present invention fall within the scope of the claims of the present invention and the scope of equivalent techniques, the present invention also includes these modifications and modifications.

Claims

1. A display substrate, A base substrate; a plurality of first pixel circuits disposed on one side of the base substrate; a plurality of first light-emitting elements arranged on a side of the first pixel circuit away from the base substrate; the first light emitting element includes a first electrode; at least one planar layer and at least one conductive layer disposed between the first pixel circuit and the first light emitting element; a pixel defining layer disposed on a side of the first electrode away from the base substrate; the first light emitting element includes the first electrode; the flat layer and the conductive layer are alternately arranged, and at least one of the first pixel circuits is electrically connected to the first electrode of at least one of the first light-emitting elements through the conductive layer via a via hole penetrating the flat layer, the via hole including a first via hole in contact with the first electrode; the pixel definition layer includes an opening exposing the first electrode, and an orthogonal projection of the opening on the base substrate and an orthogonal projection of the first via hole on the base substrate do not overlap.

2. the at least one planar layer includes a first planar layer and a second planar layer disposed on a side of the first planar layer facing the first pixel circuit, the via hole includes the first via hole penetrating the first planar layer and a second via hole penetrating the second planar layer; The display substrate of claim 1 , wherein an orthogonal projection of the first via hole on the base substrate and an orthogonal projection of the second via hole on the base substrate have an overlapping area, and the first via hole and the second via hole form a first hole group.

3. the at least one planar layer further includes a third planar layer disposed between the first planar layer and the second planar layer, and a fourth planar layer disposed on a side of the second planar layer away from the third planar layer, and the via hole further includes a third via hole penetrating the third planar layer and a fourth via hole penetrating the fourth planar layer; 3. The display substrate of claim 2, wherein an orthogonal projection of the third via hole on the base substrate and an orthogonal projection of the fourth via hole on the base substrate have an overlapping area, the third via hole and the fourth via hole form a second hole group, and the first pixel circuit is electrically connected to the first electrode via the first hole group and the second hole group.

4. the at least one planar layer further includes a fifth planar layer disposed on a side of the fourth planar layer away from the second planar layer, and the via hole further includes a fifth via hole penetrating the fifth planar layer; The display substrate of claim 3 , wherein an orthogonal projection of the fifth via hole on the base substrate and an orthogonal projection of the first via hole on the base substrate have an overlapping area, and the first group of holes further includes the fifth via hole.

5. The display substrate according to claim 3 , wherein an orthogonal projection of the second group of holes on the base substrate and an orthogonal projection of the first group of holes on the base substrate do not overlap.

6. the plurality of first light-emitting elements include element row groups sequentially arranged along a first direction, each of the element row groups including a first element row, a second element row, a third element row and a fourth element row sequentially arranged along the first direction; the first element row and the third element row include first sub-light-emitting elements and second sub-light-emitting elements arranged alternately in a second direction, and lights emitted by the first sub-light-emitting elements and the second sub-light-emitting elements have different colors; the second element row and the fourth element row include third sub-light-emitting elements and fourth sub-light-emitting elements arranged alternately in a second direction, and lights emitted by the third sub-light-emitting elements and the fourth sub-light-emitting elements have the same color; 6. The display substrate according to claim 3, wherein in the same element row group, there is a first row gap between the first element row and the second element row, and a second row gap between the third element row and the fourth element row, the first hole group and the second hole group used for connecting each of the first light-emitting elements of the first element row, and the first hole group and the second hole group used for connecting each of the first light-emitting elements of the second element row are all located in the first row gap and are arranged along a direction parallel to the second direction, and the first hole group and the second hole group used for connecting each of the first light-emitting elements of the third element row, and the first hole group and the second hole group used for connecting each of the first light-emitting elements of the fourth element row are all located in the second row gap and are arranged along a direction parallel to the second direction.

7. In the first row gap, the spacing between the centers of at least two adjacent first hole groups in each of the first hole groups used to connect the first electrodes is different; 7. The display substrate of claim 6, wherein in the second row gap, the spacing between the centers of at least two adjacent first holes in each of the first holes used to connect the first electrodes is different.

8. In the first row gap, a center-to-center spacing ratio of at least two adjacent second hole groups in each of the second hole groups used to connect the first electrodes is in the range of 0.8 to 1.2; 8. The display substrate of claim 6, wherein in the second row gap, a center-to-center spacing ratio of at least two adjacent second hole groups in each of the second hole groups used to connect the first electrodes is in the range of 0.8 to 1.

2.

9. 9. The display substrate of claim 6, wherein a spacing between the centers of at least two adjacent first hole groups in the first row gap is different from a spacing between the centers of at least two adjacent first hole groups in the second row gap.

10. 10. The display substrate of claim 6, wherein in the first row gap, the first hole group used to connect the third sub-light-emitting element, the first hole group used to connect the first sub-light-emitting element, the first hole group used to connect the fourth sub-light-emitting element, and the first hole group used to connect the second sub-light-emitting element are sequentially and periodically arranged along the second direction.

11. In one arrangement period of the first row gap, the second hole group of the third sub light emitting element is located on a side of the first hole group of the third sub light emitting element away from the first hole group of the first sub light emitting element, the second hole group of the first sub light emitting element is located between the first hole group of the first sub light emitting element and the first hole group of the third sub light emitting element; the second hole group of the fourth sub light emitting element is located between the first hole group of the first sub light emitting element and the first hole group of the fourth sub light emitting element; The display substrate of claim 10 , wherein the second group of holes of the second sub-light-emitting element is located on a side of the first group of holes of the second sub-light-emitting element that is away from the first group of holes of the fourth sub-light-emitting element.

12. 10. The display substrate of claim 6, wherein in the second row gap, the first hole group used to connect the third sub-light-emitting element, the first hole group used to connect the first sub-light-emitting element, the first hole group used to connect the fourth sub-light-emitting element, and the first hole group used to connect the second sub-light-emitting element are sequentially and periodically arranged along the second direction.

13. In one arrangement period of the second row gap, the second hole group of the third sub light emitting element is located on a side of the first hole group of the third sub light emitting element away from the first hole group of the first sub light emitting element, the second hole group of the first sub light emitting element is located between the first hole group of the third sub light emitting element and the first hole group of the first sub light emitting element; the second hole group of the fourth sub light emitting element is located between the first hole group of the first sub light emitting element and the first hole group of the fourth sub light emitting element; The display substrate of claim 9 , wherein the second hole group of the second sub-light-emitting element is located between the first hole group of the fourth sub-light-emitting element and the first hole group of the second sub-light-emitting element.

14. The first electrodes of the first light-emitting elements include a first electrode unit row and a second electrode unit row sequentially arranged along the first direction, the first electrode unit row includes a plurality of first electrode units sequentially arranged along the second direction, and the second electrode unit row includes a plurality of second electrode units sequentially arranged along the second direction; 14. The display substrate of claim 9, wherein each of the first electrode unit and the second electrode unit includes the first sub-electrode, the second sub-electrode, and the third sub-electrode and the fourth sub-electrode arranged along the first direction.

15. the first electrode unit includes a first side parallel to a long side of the third sub-electrode and a second side parallel to a long side of the fourth sub-electrode; 15. The display substrate of claim 14, wherein in the first electrode unit, the third sub-electrode includes a third sub-electrode body and a third sub-electrode transfer portion perpendicular to the first side extending from a side of the third sub-electrode body away from the second sub-electrode, and the orthogonal projection of the first group of holes on the base substrate for connecting the third sub-light-emitting element and the orthogonal projection of the third sub-electrode transfer portion on the base substrate have an overlapping area.

16. In the first electrode unit, the fourth sub-electrode includes a fourth sub-electrode main body and a fourth sub-electrode transfer portion extending from a side of the fourth sub-electrode main body away from the second sub-electrode and perpendicular to the second side, The display substrate according to claim 14 , wherein the orthogonal projection of the first group of holes on the base substrate for connecting the fourth sub-light-emitting element and the orthogonal projection of the fourth sub-electrode transfer portion on the base substrate have an overlapping area.

17. the second electrode unit includes a third side parallel to a long side of the third sub-electrode and a fourth side parallel to a long side of the fourth sub-electrode; 17. A display substrate according to claim 14, wherein in the second electrode unit, the third sub-electrode includes a third sub-electrode main body and a third sub-electrode transfer portion perpendicular to the third side extending from a side of the third sub-electrode main body away from the second sub-electrode, and the orthogonal projection of the first hole group on the base substrate for connecting the third sub-light-emitting element and the orthogonal projection of the third sub-electrode transfer portion on the base substrate have an overlapping area.

18. In the second electrode unit, the first electrode of the fourth sub-electrode includes a fourth sub-electrode main body and a fourth sub-electrode transfer portion extending from a side of the fourth sub-electrode main body close to the first sub-electrode and parallel to the fourth side, The display substrate according to claim 17 , wherein the orthogonal projection of the first group of holes on the base substrate for connecting the fourth sub-light-emitting element and the orthogonal projection of the fourth sub-electrode transfer portion on the base substrate have an overlapping area.

19. A display panel comprising the display substrate according to any one of claims 1 to 18.

20. A display device comprising the display panel according to claim 19.

21. The display device of claim 20 , further comprising an optical module disposed in the first display area.

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