Display device

Abstract

The display device includes a substrate including a display area in which a plurality of pixels are arranged, a hole area located within the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane, a printed circuit board disposed on the pad area of the substrate, a first hole crack sensing wiring disposed in the peripheral area of the substrate and extending to the bending area and the pad area, a second hole crack sensing wiring disposed in the peripheral area of the substrate, extending to the bending area and the pad area, and electrically connected to the first hole crack sensing wiring, a first transistor including a gate electrode connected to a first signal wiring and to which a first signal is applied, a first electrode, and a second electrode connected to the first hole crack sensing wiring, and a second transistor including a gate electrode connected to a second signal wiring and to which a second signal is applied, a first electrode connected to a high voltage wiring for applying a high voltage, and a second electrode connected to the first hole crack sensing wiring.

Description

Technical Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device that provides visual information.

Background Art

[0002] As information technology develops, the importance of display devices, which are connection media between users and information, is increasing. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), plasma display devices (PDPs), and quantum dot display devices is increasing.

[0003] On the other hand, when a display device is impacted, cracks occur in the substrate or the layers laminated on the substrate. The cracks grow larger over time or spread to other layers or other regions, inducing defects in the display device. For example, signal wirings such as data wirings or gate wirings are disconnected due to cracks, or their resistance increases, and moisture or the like penetrates into the display device through the cracks, resulting in a decrease in element reliability. As a result, various problems such as pixels of the display device not emitting light or emitting light erroneously occur.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a display device capable of inspecting cracks in holes formed in a hole region.

[0005] However, the object of the present invention is not limited to this, and can be variously extended without departing from the spirit and scope of the present invention.

Means for Solving the Problems

[0006] In order to achieve the object of the present invention, a display device according to an aspect of the present invention includes a display area in which a plurality of pixels are arranged, a hole area located within the display area, a peripheral area surrounding the display area, a pad area, and a substrate including a bending area located between the peripheral area and the pad area on a plane, a printed circuit board arranged on the pad area of the substrate, a first hole crack sensing wiring arranged on the peripheral area of the substrate and extending to the bending area and the pad area, a second hole crack sensing wiring arranged on the peripheral area of the substrate, extending to the bending area and the pad area, and electrically connected to the first hole crack sensing wiring, a first transistor including a gate electrode connected to a first signal wiring and to which a first signal is applied, a first electrode, and a second electrode connected to the first hole crack sensing wiring, and a second transistor including a gate electrode connected to a second signal wiring and to which a second signal is applied, a first electrode connected to a high voltage wiring for applying a high voltage, and a second electrode connected to the first hole crack sensing wiring.

[0007] When the display device is driven in a normal mode, a first signal having a low level is applied to the gate electrode of the first transistor via the first signal wiring, and the first transistor is turned on. A second signal having a high level is applied to the gate electrode of the second transistor via the second signal wiring, and the second transistor is turned off.

[0008] The first electrode of the first transistor is connected to a ground wiring of the printed circuit board. When the display device is driven in the normal mode, a ground voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the printed circuit board.

[0009] When the display device is driven in the normal mode, a low voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the printed circuit board.

[0010] When the display device is driven in the normal mode, the first hall crack sensing wiring and the second hall crack sensing wiring are in a floating state.

[0011] When the display device is driven in the inspection mode, a first signal having a high level is applied to the gate electrode of the first transistor via the first signal wiring, and the first transistor is turned off. A second signal having a low level is applied to the gate electrode of the second transistor via the second signal wiring, and the second transistor is turned on.

[0012] When the display device is driven in the inspection mode, the high voltage is applied to the first hall crack sensing wiring and the second hall crack sensing wiring via the high voltage wiring.

[0013] Furthermore, it includes a driving chip disposed in the pad region on the substrate. The driving chip is connected to the first signal wiring to provide the first signal to the first signal wiring, and provides the high voltage to the high voltage wiring via the printed circuit board.

[0014] Furthermore, it includes a first connection wiring disposed in the pad region on the substrate and providing a data signal to the pixel via the driving chip, and a second connection wiring disposed in the pad region on the substrate and providing a driving voltage to the pixel via the printed circuit board.

[0015] In the pad region, the first hall crack sensing wiring is disposed between the first connection wiring and the second connection wiring on a plane.

[0016] It is disposed in the display region on the substrate, includes a first stage and a second stage, and further includes a sensing wiring adjacent to the hall region so as to surround the periphery of the hall region.

[0017] The first stage of the sensing wiring is electrically connected to the first hall crack sensing wiring, and the second stage of the sensing wiring is electrically connected to the second hall crack sensing wiring.

[0018] Furthermore, it includes a semiconductor element including an active layer disposed in the display area on the substrate, a gate electrode overlapping the channel region of the active layer, a source electrode connected to the source region of the active layer, and a drain electrode connected to the drain region of the active layer, a connection electrode disposed on the semiconductor element and connected to the semiconductor element, a sensing connection pattern disposed on the connection electrode, and a touch sensing structure including a sensing electrode pattern disposed on the sensing connection pattern.

[0019] Each of the first hall crack sensing wiring and the second hall crack sensing wiring includes a first conductive pattern disposed in the pad region on the substrate, a bridge pattern disposed in the bending region on the substrate, extending to a part of the peripheral region and a part of the pad region, and connected to the first conductive pattern, and a second conductive pattern disposed in the peripheral region on the substrate and connected to the bridge pattern.

[0020] The first conductive pattern is disposed on the same layer as the source electrode and the drain electrode, the bridge pattern is disposed on the same layer as the connection electrode, and the second conductive pattern is disposed on the same layer as the sensing electrode pattern.

[0021] To achieve the object of the present invention, a display device according to another aspect of the present invention includes a display area in which a plurality of pixels are arranged, a hole area located within the display area, a peripheral area surrounding the display area, a pad area, and a substrate including a bending area located between the peripheral area and the pad area on a plane, a driving chip disposed on the pad area of the substrate, a first hole crack sensing wiring disposed on the peripheral area of the substrate, extending to the bending area and the pad area, and directly connected to the driving chip, and a second hole crack sensing wiring disposed on the peripheral area of the substrate, extending to the bending area and the pad area, and electrically connected to the first hole crack sensing wiring.

[0022] When the display device is driven in a normal mode, a low voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the driving chip.

[0023] When the display device is driven in a normal mode, the first hole crack sensing wiring and the second hole crack sensing wiring are connected to the ground wiring of the driving chip or are in a floating state.

[0024] When the display device is driven in an inspection mode, a high voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the driving chip.

[0025] In order to achieve the object of the present invention, a display device according to still another aspect of the present invention includes a display area in which a plurality of pixels are arranged, a hole area located within the display area, a peripheral area surrounding the display area, a pad area, and a substrate including a bending area located between the peripheral area and the pad area on a plane, a first hole crack sensing wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area, a second hole crack sensing wiring disposed in the peripheral area on the substrate, extending to the bending area and the pad area, and electrically connected to the first hole crack sensing wiring, a gate electrode connected to a signal wiring and to which a signal is applied, a first electrode connected to a high voltage wiring to which a high voltage is applied, and a transistor including a second electrode connected to the first hole crack sensing wiring.

[0026] When the display device is driven in the normal mode, a signal having a high level is applied to the gate electrode of the transistor via the signal wiring, and the transistor is turned off.

[0027] When the display device is driven in the normal mode, the first hole crack sensing wiring and the second hole crack sensing wiring are in a floating state.

[0028] When the display device is driven in the inspection mode, a signal having a low level is applied to the gate electrode of the transistor via the signal wiring, and the transistor is turned on.

[0029] When the display device is driven in the inspection mode, the high voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the high voltage wiring.

[0030] Furthermore, it includes a driving chip disposed in the pad region on the substrate and a printed circuit board disposed in the pad region on the substrate. The driving chip is connected to the signal wiring to provide the signal to the signal wiring and provides the high voltage to the high voltage wiring via the printed circuit board.

Advantages of the Invention

[0031] In a display device according to an embodiment of the present invention, when the display device is driven in a normal mode which is a mode generally used by a user, a low voltage is applied to a first hall crack sensing wiring and a second hall crack sensing wiring. When the display device is driven in an inspection mode for inspecting a crack of a hall formed in a hall region, a high voltage is applied to the first hall crack sensing wiring and the second hall crack sensing wiring. Thereby, corrosion of the first and second hall crack sensing wirings for inspecting cracks of halls formed in the hall region of the display device that occur during long-time driving in a high-temperature and high-humidity environment and a general user environment can be improved. Further, corrosion of drive signal wirings located adjacent to the first and second hall crack sensing wirings generated thereby can be improved.

[0032] However, the effects of the present invention are not limited thereto, and various extensions are possible without departing from the spirit and scope of the present invention.

Brief Description of the Drawings

[0033]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

[0034] Hereinafter, with reference to the accompanying drawings, a display device according to an embodiment of the present invention will be described in more detail. For the same components on the drawings, the same drawing reference numerals are given, and redundant descriptions of the same components are omitted.

[0035] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention. FIG. 2 is a diagram showing the bent shape of the display device in FIG. 1. FIG. 3 is a plan view showing an enlarged view of the A region in FIG. 1. For example, FIG. 3 is a plan view showing an enlarged view of the right part of the pad region (PDA) of the display device 100 in FIG. 1.

[0036] As shown in FIGS. 1, 2, and 3, a display device 100 according to an embodiment of the present invention includes a substrate 110, a plurality of pixels (PX), a first sensing wiring (M1), a second sensing wiring (M2), a third sensing wiring (M3), a driving chip (IC), and a flexible printed circuit board (FPC).

[0037] The substrate 110 includes a display area (DA), a hole area (HA), a peripheral area (PA), a bending area (BA), and a pad area (PDA). The peripheral area (PA) surrounds at least a part of the display area (DA). For example, the peripheral area (PA) entirely surrounds the display area (DA). The display area (DA) is an area that generates light or adjusts the transmittance of light provided from an external light source to display an image. The peripheral area (PA) is an area that does not display an image.

[0038] A plurality of pixels (PX) each including a semiconductor element and a light-emitting element are arranged in the display area (DA) on the substrate 110. The plurality of pixels (PX) generate light by a driving signal. The plurality of pixels (PX) are arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). Here, the second direction (DR2) is a direction substantially orthogonal to the first direction (DR1).

[0039] Wiring (LN) connected to the plurality of pixels (PX) is further arranged in the display area (DA) on the substrate 110. For example, the wiring (LN) includes data wiring, gate wiring, power supply wiring, and the like.

[0040] As shown in FIG. 2, the bending area (BA) extends from one side of the peripheral area (PA) and bends downward. That is, when the bending area (BA) bends about the first direction (DR1), the pad area (PDA) is located on the bottom surface of the display device 100. The pad area (PDA) extends from the bending area (BA) and is located under the display area (DA) or the peripheral area (PA). As shown in FIG. 1, in the unfolded state of the display device 100, the bending area (BA) is located between the display area (DA) and the pad area (PDA).

[0041] A first connection wiring (CL1) is arranged in the pad area (PDA) on the substrate 110. The first connection wiring (CL1) provides a data signal to the data wiring arranged in the display area (DA) via a driving chip (IC). The data wiring transmits the data signal to the plurality of pixels (PX).

[0042] In the pad region (PDA) on the substrate 110, a second connection wiring (CL2) is disposed. The second connection wiring (CL2) provides a driving voltage to a power supply wiring disposed in the display region (DA) via a flexible printed circuit (FPC). The power supply wiring transmits the driving voltage to a plurality of pixels (PX).

[0043] In the pad region (PDA) on the substrate 110, dummy patterns (DP1, DP2) are disposed. The dummy patterns (DP1, DP2) are spaced apart from each other in a first direction (DR1). Each of the dummy patterns (DP1, DP2) extends in a second direction (DR2) orthogonal to the first direction (DR1). The dummy patterns (DP1, DP2) are disposed between the first connection wiring (CL1) and the second connection wiring (CL2) on a plane.

[0044] The hole region (HA) is located within the display region (DA). A hole is formed in the hole region (HA). The hole penetrates the substrate 110. In one embodiment, a functional module is disposed below the substrate 110 corresponding to the hole. The functional module receives external light passing through the hole or transmits signals such as infrared rays and ultrasonic waves.

[0045] For example, the functional module includes a camera module for photographing (or recognizing) an image of an object located on the entire surface of the display device 100, a face recognition sensor module for sensing a user's face, a pupil recognition sensor module for sensing a user's pupil, an acceleration sensor module for determining the movement of the display device 100, and a geomagnetic sensor module, a proximity sensor module for sensing the presence of a surrounding object without physical contact, and an infrared sensor module, an illuminance sensor module for measuring the degree of external brightness, and the like.

[0046] In one embodiment, the hole region (HA) has a circular shape on a plane. However, the present invention is not limited thereto, and the hole region (HA) can also have a polygonal shape, an elliptical shape, etc. on the plane. Further, FIG. 1 shows that one hole region (HA) in which holes are formed is located within the display region (DA), but the present invention is not limited thereto. For example, a plurality of hole regions in which holes are respectively formed can be located within the display region (DA).

[0047] On the display region (DA) on the substrate 110, a third sensing wiring (M3) adjacent to the hole region (HA) is arranged. The third sensing wiring (M3) is arranged adjacent to the hole region (HA) in a shape surrounding the periphery of the hole region (HA) while one end and the other end are separated and isolated. The third sensing wiring (M3) is a wiring for inspecting cracks formed in the hole region (HA) of the layer constituting the display device 100.

[0048] On the peripheral region (PA), bending region (BA), and pad region (PDA) on the substrate 110, a first sensing wiring (M1) and a second sensing wiring (M2) are arranged. The first sensing wiring (M1) includes a first - 1 hole crack sensing wiring (HCD1 - 1) and a second - 1 hole crack sensing wiring (HCD2 - 1). One end of the first - 1 hole crack sensing wiring (HCD1 - 1) is electrically connected to the printed circuit board (FPC), and the other end of the first - 1 hole crack sensing wiring (HCD1 - 1) is electrically connected to one end of the third sensing wiring (M3). One end of the second - 1 hole crack sensing wiring (HCD2 - 1) is electrically connected to the wiring (LN), and the other end of the second - 1 hole crack sensing wiring (HCD2 - 1) is electrically connected to the other end of the third sensing wiring (M3).

[0049] The first hole crack sensing wiring (HCD1-1) and the second hole crack sensing wiring (HCD2-1) are located in the lower, left, and upper peripheral areas (PA) centered on the display area (DA). The first hole crack sensing wiring (HCD1-1) and the second hole crack sensing wiring (HCD2-1) extend side by side along the edge of the display area (DA).

[0050] The second sensing wiring (M2) includes the first hole crack sensing wiring (HCD1-2) and the second hole crack sensing wiring (HCD2-2). One end of the first hole crack sensing wiring (HCD1-2) is electrically connected to the printed circuit board (FPC), and the other end of the first hole crack sensing wiring (HCD1-2) is electrically connected to one end of the third sensing wiring (M3). One end of the second hole crack sensing wiring (HCD2-2) is electrically connected to the wiring (LN), and the other end of the second hole crack sensing wiring (HCD2-2) is electrically connected to the other end of the third sensing wiring (M3).

[0051] The first hole crack sensing wiring (HCD1-2) and the second hole crack sensing wiring (HCD2-2) are located in the lower, right, and upper peripheral areas (PA) centered on the display area (DA). The first hole crack sensing wiring (HCD1-2) and the second hole crack sensing wiring (HCD2-2) extend side by side along the edge of the display area (DA).

[0052] The display device 100 is driven in a normal mode, which is a mode generally used by the user, or an inspection mode for inspecting cracks formed in the hole area (HA) in the layer constituting the display device 100. When the display device 100 is driven in the normal mode, the driving chip (IC) outputs the data signal. When the display device 100 is driven in the inspection mode, the driving chip (IC) provides a voltage (for example, a high voltage) to the printed circuit board (FPC). In this case, the driving chip (IC) does not output the data signal.

[0053] When the display device 100 is driven in the inspection mode, a voltage (e.g., a high voltage) is applied to the first hall crack sensing wiring (HCD1-1) and the first-2 hall crack sensing wiring (HCD1-2) via a printed circuit board (FPC). The voltage is applied to a wiring (LN) disposed in the display area (DA) via the third sensing wiring (M3), the second-1 hall crack sensing wiring (HCD2-1), and the second-2 hall crack sensing wiring (HCD2-2).

[0054] When the display device 100 is driven in the inspection mode and no crack occurs in the hole area (HA) in the layer constituting the display device 100, the voltage passing through the third sensing wiring (M3) has a predetermined value.

[0055] When the display device 100 is driven in the inspection mode and a crack occurs in the hole area (HA) in the layer constituting the display device 100, the magnitude of the voltage passing through the third sensing wiring (M3) decreases. In this case, the display area (DA) displays bright vertical stripes. Thereby, the crack of the hole formed in the hole area (HA) in the layer constituting the display device 100 can be detected.

[0056] In one embodiment, the first to second hole crack sensing wirings (HCD1-2) are disposed between, on a plane, a first connection wiring (CL1) that provides the data signal to the data wiring and a second connection wiring (CL2) that provides the driving voltage to the power supply wiring. That is, the first to second hole crack sensing wirings (HCD1-2) are adjacent to the second connection wiring (CL2). That is, the first to second hole crack sensing wirings (HCD1-2) are disposed between dummy patterns (DP1, DP2) on a plane. However, in FIG. 3, the first to second hole crack sensing wirings (HCD1-2) are described as an example, but the present invention is not limited thereto. For example, the first to first hole crack sensing wiring (HCD1-1) also provides the data signal to the data wiring on a plane and is disposed between a first connection wiring (CL1) disposed in a pad region (PDA) and a second connection wiring (CL2) that provides the driving voltage to the power supply wiring and is disposed in the pad region (PDA).

[0057] A printed circuit board (FPC) is disposed on a pad region (PDA) on the substrate 110. Specifically, a part of the printed circuit board (FPC) overlaps the pad region (PDA). One end of the printed circuit board (FPC) is electrically connected to a pad disposed in the pad region (PDA) on the substrate 110, and the other end of the printed circuit board (FPC) is electrically connected to an external device. That is, electrical signals, voltages, etc. generated from the external device are provided to the driving chip (IC) and the plurality of pixels (PX) via the printed circuit board (FPC).

[0058] A driving chip (IC) is disposed on a pad region (PDA) on the substrate 110. The driving chip (IC) can convert a digital data signal among electrical signals into an analog data signal and provide it to a plurality of pixels (PX). For example, the driving chip (IC) is a data driving unit. Also, the driving chip (IC) provides a voltage (for example, a high voltage) to the printed circuit board (FPC).

[0059] However, although FIG. 1 shows a chip on plastic (COP) structure or a chip on glass (COG) structure in which a driving chip (IC) is directly disposed on a substrate 110, the present invention is not limited thereto. For example, the driving chip (IC) may have a chip on film (COF) structure directly disposed on a flexible film. In this case, a printed circuit board (FPC) is electrically connected to the flexible film.

[0060] FIG. 4 is a cross-sectional view showing a part of a display area of the display device in FIG. 1.

[0061] As shown in FIG. 4, a display device 100 according to an embodiment of the present invention includes a substrate 110, a display layer 200, a thin film encapsulation structure 300, a touch sensing structure 400, a polarizing layer (POL), and a cover window (CW).

[0062] The substrate 110 includes a transparent or opaque material. The substrate 110 is made of a transparent resin substrate. For example, the transparent resin substrate used as the substrate 110 may include a polyimide substrate. In such a case, the polyimide substrate includes a first polyimide layer, a barrier film layer, a second polyimide layer, and the like.

[0063] The display layer 200 is disposed on the substrate 110. The display layer 200 includes semiconductor elements, insulating layers, light emitting elements, and the like. Specific descriptions of the components of the display layer 200 will be described later.

[0064] The thin film encapsulation structure 300 is disposed on the display layer 200. The thin film encapsulation structure 300 covers the display layer 200. The thin film encapsulation structure 300 prevents the display layer 200 from being damaged by moisture, oxygen, and the like. Specific descriptions of the components of the thin film encapsulation structure 300 will be described later.

[0065] A touch sensing structure 400 is disposed on the thin film encapsulation structure 300. The touch sensing structure 400 acquires coordinate information from an external input. For example, the touch sensing structure 400 senses the external input in a mutual capacitance method or a self - capacitance method. A specific description of the components of the touch sensing structure 400 will be described later.

[0066] A polarizing layer (POL) is disposed on the touch sensing structure 400. The polarizing layer (POL) blocks external light incident on the display device 100 from the outside.

[0067] A cover window (CW) is disposed on the polarizing layer (POL). For example, the cover window (CW) is formed using tempered glass, reinforced plastic, or the like.

[0068] FIG. 5 is a cross - sectional view taken along lines I - I' and II - II' of FIG. 1. FIG. 6 is a plan view for explaining the touch sensing structure included in the display device in FIG. 5.

[0069] As shown in FIGS. 5 and 6, the display device 100 according to an embodiment of the present invention includes a substrate 110, a gate insulating layer 120, a first interlayer insulating layer 130a, a second interlayer insulating layer 130b, a semiconductor element 150, a first planarization layer 140a, a second planarization layer 140b, a connection electrode (CE), a pixel defining film 160, a light - emitting element 170, a thin film encapsulation structure 300, a touch sensing structure 400, and a first - 1 hole crack sensing wiring (HCD1 - 1).

[0070] Here, the semiconductor element 150 includes an active layer (ACT), a first gate electrode (GE1), a second gate electrode (GE2), a source electrode (SE), and a drain electrode (DE), and the light-emitting element 170 includes a lower electrode 171, a light-emitting layer 172, and an upper electrode 173. The thin-film encapsulation structure 300 includes a first inorganic thin-film encapsulation layer 181, an organic thin-film encapsulation layer 182, and a second inorganic thin-film encapsulation layer 183, and the touch sensing structure 400 includes a sensing connection pattern 220, a first sensing electrode pattern 240a, a second sensing electrode pattern 240b, and a connection part 241. The first-1 hole crack sensing wiring (HCD1-1) includes a first conductive pattern 135, a bridge pattern 155, and a second conductive pattern 245.

[0071] As described above, the display device 100 includes a display area (DA), a hole area (HA), a peripheral area (PA), a bending area (BA), and a pad area (PDA). Since the display device 100 includes the display area (DA), the hole area (HA), the peripheral area (PA), the bending area (BA), and the pad area (PDA), the substrate 110 also includes the display area (DA), the hole area (HA), the peripheral area (PA), the bending area (BA), and the pad area (PDA).

[0072] A buffer layer can also be disposed on the substrate 110. The buffer layer can prevent metal atoms and impurities from diffusing from the substrate 110 to upper structures (such as the semiconductor element 150, the light-emitting element 170, etc.), and can also adjust the heat transfer rate during the crystallization process for forming the active layer (ACT) to obtain a substantially uniform active layer (ACT). Further, when the surface of the substrate 110 is not uniform, the buffer layer plays a role in improving the flatness of the surface of the substrate 110. For example, the buffer layer includes an organic insulating substance or an inorganic insulating substance.

[0073] An active layer (ACT) is disposed on a display area (DA) of a substrate 110. The active layer (ACT) includes a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polysilicon), or an organic semiconductor. The active layer (ACT) includes a source region, a drain region, and a channel region located between the source region and the drain region.

[0074] A gate insulating layer 120 is disposed on a display area (DA), a peripheral area (PA), and a pad area (PDA) of the substrate 110. The gate insulating layer 120 has an opening exposing an upper surface of the substrate 110 located in a bending region (BA). The gate insulating layer 120 covers the active layer (ACT) on the substrate 110 and is disposed along the profile of the active layer (ACT) with a uniform thickness. Or, the gate insulating layer 120 can sufficiently cover the active layer (ACT) on the substrate 110, form no step around the active layer (ACT), and have a substantially flat upper surface. The gate insulating layer 120 includes a silicon compound, a metal oxide, etc. For example, the gate insulating layer 120 includes silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiCx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), etc. These can be used alone or in combination with each other.

[0075] A first gate electrode (GE1) is disposed on a display area (DA) of the gate insulating layer 120. The first gate electrode (GE1) overlaps the channel region of the active layer (ACT). For example, the first gate electrode (GE1) includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other.

[0076] A first interlayer insulating layer 130a is disposed on the display area (DA), the peripheral area (PA), and the pad area (PDA) on the gate insulating layer 120. The first interlayer insulating layer 130a has an opening that exposes the upper surface of the substrate 110 located in the bending area (BA). The first interlayer insulating layer 130a covers the first gate electrode (GE1) and is disposed with a uniform thickness. Or, the first interlayer insulating layer 130a may have a substantially flat upper surface without forming a step around the first gate electrode (GE1) on the gate insulating layer 120. For example, the first interlayer insulating layer 130a includes a silicon compound, a metal oxide, etc.

[0077] A second gate electrode (GE2) is disposed on the display area (DA) on the first interlayer insulating layer 130a. That is, the second gate electrode (GE2) overlaps the first gate electrode (GE1). For example, the second gate electrode (GE2) includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc. These can be used alone or in combination with each other.

[0078] A second interlayer insulating layer 130b is disposed on the display area (DA), the peripheral area (PA), and the pad area (PDA) on the first interlayer insulating layer 130a. The second interlayer insulating layer 130b has an opening that exposes the upper surface of the substrate 110 located in the bending area (BA). The second interlayer insulating layer 130b covers the second gate electrode (GE2) and is disposed with a uniform thickness. Or, the second interlayer insulating layer 130b may have a substantially flat upper surface without forming a step around the second gate electrode (GE2) on the first interlayer insulating layer 130a. For example, the second interlayer insulating layer 130b includes a silicon compound, a metal oxide, etc.

[0079] On the display area (DA) on the second interlayer insulating layer 130b, a source electrode (SE) and a drain electrode (DE) are arranged. The source electrode (SE) is connected to the source region of the active layer (ACT) through a contact hole formed by removing the gate insulating layer 120, the first interlayer insulating layer 130a, and the first portion of the second interlayer insulating layer 130b. The drain electrode (DE) is connected to the drain region of the active layer (ACT) through a contact hole formed by removing the gate insulating layer 120, the first interlayer insulating layer 130a, and the second portion of the second interlayer insulating layer 130b. For example, each of the source electrode (SE) and the drain electrode (DE) includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other.

[0080] On the pad area (PDA) on the second interlayer insulating layer 130b, a first conductive pattern 135 is arranged. For example, the first conductive pattern 135 includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In one embodiment, the first conductive pattern 135 is arranged on the same layer as the source electrode (SE) and the drain electrode (DE). That is, the first conductive pattern 135 includes the same material as the source electrode (SE) and the drain electrode (DE). In other embodiments, the first conductive pattern 135 can also be arranged on the same layer as the first gate electrode (GE1) or the second gate electrode (GE2).

[0081] A first planarization layer 140a is disposed on a display area (DA), a peripheral area (PA), and a pad area (PDA) on the second interlayer insulating layer 130b. The first planarization layer 140a has an opening that exposes the upper surface of the substrate 110 located in the bending area (BA). For example, the first planarization layer 140a is disposed with a relatively thick thickness so as to sufficiently cover the source electrode (SE), the drain electrode (DE), and the first conductive pattern 135 on the second interlayer insulating layer 130b. In such a case, the first planarization layer 140a has a substantially flat upper surface. In order to embody such a flat upper surface of the first planarization layer 140a, a planarization process can be added to the first planarization layer 140a. The first planarization layer 140a has a first contact hole that exposes the upper surface of the drain electrode (DE) in the display area (DA), and a second contact hole that exposes the upper surface of the first conductive pattern 135 in the pad area (PDA).

[0082] The first planarization layer 140a includes an organic insulating material or an inorganic insulating material. In one embodiment, the first planarization layer 140a includes an organic insulating material. For example, the first planarization layer 140a includes a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc. These can be used alone or in combination with each other.

[0083] An organic layer 145 is disposed in the bending area (BA) on the substrate 110. The organic layer 145 fills each of the openings of the gate insulating layer 120, the first interlayer insulating layer 130a, the second interlayer insulating layer 130b, and the first planarization layer 140a. The organic layer 145 can relieve stress in the bending area (BA). For example, the organic layer 145 includes a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc. These can be used alone or in combination with each other.

[0084] On the display area (DA) on the first planarization layer 140a, a connection electrode (CE) is disposed. The connection electrode (CE) is connected to the drain electrode (DE) through the first contact hole of the first planarization layer 140a. For example, the connection electrode (CE) includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other.

[0085] On the bending area (BA) on the organic layer 145, a bridge pattern 155 is disposed. The bridge pattern 155 extends to a part of the peripheral area (PA) and a part of the pad area (PDA). The bridge pattern 155 is connected to the first conductive pattern 135 through the second contact hole of the first planarization layer 140a. For example, the bridge pattern 155 includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In one embodiment, the bridge pattern 155 is disposed on the same layer as the connection electrode (CE). That is, the bridge pattern 155 includes the same material as the connection electrode (CE).

[0086] On the display area (DA) on the first planarization layer 140a, a second planarization layer 140b is disposed. That is, the second planarization layer 140b is not disposed in the peripheral area (PA) and the pad area (PDA). For example, the second planarization layer 140b is disposed with a relatively thick thickness so as to sufficiently cover the connection electrode (CE) on the first planarization layer 140a. In such a case, the second planarization layer 140b has a substantially flat upper surface. In order to embody such a flat upper surface of the second planarization layer 140b, a planarization process can be added to the second planarization layer 140b. Also, the second planarization layer 140b has a contact hole for exposing the upper surface of the connection electrode (CE). For example, the second planarization layer 140b includes an organic insulating material or an inorganic insulating material.

[0087] On the display area (DA) on the second planarization layer 140b, a lower electrode 171 is disposed. The lower electrode 171 is connected to a connection electrode (CE) through the contact hole in the second planarization layer 140b. Thus, the lower electrode 171 is electrically connected to the semiconductor element 150. For example, the lower electrode 171 includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc. These can be used alone or in combination with each other.

[0088] On the display area (DA) on the second planarization layer 140b, a pixel definition film 160 is disposed. The pixel definition film 160 has an opening that covers the side portion of the lower electrode 171 and exposes the upper surface of the lower electrode 171. For example, the pixel definition film 160 includes an organic insulating substance or an inorganic insulating substance. In one embodiment, the pixel definition film 160 includes an organic insulating substance.

[0089] On the display area (DA) on the lower electrode 171, a light-emitting layer 172 is disposed. That is, the light-emitting layer 172 is disposed on the lower electrode 171 exposed by the opening of the pixel definition film 160. The light-emitting layer 172 is formed using at least one light-emitting substance that emits red light, green light, blue light, etc., depending on the type of sub-pixel. Alternatively, the light-emitting layer 172 can also emit white light as a whole by laminating a plurality of light-emitting substances that generate other color lights such as red light, green light, and blue light.

[0090] On the display area (DA) on the pixel definition film 160 and the light-emitting layer 172, an upper electrode 173 is disposed. For example, the upper electrode 173 includes a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc. These can be used alone or in combination with each other.

[0091] Thereby, a light-emitting element 170 including the lower electrode 171, the light-emitting layer 172, and the upper electrode 173 is disposed in the display area (DA) on the substrate 110.

[0092] A first inorganic thin film encapsulation layer 181 is disposed on a display area (DA) of the upper electrode 173. The first inorganic thin film encapsulation layer 181 covers the upper electrode 173 and is disposed along the profile of the upper electrode 173 with a uniform thickness. The first inorganic thin film encapsulation layer 181 prevents the light-emitting element 170 from deteriorating due to the penetration of moisture, oxygen, etc. Further, the first inorganic thin film encapsulation layer 181 also functions to protect the light-emitting element 170 from external impacts. For example, the first inorganic thin film encapsulation layer 181 contains a flexible inorganic insulating material.

[0093] An organic thin film encapsulation layer 182 is disposed on the first inorganic thin film encapsulation layer 181. The organic thin film encapsulation layer 182 improves the flatness of the display device 100 and protects the light-emitting element 170 together with the first inorganic thin film encapsulation layer 181. For example, the organic thin film encapsulation layer 182 contains a flexible organic material.

[0094] A second inorganic thin film encapsulation layer 183 is disposed on the organic thin film encapsulation layer 182. The second inorganic thin film encapsulation layer 183 covers the organic thin film encapsulation layer 182 and is disposed along the profile of the organic thin film encapsulation layer 182 with a uniform thickness. The second inorganic thin film encapsulation layer 183, together with the first inorganic thin film encapsulation layer 181, prevents the light-emitting element 170 from deteriorating due to the penetration of moisture, oxygen, etc. Further, the second inorganic thin film encapsulation layer 183, together with the first inorganic thin film encapsulation layer 181 and the organic thin film encapsulation layer 182, also functions to protect the light-emitting element 170 from external impacts. For example, the second inorganic thin film encapsulation layer 183 contains a flexible inorganic insulating material.

[0095] Alternatively, the thin film encapsulation structure 300 can also have a five-layer phase structure laminated with three inorganic thin film encapsulation layers and two organic thin film encapsulation layers, or a seven-layer structure laminated with four inorganic thin film encapsulation layers and three organic thin film encapsulation layers.

[0096] On the display area (DA) on the second inorganic thin film encapsulation layer 183, a lower touch insulating layer 210 is disposed. The lower touch insulating layer 210 extends to the peripheral area (PA), the bending area (BA), and the pad area (PDA). For example, the lower touch insulating layer 210 includes an inorganic insulating material or an organic insulating material. Or, the lower touch insulating layer 210 can also have a multilayer structure including a plurality of insulating layers. For example, the insulating layers have different thicknesses from each other or include different substances from each other.

[0097] On the display area (DA) on the lower touch insulating layer 210, a sensing connection pattern 220 is disposed. As shown in FIG. 6, the sensing connection pattern 220 electrically connects the first sensing electrode pattern 240a and the second sensing electrode pattern 240b via contact holes. For example, the sensing connection pattern 220 can also include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, etc. These can be used alone or in combination with each other.

[0098] The sensing connection pattern 220 and the first and second sensing electrode patterns 240a, 240b include the same substance. Or, the sensing connection pattern 220 and the first and second sensing electrode patterns 240a, 240b can also include different substances from each other.

[0099] On the display area (DA), the peripheral area (PA), the bending area (BA), and the pad area (PDA) on the lower touch insulating layer 210, an interlayer touch insulating layer 230 is disposed. The interlayer touch insulating layer 230 sufficiently covers the sensing connection pattern 220. For example, the interlayer touch insulating layer 230 includes an organic insulating material or an inorganic insulating material. Or, the interlayer touch insulating layer 230 can also have a multilayer structure including a plurality of insulating layers. For example, the insulating layers have different thicknesses from each other or include different substances from each other.

[0100] On the display area (DA) of the interlayer touch insulation layer 230, a first sensing electrode pattern 240a, a second sensing electrode pattern 240b, and a connection portion 241 are arranged. Also, as shown in FIG. 6, a third sensing electrode pattern 242 is arranged on the display area (DA) of the interlayer touch insulation layer 230, and the third sensing electrode pattern 242 is arranged on the same layer as the connection portion 241. In one embodiment, each of the first sensing electrode pattern 240a, the second sensing electrode pattern 240b, the third sensing electrode pattern 242, and the connection portion 241 includes carbon nanotube (CNT), transparent conductive oxide, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), graphene, silver nanowire (AgNW), copper (Cu), chromium (Cr), titanium (Ti), aluminum (Al), etc. These can be used alone or in combination with each other. For example, each of the first sensing electrode pattern 240a, the second sensing electrode pattern 240b, the third sensing electrode pattern 242, and the connection portion 241 has a multilayer structure including Ti / Al / Ti.

[0101] For example, the first sensing electrode pattern 240a and the second sensing electrode pattern 240b include an electrode pattern array arranged spaced apart from each other in the second direction (D2). Also, the third sensing electrode pattern 242 includes an electrode pattern array extending in the second direction (D2) and arranged spaced apart from each other in the first direction (D1).

[0102] A second conductive pattern 245 is disposed in a peripheral area (PA) on the interlayer touch insulating layer 230. The second conductive pattern 245 is connected to the bridge pattern 155 through contact holes formed in the lower touch insulating layer 210 and the interlayer touch insulating layer 230. In one embodiment, the second conductive pattern 245 can be disposed on and formed simultaneously with the same layer as the first sensing electrode pattern 240a, the second sensing electrode pattern 240b, the third sensing electrode pattern 242, and the connecting portion 241. That is, the second conductive pattern 245 includes the same material as the first sensing electrode pattern 240a, the second sensing electrode pattern 240b, the third sensing electrode pattern 242, and the connecting portion 241. In other embodiments, the second conductive pattern 245 can also be disposed on the same layer as the sensing connection pattern 220.

[0103] Accordingly, a first - 1 hole crack sensing wiring (HCD1 - 1) including the first conductive pattern 135, the bridge pattern 155, and the second conductive pattern 245 is disposed in a peripheral area (PA), a bending area (BA), and a pad area (PDA) on the substrate 110. However, in FIG. 5, the first - 1 hole crack sensing wiring (HCD1 - 1) is described as an example, but the present invention is not limited thereto. For example, each of the first - 2 hole crack sensing wiring (HCD1 - 2), the second - 1 hole crack sensing wiring (HCD2 - 1), and the second - 2 hole crack sensing wiring (HCD2 - 2) in FIG. 1 includes the same components as the first - 1 hole crack sensing wiring (HCD1 - 1).

[0104] A protective layer 250 is disposed in a display area (DA) on the interlayer touch insulating layer 230, the first sensing electrode pattern 240a, the second sensing electrode pattern 240b, and the connecting portion 241. The protective layer 250 sufficiently covers the first sensing electrode pattern 240a, the second sensing electrode pattern 240b, and the connecting portion 241.

[0105] The touch sensing structure 400 of the present invention is not limited to the structure shown in FIGS. 5 and 6, and can have various structures. For example, in other embodiments, the lower touch insulating layer 210 can also be omitted. Further, the first and second sensing electrode patterns 240a, 240b and the third sensing electrode pattern 242 can be arranged in different layers, and the first and second sensing electrode patterns 240a, 240b can also have a continuous structure without the sensing connection pattern 220.

[0106] In addition, although the display device 100 of the present invention is described by limiting it to an organic light emitting display device, the configuration of the present invention is not limited thereto. In other embodiments, the display device 100 can also include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), an electrophoretic image display device (EPD), an inorganic light emitting display device (ILED), or a quantum dot display device.

[0107] FIGS. 7 and 8 are diagrams schematically showing circuit structures for explaining the normal mode and the inspection mode of the display device of FIG. 1.

[0108] As shown in FIGS. 1, 7, and 8, a display device 100 according to an embodiment of the present invention includes a substrate 110, a plurality of pixels (PX), a first sensing wiring (M1), a second sensing wiring (M2), a third sensing wiring (M3), a driving chip (IC), and a flexible printed circuit (FPC).

[0109] Here, the first sensing wiring (M1) includes a first-1 hall crack sensing wiring (HCD1-1) and a second-1 hall crack sensing wiring (HCD2-1), and the second sensing wiring (M2) includes a first-2 hall crack sensing wiring (HCD1-2) and a second-2 hall crack sensing wiring (HCD2-2). The first-1 hall crack sensing wiring (HCD1-1) and the first-2 hall crack sensing wiring (HCD1-2) are defined as the first hall crack sensing wiring (HCD1), and the second-1 hall crack sensing wiring (HCD2-1) and the second-2 hall crack sensing wiring (HCD2-2) are defined as the second hall crack sensing wiring (HCD2).

[0110] The display device 100 according to an embodiment of the present invention further includes a first bending crack sensing wiring (BCD1), a second bending crack sensing wiring (BCD2), a module crack sensing wiring (MCD), a first signal wiring (SL1), a second signal wiring (SL2), a high voltage wiring (VGHL), a first transistor (T1), and a second transistor (T2).

[0111] The first bending crack sensing wiring (BCD1) and the second bending crack sensing wiring (BCD2) inspect cracks generated in the bending region (for example, the bending region (BA) in FIG. 1). The module crack sensing wiring (MCD) inspects cracks generated in the outermost region of the display device 100.

[0112] The second hall crack sensing wiring (HCD2) is electrically connected to the first hall crack sensing wiring (HCD1). The first bending crack sensing wiring (BCD1) is connected to the module crack sensing wiring (MCD). The second bending crack sensing wiring (BCD2) is integrally formed with the first crack sensing wiring (BCD1). The module crack sensing wiring (MCD) is connected to the first hall crack sensing wiring (HCD1). The high voltage wiring (VGHL) is connected to the driving chip (IC) and the printed circuit board (FPC). The driving chip (IC) provides a high voltage to the high voltage wiring (VGHL) via the printed circuit board (FPC).

[0113] The first signal wiring (SL1) is connected to the driving chip (IC). Specifically, the first signal wiring (SL1) is connected to a driving dummy pad (IC-DP) included in the driving chip (IC). The driving chip (IC) provides a first signal to the first signal wiring (SL1).

[0114] The first transistor (T1) includes a first electrode, a second electrode, and a gate electrode. The first electrode of the first transistor (T1) is connected to the printed circuit board (FPC). In one embodiment, the first electrode of the first transistor (T1) is connected to the ground wiring of the printed circuit board (FPC) (see FIG. 7). In other embodiments, the first electrode of the first transistor (T1) can also be connected to the ground wiring disposed in the display area (DA) (see FIG. 8). The second electrode of the first transistor (T1) is connected to the node to which the second electrode of the second transistor (T2) is connected. The gate electrode of the first transistor (T1) is connected to the first signal wiring (SL1). A first signal is applied to the gate electrode of the first transistor (T1) via the first signal wiring (SL1).

[0115] The second transistor (T2) includes a first electrode, a second electrode, and a gate electrode. The first electrode of the second transistor (T2) is connected to the high voltage wiring (VGHL). The second electrode of the second transistor (T2) is connected to the node to which the second electrode of the first transistor (T1) is connected. The gate electrode of the second transistor (T2) is connected to the second signal wiring (SL2). A second signal is applied to the gate electrode of the second transistor (T2) via the second signal wiring (SL2).

[0116] The display device 100 is driven in a normal mode, which is a mode generally used by the user, or an inspection mode for inspecting cracks formed in the whole area (HA). Hereinafter, the normal mode and the inspection mode will be described.

[0117] When the display device 100 is driven in the normal mode, the first transistor (T1) is turned on by a first signal provided via the first signal wiring (SL1), and the second transistor (T2) is turned off by a second signal provided via the second signal wiring (SL2). Here, the first signal has a low level, and the second signal has a high level. Therefore, when the display device 100 is driven in the normal mode, a ground voltage is applied to the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2) via a flexible printed circuit (FPC). Alternatively, when the display device 100 is driven in the normal mode, the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2) are also in a floating state. Alternatively, when the display device 100 is driven in the normal mode, a low voltage can also be applied to the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2) via a flexible printed circuit (FPC).

[0118] When the display device 100 is driven in the inspection mode, the first transistor (T1) is turned off by a first signal provided via the first signal wiring (SL1), and the second transistor (T2) is turned on by a second signal provided via the second signal wiring (SL2). Here, the first signal has a high level, and the second signal has a low level. Therefore, when the display device 100 is driven in the inspection mode, a high voltage is applied to the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2) via a high voltage wiring (VGHL).

[0119] According to the comparative example, when the display device 100 is driven in the normal mode, which is a mode generally used by users, a high voltage is applied to the first and second hall crack sensing wirings (HCD1, HCD2). In this case, iodine in the polarizing layer (for example, the polarizing layer (POL) in FIG. 4) may elute into the first and second hall crack sensing wirings (HCD1, HCD2) in a high-temperature and high-humidity environment and a general user environment, and corrosion of the first and second hall crack sensing wirings (HCD1, HCD2) may occur. Further, when the iodine elutes into the first and second hall crack sensing wirings (HCD1, HCD2), corrosion of the drive signal wiring located adjacent to the first and second hall crack sensing wirings (HCD1, HCD2) can occur.

[0120] In the display device 100 according to an embodiment of the present invention, when the display device 100 is driven in the normal mode, a low voltage is applied to the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2), and when the display device 100 is driven in the inspection mode, a high voltage is applied to the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2). Thereby, it is possible to improve the corrosion of the first and second hall crack sensing wirings (HCD1, HCD2) for inspecting cracks formed in the hall region (HA) of the display device 100 that occur during long-time driving in a high-temperature and high-humidity environment and a general user environment. Further, it is possible to improve the corrosion of the drive signal wiring located adjacent to the first and second hall crack sensing wirings (HCD1, HCD2) caused by the corrosion of the first and second hall crack sensing wirings (HCD1, HCD2).

[0121] FIG. 9 is a diagram schematically showing a circuit structure for explaining the normal mode and the inspection mode of a display device according to another embodiment of the present invention.

[0122] As shown in FIGS. 1 and 9, a display device according to another embodiment of the present invention includes a substrate 110, a plurality of pixels (PX), a first sensing wiring (M1), a second sensing wiring (M2), a third sensing wiring (M3), a driving chip (IC), and a printed circuit board (FPC). Hereinafter, descriptions overlapping with those of the display device 100 described in FIGS. 1, 7, and 8 will be omitted.

[0123] The display device according to another embodiment of the present invention further includes a first bending crack sensing wiring (BCD1), a second bending crack sensing wiring (BCD2), a module crack sensing wiring (MCD), and a high voltage wiring (VGHL).

[0124] The second hole crack sensing wiring (HCD2) is electrically connected to the first hole crack sensing wiring (HCD1). The first bending crack sensing wiring (BCD1) is connected to the high voltage wiring (VGHL). The second bending crack sensing wiring (BCD2) is formed integrally with the first bending crack sensing wiring (BCD1). The module crack sensing wiring (MCD) is connected to the high voltage wiring (VGHL). The high voltage wiring (VGHL) is connected to the driving chip (IC) and the printed circuit board (FPC). The driving chip (IC) provides a high voltage to the high voltage wiring (VGHL) via the printed circuit board (FPC).

[0125] The first hole crack sensing wiring (HCD1) is directly connected to the driving chip (IC). Specifically, the first hole crack sensing wiring (HCD1) is directly connected to a driving dummy pad (IC-DP) included in the driving chip (IC). In one embodiment, the driving chip (IC) provides a voltage (e.g., a low voltage, a high voltage, etc.) to the first hole crack sensing wiring (HCD1). In other embodiments, the driving chip (IC) and the driving dummy pattern (IC-DP) are not electrically connected. In this case, the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) are in a floating state. In other embodiments, the first hole crack sensing wiring (HCD1) can also be connected to the ground of the driving chip (IC).

[0126] The display device is driven in a normal mode which is a mode generally used by the user, or in an inspection mode for inspecting cracks in the holes formed in the hall region (HA). Hereinafter, the normal mode and the inspection mode will be described.

[0127] When the display device is driven in the normal mode, a low voltage is applied to the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) via a driving chip (IC). Or, when the display device is driven in the normal mode, the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) are also in a floating state. Or, when the display device is driven in the normal mode, the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) can also be connected to the ground of the driving chip (IC). In this case, a ground voltage is applied to the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) via the driving chip (IC).

[0128] When the display device is driven in the inspection mode, a high voltage is applied to the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) via a driving chip (IC).

[0129] Accordingly, when the display device is driven in the normal mode, a low voltage is applied to the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2), and when the display device is driven in the inspection mode, a high voltage is applied to the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2).

[0130] FIG. 10 is a diagram schematically showing a circuit structure for explaining the normal mode and the inspection mode of a display device according to still another embodiment of the present invention.

[0131] As shown in FIGS. 1 and 10, a display device according to still another embodiment of the present invention includes a substrate 110, a plurality of pixels (PX), a first sensing wiring (M1), a second sensing wiring (M2), a third sensing wiring (M3), a driving chip (IC), and a flexible printed circuit board (FPC). Hereinafter, descriptions overlapping with those of the display device 100 described in FIGS. 1, 7, and 8 will be omitted.

[0132] The display device according to still another embodiment of the present invention further includes a first bending crack sensing wiring (BCD1), a second bending crack sensing wiring (BCD2), a module crack sensing wiring (MCD), a high voltage wiring (VGHL), a third transistor (T3), and a third signal wiring (SL3).

[0133] The second hole crack sensing wiring (HCD2) is electrically connected to the first hole crack sensing wiring (HCD1). The first bending crack sensing wiring (BCD1) is connected to the high voltage wiring (VGHL). The second bending crack sensing wiring (BCD2) is formed integrally with the first bending crack sensing wiring (BCD1). The module crack sensing wiring (MCD) is connected to the high voltage wiring (VGHL). The high voltage wiring (VGHL) is connected to the driving chip (IC) and the flexible printed circuit board (FPC). The driving chip (IC) provides a high voltage to the high voltage wiring (VGHL) via the flexible printed circuit board (FPC).

[0134] The third signal wiring (SL3) is connected to the driving chip (IC). Specifically, the third signal wiring (SL3) is connected to a driving dummy pad (IC-DP) included in the driving chip (IC). The driving chip (IC) provides a third signal to the third signal wiring (SL3).

[0135] The third transistor (T3) includes a first electrode, a second electrode, and a gate electrode. The first electrode of the third transistor (T3) is connected to the high-voltage wiring (VGHL). The second electrode of the third transistor (T3) is connected to the first hole crack sensing wiring (HCD1). The gate electrode of the third transistor (T3) is connected to the third signal wiring (SL3). The third signal is applied to the gate electrode of the third transistor (T3) via the third signal wiring (SL3).

[0136] The display device is driven in a normal mode, which is a mode generally used by a user, or an inspection mode for inspecting cracks in the holes formed in the hole region (HA). Hereinafter, the normal mode and the inspection mode will be described.

[0137] When the display device is driven in the normal mode, the third transistor (T3) is turned off by the third signal provided via the third signal wiring (SL3). Here, the third signal has a high level. Therefore, when the display device is driven in the normal mode, the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) are in a floating state.

[0138] When the display device is driven in the inspection mode, the third transistor (T3) is turned on by the third signal provided via the third signal wiring (SL3). Here, the third signal has a low level. Therefore, when the display device is driven in the inspection mode, a high voltage is applied to the first hole crack sensing wiring (HCD1) and the second hole crack sensing wiring (HCD2) via the high-voltage wiring (VGHL).

[0139] Accordingly, when the display device is driven in the normal mode, the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2) are in a floating state, and when the display device is driven in the inspection mode, a high voltage is applied to the first hall crack sensing wiring (HCD1) and the second hall crack sensing wiring (HCD2).

[0140] In the above, exemplary embodiments of the present invention have been described with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the following claims.

Industrial Applicability

[0141] The present invention is applicable to various display devices including a display device. For example, the present invention can be applied to high-resolution smartphones, mobile phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, notebook computers, and the like.

Explanation of Signs

[0142] 100: Display device DA: Display area HA: Hall area PA: Peripheral area BA: Bending area PDA: Pad area IC: Driving chip FPC: Printed circuit board M1, M2, M3: First to third sensing wirings HCD1-1, HCD1-2: First-1 and first-2 hall crack sensing wirings HCD2-1, HCD2-2: Second-1 and second-2 hall crack sensing wirings BCD1, BCD2: First and second bending crack sensing wirings MCD: Module crack sensing wiring SL1, SL2, SL3: First to third signal wirings T1, T2, T3: First to third transistors

Claims

1. A substrate including a display area in which a plurality of pixels are arranged, a hole area located within the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane; A printed circuit board disposed on the pad area of the substrate; A first hole crack sensing wiring disposed on the peripheral area of the substrate and extending to the bending area and the pad area; A second hole crack sensing wiring disposed on the peripheral area of the substrate, extending to the bending area and the pad area, and electrically connected to the first hole crack sensing wiring; A first transistor including a gate electrode connected to a first signal wiring and to which a first signal is applied, a first electrode, and a second electrode connected to the first hole crack sensing wiring; A second transistor including a gate electrode connected to a second signal wiring and to which a second signal is applied, a first electrode connected to a high voltage wiring for applying a high voltage, and a second electrode connected to the first hole crack sensing wiring, the display device being characterized by including the same.

2. When the display device is driven in a normal mode, A first signal having a low level is applied to the gate electrode of the first transistor via the first signal wiring, and the first transistor is turned on; A second signal having a high level is applied to the gate electrode of the second transistor via the second signal wiring, and the second transistor is turned off, the display device according to claim 1 being characterized by this.

3. The first electrode of the first transistor is connected to a ground wiring of the printed circuit board; When the display device is driven in the normal mode, a ground voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the printed circuit board, the display device according to claim 2 being characterized by this.

4. When the display device is driven in the normal mode, a low voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the printed circuit board, the display device according to claim 2 being characterized by this.

5. The display device according to claim 2, wherein when the display device is driven in the normal mode, the first hall crack sensing wiring and the second hall crack sensing wiring are in a floating state.

6. When the display device is driven in the inspection mode, a first signal having a high level is applied to the gate electrode of the first transistor via the first signal wiring, and the first transistor is turned off. The display device according to claim 1, wherein a second signal having a low level is applied to the gate electrode of the second transistor via the second signal wiring, and the second transistor is turned on.

7. The display device according to claim 6, wherein when the display device is driven in the inspection mode, the high voltage is applied to the first hall crack sensing wiring and the second hall crack sensing wiring via the high voltage wiring.

8. Furthermore, it includes a driving chip disposed in the pad region on the substrate. The driving chip is connected to the first signal wiring to provide the first signal to the first signal wiring, and provides the high voltage to the high voltage wiring via the printed circuit board. The display device according to claim 1, characterized in that.

9. Furthermore, a first connection wiring disposed in the pad region on the substrate and providing a data signal to the pixel via the driving chip; The display device according to claim 8, further comprising a second connection wiring disposed in the pad region on the substrate and providing a driving voltage to the pixel via the printed circuit board.

10. The display device according to claim 9, wherein the first hall crack sensing wiring is disposed between the first connection wiring and the second connection wiring in a plane in the pad region.

11. The display device according to claim 1, further comprising a sensing wiring disposed in the display region on the substrate, including a first stage and a second stage, and adjacent to the hall region so as to surround the periphery of the hall region.

12. The display device according to claim 11, wherein the first stage of the sensing wiring is electrically connected to the first hall crack sensing wiring, and the second stage of the sensing wiring is electrically connected to the second hall crack sensing wiring.

13. Furthermore, a semiconductor element including an active layer disposed in the display region on the substrate, a gate electrode overlapping the channel region of the active layer, a source electrode connected to the source region of the active layer, and a drain electrode connected to the drain region of the active layer; a connection electrode disposed on the semiconductor element and connected to the semiconductor element; a touch sensing structure including a sensing connection pattern disposed on the connection electrode and a sensing electrode pattern disposed on the sensing connection pattern, the display device according to claim 1, characterized in that it comprises.

14. Each of the first hole crack sensing wiring and the second hole crack sensing wiring a first conductive pattern disposed in the pad region on the substrate; a bridge pattern disposed in the bending region on the substrate, extending to a part of the peripheral region and a part of the pad region, and connected to the first conductive pattern; a second conductive pattern disposed in the peripheral region on the substrate and connected to the bridge pattern, the display device according to claim 13, characterized in that it comprises.

15. The first conductive pattern is disposed on the same layer as the source electrode and the drain electrode, the bridge pattern is disposed on the same layer as the connection electrode, and the second conductive pattern is disposed on the same layer as the sensing electrode pattern, the display device according to claim 14, characterized in that.

16. A substrate including a display region in which a plurality of pixels are arranged, a hole region located within the display region, a peripheral region surrounding the display region, a pad region, and a bending region located between the peripheral region and the pad region on a plane; a driving chip disposed in the pad region on the substrate; a first hole crack sensing wiring disposed in the peripheral region on the substrate, extending to the bending region and the pad region, and directly connected to the driving chip; a second hole crack sensing wiring disposed in the peripheral region on the substrate, extending to the bending region and the pad region, and electrically connected to the first hole crack sensing wiring, the display device characterized by comprising.

17. When the display device is driven in the normal mode, a low voltage is applied to the first hole crack sensing wiring and the second hole crack sensing wiring via the driving chip, the display device according to claim 16, characterized in that.

18. When the display device is driven in the normal mode, the first hall crack sensing wiring and the second hall crack sensing wiring are connected to the ground wiring of the drive chip or are in a floating state. The display device according to claim 16.

19. When the display device is driven in the inspection mode, a high voltage is applied to the first hall crack sensing wiring and the second hall crack sensing wiring via the drive chip. The display device according to claim 16.

20. A substrate including a display area in which a plurality of pixels are arranged, a hall area located within the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane, A first hall crack sensing wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area, A second hall crack sensing wiring disposed in the peripheral area on the substrate, extending to the bending area and the pad area, and electrically connected to the first hall crack sensing wiring, A transistor including a gate electrode connected to a signal wiring to which a signal is applied, a first electrode connected to a high voltage wiring to which a high voltage is applied, and a second electrode connected to the first hall crack sensing wiring. The display device characterized by including.

21. When the display device is driven in the normal mode, a signal having a high level is applied to the gate electrode of the transistor via the signal wiring, and the transistor is turned off. The display device according to claim 20.

22. When the display device is driven in the normal mode, the first hall crack sensing wiring and the second hall crack sensing wiring are in a floating state. The display device according to claim 21.

23. When the display device is driven in the inspection mode, a signal having a low level is applied to the gate electrode of the transistor via the signal wiring, and the transistor is turned on. The display device according to claim 20.

24. When the display device is driven in the inspection mode, the high voltage is applied to the first hall crack sensing wiring and the second hall crack sensing wiring via the high voltage wiring. The display device according to claim 23.

25. Furthermore, it includes a drive chip disposed in the pad region on the substrate, and a printed circuit board disposed in the pad region on the substrate, wherein the drive chip is connected to the signal wiring to provide the signal to the signal wiring, and provides the high voltage to the high voltage wiring via the printed circuit board. The display device according to claim 20, characterized in that.

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