Array substrate, method for manufacturing the same, and display device

Abstract

The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a base structure, an active layer on the base structure, a patterned first insulating layer on a side of the active layer far from the base structure, the first insulating layer having a first through hole exposing a part of the active layer, a first conductive layer in the first through hole and in contact with the active layer, and a first connection member on a side of the first insulating layer far from the base structure, the first connection member being in contact with the first conductive layer, covering a first portion of the first conductive layer, and not covering a second portion of the first conductive layer. The present disclosure can reduce the possibility of a missing portion appearing in the active layer and further improve the performance of the array substrate and the display device formed thereby.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority based on an application with a Chinese application number of 202210590935.4 and a filing date of May 27, 2022, and the disclosure content of the Chinese application is hereby incorporated into this application in its entirety. The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] Currently, OLED (Organic Light - Emitting Diode) technology is becoming increasingly mature. In some OLED display panels, a 5 - mask process (which can be called 5 Mask) may be adopted for the array substrate. During the manufacturing process of the array substrate, it is necessary to manufacture TFT transistors (Thin Film Transistors).

Summary of the Invention

[0003] According to one aspect of the present disclosure, there is provided an array substrate including a base structure, an active layer on the base structure, a patterned first insulating layer on the side of the active layer far from the base structure, the first insulating layer having a first through - hole exposing a part of the active layer, a first conductive layer in the first through - hole and in contact with the active layer, and a first connection member on the side of the first insulating layer far from the base structure, the first connection member being in contact with the first conductive layer, covering a first part of the first conductive layer, and not covering a second part of the first conductive layer.

[0004] In some embodiments, the first insulating layer further has a second through-hole that exposes another part of the active layer, and the array substrate further includes a second conductive layer in the second through-hole, a second connection member electrically connected to the second conductive layer, and a gate located on a side of the first insulating layer far from the active layer. Among them, the second connection member and the gate are in the same layer, and both the first connection member and the second connection member are spaced apart from the gate.

[0005] In some embodiments, the base structure includes a base substrate, a light-shielding layer and a third conductive layer on the base substrate, a positive projection of the light-shielding layer on the base substrate at least partially overlaps with a positive projection of the active layer on the base substrate, and among them, the third conductive layer covers the light-shielding layer, or the light-shielding layer covers the third conductive layer, and a buffer layer between the third conductive layer and the active layer.

[0006] In some embodiments, a positive projection of the first conductive layer on the base substrate at least partially overlaps with a positive projection of the light-shielding layer on the base substrate.

[0007] In some embodiments, the second through-hole further exposes a part of the buffer layer, and the second conductive layer includes a third part located on the surface of the active layer and a fourth part located on the surface of the buffer layer.

[0008] In some embodiments, the materials of the first conductive layer, the second conductive layer and the third conductive layer all include transparent conductive materials.

[0009] In some embodiments, the thickness of the third conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is equal to the thickness of the first conductive layer.

[0010] In some embodiments, the thickness of the first conductive layer is greater than the thickness of the active layer.

[0011] In some embodiments, the area of the overlapping portion between the first connection member and the first conductive layer is smaller than the area of the overlapping portion between the second connection member and the second conductive layer.

[0012] In some embodiments, the first insulating layer includes a gate insulating layer located below the gate, the active layer includes a first conductive region electrically connected to the first connection member, a second conductive region electrically connected to the second connection member, and a channel region between the first conductive region and the second conductive region, and the channel region and the gate insulating layer have aligned edges.

[0013] In some embodiments, the width of the overlapping portion between the first connection member and the first conductive layer along the direction from the first connection member towards the gate is smaller than the distance between the edge of the first conductive layer and the channel region.

[0014] In some embodiments, the area of the first conductor layer is larger than the area of the overlapping portion between the first connection member and the first conductive layer.

[0015] In some embodiments, the area of the first conductor layer is smaller than the area of the channel region.

[0016] In some embodiments, the width of the overlapping portion between the first conductive layer and the active layer along the direction from the first connection member towards the gate is smaller than the width of the overlapping portion between the second conductive layer and the active layer along the direction from the first connection member towards the gate.

[0017] In some embodiments, the distance between the first conductive layer and the gate is greater than the width of the overlapping portion of the first connection member and the first conductive layer along the direction from the first connection member towards the gate, and the width of the overlapping portion of the first connection member and the first conductive layer along the direction from the first connection member towards the gate is greater than the width of the second portion of the first conductive layer along the direction from the first connection member towards the gate.

[0018] In some embodiments, the array substrate further includes a second insulating layer covering the first connection member, the second connection member, and the gate, a planarization layer on the side of the second insulating layer away from the base structure, and a first electrode layer and a pixel defining layer on the side of the planarization layer away from the base structure. The first electrode layer is electrically connected to the second connection member, and the pixel defining layer has a first opening exposing at least a part of the first electrode layer, and further includes a light emitting layer at least located within the first opening, and a second electrode layer electrically connected to the light emitting layer.

[0019] In some embodiments, the width of the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the third conductive layer on the base substrate along the direction from the first connection member towards the gate is smaller than the width of the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the first electrode layer on the base substrate along the direction from the first connection member towards the gate.

[0020] In some embodiments, the width of the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the third conductive layer on the base substrate along the direction from the first connection member towards the gate is smaller than the width of the overlapping portion between the orthographic projection of the third conductive layer on the base substrate and the orthographic projection of the first electrode layer on the base substrate along the direction from the first connection member towards the gate.

[0021] According to another aspect of the present disclosure, there is provided an array substrate including a base structure and a thin film transistor on the base structure. The thin film transistor includes an active layer on the base structure, a patterned first insulating layer on a side of the active layer away from the base structure and having a first through hole exposing a part of the active layer, a first conductive layer in the first through hole and in contact with the active layer, a first connection member, a second connection member and a gate on a side of the first insulating layer away from the base structure, the first connection member being in contact with the first conductive layer, the first connection member, the second connection member and the gate being in the same layer and spaced apart from each other, and the gate being located between the first connection member and the second connection member. Among them, the active layer includes a first conductive region electrically connected to the first connection member, a second conductive region electrically connected to the second connection member, and a channel region between the first conductive region and the second conductive region. The channel region is below the gate. The first conductive layer includes a first portion away from the gate and a second portion close to the gate. The first portion is completely covered by the first connection member, the second portion is not covered by the first connection member, and a positive projection of the first conductive layer on the base structure is located inside a positive projection of the active layer on the base structure.

[0022] In some embodiments, a width of the second portion along a direction from the first connection member towards the gate is smaller than a width of the first portion along the direction from the first connection member towards the gate.

[0023] In some embodiments, a width of the second portion along a direction from the first connection member towards the gate is smaller than a width of the channel region along the direction from the first connection member towards the gate.

[0024] In some embodiments, a thickness of the second portion is smaller than a thickness of the first portion.

[0025] In some embodiments, the width of the first portion is 2 to 5 times the width of the second portion.

[0026] In some embodiments, the active layer further includes a semiconductor region located on a side far from the channel region in the first conductive region, wherein the width of the second portion along the direction from the first connection member to the gate is smaller than the width of the semiconductor region along the direction from the first connection member to the gate.

[0027] According to another aspect of the present disclosure, a display device including the array substrate described above is provided.

[0028] According to another aspect of the present disclosure, a method for manufacturing an array substrate includes forming an active layer on a base structure; forming, on a side of the active layer far from the base structure, a patterned first insulating layer having a first through hole exposing a part of the active layer; performing a first conductorization process on the exposed part of the active layer; forming a first conductive layer contacting the active layer in the first through hole; forming a connection material layer on a side of the first insulating layer far from the base structure through a deposition process; patterning the connection material layer using a patterned mask layer to form a first connection member contacting the first conductive layer, the first connection member covering a first part of the first conductive layer and not covering a second part of the first conductive layer; etching the first insulating layer through a self-alignment process using the mask layer to expand the first through hole, wherein another part of the active layer is exposed by the expanded first through hole; and performing a second conductorization process on the exposed another part of the active layer.

[0029] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the drawings.

Brief Description of the Drawings

[0030] The drawings forming a part of the specification describe embodiments of the present disclosure and, together with the specification, are for interpreting the principles of the present disclosure.

[0031] With reference to the drawings, according to the following detailed description, the present disclosure can be more clearly understood.

[0032]

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[0033] It should be understood that the dimensions of each part shown in the drawings are not drawn in accordance with the actual proportional relationship. Note that the same or similar reference numerals indicate the same or similar components.

Mode for Carrying Out the Invention

[0034] Hereinafter, with reference to the drawings, each exemplary embodiment of the present disclosure will be described in detail. The description of the exemplary embodiments is merely illustrative and is in no way intended as a limitation on the present disclosure and its application or use. The present disclosure is not limited to the embodiments described in the specification and can be realized in many different forms. These embodiments are provided to thoroughly and completely disclose the present disclosure and to fully show the scope of the present disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the relative arrangements of the components and steps, the components of the materials, the numerical expressions and numerical values described in these embodiments are not limited and should be construed merely as exemplary.

[0035] The terms “first,” “second,” and similar terms used in the present disclosure do not indicate any order, quantity, or importance, but are used only to distinguish different parts. Terms such as “having” and “including” mean that the element appearing before the term includes the element appearing after the term, but it is not intended to exclude the possibility of including other elements. “Above,” “below,” “left,” “right,” etc. are used only to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0036] In the present disclosure, when it is described that a specific element is located between a first element and a second element, there may or may not be an intervening element between the specific element and the first element or the second element. When it is described that a specific element is connected to another element, the specific element may be directly connected to the other element without having an intervening element, or may have an intervening element without being directly connected to the other element.

[0037] All terms used in this disclosure (including technical or chemical terms) shall have the same meaning as understood by those skilled in the art to which this disclosure pertains, unless otherwise specified. It should also be understood that terms defined in general dictionaries and the like should be interpreted as having a meaning consistent with their meaning in the context of the related art, and should not be interpreted in an idealized or overly formalized sense unless clearly defined in the specification.

[0038] Although the technologies, methods, and devices known to those skilled in the relevant art will not be discussed in detail, where appropriate, the said technologies, methods, and devices should be regarded as part of the specification.

[0039] The inventors of the present disclosure have found that in the related art, during the formation process of the TFT of the array substrate, in the overlapping connection region between the source or drain and the active layer, the active layer is etched twice, resulting in missing portions appearing in the active layer. As a result, the conduction path in the overlapping connection region between the source or drain and the active layer becomes very short, the current flowing ability is limited, and contact failure is likely to occur, which may affect the performance of the display product.

[0040] In view of this, the embodiments of the present disclosure provide an array substrate for reducing the possibility of missing portions appearing in the active layer.

[0041] FIG. 1 is a cross-sectional schematic view showing an array substrate according to an embodiment of the present disclosure.

[0042] As shown in FIG. 1, the array substrate includes a base structure 110.

[0043] As shown in FIG. 1, the array substrate further includes an active layer 120 on the base structure 110. For example, the material of the active layer includes semiconductor materials such as IGZO (indium gallium zinc oxide).

[0044] As shown in FIG. 1, the array substrate further includes a patterned first insulating layer 130 on the side far from the base structure in the active layer 120. The first insulating layer 130 has a first through-hole 141 that exposes a part of the active layer 120. The first insulating layer 130 covers the active layer 120. For example, the material of the first insulating layer includes an inorganic insulating material (such as silicon dioxide or silicon nitride, etc.).

[0045] As shown in FIG. 1, the array substrate further includes a first conductive layer 151 that is in the first through-hole 141 and contacts the active layer 120. In some embodiments, the material of the first conductive layer includes a metal material. For example, the material of the first conductive layer includes a transparent conductive material. For example, the transparent conductive material includes ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), etc. Here, since a transparent conductive material is adopted for the first conductive layer, the light transmittance of the array substrate can be improved.

[0046] As shown in FIG. 1, the array substrate further includes a first connection member 161 on the side far from the base structure 110 in the first insulating layer 130. The first connection member 161 is in contact with the first conductive layer 151. The material of the first connection member 161 includes a metal material such as copper, for example. For example, the first connection member may be a source or a drain. The first connection member 161 covers a first part of the first conductive layer 151 and does not cover a second part of the first conductive layer 151 (to be described later in conjunction with FIG. 3).

[0047] So far, an array substrate according to some embodiments of the present disclosure has been provided. The array substrate includes a base structure, an active layer on the base structure, and a patterned first insulating layer on the side of the active layer far from the base structure, the first insulating layer having a first through hole that exposes a part of the active layer, a first conductive layer in the first through hole and in contact with the active layer, and a first connection member on the side of the first insulating layer far from the base structure, the first connection member being in contact with the first conductive layer, covering a first part of the first conductive layer, and not covering a second part of the first conductive layer. In this embodiment, since the first conductive layer is formed in the first through hole of the first insulating layer, during the manufacturing process, the first conductive layer can protect a part of the active layer below it to a certain extent. As a result, the possibility of a missing part appearing in the active layer is reduced, and further, the performance of the array substrate and the display device formed thereby is improved.

[0048] As shown in FIG. 1, the first insulating layer 130 further has a second through hole 142 that exposes another part of the active layer 120.

[0049] In some embodiments, as shown in FIG. 1, the array substrate further includes a second conductive layer 152 in the second through hole 142. The second conductive layer 152 fills the second through hole 142. For example, the material of the second conductive layer includes a transparent conductive material. For example, the transparent conductive material includes ITO or IZO, etc. Here, since a transparent conductive material is adopted for the second conductive layer, the light transmittance of the array substrate can be improved.

[0050] Similar to the aforementioned first conductive layer, since the second conductive layer can protect a part of the active layer below it, the possibility of a missing part appearing in the active layer is reduced, and further, the performance of the array substrate and the display device formed thereby is improved.

[0051] In some embodiments, as shown in FIG. 1, the width of the overlapping portion of the first conductive layer 151 and the active layer 120 along the direction from the first connection member towards the gate is smaller than the width of the overlapping portion of the second conductive layer 152 and the active layer 120 along the direction from the first connection member towards the gate. In other words, the second conductive layer 152 is relatively larger in size. For example, the area or width of the second conductive layer 152 (i.e., the lateral dimension shown in the cross-sectional view) is larger than the area or width of the first conductive layer 151. In this way, the second conductive layer can also function as one of the electrode plates of the capacitor. This is advantageous for the formation of the transparent capacitance structure and the improvement of the capacitance and conductivity capabilities.

[0052] In some embodiments, as shown in FIG. 1, the array substrate further includes a second connection member 162 electrically connected to the second conductive layer 152. The second connection member 162 is in contact with the second conductive layer 152. The material of the second connection member 162 includes a metal material such as copper, for example. The second connection member may be a source or a drain. For example, the first connection member 161 is a source and the second connection member 162 is a drain. Further, for example, the first connection member 161 is a drain and the second connection member 162 is a source.

[0053] In some embodiments, as shown in FIG. 1, the array substrate further includes a gate 163 located on the side of the first insulating layer 130 far from the active layer 120. The material of the gate 163 includes a metal material such as copper, for example.

[0054] As shown in FIG. 1, the second connection member 162 and the gate 163 are in the same layer. The first connection member 161 and the gate 163 are also in the same layer. Both the first connection member 161 and the second connection member 162 are spaced apart from the gate 163. The gate 163 is located between the first connection member 161 and the second connection member 162.

[0055] It should be noted that the "same layer" refers to a layer structure formed by adopting the same film-forming process to form a film layer for specific pattern formation, and then using the same mask plate to pattern the film layer by a single patterning process. For example, two structural layers in the same layer may be located in the same structural layer or in different structural layers. Two structural layers in the same layer may be located at different heights or may have different thicknesses.

[0056] In some embodiments, as shown in FIG. 1, the base structure 110 includes a base substrate 111. The base substrate includes a rigid substrate or a flexible substrate, etc. For example, the base substrate may include a glass substrate or the like.

[0057] As shown in FIG. 1, the base structure 110 further includes a light-shielding layer 112 on the base substrate 111. The orthographic projection of the light-shielding layer 112 on the base substrate 111 at least partially overlaps with the orthographic projection of the active layer 120 on the base substrate 111. For example, the material of the light-shielding layer includes a metal material such as aluminum, molybdenum, or copper.

[0058] As shown in FIG. 1, the base structure 110 further includes a third conductive layer 113 covering the light-shielding layer 112. The third conductive layer may extend from above the light-shielding layer 112 to above the base substrate 111. The third conductive layer 113 can function as the other electrode plate of the capacitor.

[0059] It should be noted that in some other embodiments, the positions of the light-shielding layer 112 and the third conductive layer 113 may be interchanged. For example, the third conductive layer 113 is located on the base substrate 111, and the light-shielding layer 112 is located on the side far from the base substrate in the third conductive layer, that is, the light-shielding layer may be covered on the third conductive layer.

[0060] In some embodiments, the material of the third conductive layer 113 includes a transparent conductive material. For example, the transparent conductive material includes ITO, IZO, or the like. Here, since a transparent conductive material is employed for the third conductive layer, the light transmittance of the array substrate can be improved.

[0061] As shown in FIG. 1, the base structure 110 further includes a buffer layer 114 between the third conductive layer 113 and the active layer 120. For example, the buffer layer may include an inorganic insulating material such as silicon dioxide. The buffer layer 114 covers the third conductive layer 113, the base substrate 111, and the like.

[0062] In some embodiments, as shown in FIG. 1, the base substrate 110 may further include a wiring 115. The first connection member 161 may be electrically connected to the wiring 115 through a third through hole (as a conductive through hole) 143 that penetrates the first insulating layer 130 and the buffer layer 114. The wiring 115 may be in the same layer as the light shielding layer 112. For example, the material of the wiring 115 is the same as the material of the light shielding layer 112. The wiring 115 is spaced apart from the light shielding layer 112.

[0063] In some embodiments, the orthographic projection of the first conductive layer 151 on the base substrate 111 at least partially overlaps with the orthographic projection of the light shielding layer 112 on the base substrate 111. The light shielding layer can play a role in blocking light.

[0064] In some embodiments, the thickness of the third conductive layer 113 is greater than the thickness of the second conductive layer 152. The thickness of the second conductive layer 152 is equal to the thickness of the first conductive layer 151. Thereby, since the second conductive layer is relatively thin, the light transmittance of the array substrate can be further improved. Also, since the thickness of the third conductive layer 113 is relatively thick, the electrical resistance can be reduced.

[0065] For example, the thickness of the third conductive layer 113 is from 3000 angstroms to 5000 angstroms. For example, the thickness of the second conductive layer 152 (or the first conductive layer 151) is from 500 angstroms to 1000 angstroms.

[0066] In some embodiments, the thickness of the first conductive layer 151 is greater than the thickness of the active layer 120. For example, the thickness of the active layer 120 is from 300 angstroms to 500 angstroms.

[0067] In some embodiments, as shown in FIG. 1, the area of the overlapping portion between the first connection member 161 and the first conductive layer 151 is smaller than the area of the overlapping portion between the second connection member 162 and the second conductive layer 151. Here, since the area of the overlapping portion between the second connection member and the second conductive layer is relatively large, the contact electrical resistance can be reduced.

[0068] In some embodiments, as shown in FIG. 1, the first insulating layer 130 includes a gate insulating layer 131 located below the gate 163.

[0069] As shown in FIG. 1, the active layer 120 includes a first conductivized region 121 electrically connected to the first connection member 161, a second conductivized region 122 electrically connected to the second connection member 162, and a channel region 123 between the first conductivized region 121 and the second conductivized region 122. The channel region 123 and the gate insulating layer 131 are aligned at their edges. Here, the first conductive layer 151 contacts the first conductivized region 121, and the second conductive layer 152 contacts the second conductivized region 122. By conductivizing the portions on both sides of the channel region in the active layer, the contact electrical resistance between the first conductive layer and the active layer and the contact electrical resistance between the second conductive layer and the active layer can be reduced, facilitating current transmission, and improving the performance of the array substrate and the display device formed thereby.

[0070] FIG. 3 is an enlarged schematic diagram schematically showing a portion of the frame 201 of the array substrate in FIG. 1.

[0071] As shown in FIG. 3, the first conductive layer 151 includes a first portion 1511 far from the gate 163 and a second portion 1512 close to the gate 163. The first portion 1511 is completely covered by the first connection member 161, and the second portion 1512 is not covered by the first connection member 161.

[0072] In some embodiments, as shown in FIG. 3, the width d1 of the overlapping portion of the first connection member 161 and the first conductive layer 151 along the direction from the first connection member 161 toward the gate 163 is smaller than the distance d4 between the edge of the first conductive layer 151 and the channel region 123.

[0073] In some embodiments, the area of the first conductor layer 151 is larger than the area of the overlapping portion of the first connection member 161 and the first conductive layer 151 (i.e., the portion corresponding to the width d1). This is advantageous for sufficient contact between the first connection member and the first conductive layer and for preventing the occurrence of poor contact problems.

[0074] In some embodiments, the area of the first conductor layer 151 is smaller than the area of the channel region 123. Since the area of the channel region is relatively large, it is advantageous for improving the performance of the thin film transistor.

[0075] It should be noted that the "area" described in the present disclosure refers to the surface area of the structural layer that is parallel to the plane where the base substrate is located. For example, the area may be the area of the upper surface of the structural layer. For example, the area of the upper surface of the first conductor layer 151 may be the area of the first conductor layer 151, and the area of the upper surface of the channel region 123 may be the area of the channel region 123, and so on.

[0076] In some embodiments, the distance d3 between the first conductive layer 151 and the gate 163 is greater than the width d1 of the overlapping portion of the first connection member 161 and the first conductive layer 151 along the direction from the first connection member towards the gate, and the width d1 of the overlapping portion of the first connection member 161 and the first conductive layer 151 along the direction from the first connection member towards the gate is greater than the width d2 of the second portion (i.e., the portion not covered by the first connection member 161) 1512 of the first conductive layer 151 along the direction from the first connection member towards the gate. That is, d3>d1>d2. Such a dimension design is advantageous for improving the performance of the thin film transistor, so the performance of the array substrate and the display device formed thereby is improved.

[0077] Also, as shown in FIG. 3, there is a gap 301 between the first conductive layer 151 and the gate insulating layer 131.

[0078] Returning to FIG. 1, in some embodiments, the array substrate further includes a second insulating layer 171 covering the first connection member 161, the second connection member 162, and the gate 163. For example, the material of the second insulating layer 171 includes at least one of silicon dioxide or silicon nitride.

[0079] As shown in FIG. 1, the array substrate further includes a planarization layer 172 on the side of the second insulating layer 171 far from the base structure 110. For example, the material of the planarization layer includes an organic insulating material such as resin.

[0080] As shown in FIG. 1, the array substrate further includes a first electrode layer 181 and a pixel defining layer 174 on the side of the planarization layer 172 far from the base structure 110. The first electrode layer 181 is electrically connected to the second connection member 162 (e.g., via a conductive through hole). The pixel defining layer 174 has a first opening 1742 exposing at least a part of the first electrode layer 181. For example, the first electrode layer is an anode layer. For example, the material of the first electrode layer 181 includes a metal such as copper, silver, aluminum or an aluminum alloy, or a transparent conductive material such as ITO or IZO.

[0081] As shown in FIG. 1, the array substrate further includes a light-emitting layer 180 that is at least located within the first opening 1742. The light-emitting layer includes a light-emitting layer for emitting red light, a light-emitting layer for emitting green light, or a light-emitting layer for emitting blue light.

[0082] As shown in FIG. 1, the array substrate further includes a second electrode layer 182 that is electrically connected to the light-emitting layer 180. The second electrode layer 182 covers the pixel defining layer 174 and the light-emitting layer 180. The second electrode layer may be a cathode layer. For example, the material of the second electrode layer 182 includes a metal such as copper, silver, aluminum, or an aluminum alloy, or a transparent conductive material such as ITO or IZO.

[0083] In some embodiments, the array substrate may further include other functional layers between the first electrode layer 181 and the second electrode layer 182, such as an electron transport layer, a hole transport layer, an electron blocking layer, or a hole blocking layer, etc. Therefore, the scope of the present disclosure is not limited thereto.

[0084] In some embodiments, as shown in FIG. 1, the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the third conductive layer 113 on the base substrate 111 along the direction from the first connection member to the gate is smaller than the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the first electrode layer 181 on the base substrate 111 along the direction from the first connection member to the gate. This is advantageous for improving the light transmittance of the array substrate.

[0085] In some embodiments, as shown in FIG. 1, the width of the overlapping portion between the orthographic projection of the second conductive layer 152 on the base substrate 111 and the orthographic projection of the third conductive layer 113 on the base substrate 111, along the direction from the first connection member towards the gate, is smaller than the width of the overlapping portion between the orthographic projection of the third conductive layer 113 on the base substrate 111 and the orthographic projection of the first electrode layer 181 on the base substrate 111, along the direction from the first connection member towards the gate. This is advantageous for improving the light transmittance of the array substrate.

[0086] The present disclosure provides an array substrate. As shown in FIG. 1, the array substrate includes a base structure 110 and a thin film transistor on the base structure 110.

[0087] The thin film transistor includes an active layer 120 on the base structure 110. The thin film transistor further includes a patterned first insulating layer 130 on the side of the active layer 120 far from the base structure. The first insulating layer 130 has a first through hole 141 exposing a part of the active layer 120. The thin film transistor further includes a first conductive layer 151 in the first through hole 141 and in contact with the active layer 120. The thin film transistor further includes a first connection member 161, a second connection member 162, and a gate 163 on the side of the first insulating layer 130 far from the base structure. The first connection member 161 is in contact with the first conductive layer 151. The first connection member 161, the second connection member 162, and the gate 163 are in the same layer and spaced apart from each other. The gate 163 is located between the first connection member 161 and the second connection member 162.

[0088] As shown in FIGS. 1 and 3, the active layer 120 includes a first conductive region 121 electrically connected to the first connection member 161, a second conductive region 122 electrically connected to the second connection member 162, and a channel region 123 between the first conductive region 121 and the second conductive region 122. The channel region 123 is below the gate 163.

[0089] As shown in FIG. 3, the first conductive layer 151 includes a first portion 1511 far from the gate 163 and a second portion 1512 close to the gate 163. The first portion 1511 is completely covered by the first connection member 161, and the second portion 1512 is not covered by the first connection member 161. The orthographic projection of the first conductive layer 151 on the base structure 110 is located inside the orthographic projection of the active layer 120 on the base structure 110.

[0090] In the above embodiment, since the first conductive layer is formed in the first through hole of the first insulating layer, during the manufacturing process, the first conductive layer can protect a part of the active layer below it to a certain extent. As a result, the possibility of the appearance of missing parts in the active layer is reduced, and further, the performance of the array substrate and the display device formed thereby is improved.

[0091] In some embodiments, as shown in FIG. 3, the width d2 of the second portion 1512 along the direction from the first connection member to the gate is smaller than the width d1 of the first portion 1511 along the direction from the first connection member to the gate. Here, the width of the first portion 1511 is equal to the width of the overlapping portion between the first connection member 161 and the first conductive layer 151, and both are d1.

[0092] For example, the width d1 of the first portion 1511 is 2 to 5 times the width d2 of the second portion 1512.

[0093] In some embodiments, as shown in FIG. 3, the width d2 of the second portion 1512 along the direction from the first connection member to the gate is smaller than the width d5 of the channel region 123 along the direction from the first connection member to the gate.

[0094] In some embodiments, as shown in FIG. 3, the thickness H2 of the second portion 1512 is smaller than the thickness H1 of the first portion 1511.

[0095] In some embodiments, as shown in FIGS. 1 and 3, the active layer 120 may further include a semiconductor region (which may be referred to as a first semiconductor region) 124. The semiconductor region 124 is located on the side far from the channel region 123 in the first conducting region 121. The width d2 of the second portion 1512 along the direction from the first connecting member towards the gate is smaller than the width d6 of the semiconductor region 124 along the direction from the first connecting member towards the gate.

[0096] In some other embodiments, the active layer may further include another semiconductor region (not shown) which may be referred to as a second semiconductor region. The second semiconductor region is located on the side far from the channel region 123 in the second conducting region 122.

[0097] FIG. 2 is a schematic cross-sectional view showing an array substrate according to another embodiment of the present disclosure.

[0098] The structure of the array substrate shown in FIG. 2 is similar to the structure of the array substrate shown in FIG. 1. Different from the structure of the array substrate shown in FIG. 1, in the array substrate shown in FIG. 2, the second through hole 142 further exposes a part of the buffer layer 114, and accordingly, the second conductive layer 152 includes a third portion 1521 located on the surface of the active layer 120 and a fourth portion 1522 located on the surface of the buffer layer 114. For example, in the structure shown in FIG. 2, the lateral dimension of the active layer 120 is smaller than the lateral dimension of the active layer in FIG. 1, and the area of the third portion of the second conductive layer 152 is smaller than the area of the overlapping portion between the second conductive layer and the active layer in FIG. 1. Therefore, in the array substrate shown in FIG. 2, the area of the overlapping portion between the second conductive layer and the active layer is reduced, which can improve the light transmittance of the array substrate.

[0099] FIG. 4 is a plan view schematically showing a partial structure of an array substrate according to an embodiment of the present disclosure.

[0100] For the convenience of illustration, FIG. 4 shows the first conductor region 121, the first conductive layer 151, and the first connection member 161 of the active layer of the array substrate. As shown in FIG. 4, due to the presence of the first conductive layer 151, there is no missing part in the first conductor region 121, so that current can flow from the first connection member to the first conductor region 121 relatively uniformly, providing the signal transmission ability of the array substrate.

[0101] In some embodiments of the present disclosure, a display device is further provided, including the array substrate described above, for example, the array substrate shown in FIG. 1 or FIG. 2. For example, the display device may be any product or component having a display function such as a display panel, a mobile phone, a tablet PC, a television, a display, a notebook PC, a digital photo frame, a navigator, etc.

[0102] FIG. 5 is a flowchart showing a method for manufacturing an array substrate according to an embodiment of the present disclosure. As shown in FIG. 5, the manufacturing method includes steps S502 to S508. FIGS. 6A to 6I are cross-sectional schematic views showing the structures at some stages during the manufacturing process of the array substrate according to some embodiments of the present disclosure. FIGS. 9A to 9C are cross-sectional schematic views showing the structures at some stages during the manufacturing process of the array substrate according to some other embodiments of the present disclosure. Hereinafter, in conjunction with FIGS. 5, 6A to 6I, and FIGS. 9A to 9C, the manufacturing process of the array substrate according to some embodiments of the present disclosure will be described in detail.

[0103] As shown in FIG. 5, in step S502, an active layer is formed on the base structure.

[0104] For example, as shown in FIG. 6A, an active layer 120 is formed on the base structure 110, for example, through a deposition process. The specific structure of the base structure 110 has been described in detail previously and will not be repeated here.

[0105] Returning to FIG. 5, in step S504, a patterned first insulating layer having a first through hole that exposes a part of the active layer is formed on the side of the base structure in the active layer that is far from the base structure.

[0106] For example, referring to FIGS. 6A to 6F, the formation process of the patterned first insulating layer can be described in detail.

[0107] As shown in FIG. 6A, for example, through a deposition process, a first insulating layer 130 is formed on the side of the base structure 110 in the active layer 120 that is far from the base structure.

[0108] Next, as shown in FIG. 6B, a first mask layer 610 is formed on the side of the first insulating layer 130 that is far from the base structure 110. For example, the material of the first mask layer is a positive photoresist.

[0109] Next, as shown in FIGS. 6B and 6C, for example, through exposure and development techniques, the first mask layer 610 is patterned using a patterned first mask plate 621 to form a patterned first mask layer 610, so that the patterned first mask layer has a second opening 6102 that exposes a part of the first insulating layer 130.

[0110] Next, as shown in FIGS. 6D and 6E, using the patterned first mask layer 610, through an etching process (for example, dry etching), the above-mentioned part of the first insulating layer 130 exposed by the second opening 6102 is removed to form a first through hole 141, thereby forming a patterned first insulating layer 130. The first through hole 141 exposes a part of the active layer 120.

[0111] Returning to FIG. 5, in step S506, a first conductorization process is performed on the exposed part in the active layer.

[0112] For example, as shown in FIG. 6E, a first conductor formation process may be performed on the exposed portion in the active layer 120. For example, a dry etching process may be employed to perform the first conductor formation process with He gas (helium gas).

[0113] Next, as shown in FIG. 6F, the first mask layer 610 is removed.

[0114] Returning to FIG. 5, in step S508, a first conductive layer in contact with the active layer is formed within the first through hole.

[0115] For example, with reference to FIGS. 6G to 6I, the formation process of the first conductive layer can be described in detail.

[0116] For example, as shown in FIG. 6G, through a deposition process, the first conductive layer 151 is formed on the side of the patterned first insulating layer 130 far from the base structure 110 and within the first through hole 141. For example, the material of the first conductive layer 151 includes a transparent conductive material.

[0117] Next, as shown in FIG. 6H, a second mask layer 612 is formed on the side of the first conductive layer 151 far from the base structure 110, and by performing exposure and development processes on the second mask layer 612 using the aforementioned first mask plate 621, the structure of the second mask layer 612 shown in FIG. 6H is formed. For example, the material of the second mask layer is a negative photoresist.

[0118] Next, as shown in FIG. 6H, the first conductive layer 151 is etched to remove the portion of the first conductive layer 151 not blocked by the second mask layer 612 and leave the portion of the first conductive layer 151 blocked by the second mask layer 612, thereby forming a structure as shown in FIG. 6I.

[0119] Next, as shown in FIG. 6I, the second mask layer 612 is removed.

[0120] So far, the patterned first conductive layer 151 is formed, and the first conductive layer 151 can protect the underlying active layer 120 from being etched as much as possible.

[0121] Returning to FIG. 5, in step S510, through a deposition process, a connection material layer is formed on the side of the first insulating layer far from the base structure.

[0122] For example, as shown in FIG. 9A, through a deposition process, a connection material layer 160 is formed on the side of the first insulating layer 130 far from the base structure 110. The material of the connection material layer 160 includes a metal such as copper.

[0123] Returning to FIG. 5, in step S512, the connection material layer is patterned using the patterned mask layer to form a first connection member that contacts the first conductive layer, covers the first part of the first conductive layer, and does not cover the second part of the first conductive layer.

[0124] For example, as shown in FIG. 9A, a patterned mask layer (which can be called the third mask layer) 637 is formed on the side of the connection material layer far from the base structure 110. For example, the material of the third mask layer is a photoresist.

[0125] Next, as shown in FIG. 9B, for example, through a wet etching process, the connection material layer 160 is patterned using the third mask layer 637 to form the first connection member 161. Also, in this process, the second connection member 162, the gate 163, etc. may also be formed. During the wet etching process, due to a part of the connection material layer below the edge of the third mask layer being etched by the etching solution, the formed first connection member may be recessed inward.

[0126] In this way, the first connection member is formed.

[0127] Returning to FIG. 5, in step S514, using the mask layer, the first insulating layer is etched through a self-alignment process to expand the first through-hole, and among them, another part of the active layer is exposed by the expanded first through-hole.

[0128] For example, as shown in FIG. 9C, using the patterned mask layer (i.e., the third mask layer) 637, the first insulating layer 130 is etched through a self-alignment process to expand the first through-hole 141, and among them, another part of the active layer 120 is exposed by the expanded first through-hole 141. For example, the etching is dry etching. Here, etching is performed on the entire surface of the first insulating layer to form a gap between the first conductive layer and the gate insulating layer, that is, the aforementioned gap 301.

[0129] Returning to FIG. 5, in step S516, a second conductor formation process is performed on the exposed another part in the active layer.

[0130] For example, as shown in FIG. 9C, a second conductor formation process is performed on the exposed another part in the active layer 120. For example, a dry etching process may be employed to perform the second conductor formation process with He gas (helium gas). In this process, since the first conductive layer 151 exists, the part of the active layer directly below the first conductive layer 151 can be protected from being etched.

[0131] Next, the third mask layer 637 is removed.

[0132] So far, a method for manufacturing an array substrate according to some embodiments of the present disclosure has been provided. The manufacturing method includes forming an active layer on a base structure, forming a patterned first insulating layer having a first through hole that exposes a part of the active layer on a side of the active layer far from the base structure, performing a first conductor formation process on the exposed part of the active layer, forming a first conductive layer in contact with the active layer in the first through hole, forming a connection material layer on a side of the first insulating layer far from the base structure through a deposition process, patterning the connection material layer using a patterned mask layer to form a first connection member in contact with the first conductive layer, covering a first part of the first conductive layer and not covering a second part of the first conductive layer, using the mask layer to etch the first insulating layer through a self-alignment process to expand the first through hole, so that another part of the active layer is exposed by the expanded first through hole, and performing a second conductor formation process on the another exposed part of the active layer. The manufacturing method can reduce the possibility of missing parts in the active layer and further improve the performance of the array substrate and the display device formed thereby.

[0133] Furthermore, in the above manufacturing process, since a negative photoresist is used for the second mask layer, the above-mentioned first mask plate can be used for exposure and development, and there is no need to separately manufacture the mask plate. As a result, the complexity of the process is reduced.

[0134] FIG. 7 is a cross-sectional schematic view showing a structure of a stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure. In FIG. 7, cross-sectional schematic views of structures at a stage in the formation process of a first conductive layer according to some other embodiments are shown.

[0135] For example, as shown in FIG. 7, after forming the structure shown in FIG. 6E, a first conductive layer 151 is formed on the patterned first mask layer 610 and in the first through hole 141 of the first insulating layer 130 through a deposition process.

[0136] Next, through the lift-off process, the first mask layer 610 and the portion of the first conductive layer 151 on the first mask layer 610 are removed, and the portion of the first conductive layer 151 within the first through-hole 141 is left, thereby forming a structure as shown in FIG. 6I.

[0137] In this embodiment, since the lift-off process is adopted, there is no need to add a separate masking process, and the complexity of the process is further reduced.

[0138] FIG. 8 is a cross-sectional schematic view showing a structure at a stage in the manufacturing process of an array substrate according to another embodiment of the present disclosure. In FIG. 8, cross-sectional schematic views of structures at a stage in the formation process of the first conductive layer according to several other embodiments are shown.

[0139] For example, as shown in FIG. 8, after forming the structure shown in FIG. 6F, using the patterned second mask plate 630, the first conductive layer 151 is formed within the first through-hole 141 of the first insulating layer 130 by a vapor deposition process, that is, the structure shown in FIG. 6I is formed. As shown in FIG. 8, the second mask plate 630 has through-holes (which can be called fourth through-holes), and the openings are aligned with the first through-holes 141. For example, the second mask plate is an FMM mask plate (Fine Metal Mask). Further, FIG. 8 further shows an evaporation source 635. The material of the evaporation source includes a transparent conductive material (such as ITO or IZO, etc.).

[0140] In this embodiment, since the evaporation process is adopted to form the first conductive layer, the complexity of the process can be reduced.

[0141] FIGS. 10A to 10C are cross-sectional schematic views showing structures at several stages during the manufacturing process of an array substrate according to several other embodiments of the present disclosure. Hereinafter, in conjunction with FIGS. 10A to 10C and FIG. 1, the manufacturing process of an array substrate according to several other embodiments of the present disclosure will be described in detail.

[0142] First, as shown in FIG. 10A, a base structure is prepared. The step of preparing the base structure includes the following steps.

[0143] For example, as shown in FIG. 10A, a light-shielding layer 112 is formed on a base substrate 111 through a deposition and patterning process. Also, wiring 115 is formed.

[0144] Next, as shown in FIG. 10A, a third conductive layer 113 covering the light-shielding layer 112 is formed through a deposition and patterning process.

[0145] In some other embodiments, the third conductive layer 113 may be formed on the base substrate 111 through a deposition and patterning process, and then the light-shielding layer 112 may be formed on the third conductive layer 113 through a deposition and patterning process.

[0146] Next, as shown in FIG. 10A, a buffer layer 114 covering the third conductive layer 113 is formed through a deposition process.

[0147] So far, the base structure 110 is formed.

[0148] Next, as shown in FIG. 10B, an active layer 120, a first insulating layer 130, a first through-hole 141, a first conductive layer 151, and a first connection member 161 are formed by adopting the above-described process. Here, a second through-hole 142, a third through-hole 143, a second conductive layer 152, a second connection member 162, and a gate 163 are also formed.

[0149] It should be noted that the second conductive layer 152 is formed together with the first conductive layer 151 by adopting the same process, and the second connection member 162 and the gate 163 are formed by adopting the same patterning process as the first connection member 161, which will not be repeated here.

[0150] It should be further noted that, simultaneously with the formation of the first through-hole 141, the second through-hole 142 and the third through-hole 143 may also be formed. The formation processes of the second through-hole 142 and the third through-hole 143 are similar to the formation process of the first through-hole 141, and thus will not be repeatedly described herein.

[0151] Next, as shown in FIG. 10B, through a deposition process, a second insulating layer 171 covering the first connection member 161, the second connection member 162, and the gate 163 is formed.

[0152] Next, as shown in FIG. 10C, a planarization layer 172 is formed on the side of the second insulating layer 171 far from the base structure 110.

[0153] Next, as shown in FIG. 10C, a first electrode layer 181 electrically connected to the second connection member 162 is formed on the side of the planarization layer 172 far from the base structure 110.

[0154] Next, as shown in FIG. 10C, a pixel defining layer 174 is formed on the side of the planarization layer 172 far from the base structure 110. The pixel defining layer 174 has a first opening 1742 exposing at least a part of the first electrode layer 181.

[0155] Next, as shown in FIG. 1, a light-emitting layer 180 is formed at least within the first opening 1742.

[0156] Next, as shown in FIG. 1, through a deposition process, a second electrode layer 182 electrically connected to the light-emitting layer 180 is formed.

[0157] So far, a method for manufacturing an array substrate according to some embodiments of the present disclosure has been provided. The manufacturing method can reduce the possibility of the appearance of missing parts in the active layer, and further improve the performance of the array substrate and the display device formed thereby.

[0158] So far, each embodiment of the present disclosure has been described in detail. To avoid obscuring the concept of the present disclosure, details well known in the art are not described. A person skilled in the art will be able to fully understand how to implement the technical solutions disclosed in this specification based on the above description.

[0159] Although some specific embodiments of the present disclosure have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustrations are merely for the purpose of explanation and not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified or some technical features can be equivalently substituted without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. Array substrate, Base structure and, The active layer on the base structure, A patterned first insulating layer located on the side of the active layer furthest from the base structure, the first insulating layer having first through-holes that expose a portion of the active layer, A first conductive layer located within the first through-hole and in contact with the active layer, An array substrate comprising a first connecting member located on the side of the first insulating layer furthest from the base structure, which contacts the first conductive layer, covers a first portion of the first conductive layer, and does not cover a second portion of the first conductive layer.

2. The first insulating layer further has a second through-hole that exposes another part of the active layer, The aforementioned array substrate is The second conductive layer located within the second through-hole, A second connecting member electrically connected to the second conductive layer, The first insulating layer further includes a gate located on the side furthest from the active layer, The array substrate according to claim 1, wherein the second connecting member and the gate are in the same layer, and both the first connecting member and the second connecting member are spaced apart from the gate.

3. The aforementioned base structure is Base board and A light-shielding layer and a third conductive layer on the base substrate, wherein the orthographic projection of the light-shielding layer on the base substrate at least partially overlaps with the orthographic projection of the active layer on the base substrate, and the third conductive layer covers the light-shielding layer, or the light-shielding layer covers the third conductive layer, The array substrate according to claim 2, further comprising a buffer layer located between the third conductive layer and the active layer.

4. The orthographic projection of the first conductive layer on the base substrate overlaps at least partially with the orthographic projection of the light-shielding layer on the base substrate. The aforementioned second through-hole further exposes a portion of the buffer layer, The second conductive layer includes a third portion located on the surface of the active layer and a fourth portion located on the surface of the buffer layer. The materials of the first conductive layer, the second conductive layer, and the third conductive layer all include a transparent conductive material. The array substrate according to claim 3, wherein the thickness of the third conductive layer is greater than the thickness of the second conductive layer, and the thickness of the second conductive layer is equal to the thickness of the first conductive layer.

5. The array substrate according to claim 1, wherein the thickness of the first conductive layer is greater than the thickness of the active layer.

6. The array substrate according to claim 2, wherein the area of ​​the overlap portion between the first connecting member and the first conductive layer is smaller than the area of ​​the overlap portion between the second connecting member and the second conductive layer.

7. The first insulating layer includes a gate insulating layer located below the gate. The active layer includes a first conductive region electrically connected to the first connecting member, a second conductive region electrically connected to the second connecting member, and a channel region between the first conductive region and the second conductive region, wherein the edges of the channel region and the gate insulating layer are aligned. The array substrate according to claim 3, wherein the width of the overlap portion between the first connecting member and the first conductive layer, along the direction toward the gate, is smaller than the distance between the edge of the first conductive layer and the channel region.

8. The array substrate according to claim 1, wherein the area of ​​the first conductive layer is larger than the area of ​​the overlap portion between the first connecting member and the first conductive layer.

9. The array substrate according to claim 7, wherein the area of ​​the first conductive layer is smaller than the area of ​​the channel region.

10. The array substrate according to claim 2, wherein the width of the overlap portion between the first conductive layer and the active layer, along the direction from the first connecting member toward the gate, is smaller than the width of the overlap portion between the second conductive layer and the active layer, along the direction from the first connecting member toward the gate.

11. The array substrate according to claim 2, wherein the distance between the first conductive layer and the gate is greater than the width of the overlap portion of the first connecting member and the first conductive layer in the direction toward the gate, and the width of the overlap portion of the first connecting member and the first conductive layer in the direction toward the gate is greater than the width of the second portion of the first conductive layer in the direction toward the gate.

12. The first connecting member, the second connecting member, and the second insulating layer covering the gate, The planarization layer located on the side of the second insulating layer that is far from the base structure, A first electrode layer and a pixel defining layer located on the side of the planarization layer furthest from the base structure, wherein the first electrode layer is electrically connected to the second connecting member, and the pixel defining layer has a first aperture that exposes at least a portion of the first electrode layer. A light-emitting layer located at least within the first opening, Claim 3: The array substrate further comprising a second electrode layer electrically connected to the light-emitting layer.

13. The array substrate according to claim 12, wherein the width of the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the third conductive layer on the base substrate, along the direction toward the gate, is smaller than the width of the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the first electrode layer on the base substrate, along the direction toward the gate.

14. The array substrate according to claim 12, wherein the width of the overlapping portion between the orthographic projection of the second conductive layer on the base substrate and the orthographic projection of the third conductive layer on the base substrate, along the direction toward the gate, is smaller than the width of the overlapping portion between the orthographic projection of the third conductive layer on the base substrate and the orthographic projection of the first electrode layer on the base substrate, along the direction toward the gate.

15. Array substrate, Base structure and, Includes a thin-film transistor on the base structure, The thin-film transistor is The active layer on the base structure, A patterned first insulating layer located on the side of the active layer furthest from the base structure, the first insulating layer having first through-holes that expose a portion of the active layer, A first conductive layer located within the first through-hole and in contact with the active layer, A first connecting member, a second connecting member, and a gate located on the side of the first insulating layer furthest from the base structure, wherein the first connecting member is in contact with the first conductive layer, the first connecting member, the second connecting member, and the gate are in the same layer and spaced apart from each other, and the gate is located between the first connecting member and the second connecting member, The active layer includes a first conductive region electrically connected to the first connecting member, a second conductive region electrically connected to the second connecting member, and a channel region between the first conductive region and the second conductive region, the channel region being located below the gate. An array substrate wherein the first conductive layer includes a first portion far from the gate and a second portion close to the gate, the first portion being completely covered by the first connecting member and the second portion not being covered by the first connecting member, and the orthogonal projection of the first conductive layer on the base structure is located inside the orthogonal projection of the active layer on the base structure.

16. The array substrate according to claim 15, wherein the width of the second portion in the direction toward the gate from the first connecting member is smaller than the width of the first portion in the direction toward the gate from the first connecting member.

17. The array substrate according to claim 15, wherein the width of the second portion in the direction toward the gate from the first connecting member is smaller than the width of the channel region in the direction toward the gate from the first connecting member.

18. The array substrate according to claim 15, wherein the thickness of the second portion is smaller than the thickness of the first portion.

19. The array substrate according to claim 16, wherein the width of the first portion is 2 to 5 times the width of the second portion.

20. The active layer further includes a semiconductor region located on the side of the first conductive region that is far from the channel region, The array substrate according to claim 16, wherein the width of the second portion in the direction from the first connecting member toward the gate is smaller than the width of the semiconductor region in the direction from the first connecting member toward the gate.

21. A display device comprising an array substrate according to any one of claims 1 to 20.

22. A method for manufacturing an array substrate, Forming an active layer on the base structure, A patterned first insulating layer is formed on the side of the active layer furthest from the base structure, and the first insulating layer has first through-holes that expose a portion of the active layer. Performing a first conductor treatment on the exposed portion of the active layer, A first conductive layer is formed in the first through-hole that contacts the active layer, Through the deposition process, a connecting material layer is formed on the side of the first insulating layer that is far from the base structure, By patterning the connecting material layer using a patterned mask layer, a first connecting member that contacts the first conductive layer is formed, which covers a first portion of the first conductive layer but does not cover a second portion of the first conductive layer. Using the mask layer, the first insulating layer is etched through a self-alignment process to enlarge the first through-hole, and as a result, another part of the active layer is exposed by the enlarged first through-hole. A method for manufacturing an array substrate, comprising performing a second conductor treatment on the exposed portion of the active layer.

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