Integrated circuit with an inductor in a magnetic package

Abstract

In one example, an integrated circuit (200) includes a substrate (206), a semiconductor die (104), metal interconnects (130, 132, 134) coupled between the semiconductor die and the substrate, insulating layers (240_1, 240_2, 240_3, 240_4) coupled between the semiconductor die and the substrate and surrounding the metal interconnects, an inductor (202) coupled to the substrate, and a magnetic material (208) encapsulating the semiconductor die, the inductor, the metal interconnects, and the insulating layers and having a material different from that of the insulating layers.

Description

Technical Field

[0001] An inductor can store energy in a magnetic field when current flows through it and can provide current by discharging the stored energy. The inductor can have many applications such as proximity sensing, energy storage, starting, power transmission, and filtering. The inductor may be coupled to an integrated circuit or may be part of an integrated circuit, and the integrated circuit can include circuits that operate with the inductor to support these applications. In some examples, the inductor and circuit elements are encapsulated within an integrated circuit package, thereby reducing the footprint of the integrated circuit and shortening the interconnections between the inductor and the circuit.

Summary of the Invention

[0002] An integrated circuit includes a substrate, a semiconductor die, metal interconnects, an insulating layer, an inductor, and a magnetic material. The metal interconnects are coupled between the semiconductor die and the substrate. The insulating layer is coupled between the semiconductor die and the substrate and surrounds the metal interconnects. The inductor is coupled to the substrate. The magnetic material encapsulates the semiconductor die, the inductor, the metal interconnects, and the insulating layer and has a material different from that of the insulating layer.

[0003] A method includes forming an insulating layer on a wafer, patterning the insulating layer, and forming first metal interconnects within the patterned insulating layer. The method further includes dicing the wafer to form semiconductor dice, and the diced wafer also includes the first metal interconnects and the patterned insulating layer. The method further includes attaching the semiconductor dice to a substrate, attaching an inductor to the substrate, and depositing a magnetic material on the semiconductor dice and the inductor to form a sealing package. The method further includes forming second metal interconnects outside the sealing package, and the second metal interconnects are coupled to the first metal interconnects and the inductor.

Brief Description of the Drawings

[0004]

Figure 1A

Figure 1B

[0005]

Figure 2A

Figure 2B

Figure 2C

Figure 3A

Figure 3B

Figure 3C

Figure 4A

Figure 4B

Figure 4C

[0006]

Figure 5

[0007]

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 6F

Figure 6G

Figure 6H

Figure 6I

Figure 6J

Figure 6K

Figure 6L

Figure 6M

Figure 6N

Figure 6O

Figure 6P

Figure 6Q

Figure 6R

Figure 6S

Figure 6T

Figure 6U

Figure 6V

DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1A and FIG. 1B are schematic diagrams illustrating an exemplary integrated circuit 100. FIG. 1A and FIG. 1B illustrate a perspective view and a side view of the integrated circuit 100, respectively. Referring to FIGS. 1A and 1B, the integrated circuit 100 can include an inductor 102 and a semiconductor die 104 that are attached to a package substrate 106 and encapsulated within a sealing package 108. The inductor 102 can include a metal coil surrounding a core. Examples of inductor cores include air cores, ferrite cores, or iron powder cores. Also, the inductor 102 can be a molded inductor, and the coil and core can be encapsulated within a package made of a molding compound such as a magnetic molding compound (MMC) having metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The sealing package 108 can shield the coil and core and increase the magnetic field density, thereby improving the efficiency of the inductor 102 in the conversion between electrical energy and magnetic energy. Also, the sealing package 108 can include a molding compound such as an epoxy molding compound (EMC) that can electrically insulate the inductor 102 and the semiconductor die 104 from external electrical signals such as noise signals and electrostatic signals.

[0009] The semiconductor die 104 and the inductor 102 can form a system for supporting specific application examples such as proximity detection, energy storage, start-up, power transmission, and filtering. For example, the integrated circuit 100 can include a proximity sensor, and the semiconductor die 104 can include an oscillator and a sensing circuit. The oscillator can drive the inductor 102 using an oscillating current signal, and the sensing circuit can sense the frequency of the current signal. If there is a metal object approaching the inductor 102, the inductance of the inductor 102 can change, which can change the frequency of the current signal. The sensing circuit can detect the metal object by detecting this frequency change. As another example, the integrated circuit 100 can include a switch-mode power converter for transmitting power from a power source to a load. In such an example, the inductor 102 can provide energy storage, and the semiconductor die 104 can include switches for charging and discharging the inductor 102 to set the voltage across the load.

[0010] Also, the package substrate 106 can provide mechanical support for the inductor 102 and the semiconductor die 104, and can provide electrical connections between the inductor and the semiconductor die, and between the integrated circuit 100 and an external device. For example, the package substrate 106 can include an electrical insulating material such as a polymer, a Ajinomoto build-up film (ABF), or a ceramic material. The package substrate 106 can also include metal pads 110, 112, 114, 116, and 118, which can be copper pads, on the surface 120 to which the inductor 102 and the semiconductor die 104 are attached.

[0011] Also, the semiconductor die 104 can include a passivation layer 122 that can be coupled to the metal pads 110, 112, 114, and 116 via respective metal interconnects 130, 132, 134, and 136. Each pad can be coupled to a respective metal interconnect via a solder layer. The passivation layer 122 can insulate circuit elements within the semiconductor die 104 from the metal interconnects 130, 132, 134, and 136. The metal interconnects 130 - 136 can include, for example, copper pillars, solder bumps, and under - bump metallization (UBM) interconnects. Also, the inductor 102 can be coupled to the metal pad 118 via a solder layer. The package substrate 106 can include metal interconnects on or under the surface 120 to provide electrical connections between the inductor 102 and the semiconductor die 104, such as a metal interconnect 140 between the metal pads 116 and 118.

[0012] Package substrate 106 can also include metal pads, such as metal pads 160, 162, and 164, on a surface 150 opposite to the surface 120. The metal pads can include copper pads or pads made of other metals (e.g., silver or palladium). Package substrate 106 can also include metal interconnects, such as copper interconnects, to provide electrical connections between pads on opposite surfaces. For example, package substrate 106 can include a metal interconnect 170 between metal pads 110 and 160, a metal interconnect 172 between metal pads 112 and 162, and a metal interconnect 174 between metal pads 114 and 164. The metal pads on surface 150, as well as the interconnects, can provide electrical connections between an external device and integrated circuit 100. For example, metal pads 160, 162, and 164 can be coupled to a printed circuit board (PCB) 176 via respective solder balls 180, 182, and 184, thereby providing an electrical connection between integrated circuit 100 and an external device (e.g., a power supply) on PCB 176. Package substrate 106 can also include a solder resist layer 190 on surface 150 to shield the metal interconnects (e.g., metal interconnects 170, 172, and 174) within the package substrate from the solder balls.

[0013] FIG. 2A illustrates an example of an integrated circuit 200 that can have a reduced footprint compared to the integrated circuit 100 of FIGS. 1A and 1B. FIG. 2A illustrates a side view of the integrated circuit 200. Referring to FIG. 2A, the integrated circuit 200 can include an inductor 202 and a semiconductor die 104 that are attached to a package substrate 206. The integrated circuit 200 can also include a magnetic material (e.g., MMC) on the package substrate 206. The magnetic material can encapsulate the inductor 202 and the semiconductor die 104 as an encapsulation package 208. The inductor 202 can include a coil portion 210 that can include various types of cores such as a ferrite core and an iron powder core, and support posts 212a and 212b that support the coil portion 210 on the package substrate 206. Also, the semiconductor die 104 can be disposed between the support posts 212a and 212b and under the coil portion 210 such that the coil portion 210 and the semiconductor die 104 can form a device stack. In some examples, the coil portion 210 can have a lateral opening (e.g., along the x / y axis) as illustrated in FIGS. 3A-3C. In some examples, the coil portion 210 can have an opening that faces up / down (e.g., along the z axis) across the semiconductor die 104 as shown in FIGS. 4A-4C.

[0014] The package substrate 206 can include metal pads 220, 222, 224, 226, 228, and 230, which can be copper pads on a surface 232 to which the inductor 202 and the semiconductor die 104 are attached. The integrated circuit 200 can include metal interconnects 130, 132, 134, and 136 that are coupled between the semiconductor die 104 and the respective metal pads 222, 224, 226, and 228 via solder layers. Also, the support posts 212a and 212b of the inductor 202 can be coupled to the respective metal pads 220 and 230 via solder layers.

[0015] The integrated circuit 200 can include an insulating layer 240 between the passivation layer 122 of the semiconductor die 104 and the surface 232 of the package substrate 206. The insulating layer 240 can surround the metal interconnects coupled between the semiconductor die 104 and the package substrate 206, and can include sub-layers sandwiched between adjacent metal interconnects of the semiconductor die 104 and between the metal interconnects and the support portions of the inductor 202 to provide electrical insulation between the metal interconnects between the semiconductor die 104 and the inductor 202. For example, the insulating sub-layer 240_1 can provide electrical insulation between the support portion 212a and the metal interconnect 130, the insulating sub-layer 240_2 can provide electrical insulation between the metal interconnects 130 and 132, the insulating layer 240_3 can provide electrical insulation between the metal interconnects 132 and 134, the insulating layer 240_4 can provide electrical insulation between the metal interconnects 134 and 136, and the insulating layer 240_5 can provide electrical insulation between the metal interconnect 136 and the support portion 212b. In some examples, the insulating layer 240 can include a dielectric material having a high breakdown voltage, such as a polymer material (e.g., polyimide (PI), polybenzoxazole (PBO)), or an oxide material (e.g., silicon dioxide). The insulating layer 240 and the metal interconnects 130 - 136 are all encapsulated within the encapsulation package 208.

[0016] The package substrate 206 can also include metal pads such as metal pads 252, 254, 256, and 258 on the surface 250 opposite to the surface 232, which can include pads made of copper pads or other metals (e.g., silver and palladium). The metal pads 252, 254, 256, and 258 can be coupled to external devices via solder balls such as the PCB 176 and the solder balls 180 - 184 in FIG. 1, and can provide an electrical connection between the integrated circuit 200 and the external device. The package substrate 206 can also include metal interconnections such as copper interconnections that connect between metal pads on the same or different surfaces. For example, the package substrate 206 can include a metal interconnection 260 coupled between the metal pads 220 and 222 (on the surface 232) to provide an electrical connection between the inductor 202 and the semiconductor die 104. The package substrate 206 can also include a metal interconnection 262 coupled between the metal pads 224 and 252, a metal interconnection 264 coupled between the metal pads 226 and 254, a metal interconnection 266 coupled between the metal pads 228 and 256, and a metal interconnection 268 coupled between the metal pads 230 and 258 to provide an electrical connection between the external device and the inductor 202 and / or the semiconductor die 104. The package substrate 206 can include an electrical insulation layer 269 such as a polymer, ABF, or ceramic material to provide electrical insulation between the metal interconnection and the metal pad. Also, the package substrate 206 can include a solder resist layer 270 under the surface 250 to shield the metal interconnections (e.g., metal interconnections 260, 262, 264, 266, and 268) within the package substrate from the solder balls and the external device.

[0017] Also, as described above, the inductor 202 and the semiconductor die 104 can be encapsulated within an encapsulation package 208 on the package substrate 206, and the encapsulation package 208 can include a magnetic material such as MMC. The MMC can have metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. The encapsulation package 208 can shield the inductor 202 and increase the magnetic field density, thereby improving the efficiency of the inductor 202 in the conversion between electrical energy and magnetic energy. The MMC material of the encapsulation package 208 can fill the space within the inductor 202, such as at the center of the coil portion 210 (e.g., when the inductor 202 has a hollow core) and between the individual coils of the coil portion 210. The MMC material can also fill the space between the coil portion 210 and the semiconductor die 104, except for the space filled by the insulating layer 240, and can encapsulate the insulating layer 240 and the metal interconnects 130 - 136. The insulating layer 240 can have a breakdown voltage higher than that of the MMC material.

[0018] FIG. 2B illustrates another example of the integrated circuit 200. Referring to FIG. 2B, the semiconductor die 104 can be disposed adjacent to and outside the inductor 202. The integrated circuit 200 can include another circuit component such as a capacitor 280 disposed under the coil portion 210 and the support portions 212a and 212b such that the coil portion 210 and the capacitor 280 can form a device stack. In some examples, the semiconductor die 104 and the capacitor 280 can also be disposed under the coil portion 210 and the support portions 212a and 212b to form a device stack.

[0019] The package substrate 206 can include metal pads 234 (e.g., copper pads) in addition to the metal pads 220 - 230 on the surface 232 to which the semiconductor die 104 and the capacitor 280 are attached. The integrated circuit 200 can also include metal interconnects 130, 132, and 136 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the semiconductor die 104 and the respective metal pads 222, 224, and 226 of the package substrate 206. The integrated circuit 200 can also include metal interconnects 282 and 284 (e.g., copper pillars, solder bumps, or UBM interconnects) coupled between the capacitor 280 and the respective metal pads 228 and 234. The package substrate 206 can also include metal interconnects coupled between the metal pads on the surface 232 and the metal pads on the surface 250 to provide external access to the semiconductor die 104, the inductor 202, and the capacitor 280. For example, the package substrate 206 can include a metal interconnect 262 coupled between the metal pads 222 and 252, a metal interconnect 264 coupled between the metal pads 224 and 254, a metal interconnect 266 coupled between the metal pads 234 and 256, and a metal interconnect 268 coupled between the metal pads 230 and 258. The package substrate 206 can also include a metal interconnect 260 coupled between the metal pads 220, 226, and 228 to provide internal electrical connections between the semiconductor die 104, the inductor 202, and the capacitor 280.

[0020] In addition, the integrated circuit 200 can include an insulating layer 240 between the passivation layer 122 of the semiconductor die 104 and the surface 232 of the package substrate 206, and an insulating layer 290 between the capacitor 280 and the surface 232 of the package substrate 206. The insulating layers 240 and 290 can surround the metal interconnects of the respective semiconductor die 104 and capacitor 280, and can include sub-layers sandwiched between adjacent metal interconnects to provide electrical insulation. For example, the insulating sub-layer 240_1 can provide electrical insulation between the metal interconnect 130 and the outside of the encapsulation package 208, the insulating sub-layer 240_2 can provide electrical insulation between the metal interconnects 130 and 132, the insulating layer 240_3 can provide electrical insulation between the metal interconnects 132 and 134, and the insulating layer 240_4 can provide electrical insulation between the metal interconnect 134 and the support portion 212a. Also, the insulating sub-layer 290_1 can provide an electrically insulating layer between the support portion 212a and the metal interconnect 282, the insulating sub-layer 290_2 can provide an electrically insulating layer between the metal interconnects 282 and 284, and the insulating sub-layer 290_3 can provide an electrically insulating layer between the metal interconnect 290_3 and the support portion 212b. Both the insulating layers 240 and 290 can include a dielectric material having a breakdown voltage higher than that of the MMC material of the encapsulation package 208, such as PI, PBO, or silicon dioxide.

[0021] By disposing the semiconductor die 104 and / or the capacitor 280 under the coil portion 210 of the inductor 202, the integrated circuit 200 of FIGS. 2A and 2B can have a reduced footprint (e.g., in the x-y plane), and thereby shorten the metal interconnect (e.g., metal interconnect 260) between the semiconductor die 104 and the inductor 202 and reduce their parasitic capacitances. The arrangements of FIGS. 2A and 2B also enable the coil portion of the inductor to cover a majority of the footprint of the integrated circuit 200, allowing a larger inductor with increased inductance to be included in the integrated circuit 200. Further, by encapsulating the inductor 202 within the MMC package, the magnetic field density within the integrated circuit 200 can be increased, thereby improving the efficiency of the inductor 202 in the conversion between electrical and magnetic energy. Also, the metal interconnects (e.g., copper pillars and / or UBMs) of the semiconductor die 104 can be encapsulated (and insulated) with an insulating layer 240 made of a material having a breakdown voltage higher than that of the MMC, such as PI and PBO, reducing the risk of electrical short circuits between adjacent interconnects and between the inductor 202 and the interconnects, thereby allowing the coil portion 210 to be encapsulated within the MMC to improve the magnetic field density while improving safety and reliability. All of these can improve the performance of the integrated circuit 200.

[0022] FIGS. 5 and 6A - 6V illustrate an example of a method of manufacturing an integrated circuit having an inductor within a magnetic package, such as the integrated circuit 200 of FIGS. 2 - 4C. FIG. 5 shows a flowchart 500 of an exemplary method of manufacturing an integrated circuit, and FIGS. 6A - 6V are schematic diagrams illustrating various operations of the exemplary method of FIG. 5.

[0023] Referring to FIGS. 5 and 6A, in operation 502, a first insulating layer such as insulating layer 602 can be formed on wafer 604. Wafer 604 can be coated with a passivation layer 122 and can include vias 606 that penetrate passivation layer 122 to provide electrical connections to devices within wafer 604. Insulating layer 602 can include a dielectric material having a high breakdown voltage, such as a polymer material (e.g., PI and PBO), or an oxide material (e.g., silicon dioxide). Insulating layer 602 can be coated on wafer 604 or can be formed on wafer 604 by a chemical process (e.g., oxidation).

[0024] In operation 504, insulating layer 602 can be patterned. For example, referring to FIG. 6B, insulating layer 602 can be patterned to create an opening 608 that exposes via 606. The patterning can be performed, for example, based on photolithography, followed by an etching process and a plasma cleaning process.

[0025] In operation 506, metal interconnects such as metal interconnect 610 can be formed within the patterned insulating layer 602. For example, referring to FIG. 6C, metal interconnects 610 such as UBM interconnects or copper pillars can be formed within opening 608. If the first metal interconnects (e.g., metal interconnect 610) include UBM, they can be formed by an electroplating operation. After the UBM is formed, solder balls 611 can be formed on the UBM by a reflow process. In some examples, operations 502, 504, and 506 can be part of a wafer-level chip scale package (CSP) operation.

[0026] In operation 508, the wafer 604 can be diced to form semiconductor dies such as semiconductor die 104. The diced wafer 604 also includes metal interconnects 610 and a patterned insulating layer 602. Referring to FIG. 6D, the insulating layer 602 can be represented by insulating layer 240, and the metal interconnects 610 and vias 606 can be represented by one of metal interconnects 130-136.

[0027] In operation 510, the semiconductor die 104 can be attached to a substrate that can serve as a carrier substrate, or to a package substrate on which metal interconnects are formed in subsequent operations. Referring to FIG. 6E, a plurality of semiconductor dies 104 can be attached to a carrier substrate 612 via first metal interconnects 130-136 and insulating layer 240. For example, semiconductor die 104a can be attached to carrier substrate 612 via metal interconnects 130a-136a and insulating layer 240a, and semiconductor die 104b can be attached to carrier substrate 612 via metal interconnects 130b-136b and insulating layer 240b. In some examples, semiconductor dies 104a and 104b can be attached to carrier substrate 612 using a flip chip bonder, which can be pre-programmed to transfer the die to a specific location on carrier substrate 612. The carrier substrate 612 can be made from various rigid materials such as metal (e.g., iron), glass, or silicon. In some examples, the carrier substrate 612 can include a layer of adhesive carrier tape on its surface, and the flip chip bonder can apply a pressing force to adhere the semiconductor die onto the carrier tape.

[0028] Referring back to FIG. 5, in operation 512, the inductor 202 can be attached to the substrate. Referring to FIG. 6F, a plurality of inductors 202 can be attached to the carrier substrate 612 and on top of each semiconductor die 104. For example, the post portion of inductor 202a can be attached to the carrier substrate 612 (e.g., via a carrier tape) such that the coil portion is on top of semiconductor die 104a and forms a device stack 614a, and the post portion of inductor 202b can be attached to the carrier substrate 612 such that the coil portion is on top of semiconductor die 104b and forms a device stack 614b. In some examples, inductors 202a and 202b can be attached to the carrier substrate 612 using a surface mounter, which can be pre-programmed to transfer the inductors to specific locations on the carrier substrate 612 and align with the respective semiconductor dies. Thus, the carrier substrate 612 can maintain the relative positions of the inductors 202a and 202b and the semiconductor dies 104a and 104b within the respective device stacks 614a and 614b, as well as the relative positions of the device stacks 614a and 614b.

[0029] Referring back to FIG. 5, in operation 514, a magnetic material such as MMC can be deposited on semiconductor die 104 and inductor 202 to form encapsulation package 208. MMC can include metal particles (e.g., iron particles) and an insulating material (e.g., a polymer resin) in which the metal particles are suspended. Referring to FIG. 6G, encapsulation package 208 can be formed by depositing MMC on top of device stack 614a and on top of device stack 614b to encapsulate both device stacks. The MMC can then be shaped to form encapsulation package 208. In some examples, shaping can be performed with a compression molding machine, where the MMC having the device stacks and carrier substrate 612 can be placed in a hot mold. The mold can then be closed by a press (e.g., a hydraulic press). The pressure applied to the mold by the press can push the MMC into the empty space (excluding the space filled by insulating layer 240) between the inductor and the semiconductor die within each device stack and shape the MMC into encapsulation package 208. After the MMC has cured and solidified, the mold can be opened to release encapsulation package 208 and carrier substrate 612.

[0030] Referring back to FIG. 5, in operation 516, a second metal interconnect such as metal interconnects 260-268 of FIGS. 2A and 2B can be formed outside encapsulation package 208 where the second metal interconnect is coupled to inductor 202 and metal interconnects 130-136.

[0031] Figures 6H to 6V illustrate examples of sub-operations of operation 516 for forming a second metal interconnect. Referring to Figure 6H, when the substrate of operation 512 is carrier substrate 612, in sub-operation 516a of operation 516, carrier substrate 612 can be separated from encapsulation package 208 and device stacks 614a and 614b, and a partial package stack 618 including encapsulation package 208 and device stacks 614a and 614b can be formed. As described above, encapsulation package 208 can be cured from the curing of the MMC in operation 514 and can maintain the relative positions of inductor 202 and semiconductor die 104. Thus, carrier substrate 612 can be separated from encapsulation package 208 and the device stacks. The separation of carrier substrate 612 can be performed, for example, by heating the carrier tape or removing the carrier tape after irradiating the carrier tape with ultraviolet light. After carrier substrate 612 is separated from encapsulation package 208 and device stacks 614a and 614b, surface 620 of partial package stack 618 including the support portion of inductor 202, metal interconnects 130 to 136, and insulating layer 240 can be exposed.

[0032] Referring to Figure 6I, in sub-operation 516b, encapsulation package 208 and device stacks 614a and 614b can be inverted, and a second insulating layer such as insulating layer 622 can be formed on surface 620. Insulating layer 622 can contact the support portion of inductor 202, metal interconnects 130 to 136 of semiconductor die 104, and insulating layer 240 that insulates the metal interconnects. Insulating layer 622 can include, for example, a polymer, ABF, or ceramic material. In some examples, insulating layer 622 can be formed on surface 620 by a lamination process using, for example, a vacuum laminator.

[0033] Referring to FIG. 6J, in sub-operation 516c, the insulating layer 622 can be patterned. As a result of the patterning, openings 630, 632, 634, 636, 638, and 640 are created, exposing the inductor 202 and the pillar portions of the metal interconnects 130 - 136 of the semiconductor die 104. For example, openings 630a - 640a can be formed over the device stack 614a, and openings 630b - 640b can be formed over the device stack 614b. The patterning can be performed, for example, based on photolithography, followed by etching and plasma cleaning. The patterned insulating layer 622 can become the electrical insulating layer 269 of the package substrate 206 of FIGS. 2A and 2B.

[0034] Referring to FIG. 6K, in sub-operation 516d, a metal layer 642 can be formed over the patterned insulating layer 622. The metal seed layer can cover the surface of the patterned insulating layer 622, the pillar portions of the inductor 202, and the metal interconnects 130 - 136 of the semiconductor die 104, and can become the metal pads 220 - 230 of FIGS. 2A and 2B. In some examples, the metal layer 642 can be a metal seed layer such as a titanium seed layer to provide a starting material for forming metal interconnects within the package substrate 206 in subsequent processing operations. The metal layer 642 can be formed over the patterned insulating layer 622 using various processes such as an electroplating process or a sputtering process.

[0035] Following the sub-operation 516d, additional processing operations can be performed to form a second metal interconnect within the package substrate 206. Examples of processing operations can include semi-additive processes and subtractive processes. The semi-additive process can provide finer line and space patterning of the metal interconnects than the subtractive process. FIGS. 6L-6O illustrate the sub-operations 516e1-516h1 of the semi-additive process, and FIGS. 6P-6S illustrate the sub-operations 516e2-516h2 of the subtractive process. The sub-operations of FIGS. 6L-6S can be repeated to manufacture a package substrate having multiple layers of metal interconnects.

[0036] Referring to FIG. 6L, in sub-operation 516e1, a photoresist 650 can be formed on the metal layer 642. The photoresist 650 can be used to define the location of the metal interconnects within the package substrate 206 in subsequent processing. In some examples, the photoresist 650 can include a dry film material that can be cured by ultraviolet light. In some examples, the photoresist 650 can be formed on the metal layer 642 by a lamination process using, for example, a vacuum laminator.

[0037] Referring to FIG. 6M, in sub-operation 516f1, the photoresist 650 can be patterned into photoresist portions 650a-650g. After patterning, openings 652a-652f can be created to expose a portion of the metal layer 642 and the underlying openings of the insulating layer 622. The patterning can be performed, for example, based on photolithography, followed by removal of the photoresist with a stripping solution.

[0038] Referring to FIG. 6N, in sub-operation 516g1, a metal layer 670 can be formed within the opening 652 (e.g., openings 652a to 652f) and on the exposed portion of the metal layer 642. The metal layer 670 can include a copper layer. The metal layer 670 can include second metal interconnections within the package substrate 206, such as the metal interconnections 260 to 268 of FIGS. 2A and 2B. The metal layer 670 can be formed by various processes such as an electroplating process, a sputtering process, or the like.

[0039] Referring to FIG. 6O, in sub-operation 516h1, the photoresist portions 650a to 650g and the portions of the metal layer 642 under the photoresist portions 650a to 650g can be removed. The photoresist portions 650a to 650g can be removed by a stripping solution. After the photoresist portions are removed, the underlying portions of the exposed metal layer 642 can be removed by an etching process.

[0040] FIGS. 6P to 6S illustrate sub-operations 516e2 to 516h2 of the subtractive process. Referring to FIG. 6P, in sub-operation 516e2, a metal layer 670 (e.g., a copper layer) can be formed on the metal layer 642. The metal layer 670 can be formed by various processes such as an electroplating process or a sputtering process.

[0041] Referring to FIG. 6Q, in sub-operation 516f2, a photoresist 650 can be formed on the metal layer 670 and patterned into photoresist portions 650a to 650f. After patterning, openings 672a to 672g can be created to expose a portion of the metal layer 670. The patterning can be performed based on, for example, photolithography followed by removal of the photoresist with a stripping solution.

[0042] Referring to FIG. 6R, in sub-operation 516g2, the exposed portions of the metal layer 670 within the openings 672a - 672g can be removed by an etching process, and a portion of the metal layer 642 can be exposed. The remaining portions of the metal layer 670 can become the metal interconnections 260 - 268 of FIGS. 2A and 2B.

[0043] Referring to FIG. 6S, in sub-operation 516h2, the photoresist portions 650a - 650f and the portions of the metal layer 642 exposed by the removal of the metal layer 670 can be removed. The photoresist portions 650a - 650f can be removed by a stripping solution. The exposed portions of the metal layer 642 can be removed by an etching process.

[0044] FIGS. 6T - 6U illustrate examples of sub-operations 516i - 516k for manufacturing other components of the package substrate. Referring to FIG. 6T, in sub-operation 516i, a solder resist layer 690 can be formed over the metal layer 670 and the portions of the insulating layer 622 not covered by the metal layer 670. Examples of solder resist materials include alkali-developable solder resist, UV-curable solder resist, thermosetting solder resist, etc. The solder resist layer 690 can be formed over the metal layer 670 and a part of the insulating layer 622 by various processes such as a coating process or a lamination process using a vacuum laminator.

[0045] Referring to FIG. 6U, in sub-operation 516j, the solder resist layer 690 can be patterned into the solder resist portions 690a - 690g. After patterning, openings 692a - 692f can be created to expose a portion of the metal layer 670. The patterning of the solder resist layer 690 can be performed by a screen printing process. The patterned solder resist layer 690 can become the solder resist layer 270 of FIGS. 2A and 2B.

[0046] Referring to FIG. 6V, in sub-operation 516k, in order to form the package stack 696, metal pads 694a - 694f can be formed on the exposed portions of the metal layer 670 within each of the openings 692a - 692f. The metal pads 694a - 694f can represent the metal pads 252 - 258 of FIGS. 2A and 2B for improving the electrical connection between the metal layer 670 (and metal interconnects) and the solder balls. The metal pads 694a - 694f can include silver (Au) or palladium (Pd) metal and can be formed on the exposed portions of the metal layer 670 by an electroplating process.

[0047] After sub-operation 516k, a plurality of integrated circuits 200 can be manufactured by dicing the package stack 696. As a result, each integrated circuit 200 can include an inductor 202 and a device stack of the semiconductor die 104, an insulating layer 240, and metal interconnects 130 - 136, all of which can be attached to a package substrate 206 including an insulating layer 622, a metal layer 670, a solder resist layer 690, and metal pads 694. Each integrated circuit 200 can also include an MMC that seals the device stack and the insulating layer 240 as a sealing package 208.

[0048] If the substrate of operation 512 is a package substrate, the package substrate can be pre-manufactured from a second insulating layer and can include a second metal interconnect. In such an example, sub-operation 516a can be skipped, sub-operations 516b - 516k can be performed to form the package substrate, and then operations 510 - 514 can follow to attach the semiconductor die 104 and the inductor 202 to the package substrate and deposit an MMC on the semiconductor die 104 and the inductor 202 to form a sealing package 208.

[0049] Any of the methods described herein may be implemented, in whole or in part, using a computing system that includes one or more processors configured to perform such steps. Therefore, some examples may be directed to a computing system configured to perform steps of any of the methods described herein, and potentially, different components may perform respective steps or respective groups of steps. Although shown as numbered steps, the steps of the methods herein may be performed simultaneously or in a different order. Also, some of these steps may be used in conjunction with some of the steps from other methods. Also, all or part of the steps may be optional. Also, any of the steps of any method may be implemented using a module, unit, circuit, or other means for performing these steps.

[0050] As used herein, the term "coupled" may include a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A provides a signal for controlling device B to perform a certain action, (a) in a first example, device A is directly coupled to device B, or (b) in a second example, if intervening component C does not substantially change the functional relationship between device A and device B, device A is indirectly coupled to device B via intervening component C, such that device B is controlled by device A via the control signal provided by device A.

[0051] A device "configured to" perform a task or function is configured (e.g., programmed and / or wired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the construction and / or layout of hardware components, via the interconnection of the device, or via a combination thereof.

[0052] A circuit or device described herein as including certain components may instead be combined with those components and adapted to form the described circuit or device. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more supply sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (such as a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be combined with at least some of the passive elements and / or supply sources, either during or after manufacture, by an end user and / or a third party, etc., to form the described structure.

[0053] Although certain components may be described herein as being of a particular process technology, these components may be exchanged with components of other process technologies. The circuits described herein are reconfigurable to include the exchanged components in order to provide at least partially similar functionality to that available prior to the component exchange. A component shown as a resistor generally represents any one or more elements that are coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor, unless otherwise specified. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors coupled in series or in parallel between the same two nodes as, respectively, a single resistor or capacitor.

[0054] The use of the phrase "ground voltage potential" herein includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this specification. In this specification, unless otherwise specified, "about", "approximately", or "substantially" preceding a parameter means within + / - 10% of that parameter.

[0055] Within the scope of the claims, modifications can be made to the examples described, and other examples are also possible.

Claims

1. It is an integrated circuit, A substrate having a first surface and a second surface opposite to the first surface, A semiconductor die having a first surface and a second surface opposite to the first surface, A first metal interconnection between the first surface of the semiconductor die and the first surface of the substrate, A first insulating layer between the first surface of the semiconductor die and the first surface of the substrate, the first insulating layer surrounding each individual metal interconnect of the metal interconnect, An inductor coupled to the substrate, A magnetic material for sealing the semiconductor die, the inductor, the first metal interconnect, and the first insulating layer, comprising a material different from the first insulating layer, An integrated circuit, including

2. The integrated circuit according to claim 1, An integrated circuit in which the inductor includes a coil portion and a support portion, and the support portion is coupled to the substrate.

3. The integrated circuit according to claim 2, An integrated circuit in which the coil portion is located on the semiconductor die.

4. The integrated circuit according to claim 2, A capacitor sealed within the magnetic material, further comprising the capacitor coupled to the substrate, An integrated circuit in which the coil portion is located on top of the capacitor.

5. The integrated circuit according to claim 1, An integrated circuit in which the magnetic material comprises metal particles and an epoxy resin in which the metal particles are suspended.

6. The integrated circuit according to claim 1, An integrated circuit in which the first insulating layer has a higher breakdown voltage than the magnetic material.

7. The integrated circuit according to claim 6, An integrated circuit in which the first insulating layer includes a dielectric material.

8. The integrated circuit according to claim 7, An integrated circuit in which the dielectric material includes at least one of a polyimide material, a polybenzoxazole material, or an oxide material.

9. The integrated circuit according to claim 1, An integrated circuit in which the semiconductor die includes a passivation layer coupled to the first metal interconnect.

10. The integrated circuit according to claim 1, An integrated circuit in which the first metal interconnect includes at least one pillar or underbump metallization (UBM) interconnect.

11. The integrated circuit according to claim 1, The aforementioned substrate, A first metal pad on the first surface of the substrate, which is coupled to the first metal interconnect, The second metal pad on the second surface of the substrate, A second insulating layer between the first surface and the second surface of the substrate, A second metal interconnect in the second insulating layer, wherein the second metal interconnect is coupled between the first metal pad and the second metal pad, An integrated circuit, including

12. The integrated circuit according to claim 11, The first metal pad and the second metal interconnect include copper metal. The second metal pad comprises at least one of palladium metal or silver metal. An integrated circuit in which the second insulating layer comprises at least one of a polymer material, an Ajinomoto build-up film, or a ceramic material.

13. The integrated circuit according to claim 11, An integrated circuit wherein the substrate further includes a solder resist layer on the second surface.

14. An integrated circuit according to claim 1, An integrated circuit in which the first insulating layer is adjacent to the magnetic material.

15. An integrated circuit according to claim 1, An integrated circuit in which the first insulating layer has a higher breakdown voltage than the magnetic material.

16. An integrated circuit according to claim 1, An integrated circuit in which the first insulating layer fills the space between adjacent pairs of the first metal interconnects.

17. An integrated circuit, A substrate having a first surface and a second surface opposite to the first surface, A semiconductor die having a first surface and a second surface opposite to the first surface, A metal interconnection between the first surface of the semiconductor die and the first surface of the substrate, A first insulating layer between the first surface of the semiconductor die and the first surface of the substrate, the first insulating layer overlapping the semiconductor die and surrounding the metal interconnect, A second insulating layer covering at least a portion of the semiconductor die, the metal interconnect, and the first insulating layer, wherein the second insulating layer comprises a material different from the material of the first insulating layer, An integrated circuit, including

18. The integrated circuit according to claim 17, An integrated circuit in which the first insulating layer has a higher breakdown voltage than the second insulating layer.

19. The integrated circuit according to claim 17, An integrated circuit in which the second insulating layer contains a magnetic mold compound.

20. The integrated circuit according to claim 17, An integrated circuit in which the first insulating layer fills the space between adjacent pairs of metal interconnects.

Images