Copackages for qubits and parametric Josephson devices

Abstract

Systems and techniques are provided that facilitate high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices. In various embodiments, the device may include a superconducting qubit wafer that may be bonded to a parametric Josephson wafer by one or more first bump bonds. In various aspects, the device may further include a first underfill surrounding the one or more first bump bonds. In various examples, the first underfill may protect the parametric Josephson wafer from mechanical and / or chemical degradation associated with subsequent fabrication, processing, and / or handling of the superconducting qubit wafer.

Description

[Background technology]

[0001] The subject disclosure relates to qubits, and more particularly to high-density flip-chip co-packages for superconducting qubits and parametric Josephson devices.

[0002] Superconducting quantum computing hardware systems utilize parametric Josephson devices for the purposes of signal boosting and / or noise mitigation. Generally, such superconducting quantum computing hardware systems involve independently packaged superconducting qubit chips coupled to individually packaged parametric Josephson chips by superconducting wires and / or coaxial cables. Unfortunately, such individual packages occupy an excessive amount of physical space and make it more difficult to facilitate cryogenic cooling and / or temperature control.

[0003] Therefore, systems and / or techniques that can address one or more of these technical problems would be desirable. Summary of the Invention

[0004] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, devices, systems, computer-implemented methods, apparatus, and / or computer program products are described that can facilitate high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices.

[0005] According to one or more embodiments, a device is provided. In various aspects, the device may include a superconducting qubit wafer bonded to a parametric Josephson wafer by one or more first bump bonds. In various examples, the device may further include a first underfill surrounding the one or more first bump bonds. In various cases, at least one first parametric Josephson device may be disposed on a first side of the parametric Josephson wafer, and at least one superconducting qubit including a Josephson junction may be disposed on the first side of the superconducting qubit wafer. In various aspects, the superconducting qubit wafer may include at least one first through-substrate via electrically connecting the first side of the superconducting qubit wafer to a second side of the superconducting qubit wafer. In various examples, the one or more first bump bonds may bond the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer. In various cases, the first underfill may protect the at least one first parametric Josephson device from mechanical and / or chemical degradation associated with processing to fabricate the at least one superconducting qubit.

[0006] According to one or more embodiments, a flip chip package is provided. In various aspects, the flip chip package may include a first wafer bump-bonded to a second wafer. In various examples, the first wafer may include one or more parametric Josephson devices, and the second wafer may include one or more superconducting qubits. In various cases, the flip chip package may further include an underfill separating the first wafer from the second wafer. In various aspects, the underfill may protect / preserve the one or more parametric Josephson devices from mechanical / chemical damage associated with fabrication, processing, and / or handling of the one or more superconducting qubits.

[0007] In various embodiments, the above-described devices and / or flip-chip packages may be implemented as methods of manufacture.

[0008] Various other details of the various embodiments described herein are presented in the following sections.

[0009] Item 1: A device comprising: a superconducting qubit wafer bonded to a parametric Josephson wafer by one or more first bump bonds; and a first underfill surrounding the one or more first bump bonds. As described herein, the first underfill may act as a protective barrier that may help prevent the parametric Josephson wafer from experiencing excessive mechanical and / or chemical degradation during subsequent fabrication and / or processing of the superconducting qubit wafer.

[0010] Item 2: A device described in any preceding item specified in the Summary of the Invention, wherein the first underfill is a composite material having an epoxy polymer and a filler, and the filler is selected from the group consisting of silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and graphene.

[0011] Section 3: The device of any preceding section specified in the Summary of the Invention, wherein the at least one first parametric Josephson device is disposed on a first side of a parametric Josephson wafer, the at least one superconducting qubit is disposed on the first side of the superconducting qubit wafer, the superconducting qubit wafer including at least one first through-substrate via electrically connecting the first side of the superconducting qubit wafer to a second side of the superconducting qubit wafer, and one or more first bump bonds bond the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer. Again, as described herein, the first underfill may help protect the at least one first parametric Josephson device from mechanical and / or chemical damage during subsequent fabrication and / or handling of the at least one superconducting qubit. Furthermore, as described herein, the first underfill may also help mitigate crosstalk between adjacent ones of the at least one first parametric Josephson device.

[0012] Clause 4: A device according to any preceding clause specified in the Summary of the Invention, wherein the at least one first parametric Josephson device comprises a Josephson parametric amplifier, a Josephson traveling wave parametric amplifier, a Josephson directional amplifier, a Josephson parametric converter, a Josephson circulator, or a Josephson isolator.

[0013] Clause 5: The device of any preceding clause specified in the Summary of the Invention, further comprising an interposer wafer bump-bonded to the superconducting qubit wafer by one or more second bump bonds, wherein at least one resonator is disposed on the first side of the interposer wafer.

[0014] Clause 6: A device as described in any preceding clause specified in the Summary of the Invention, wherein one or more second bump bonds couple the first side of the interposer wafer to the first side of the superconducting qubit wafer.

[0015] Item 7: A device described in any preceding item specified in the Summary of the Invention, wherein the first surface of the interposer wafer is bump-bonded to an organic substrate, the organic substrate being selected from the group consisting of a printed circuit board, a flexible printed circuit board, and a laminate.

[0016] Item 8: A device described in any preceding item specified in the Summary of the Invention, further comprising: a first interposer wafer bump-bonded to a second interposer wafer by one or more second bump bonds; and a second underfill surrounding the one or more second bump bonds.

[0017] Clause 9: A device as described in any preceding clause specified in the Summary of the Invention, wherein at least one second parametric Josephson device is disposed on the first surface of the first interposer wafer and at least one resonator is disposed on the first surface of the second interposer wafer.

[0018] Clause 10: A device described in any preceding clause specified in the Summary of the Invention, wherein at least one second through-substrate via electrically connects the first surface of the second interposer wafer to the second surface of the second interposer wafer, and one or more second bump bonds join the first surface of the first interposer wafer to the second surface of the second interposer wafer.

[0019] Item 11: The device of any preceding item specified in the Summary of the Invention, wherein the first side of the superconducting qubit wafer is bump-bonded to the first side of a second interposer wafer by one or more third bump bonds, and the first side of the second interposer wafer is bump-bonded to an organic substrate, the organic substrate being selected from the group consisting of a printed circuit board, a flexible printed circuit board, and a laminate. Again, as described herein, the second underfill can help protect the at least one second parametric Josephson device from mechanical and / or chemical damage that might otherwise occur after fabrication.

[0020] Clause 12: A device as described in any preceding clause specified in the Summary of the Invention, wherein at least one segmented electrode corresponding to at least one superconducting quantum bit is disposed on the second side of the superconducting quantum bit wafer, the at least one segmented electrode including at least one air bridge that is trimmable to adjust the operating frequency of the at least one superconducting quantum bit, and at least one hollow photoresist column extends from the first side of the parametric Josephson wafer to the second side of the superconducting quantum bit wafer, and prevents the first underfill from covering the at least one air bridge.

[0021] Item 13: The device of any preceding item specified in the Summary of the Invention, further comprising: an interposer wafer; another superconducting qubit wafer coupled to another parametric Josephson wafer by one or more second bump bonds; and a second underfill surrounding the one or more second bump bonds and surrounding one or more second parametric Josephson devices of the another parametric Josephson wafer, wherein both the superconducting qubit wafer and the another superconducting qubit wafer are bump-bonded to the interposer wafer by one or more third bump bonds, and the interposer wafer is bump-bonded to an organic substrate.

[0022] In various embodiments, any combination of any of paragraphs 1-13 may be implemented.

[0023] Item 14: A method comprising: bonding a superconducting qubit wafer to a parametric Josephson wafer by one or more first bump bonds; and injecting a first underfill between the superconducting qubit wafer and the parametric Josephson wafer, such that the first underfill surrounds the one or more first bump bonds. As described herein, the first underfill may act as a protective barrier that may help prevent the parametric Josephson wafer from experiencing excessive mechanical and / or chemical degradation during subsequent fabrication and / or processing of the superconducting qubit wafer.

[0024] Item 15: The method of any preceding item specified in the Summary of the Invention, wherein the first underfill is a composite material having an epoxy polymer and a filler, and the filler is selected from the group consisting of silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and graphene.

[0025] Clause 16: The method of any preceding clause specified in the Summary of the Invention, wherein at least one first parametric Josephson device is disposed on a first side of a parametric Josephson wafer, at least one superconducting qubit is disposed on the first side of a superconducting qubit wafer, the superconducting qubit wafer including at least one first through-substrate via electrically connecting the first side of the superconducting qubit wafer to a second side of the superconducting qubit wafer, and one or more first bump bonds bond the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer. Again, as described herein, the first underfill may help protect the at least one first parametric Josephson device from mechanical and / or chemical damage during subsequent fabrication and / or handling of the at least one superconducting qubit. Furthermore, as described herein, the first underfill may also help mitigate crosstalk between adjacent ones of the at least one first parametric Josephson device.

[0026] Clause 17: A method according to any preceding clause specified in the Summary of the Invention, wherein the at least one first parametric Josephson device comprises a Josephson parametric amplifier, a Josephson traveling wave parametric amplifier, a Josephson directional amplifier, a Josephson parametric converter, a Josephson circulator, or a Josephson isolator.

[0027] Clause 18: The method of any preceding clause specified in the Summary of the Invention, further comprising bonding the interposer wafer to the superconducting qubit wafer by one or more second bump bonds, wherein at least one resonator is disposed on the first side of the interposer wafer.

[0028] Clause 19: The method of any preceding clause specified in the Summary of the Invention, wherein one or more second bump bonds couple the first side of the interposer wafer to the first side of the superconducting qubit wafer.

[0029] Item 20: A method as described in any preceding item specified in the Summary of the Invention, wherein the first surface of the interposer wafer is bump-bonded to an organic substrate, the organic substrate being selected from the group consisting of a printed circuit board, a flexible printed circuit board, and a laminate.

[0030] Item 21: A method as described in any preceding item specified in the Summary of the Invention, further comprising the steps of: bonding the first interposer wafer to the second interposer wafer by one or more second bump bonds; and injecting a second underfill between the first interposer wafer and the second interposer wafer such that the second underfill surrounds the one or more second bump bonds.

[0031] Clause 22: A method according to any preceding clause specified in the Summary of the Invention, wherein at least one second parametric Josephson device is disposed on a first surface of a first interposer wafer, and at least one resonator is disposed on a first surface of a second interposer wafer.

[0032] Clause 23: A method as specified in any preceding clause in the Summary of the Invention, wherein at least one second through-substrate via electrically connects the first surface of the second interposer wafer to the second surface of the second interposer wafer, and one or more second bump bonds join the first surface of the first interposer wafer to the second surface of the second interposer wafer.

[0033] Clause 24: The method of any preceding clause specified in the Summary of the Invention, wherein the first side of the superconducting qubit wafer is bump-bonded to the first side of a second interposer wafer by one or more third bump bonds, and the first side of the second interposer wafer is bump-bonded to an organic substrate, the organic substrate being selected from the group consisting of a printed circuit board, a flexible printed circuit board, and a laminate. Again, as described herein, the second underfill can help protect the at least one second parametric Josephson device from mechanical and / or chemical damage that might otherwise occur after fabrication.

[0034] Clause 25: The method of any preceding clause specified in the Summary of the Invention, wherein at least one segmented electrode corresponding to at least one superconducting quantum bit is disposed on the second side of the superconducting quantum bit wafer, the at least one segmented electrode including at least one air bridge trimmable to adjust the operating frequency of the at least one superconducting quantum bit, and at least one hollow photoresist column extends from the first side of the parametric Josephson wafer to the second side of the superconducting quantum bit wafer, and the first underfill prevents the at least one air bridge from covering the at least one air bridge.

[0035] Clause 26: The method of any preceding clause specified in the Summary of the Invention, further comprising: bonding the another superconducting qubit wafer to the another parametric Josephson wafer by one or more second bump bonds; injecting a second underfill between the another superconducting qubit wafer and the another parametric Josephson wafer such that the second underfill surrounds the one or more second bump bonds and surrounds one or more second parametric Josephson devices of the another parametric Josephson wafer; and bonding both the superconducting qubit wafer and the another superconducting qubit wafer to an interposer wafer by one or more third bump bonds, wherein the interposer wafer is bump-bonded to an organic substrate.

[0036] In various embodiments, any combination of any of clauses 14-26 may be implemented.

[0037] Item 27: A flip-chip package comprising: a first wafer bump-bonded to a second wafer, where the first wafer has one or more parametric Josephson devices and the second wafer has one or more superconducting qubits; and an underfill separating the first wafer from the second wafer, where the one or more parametric Josephson devices are disposed between the underfill and the first wafer. As described herein, the underfill may act as a protective barrier that may help prevent the one or more parametric Josephson devices from experiencing excessive mechanical and / or chemical degradation during subsequent fabrication and / or processing of the one or more superconducting qubits.

[0038] Item 28: A flip chip package according to any preceding item specified in the Summary of the Invention, further comprising an interposer bump-bonded to both the second wafer and the organic substrate.

[0039] Item 29: A flip chip package according to any preceding item specified in the Summary of the Invention, wherein the interposer has one or more resonators.

[0040] Clause 30: A flip chip package as described in any preceding clause specified in the Summary of the Invention, wherein the interposer has a first interposer wafer bump-bonded to a second interposer wafer, the first interposer wafer including one or more other parametric Josephson devices, and the second interposer wafer including one or more resonators, wherein another underfill separates the first interposer wafer from the second interposer wafer, the second wafer being bump-bonded to the second interposer wafer, and the another underfill is configured to protect the one or more other parametric Josephson devices from mechanical or chemical damage.

[0041] In various embodiments, any combination of any of clauses 27-30 may be implemented. [Brief explanation of the drawings]

[0042] [Figure 1] FIG. 1 illustrates a cross-sectional view of an exemplary, non-limiting, high-density flip-chip co-package for superconducting qubits and parametric Josephson devices, according to one or more embodiments described herein.

[0043] [Figure 2] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 3] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 4] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 5] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 6] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 7] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 8] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 9] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 10] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 11] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 12] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein. [Figure 13] 1A-1C show exemplary, non-limiting cross-sectional diagrams illustrating how high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices can be fabricated in accordance with one or more embodiments described herein.

[0044] [Figure 14] FIG. 1 shows an exemplary, non-limiting block diagram illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices may be fabricated in accordance with one or more embodiments described herein. [Figure 15] FIG. 1 shows an exemplary, non-limiting block diagram illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices may be fabricated in accordance with one or more embodiments described herein. [Figure 16] FIG. 1 shows an exemplary, non-limiting block diagram illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices may be fabricated in accordance with one or more embodiments described herein.

[0045] [Figure 17] FIG. 1 shows exemplary, non-limiting cross-sectional diagrams illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices may be bonded to an interposer and / or organic substrate in accordance with one or more embodiments described herein. [Figure 18] FIG. 1 shows exemplary, non-limiting cross-sectional diagrams illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices may be bonded to an interposer and / or organic substrate in accordance with one or more embodiments described herein.

[0046] [Figure 19]FIG. 1 shows exemplary, non-limiting cross-sectional diagrams illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices can be bonded to alternative interposers and / or organic substrates in accordance with one or more embodiments described herein. [Figure 20] FIG. 1 shows exemplary, non-limiting cross-sectional diagrams illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices can be bonded to alternative interposers and / or organic substrates in accordance with one or more embodiments described herein.

[0047] [Figure 21] FIG. 1 illustrates a cross-sectional view of an exemplary, non-limiting, high-density flip-chip co-package for superconducting qubits and parametric Josephson devices including a trimmable air bridge for frequency tuning, according to one or more embodiments described herein.

[0048] [Figure 22] FIG. 10 shows exemplary, non-limiting cross-sectional diagrams illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices including a trimmable air bridge for frequency tuning can be bonded to an interposer and / or organic substrate in accordance with one or more embodiments described herein. [Figure 23] FIG. 10 shows exemplary, non-limiting cross-sectional diagrams illustrating how a high-density flip-chip co-package for superconducting qubits and parametric Josephson devices including a trimmable air bridge for frequency tuning can be bonded to an interposer and / or organic substrate in accordance with one or more embodiments described herein.

[0049] [Figure 24] FIG. 1 illustrates a cross-sectional view of another exemplary, non-limiting, high-density flip-chip co-package for superconducting qubits and parametric Josephson devices bonded to an interposer and / or organic substrate, according to one or more embodiments described herein. [Figure 25] FIG. 1 illustrates a cross-sectional view of another exemplary, non-limiting, high-density flip-chip co-package for superconducting qubits and parametric Josephson devices bonded to an interposer and / or organic substrate, according to one or more embodiments described herein.

[0050] [Figure 26] FIG. 1 shows a block diagram of an exemplary, non-limiting method for facilitating high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices, according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0051] The following detailed description is merely exemplary and is not intended to limit the embodiments and / or the application or uses of the embodiments, nor is there any intention to be bound by any express or implied information presented in the preceding Background or Summary sections or in the Detailed Description section.

[0052] One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various instances one or more embodiments may be practiced without these specific details.

[0053] Superconducting quantum computing hardware systems (e.g., quantum computers utilizing superconducting qubits composed of Josephson junctions, such as transmon qubits) may utilize parametric Josephson devices for signal boosting and / or noise mitigation purposes. In various cases, the parametric device may be any suitable electronic circuit that utilizes a time-varying parameter to couple multiple modes of operation. In various examples, the parametric Josephson device may be a parametric device in which the time-varying parameter is Josephson inductance. Non-limiting examples of parametric Josephson devices may include Josephson traveling-wave parametric amplifiers, Josephson parametric amplifiers, Josephson directional amplifiers, Josephson parametric converters, Josephson circulators, Josephson isolators, traveling-wave frequency converters, and / or traveling-wave frequency isolators. In any case, as superconducting quantum computing hardware systems scale up, they can be expected to include up to millions of qubits and require near-perfect yields of all cryogenic components during assembly. Because parametric Josephson devices often multiplex signals from multiple qubits, failure of such parametric Josephson devices may be particularly problematic.

[0054] Generally, a superconducting quantum computing hardware system may involve an independently packaged superconducting qubit chip (e.g., a silicon chip having one or more superconducting qubits fabricated thereon) coupled by superconducting wire and / or coaxial cable to an independently packaged parametric Josephson chip (e.g., a silicon chip having one or more parametric Josephson devices fabricated thereon. Such individual packaging is implemented to enable individual removal / maintenance of the parametric Josephson chip and / or the superconducting qubit chip in a large-scale quantum computing system.

[0055] Unfortunately, while such individual packaging lends itself to easy maintenance / repair of the individual components, such individual packaging occupies an excessive amount of physical space, making it more difficult to facilitate cryogenic cooling. More specifically, a significant amount of physical volume within a cryogenic refrigerator may be occupied not only by the superconducting qubit chip and the individually packaged parametric Josephson chip themselves, but also by the mounting brackets, magnetic shielding, and / or cooling devices required by the superconducting qubit chip, and further by the individual / duplicate mounting brackets, individual / duplicate magnetic shielding, and / or individual / duplicate cooling devices required by the individually packaged parametric Josephson chip, and even further by the long superconducting wires and / or coaxial cables required to couple the superconducting qubit chip to the individually packaged parametric Josephson chip. Thus, as superconducting quantum computing hardware systems scale to hundreds, thousands, or even millions of qubits, individually packaging the superconducting qubit chip and parametric Josephson chip may require increasingly large cryogenic refrigerators, which may quickly become impractical. In other words, packaging the superconducting qubit chip and the parametric Josephson chip separately may be disadvantageous due to excessive consumption of physical space and / or due to the attendant cooling challenges caused by such excessive consumption of physical space.

[0056] One potential solution to such excessive consumption of physical space is to implement flip-chip packaging for the superconducting qubit chip and the parametric Josephson chip. That is, by flip-chip bonding the superconducting qubit chip to the parametric Josephson chip, space may be saved because separate / duplicate mounting brackets, separate / duplicate magnetic shielding, and / or separate / duplicate cooling devices may then be omitted. Unfortunately, however, existing techniques for implementing such flip-chip packaging often result in significant mechanical and / or chemical degradation of the parametric Josephson device, which may be undesirable.

[0057] Therefore, systems and / or techniques that can address one or more of these technical problems would be desirable.

[0058] Various embodiments described herein may address one or more of these technical problems. In particular, various embodiments described herein may provide systems and / or techniques that may facilitate high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices. In other words, the inventors of various embodiments described herein have devised a unified packaging architecture that may implement both superconducting qubits and parametric Josephson devices, thereby eliminating the excessive consumption of physical space that characterizes separate packaging techniques, while at the same time avoiding the mechanical and / or chemical degradation of parametric Josephson devices that plague existing flip-chip packaging techniques. That is, the inventors have devised a technique for fabricating both a superconducting qubit and a parametric Josephson device together in a single flip-chip package, wherein such a single flip-chip package may exhibit a higher spatial density (e.g., may be geometrically more compact) than would be the case if the superconducting qubit and the parametric Josephson device were packaged separately, and wherein such a single flip-chip packaged parametric Josephson device may not exhibit any (and / or at most negligible) mechanical and / or chemical degradation.

[0059] In particular, the architectures contemplated by the inventors may, in various embodiments, include a superconducting qubit wafer and a parametric Josephson wafer. In various examples, the superconducting qubit wafer may be composed of any suitable quantum computing wafer / substrate material (e.g., silicon) as desired and / or may have any suitable shape, size, and / or dimensions. In various cases, the superconducting qubit wafer may be considered to have a first side (e.g., a top side) and a second side (e.g., a bottom side). In various embodiments, the first side of the superconducting qubit wafer and the second side of the superconducting qubit wafer may be electrically connected together by one or more through-substrate vias composed of any suitable superconducting material. In various examples, one or more superconducting qubits (e.g., transmon qubits) may be fabricated on the first side of the superconducting qubit wafer (e.g., via photolithography, vapor deposition, etching, and / or double-angle evaporation).

[0060] In various aspects, the parametric Josephson wafer may be composed of any suitable quantum computing wafer / substrate material (e.g., silicon) as desired and / or may have any suitable shape, size, and / or dimensions. In various examples, similar to the above, the parametric Josephson wafer may be considered to have a first side (e.g., a top side) and a second side (e.g., a bottom side). In various cases, one or more parametric Josephson devices (e.g., Josephson traveling-wave parametric amplifiers, Josephson parametric amplifiers, Josephson directional amplifiers, Josephson parametric converters, Josephson circulators, Josephson isolators, traveling-wave frequency converters, traveling-wave frequency isolators) may be fabricated (e.g., via photolithography, deposition, etching, and / or double angle evaporation) on the first side of the parametric Josephson wafer.

[0061] In various embodiments, the second side of the superconducting qubit wafer and the first side of the parametric Josephson wafer may be bonded (e.g., through reflow bonding, thermocompression bonding, cold welding) by one or more bump bonds (which may be fabricated, e.g., via photolithography, vapor deposition, etching, dual angle evaporation, injection molding, and / or electroplating). In various cases, each bump bond may include a solder bump sandwiched between two under-bump metallizations. Thus, the superconducting qubit wafer and the parametric Josephson wafer may be considered to be bonded together in a single and / or spatially compact flip-chip package. Such a single compact flip-chip package may consume less geometric volume than the techniques described above that fabricate the superconducting qubit and the parametric Josephson device in separate packages (e.g., if the parametric Josephson device were packaged separately from the superconducting qubit, separate / duplicate mounting brackets, separate / duplicate magnetic shielding, and / or separate / duplicate cooling devices may be required; in contrast, if the parametric Josephson device is packaged with the superconducting qubit in a single compact flip-chip package described herein, separate / duplicate mounting brackets, separate / duplicate magnetic shielding, and / or separate / duplicate cooling devices may be avoided).

[0062] Furthermore, while the first side of the parametric Josephson wafer and the second side of the superconducting qubit wafer may be joined by one or more bump bonds, there may still be a void space gap surrounding one or more bump bonds, surrounding one or more parametric Josephson devices, and / or separating the first side of the parametric Josephson wafer from the second side of the superconducting qubit wafer. In various cases, an underfill may be injected into such a void space gap, such that the underfill surrounds one or more bump bonds, surrounds / covers one or more parametric Josephson devices, and / or separates the first side of the parametric Josephson wafer from the second side of the superconducting qubit wafer. In various embodiments, the underfill may be any suitable type of thermosetting epoxy. As a non-limiting example, the underfill may be a composite material having any suitable epoxy polymer combined with any suitable filler. Non-limiting examples of such fillers can be silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and / or graphene. In various cases, the underfill can include any other suitable material, such as a flow agent, an adhesion promoter, and / or a dye. In various examples, the composition of the underfill can be controlled to ensure that the underfill is thermal expansion coefficient matched (e.g., CTE matched) with the superconducting qubit wafer and / or the parametric Josephson wafer (e.g., because the superconducting qubit wafer and the parametric Josephson wafer can both be silicon, they can have the same thermal expansion coefficient). Furthermore, in various embodiments, any suitable curing process (e.g., any suitable curing temperature and / or curing time) can be implemented after injection of the underfill.

[0063] In either case, the inventors recognize that the underfill can act as an intermediate physical barrier that can protect the parametric Josephson device from mechanical stress and / or chemical degradation that would otherwise occur during subsequent fabrication / processing. More specifically, given the practical realities of modern microfabrication and / or nanofabrication equipment, the order in which the various components of the single, compact flip-chip package described herein may be fabricated may be as follows: a parametric Josephson device may be fabricated on a first side of a first substrate, thereby resulting in a parametric Josephson wafer; a second side of a second substrate, which may have through-substrate vias but may lack superconducting qubits, may be bump-bonded in a flip-chip manner to the first side of the parametric Josephson wafer; an underfill may be injected between the first side of the parametric Josephson wafer and the second side of the second substrate, such that the underfill surrounds / covers the bump bond and / or the parametric Josephson device; and, thereafter, a superconducting qubit may be fabricated on the first side of the second substrate, thereby resulting in a superconducting qubit wafer. With such a relative fabrication order, the underfill may be considered to physically preserve and / or physically reinforce the parametric Josephson device during subsequent fabrication of the superconducting qubit. In other words, if the underfill is omitted, subsequent fabrication of the superconducting qubits (e.g., via photolithography, deposition, etching, dual angle evaporation) on the first surface of the second substrate will subject the already-fabricated parametric Josephson device to high levels of mechanical stress (which may result in physical fracture of the parametric Josephson device) and / or will subject the already-fabricated parametric Josephson device to high levels of chemical corrosion (which may adversely affect the signal boost and / or noise mitigation performance of the parametric Josephson device).In contrast, when an underfill is included as described herein, mechanical stress and / or chemical corrosion of the parametric Josephson device that would otherwise occur during subsequent fabrication of the superconducting qubit can be mitigated and / or reduced to negligible levels. Thus, the underfill can be considered an intermediate physical barrier that preserves the parametric Josephson device from mechanical and / or chemical damage that would otherwise occur during subsequent fabrication / processing that the single compact flip-chip package described herein undergoes.

[0064] In this regard, the underfill may also be considered to protect the parametric Josephson device and / or bump bonds from mechanical damage that may otherwise occur during post-fabrication handling of the single compact flip chip package described herein. For example, post-fabrication handling of the single compact flip chip package described herein may present many different opportunities for physical damage (e.g., placing the single compact flip chip package in various clamps and / or mounts may generate transient and / or non-transient mechanical stresses in / around the parametric Josephson device and / or in / around the bump bonds). In various cases, the underfill may be considered to enhance the physical durability of the parametric Josephson device and / or bump bonds, such that the parametric Josephson device and / or bump bonds may be more likely to withstand such mechanical stresses that may occur during post-fabrication handling without suffering damage.

[0065] In various embodiments, the inventors have recognized that an additional benefit of the underfill may be the mitigation of crosstalk between adjacent parametric Josephson devices. In particular, a material with relatively high radio frequency absorption, such as carbon nanotubes, may be used as the primary filler / constituent of the underfill. In such cases, the underfill may therefore serve to attenuate free-space electromagnetic fields (e.g., crosstalk) that may occur between adjacent parametric Josephson devices.

[0066] It should be noted that prior to the inventors' ingenuity and / or the present teachings described in this disclosure, underfill was used only to compensate for mismatches in thermal expansion coefficients between silicon wafers and non-silicon organic substrates (e.g., printed circuit boards, laminates). In other words, prior to the teachings described herein, underfill was generally used between silicon wafers and organic substrates (e.g., because the silicon wafers and organic substrates may have different thermal expansion coefficients), but underfill was not generally used between two silicon wafers (e.g., because the silicon wafers may already have the same thermal expansion coefficients as each other). Furthermore, prior to the teachings described herein, underfill was not used in any way as a physical barrier to protect parametric Josephson devices from mechanical and / or chemical damage caused by subsequent fabrication / processing of superconducting qubits. Indeed, prior to the teachings described herein, there was even no suggestion that underfill could serve as a suitable barrier to provide such mechanical / chemical protection. In fact, the very concept of a shield / barrier to protect the parametric Josephson device from mechanical / chemical damage caused by the subsequent fabrication of the superconducting qubit did not exist prior to the teachings described herein. Instead, as explained above, such mechanical / chemical damage was avoided by existing techniques through separate packaging of the superconducting qubit and the parametric Josephson device, at the cost of excessive consumption of space.

[0067] In either case, the single, compact flip-chip package described herein may package the superconducting qubit and the parametric Josephson device in a high-density (e.g., geometrically compact) manner with no and / or negligible mechanical / chemical damage (e.g., due to underfill). Accordingly, such a single, compact flip-chip package may be considered advantageous compared to techniques that involve packaging the superconducting qubit and the parametric Josephson device separately (e.g., such separate packaging techniques may avoid undesirable mechanical / chemical damage to the parametric Josephson device, but such separate packaging techniques consume an excessive amount of physical space).

[0068] Various embodiments of the present invention may be employed to use hardware and / or software to solve inherently highly technical problems that are not abstract, not merely laws of nature, not merely natural phenomena, and that cannot be implemented as a series of mental actions by humans (e.g., to facilitate high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices). Instead, various embodiments described herein include tangible electrical circuit structures / architectures and / or methodologies related to such tangible electrical circuit structures / architectures that can be utilized to implement superconducting qubits and parametric Josephson devices without mechanical / chemical degradation (e.g., with at most negligible mechanical / chemical degradation) and with reduced physical size and / or spatial footprint. Indeed, as discussed above, existing techniques involve separately packaging the superconducting qubits and parametric Josephson devices. Such separate packaging prevents undesirable mechanical / chemical degradation of the parametric Josephson devices, at the cost of excessive space consumption.

[0069] In contrast, various embodiments described herein may address one or more of such technical problems. Specifically, the systems / techniques described herein may comprise bump-bonding a superconducting qubit wafer to a parametric Josephson wafer, and may further comprise injecting an underfill between the superconducting qubit wafer and the parametric Josephson wafer. In various examples, such architectures may consume less space than existing techniques that utilize discrete packaging, and the parametric Josephson devices in such architectures may also experience no and / or negligible mechanical / chemical degradation. More specifically, because the superconducting qubit wafer may be bump-bonded to the parametric Josephson wafer in a flip-chip manner, such architectures may be viewed as consuming less physical / geometric space than existing techniques that utilize discrete packaging. Indeed, if the superconducting qubit wafer and the parametric Josephson wafer were instead packaged separately, one set of mounting brackets, magnetic shielding, and / or cooling devices would be required for the superconducting qubit wafer, and a duplicate set of mounting brackets, magnetic shielding, and / or cooling devices would be required for the parametric Josephson wafer. In contrast, because the superconducting qubit wafer can be bump bonded to the parametric Josephson wafer, a single set of mounting brackets, magnetic shielding, and / or cooling devices may be sufficient (e.g., a duplicate set of mounting brackets, magnetic shielding, and / or cooling devices may be avoided). Furthermore, while existing techniques for facilitating bump bonding can cause the parametric Josephson wafer to experience excessive mechanical / chemical degradation during subsequent fabrication / processing of the superconducting qubit wafer, the underfill may prevent such mechanical / chemical degradation from occurring and / or otherwise reduce such mechanical / chemical degradation to negligible levels.That is, the underfill injected between the superconducting qubit wafer and the parametric Josephson wafer can be considered to protect, preserve, and / or otherwise shield the parametric Josephson wafer from mechanical and / or chemical damage that would otherwise occur during fabrication / processing of the superconducting qubit wafer. Thus, the architecture described herein may consume less physical space than existing techniques that rely on separate packaging, without sacrificing performance of the superconducting qubit wafer and / or the parametric Josephson wafer. Such an architecture certainly constitutes a concrete, tangible technological improvement in the field of qubits.

[0070] As an added benefit, the underfill may, in some cases, even serve to mitigate / attenuate electromagnetic crosstalk that would otherwise occur between adjacent parametric Josephson devices on a parametric Josephson wafer. Again, such architectures certainly constitute concrete, tangible technological improvements in the field of qubits.

[0071] Furthermore, it must be emphasized that, prior to the teachings described herein, conventional wisdom discouraged the use of underfill materials in conjunction with quantum computing hardware. Indeed, it may even be considered surprising to those skilled in the art that underfill materials could be used in conjunction with such quantum computing hardware. After all, on the one hand, such underfill materials may typically have very high loss tangents (e.g., on the order of 1E-3), and on the other hand, quantum circuits are typically engineered to be ultra-low loss in order to maintain maximum qubit coherence. Thus, conventional wisdom would advise against implementing such high-loss underfills with quantum hardware intended / desired to be low-loss. However, the inventors have recognized that this conventional wisdom is incorrect with respect to parametric Josephson devices. More specifically, the inventors have recognized that parametric Josephson devices may often include dielectrics with comparable loss tangents within their constituent components and may typically be engineered to have low quality factors (or even no resonant structures in their traveling-wave geometry), and therefore may typically be more tolerant to loss. That is, electromagnetic signals manipulated by and / or otherwise associated with a parametric Josephson device may have limited interaction with lossy elements near such a parametric Josephson device. Furthermore, a parametric Josephson device may be engineered to have limited electromagnetic involvement within the underfill (e.g., which may be considered a lossy element) through the use of lumped element components such as parallel plate capacitors, Josephson junctions, and / or meander inductors. Thus, even materials with very high radio frequency absorption may be used within the underfill without high losses that would adversely affect the parametric Josephson device.Furthermore, a superconducting ground plane can be fabricated on the backside of the superconducting qubit wafer, which can limit undesired electromagnetic interactions between the superconducting qubits and the lossy underfill. Indeed, such a superconducting ground plane can also serve to prevent crosstalk that might otherwise occur between the superconducting qubits of the superconducting qubit wafer and the parametric Josephson devices of the parametric Josephson wafer. In either case, contrary to conventional wisdom, the inventors have devised a technique for implementing a lossy underfill to physically protect the parametric Josephson devices from mechanical / chemical degradation without experiencing performance degradation due to the underfill's high loss tangent. Again, such a technique would certainly be a concrete, tangible technological improvement in the field of qubits.

[0072] Furthermore, various embodiments described herein may include tangible hardware-based devices based on the disclosed teachings. For example, the embodiments described herein may include tangible qubits (e.g., superconducting qubits composed of Josephson junctions, such as transmon qubits) and / or tangible wafers (e.g., silicon wafers) on which such tangible qubits may be fabricated.

[0073] It is to be understood that the drawings and disclosure herein illustrate non-limiting examples of various embodiments. Further, it is to be understood that the drawings are not necessarily drawn to scale.

[0074] 1 shows a cross-sectional view of an exemplary, non-limiting high-density flip-chip co-package 100 for superconducting qubits and parametric Josephson devices according to one or more embodiments described herein. More specifically, FIG. 1 can be considered to depict a side view of the high-density flip-chip co-package 100.

[0075] As shown, high-density flip chip co-package 100 may include silicon wafer 102 and silicon wafer 104. In various embodiments, silicon wafer 102 may have any suitable shape (e.g., rectangular, circular, triangular, hexagonal, irregular) and / or dimensions (e.g., length, width, thickness) as desired. Similarly, silicon wafer 104 may have any suitable shape and / or dimensions as desired. In various examples, silicon wafer 102 and silicon wafer 104 may have the same and / or different shapes and / or the same and / or different dimensions. In either case, silicon wafer 102 may be considered to have a first side 106 and a second side 108. Similarly, silicon wafer 104 may be considered to have a first side 110 and a second side 112.

[0076] In various embodiments, as shown, a set of parametric Josephson devices 120 may be fabricated on the first side 106 of the silicon wafer 102. While FIG. 1 depicts the set of parametric Josephson devices 120 as including four parametric Josephson devices, this is merely a non-limiting example for ease of illustration. In various aspects, the set of parametric Josephson devices 120 may include any suitable number of parametric Josephson devices (e.g., at least one parametric Josephson device) as desired. As described above, a parametric device may be any suitable electronic circuit that utilizes a time-varying parameter to couple multiple modes of operation, and the parametric Josephson device may be a parametric device in which the time-varying parameter is a Josephson inductance. In various examples, one or more of the set of parametric Josephson devices 120 may be a Josephson traveling-wave parametric amplifier. In various other examples, one or more of the set of parametric Josephson devices 120 may be a Josephson parametric amplifier. In still other examples, one or more of the set of parametric Josephson devices 120 may be Josephson directional amplifiers. In yet other examples, one or more of the set of parametric Josephson devices 120 may be Josephson parametric converters. In yet other examples, one or more of the set of parametric Josephson devices 120 may be Josephson circulators. In various other examples, one or more of the set of parametric Josephson devices 120 may be Josephson isolators. In still various other examples, one or more of the set of parametric Josephson devices 120 may be traveling-wave frequency converters. In still various other examples, one or more of the set of parametric Josephson devices 120 may be traveling-wave frequency isolators.In some cases, the set of parametric Josephson devices 120 may include any suitable combination of singular and / or plural parametric Josephson devices of the types described above. Additionally, in various cases, any other suitable types of parametric Josephson devices may be included in the set of parametric Josephson devices 120.

[0077] In various embodiments, the set of parametric Josephson devices 120 may be fabricated on the first side 106 of the silicon wafer 102 by any suitable micro- and / or nano-fabrication techniques as desired. Non-limiting examples of such micro- and / or nano-fabrication techniques may include photolithography, vapor deposition, etching, dual angle evaporation, and / or electroplating. In various examples, the set of parametric Josephson devices 120 may be fabricated at any suitable locations and / or positions on / along the first side 106 of the silicon wafer 102 (e.g., the locations / positions of the set of parametric Josephson devices 120 on / along the first side 106 depicted in FIG. 1 are merely non-limiting examples for illustrative purposes).

[0078] In various embodiments, the set of superconducting qubits 124 may be fabricated on the first side 110 of the silicon wafer 104 as shown. While FIG. 1 depicts the set of superconducting qubits 124 as including three superconducting qubits, this is merely a non-limiting example for ease of illustration. In various cases, the set of superconducting qubits 124 may include any suitable number of superconducting qubits (e.g., at least one superconducting qubit) as desired. In various examples, one or more of the set of superconducting qubits 124 may be charge qubits. In other examples, one or more of the set of superconducting qubits 124 may be flux qubits. In yet other examples, one or more of the set of superconducting qubits 124 may be phase qubits. In yet other examples, one or more of the set of superconducting qubits 124 may be transmon qubits. In still other examples, one or more of the set of superconducting qubits 124 may be xmon qubits. In various other examples, one or more of the set of superconducting qubits 124 may be fluxonium qubits. In still various other examples, one or more of the set of superconducting qubits 124 may be quantronium qubits. In some cases, the set of superconducting qubits 124 may include any suitable combination and / or combinations of the above-mentioned types of superconducting qubits. Furthermore, in various cases, any other suitable type of superconducting qubit (e.g., any superconducting qubit architecture utilizing one or more Josephson junctions) may be included in the set of superconducting qubits 124.

[0079] In various embodiments, the set of superconducting qubits 124 may be fabricated on the first side 110 of the silicon wafer 104 by any suitable micro- and / or nano-fabrication techniques as desired. As mentioned above, such micro- and / or nano-fabrication techniques may include, for example, photolithography, vapor deposition, etching, dual-angle evaporation, and / or electroplating. In various cases, the set of superconducting qubits 124 may be fabricated at any suitable locations and / or positions on / along the first side 110 of the silicon wafer 104 (e.g., the locations / positions of the set of superconducting qubits 124 on / along the first side 110 depicted in FIG. 1 are merely non-limiting examples for illustrative purposes).

[0080] In various embodiments, as shown, the silicon wafer 104 may include a set of through-substrate vias 122 that may electrically couple / connect the first side 110 to the second side 112. While FIG. 1 depicts the set of through-substrate vias 122 as including 12 through-substrate vias, this is merely a non-limiting example for ease of illustration. In various cases, the set of through-substrate vias 122 may include any suitable number of through-substrate vias as desired (e.g., at least one through-substrate via). In various examples, the set of through-substrate vias 122 may be comprised of any suitable superconducting material as desired (e.g., aluminum, indium, niobium, tin, silver, or any suitable alloy thereof). While FIG. 1 depicts each of the set of through-substrate vias 122 as being made of the same material as one another, this is merely a non-limiting example for ease of illustration. In various cases, different ones of the set of through-substrate vias 122 may be comprised of the same and / or different superconducting materials as one another. 1 depicts each of the sets of through-substrate vias 122 as having the same shape and / or dimensions as one another, this is merely a non-limiting example for ease of illustration. In various embodiments, different ones of the sets of through-substrate vias 122 can have the same and / or different shapes / dimensions as one another.

[0081] In various embodiments, the set of through-substrate vias 122 can be fabricated between the first side 110 and the second side 112 of the silicon wafer 104 by any suitable micro- and / or nano-fabrication technique (e.g., photolithography, deposition, etching, dual angle evaporation, electroplating) as desired. In various examples, the set of through-substrate vias 122 can be fabricated in any suitable location and / or position between the first side 110 and the second side 112 of the silicon wafer 104 (e.g., the location / position of the set of through-substrate vias 122 between the first side 110 and the second side 112 depicted in FIG. 1 is merely a non-limiting example for illustrative purposes).

[0082] In various embodiments, as shown, the first side 106 of the silicon wafer 102 can be coupled to the second side 112 of the silicon wafer 104 by a set of bump bonds 114. While FIG. 1 depicts the set of bump bonds 114 as including three bump bonds, this is merely a non-limiting example for ease of illustration. In various cases, the set of bump bonds 114 can include any suitable number of bump bonds (e.g., at least one bump bond) as desired. In various examples, as shown, each of the set of bump bonds 114 can be comprised of a solder bump 116 sandwiched between two underbump metallizations 118. In various cases, the solder bumps 116 and / or the underbump metallizations 118 can be comprised of any suitable superconducting and / or solder material as desired. Non-limiting examples of such materials can include indium, an indium-tin alloy, an indium-silver alloy, tin, and / or a lead-tin alloy. In various embodiments, the solder bumps 116 and / or underbump metallization 118 can have any suitable shape and / or size as desired. While Figure 1 depicts each of the sets of bump bonds 114 as having the same shape and / or size as one another, this is merely a non-limiting example for ease of illustration. In various embodiments, different ones of the sets of bump bonds 114 can have the same and / or different shapes / sizes as one another.

[0083] In various embodiments, the set of bump bonds 114 can be fabricated by any suitable micro- and / or nano-fabrication technique (e.g., photolithography, vapor deposition, etching, dual angle evaporation, electroplating, injection molding) as desired. In various examples, the set of bump bonds 114 can be fabricated at any suitable location and / or position between the first side 106 of the silicon wafer 102 and the second side 112 of the silicon wafer 104 (e.g., the locations / positions of the set of bump bonds 114 between the first side 106 and the second side 112 depicted in FIG. 1 are merely non-limiting examples for illustrative purposes).

[0084] 1 , any other suitable superconducting wiring, non-superconducting wiring, coaxial cable wiring, superconducting circuit structures, non-superconducting circuit structures, and / or dielectric materials / structures may be fabricated on the first side 110 of the silicon wafer 104, on the second side 112 of the silicon wafer 104, on the first side 106 of the silicon wafer 102, on the second side 108 of the silicon wafer 104, between the first side 110 and the second side 112 of the silicon wafer 104, and / or between the first side 106 and the second side 108 of the silicon wafer 102. Such other wiring and / or structures have been omitted from FIG. 1 for ease of illustration and / or visual clarity.

[0085] In various examples, underfill 126 can be injected between first side 106 of silicon wafer 102 and second side 112 of silicon wafer 104 such that underfill 126 surrounds the set of bump bonds 114, surrounds / covers the set of parametric Josephson devices 120, and / or separates silicon wafer 102 from silicon wafer 104. In various embodiments, underfill 126 can be any suitable thermosetting epoxy. That is, underfill 126 can be any suitable composite material including both any suitable epoxy polymer combined with any suitable amount of any suitable filler. Non-limiting examples of such fillers can include silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and / or graphene. In some examples, the composition of underfill 126 may be controlled so that the thermal expansion coefficient of underfill 126 matches that of silicon wafer 102 and / or silicon wafer 104 (e.g., silicon wafer 102 and silicon wafer 104 may both be made of silicon and therefore have the same thermal expansion coefficient). In either case, underfill 126 may function and / or act as a barrier layer that prevents and / or otherwise mitigates mechanical stress and / or chemical corrosion that the set of parametric Josephson devices 120 would otherwise experience during subsequent fabrication / processing of the set of superconducting qubits 124. Furthermore, in various embodiments, underfill 126 may be considered to mitigate / ameliorate electromagnetic crosstalk that would otherwise occur between adjacent ones of the set of parametric Josephson devices 120.

[0086] Accordingly, high-density flip-chip co-package 100 may be viewed as a physical structure and / or architecture for packaging both a set of superconducting qubits 124 and a set of parametric Josephson devices 120 in a space-efficient and / or geometrically compact manner, without exposing the set of parametric Josephson devices 120 to excessive mechanical / chemical degradation caused by subsequent fabrication / processing of the set of superconducting qubits 124. For at least this reason, high-density flip-chip co-package 100 may be viewed as advantageous over existing techniques that involve separately packaging the set of superconducting qubits 124 and the set of parametric Josephson devices 120.

[0087] It should be noted that because the set of superconducting qubits 124 may be fabricated on silicon wafer 104, silicon wafer 104 may be considered and / or otherwise referred to as a superconducting qubit wafer. Similarly, because the set of parametric Josephson devices 120 may be fabricated on silicon wafer 102, silicon wafer 102 may be considered and / or otherwise referred to as a parametric Josephson wafer.

[0088] Although not explicitly shown in FIG. 1 , second side 112 of silicon wafer 104 may be equipped with any suitable grounded superconducting shield. In various aspects, the grounded superconducting shield may be one or more layers of superconducting material coupled to (e.g., grounded) ground. In some examples, such one or more layers of superconducting material may be equipped with any suitable array of holes / vias that may help trap magnetic flux. In various examples, when one or more grounded superconducting shields are present between second side 112 and first side 106, such one or more grounded superconducting shields may isolate, block, mitigate, and / or otherwise prevent undesired electromagnetic interactions (e.g., crosstalk) between the set of superconducting qubits 124 and the set of parametric Josephson devices 120. Furthermore, in various embodiments, such one or more grounded superconducting shields may isolate, inhibit, mitigate, and / or otherwise prevent the set of superconducting qubits 124 from being adversely affected by the high loss tangent of the underfill 126.

[0089] 2-13 show exemplary, non-limiting cross-sectional views 200-1300 illustrating how high-density flip-chip co-packages for superconducting qubits and parametric Josephson devices may be fabricated in accordance with one or more embodiments described herein. More specifically, FIGS. 2-13 depict various intermediate substrate structures that may be involved in fabricating high-density flip-chip co-package 100.

[0090] Consider first the cross-sectional view 200 of FIG. 2 . In various embodiments, as shown, a silicon wafer 102 may be provided and / or obtained in any suitable manner, and a set of parametric Josephson devices 120 may be fabricated on a first side 106 of the silicon wafer 102. As described above, any suitable micro- and / or nano-fabrication techniques may be implemented to fabricate the set of parametric Josephson devices 120, such as photolithography, deposition, etching, dicing, dual angle evaporation, and / or electroplating techniques. While not explicitly shown in FIG. 2 for ease of illustration and / or visual clarity, any other suitable circuit structures may be fabricated on the first side 106 of the silicon wafer 102 by such micro- and / or nano-fabrication techniques. Non-limiting examples of such other circuit structures may include superconducting wiring, non-superconducting wiring, coaxial cable wiring, under-bump metallization, and / or dielectric materials. Similarly, although not explicitly shown in FIG. 2 for ease of illustration and / or visual clarity, any such other suitable circuit structures may be fabricated by such micro- and / or nano-fabrication techniques on the second side 108 of the silicon wafer 102. In such cases, although not explicitly shown in FIG. 2 for ease of illustration and / or visual clarity, any suitable number of through-substrate vias may be fabricated between the first side 106 and the second side 108 of the silicon wafer 102 to electrically connect / couple the first side 106 to the second side 108.

[0091] Consider now the cross-sectional view 300 of FIG. 3 . In various embodiments, as shown, a photoresist layer 302 may be deposited on and / or across the first side 106 of the silicon wafer 102. In various aspects, the photoresist layer 302 may be composed of any suitable photoresist material as desired. For example, the photoresist layer 302 may be implemented using any suitable polymer, any suitable sensitizer, and / or any suitable solvent. In various cases, the photoresist layer 302 may have any suitable shape and / or dimension as desired. For example, the photoresist layer 302 may have any suitable thickness, and such thickness may be uniform and / or non-uniform throughout the photoresist layer 302 as desired. In some cases, the thickness of the photoresist layer 302 may correspond to (e.g., may be equal to and / or otherwise based on) the desired height of each of the set of bump bonds 114. While Figure 3 depicts the top surface of photoresist layer 302 as smooth, flat, and / or uniform, this is merely a non-limiting example for ease of illustration. Note that in practice, the top surface of photoresist layer 302 may be uneven in nature because photoresist layer 302 may be deposited on top of a set of parametric Josephson devices 120. More specifically, some portions of photoresist layer 302 may be displaced upward by the set of parametric Josephson devices 120, resulting in ridges along the top surface of photoresist layer 302. Such unevenness and / or ridges have been omitted from Figure 3 for ease of illustration and / or visual clarity.

[0092] In various aspects, a patterned mask 304 may be applied and / or positioned above the photoresist layer 302, as shown. In various examples, the patterned mask 304 may be composed of any suitable mask material, as desired. Furthermore, in various instances, the patterned mask 304 may assume any suitable shape and / or dimensions, as desired. Furthermore, in various aspects, the patterned mask 304 may include a set of cutouts 306. In various embodiments, the set of cutouts 306 may be positioned within the patterned mask 304 according to the desired locations of the set of bump bonds 114, and the set of cutouts 306 may be sized according to the desired size (e.g., desired width and / or desired diameter) of the set of bump bonds 114.

[0093] Consider now the cross-sectional view 400 of FIG. 4 . In various embodiments, as shown, a set of trenches may be excavated in the photoresist layer 302 by applying any suitable etching technique. More specifically, such etching may leave the patterned mask 304 unaffected and may also leave portions of the photoresist layer 302 protected by the patterned mask 304 unaffected. However, as shown, other portions of the photoresist layer 302 not protected by the patterned mask 304 (e.g., portions of the photoresist layer 302 underlying the set of cutouts 306) may be removed by such etching. Accordingly, the set of trenches may be positioned in the photoresist layer 302 according to the set of cutouts 306 (e.g., the set of trenches may correspond to and / or otherwise line up with the set of cutouts 306). In various cases, each of the set of trenches may extend all the way through the photoresist layer 302 to the first side 106 of the silicon wafer 102. After such trenches are excavated / etched into the photoresist layer 302, a layer of underbump metallization material may be deposited into each of the set of trenches above and / or across the first side 106 of the silicon wafer 102, thereby obtaining the underbump metallization 118. In various embodiments, the thickness of the underbump metallization 118 may depend on the extent and / or duration of deposition of the underbump metallization material, and the shape and / or lateral dimensions of the underbump metallization 118 may depend on the shape and / or dimensions of the set of trenches and / or of the set of cutouts 306. Similarly, after deposition of the underbump metallization 118, a layer of solder material may be deposited into each of the set of trenches above and / or across the underbump metallization 118, thereby obtaining the solder bumps 116.Again, in various cases, the thickness of the solder bump 116 may depend on the extent and / or duration of deposition of the solder bump material, and the shape and / or lateral dimensions of the solder bump 116 may depend on the shape and / or dimensions of the set of trenches and / or the set of cutouts 306. Although not explicitly shown in FIG. 4 , in various cases, such deposition may deposit a layer of under-bump metallization material and / or a layer of solder bump material above the patterned mask 304 (e.g., above the non-cutout portions of the patterned mask 304). Such deposited layers above the patterned mask 304 have been omitted from FIG. 4 for ease of illustration and / or visual clarity.

[0094] Consider now the cross-sectional view 500 of FIG. 5. In various embodiments, as shown, the photoresist layer 302 and / or the patterned mask 304 (and / or any deposited layers of under-bump metallization material and / or solder bump material deposited above the patterned mask 304) may be stripped and / or removed via any suitable technique. Thus, the set of parametric Josephson devices 120, the under-bump metallization 118, and / or the solder bumps 116 may remain on the first side 106 of the silicon wafer 102. Furthermore, as shown, the solder bumps 116 may be pre-formed into a bump shape via any suitable technique (e.g., reflow, electroplating, stencil printing, injection molding, annealing) as desired. In various cases, the silicon wafer 102 may now be considered prepared and / or ready for bump bonding.

[0095] Consider now the cross-sectional view 600 of FIG. 6 . In various embodiments, as shown, a silicon wafer 104 may be provided and / or obtained in any suitable manner, and a patterned mask 602 may be applied and / or positioned over the second side 112 of the silicon wafer 104. In various examples, the patterned mask 602 may be composed of any suitable mask material, as desired. Further, in various cases, the patterned mask 602 may assume any suitable shape and / or size, as desired. Further, in various aspects, the patterned mask 602 may include a set of cutouts 604. In various examples, the set of cutouts 604 may include any suitable number of cutouts. In some cases, the set of cutouts 604 may include one unique / unique cutout for each unique / unique through-substrate via in the set of through-substrate vias 122. In various embodiments, each of the sets of cutouts 604 can have any suitable shape and / or dimensions (e.g., any suitable length and / or width) as desired. In various cases, the sets of cutouts 604 can be positioned within the patterned mask 602 according to desired locations of the sets of through-substrate vias 122, and the sets of cutouts 604 can be sized according to desired sizes (e.g., desired widths and / or desired diameters) of the sets of through-substrate vias 122.

[0096] Consider now the cross-sectional view 700 of FIG. 7 . In various embodiments, as shown, a set of trenches may be excavated into the silicon wafer 104 by applying any suitable etching technique. More specifically, such etching may leave the patterned mask 602 unaffected and may also leave portions of the silicon wafer 104 protected by the patterned mask 602 unaffected. However, as shown, other portions of the silicon wafer 104 not protected by the patterned mask 602 (e.g., portions of the silicon wafer 104 underlying the set of cutouts 604) may be removed by such etching. Thus, the set of trenches may be positioned within the silicon wafer 104 according to the set of cutouts 604 (e.g., the set of trenches may correspond to and / or otherwise coincide with the set of cutouts 604). In some cases, as shown, each of the set of trenches may extend partially through the silicon wafer 104 from the second side 112 without reaching the first side 110. However, in other cases, any and / or all of the set of trenches may extend completely through the silicon wafer 104, from the second side 112 to the first side 110. In either case, after such trenches are drilled / etched into the silicon wafer 104, a layer of superconducting material may be deposited within each of the set of trenches in the silicon wafer 104, thereby resulting in a set of through-substrate vias 122. In various embodiments, the thickness of the set of through-substrate vias 122 may depend on the extent and / or duration of the deposition of the superconducting material, and the shape and / or lateral dimensions of the set of through-substrate vias 122 may depend on the shape and / or dimensions of the set of trenches and / or the set of cutouts 604. Although not explicitly shown in FIG. 7 , in various cases, such deposition may deposit a layer of superconducting material above the patterned mask 602 (e.g., above the non-cutout portions of the patterned mask 602).Such deposited layers above the patterned mask 602 have been omitted from FIG. 7 for ease of illustration and / or visual clarity.

[0097] Consider now the cross-sectional view 800 of FIG. 8 . In various embodiments, as shown, the patterned mask 602 may be removed, and a photoresist layer 802 may be deposited on and / or across the second side 112 of the silicon wafer 104. In various aspects, the photoresist layer 802 may be composed of any suitable photoresist material, as desired. For example, as described above, the photoresist layer 802 may be implemented using any suitable polymer, any suitable sensitizer, and / or any suitable solvent. In various cases, and similar to the above, the photoresist layer 802 may have any suitable shape and / or dimensions, as desired. For example, the photoresist layer 802 may have any suitable thickness, and such thickness may be uniform and / or non-uniform throughout the photoresist layer 802. In some cases, the thickness of the photoresist layer 802 may correspond to (eg, be equal to and / or otherwise be based on) the desired height of each of the sets of under bump metallization 118 .

[0098] In various embodiments, a patterned mask 804 may be applied and / or positioned above the photoresist layer 802, as shown. In various examples, the patterned mask 804 may be composed of any suitable mask material as desired. Further, in various cases, the patterned mask 804 may assume any suitable shape and / or dimensions as desired. Further, in various embodiments, the patterned mask 804 may include a set of cutouts 806. In various examples, the set of cutouts 806 may include any suitable number of cutouts. In some cases, the set of cutouts 806 may include one unique / unique cutout for each unique / unique bump bond in the set of bump bonds 114. In various embodiments, each of the set of cutouts 806 may have any suitable shape and / or dimensions (e.g., any suitable length and / or width) as desired. In various cases, the set of cutouts 806 may be positioned within the patterned mask 804 according to the desired locations of the set of bump bonds 114, and the set of cutouts 806 may be sized according to the desired size (e.g., desired width and / or desired diameter) of the set of bump bonds 114.

[0099] Consider now the cross-sectional view 900 of FIG. 9 . In various embodiments, as shown, a set of trenches may be excavated in the photoresist layer 802 by applying any suitable etching technique. More specifically, such etching may leave the patterned mask 804 unaffected and may also leave portions of the photoresist layer 802 protected by the patterned mask 804 unaffected. However, as shown, other portions of the photoresist layer 802 not protected by the patterned mask 804 (e.g., portions of the photoresist layer 802 underlying the set of cutouts 806) may be removed by such etching. Accordingly, the set of trenches may be positioned in the photoresist layer 802 according to the set of cutouts 806 (e.g., the set of trenches may correspond to and / or otherwise coincide with the set of cutouts 806). In various cases, each of the set of trenches may extend all the way through the photoresist layer 802 to the second side 112 of the silicon wafer 104. After such trenches are recessed / etched into the photoresist layer 802, a layer of underbump metallization material may be deposited in each of the set of trenches over and / or across the second side 112 of the silicon wafer 104, thereby resulting in underbump metallization 118. In various embodiments, the thickness of the underbump metallization 118 may depend on the extent and / or duration of the deposition of the underbump metallization material, and the shape and / or lateral dimensions of the underbump metallization 118 may depend on the shape and / or dimensions of the set of trenches and / or of the set of cutouts 806. Although not explicitly shown in FIG. 9 , in various cases, such deposition may deposit a layer of underbump metallization material over the patterned mask 804 (e.g., over the non-cutout portions of the patterned mask 804).Such deposited layers above the patterned mask 804 have been omitted from FIG. 9 for ease of illustration and / or visual clarity.

[0100] Consider now the cross-sectional view 1000 of Figure 10. In various embodiments, as shown, the photoresist layer 802 and / or the patterned mask 804 (and / or any deposited layer of under-bump metallization material deposited above the patterned mask 804) may be stripped and / or removed via any suitable technique. Thus, the under-bump metallization 118 may remain on the second side 112 of the silicon wafer 104. In various cases, the silicon wafer 104 may now be considered prepared and / or ready for bump bonding.

[0101] Consider now the cross-sectional view 1100 of FIG. 11 . In various embodiments, as shown, underbump metallization 118 on the second side 112 of silicon wafer 104 may be bonded to solder bumps 116 on the first side 106 of silicon wafer 102. In various aspects, any suitable bonding technique may be implemented to accomplish this. Non-limiting examples of such bonding techniques may include reflow bonding using magnetic flux or formic acid. Another non-limiting example of such a bonding technique may include thermocompression bonding. Yet another non-limiting example of such a bonding technique may include cold welding. In either case, a set of bump bonds 114 may be formed between the first side 106 of silicon wafer 102 and the second side 112 of silicon wafer 104, thereby bonding silicon wafer 102 to silicon wafer 104.

[0102] Consider now the cross-sectional view 1200 of FIG. 12 . In various embodiments, as shown, a set of bump bonds 114 may be considered to couple the first side 106 of the silicon wafer 102 to the second side 112 of the silicon wafer 104, but there may nevertheless be interstitial spaces and / or interstitial gaps surrounding each of the sets of bump bonds 114 and / or separating the first side 106 of the silicon wafer 102 from the second side 112 of the silicon wafer 104. In various aspects, underfill 126 may be injected into such interstitial spaces and / or interstitial gaps via any suitable injection technique. Accordingly, underfill 126 may now be considered to surround each of the sets of bump bonds 114, to surround each of the sets of parametric Josephson devices 120, and / or to separate the first side 106 of the silicon wafer 102 from the second side 112 of the silicon wafer 104. In various examples, any suitable curing technique may be implemented to cure the underfill 126. In other words, the underfill 126 may be cured at any suitable curing temperature and for any suitable curing period (e.g., at a high temperature for a short period or at a low temperature for a long period). As discussed above, the underfill 126 may be any suitable thermosetting epoxy as desired. That is, the underfill 126 may be any suitable composite comprised of a filler suspended within an epoxy polymer. Non-limiting examples of fillers may include silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and / or graphene. In various examples, the underfill 126 may exhibit any suitable ratio of filler to epoxy polymer.

[0103] Consider now the cross-sectional view 1300 of FIG. 13 . As mentioned above, the set of through-substrate vias 122 may, in some cases, be created so that they do not initially penetrate completely from the second side 112 of the silicon wafer 104 to the first side 110 of the silicon wafer 104. In such cases, as shown in FIG. 13 , the first side 110 of the silicon wafer 104 may be polished to expose the set of through-substrate vias 122 vias ....

[0104] In either case, after the set of through-substrate vias 122 are exposed in the first side 110 of the silicon wafer 104, the set of superconducting qubits 124 may be fabricated on the first side 110 of the silicon wafer 104. As mentioned above, any suitable micro- and / or nano-fabrication techniques may be implemented to fabricate the set of superconducting qubits 124, such as photolithography, deposition, etching, dicing, dual-angle evaporation, and / or electroplating techniques. Although not explicitly shown in FIG. 13 for ease of illustration and / or visual clarity, any other suitable circuit structures may be fabricated on the first side 110 of the silicon wafer 104 by such micro- and / or nano-fabrication techniques. Non-limiting examples of such other circuit structures may include superconducting wiring, non-superconducting wiring, coaxial cable wiring, under-bump metallization, and / or dielectric materials. It should be noted that underfill 126 may be considered to protect the set of parametric Josephson devices 120 during such micro- and / or nano-fabrication. In other words, underfill 126 may be considered a protective barrier that preserves the set of parametric Josephson devices 120 during subsequent fabrication processes (e.g., underfill 126 may prevent the set of parametric Josephson devices 120 from being mechanically and / or chemically damaged during polishing of silicon wafer 104 and / or fabrication of the set of superconducting qubits 124). In various embodiments, such fabrication may result in a high-density flip-chip co-package 100, as shown in FIG. 1 .

[0105] 14-16 show exemplary, non-limiting block diagrams 1400, 1500, and 1600 illustrating how high-density flip-chip co-packages for superconducting qubits and parametric Josephson devices may be fabricated in accordance with one or more embodiments described herein. That is, FIGS. 14-16 are helpful in illustrating how high-density flip-chip co-package 100 may be manufactured.

[0106] Consider first block diagram 1400 of Figure 14. In various embodiments, as shown, operation 1402 may include fabricating a set of parametric Josephson devices (e.g., 120) on a first side (e.g., 106) of a first silicon wafer (e.g., 102). In some cases, this may include fabricating any other suitable superconducting wiring, coaxial cabling, dielectric layers, and / or circuit structures on the first side of the first silicon wafer as desired.

[0107] In various embodiments, operation 1404 may include depositing a first photoresist layer (e.g., 302) on a first side of a first silicon wafer and disposing a first patterned mask (e.g., 304) above the first photoresist layer.

[0108] In various examples, operation 1406 may include etching a set of first trenches (e.g., trenches formed due to 306) in the first photoresist layer using a first patterned mask, and filling each of the set of first trenches with an underbump metallization layer (e.g., 118) and / or a solder layer (e.g., 116).

[0109] In various cases, operation 1408 may include removing / stripping the first patterned mask and / or the first photoresist layer from the first side of the first silicon wafer and preforming the solder layer into a bump shape.

[0110] Consider now block diagram 1500 of Figure 15. In various embodiments, operation 1502 may include placing a second patterned mask (e.g., 602) over a second side (e.g., 112) of a second silicon wafer (e.g., 104).

[0111] In various aspects, operation 1504 may include etching a set of second trenches (e.g., trenches formed due to 604) in a second silicon wafer using a second patterned mask and filling each of the set of second trenches with a superconducting material. Thus, the set of second trenches filled with superconducting material may be considered a set of through-substrate vias (e.g., 122).

[0112] In various examples, operation 1506 may include removing / stripping the second patterned mask, depositing a second photoresist layer (e.g., 802) on the second side of the second silicon wafer, and placing a third patterned mask (e.g., 804) on the second photoresist layer.

[0113] In various cases, operation 1508 may include etching a set of third trenches (e.g., trenches formed due to 806) in the second photoresist layer using a third patterned mask, and filling each of the set of third trenches with an underbump metallization layer (e.g., 118).

[0114] In various embodiments, operation 1510 can include removing / stripping the third patterned mask and the second photoresist layer from the second side of the second silicon wafer.

[0115] Consider now block diagram 1600 of Figure 16. In various embodiments, operation 1602 may include bonding an under-bump metallization layer disposed on the second side of the second silicon wafer to a pre-formed solder layer disposed on the first side of the first silicon wafer, thereby forming a set of bump bonds (e.g., 114) that bond the first silicon wafer to the second silicon wafer.

[0116] In various embodiments, operation 1604 may include injecting an underfill (e.g., 126) between the first side of the first silicon wafer and the second side of the second silicon wafer. The underfill may therefore be considered to separate the first silicon wafer from the second silicon wafer and / or surround the set of bump bonds.

[0117] In various examples, operation 1606 may include polishing the first side (e.g., 110) of the second silicon wafer to expose the set of through-substrate vias, as appropriate and / or required. If the set of through-substrate vias is already exposed through the first side of the second silicon wafer, such polishing may be omitted.

[0118] In various cases, operation 1608 may include fabricating a set of superconducting qubits (e.g., 124) including Josephson junctions on the polished first surface of the second silicon wafer. In some cases, this may include fabricating any other suitable superconducting wiring, coaxial cabling, dielectric layers, and / or circuit structures on the polished first surface of the second silicon wafer, as desired.

[0119] 17-18 show exemplary, non-limiting cross-sectional views 1700-1800 illustrating how high-density flip-chip co-packages for superconducting qubits and parametric Josephson devices can be bonded to interposers and / or organic substrates in accordance with one or more embodiments described herein.

[0120] Consider first cross-sectional view 1700 of FIG. 17. In various embodiments, there may be an interposer wafer 1702 as shown. In various aspects, interposer wafer 1702 may have any suitable shape (e.g., rectangular, circular, triangular, hexagonal, irregular) and / or dimensions (e.g., length, width, thickness) as desired. In various examples, interposer wafer 1702 may be composed of any suitable quantum computing substrate material (e.g., silicon) as desired. In either case, interposer wafer 1702 may be considered to have a first side 1704 and a second side 1706.

[0121] In various embodiments, the set of resonators 1708 may be fabricated on the first side 1704 of the interposer wafer 1702 as shown. While FIG. 17 depicts the set of resonators 1708 as including seven resonators, this is merely a non-limiting example for ease of illustration. In various aspects, the set of resonators 1708 may include any suitable number of resonators (e.g., at least one resonator) as desired. In various examples, the set of resonators 1708 may include any suitable type and / or types of resonators (e.g., quantum readout resonators) exhibiting any suitable resonator architecture as desired. In various cases, the set of resonators 1708 may be fabricated on the first side 1704 of the interposer wafer 1702 by any suitable microfabrication and / or nanofabrication techniques (e.g., photolithography, deposition, etching, dual angle evaporation, electroplating) as desired. In various examples, the set of resonators 1708 may be fabricated at any suitable location and / or position on or along the first surface 1704 of the interposer wafer 1702 (e.g., the locations / positions of the set of resonators 1708 on or along the first surface 1704 depicted in FIG. 17 are merely non-limiting examples for illustrative purposes).

[0122] In various embodiments, as shown, the high-density flip-chip copackage 100 may be bump-bonded to the interposer wafer 1702. More specifically, a set of bump bonds 1710 may couple the first side 110 of the silicon wafer 104 to the first side 1704 of the interposer wafer 1702. While FIG. 17 depicts the set of bump bonds 1710 as including two bump bonds, this is merely a non-limiting example for ease of illustration. In various examples, the set of bump bonds 1710 may include any suitable number of bump bonds (e.g., at least one bump bond) as desired. In various examples, as shown, each of the set of bump bonds 1710 may be comprised of a solder bump sandwiched between two under-bump metallizations, similar to each of the set of bump bonds 114. 17 depicts each of the set of bump bonds 1710 as having the same shape, size, and / or composition as each of the set of bump bonds 114, this is merely a non-limiting example for ease of illustration. In various cases, any of the set of bump bonds 1710 can have the same and / or different shape, size, and / or composition as any of the set of bump bonds 114. Indeed, in some cases, the set of bump bonds 114 can be physically smaller than each of the set of bump bonds 1710, which can be beneficial to conserve space. In various embodiments, the set of bump bonds 1710 can be fabricated by any suitable micro- and / or nano-fabrication technique (e.g., photolithography, vapor deposition, etching, dual angle evaporation, electroplating) as desired. In various examples, the set of bump bonds 1710 may be fabricated at any suitable location and / or position between the first surface 110 of the silicon wafer 104 and the first surface 1704 of the interposer wafer 1702 (e.g., the locations / positions of the set of bump bonds 1710 between the first surface 110 and the first surface 1704 depicted in FIG. 17 are merely non-limiting examples for illustrative purposes).

[0123] Although not explicitly shown in Figure 17, any other suitable superconducting wiring, non-superconducting wiring, coaxial cable wiring, superconducting circuit structures, non-superconducting circuit structures, and / or dielectric materials / structures may be fabricated on first side 1704 of interposer wafer 1702, as desired, on second side 1706 of interposer wafer 1702, and / or between first side 1704 and second side 1706 of interposer wafer 1702, as desired. Such other wiring and / or structures have been omitted from Figure 17 for ease of illustration and / or visual clarity.

[0124] Consider now the cross-sectional view 1800 of FIG. 18 . In various embodiments, an organic substrate 1802 may be present, as shown. In various aspects, the organic substrate 1802 may have any suitable shape (e.g., rectangular, circular, triangular, hexagonal, irregular) and / or dimensions (e.g., length, width, thickness) as desired. In various examples, the organic substrate 1802 may be composed of any suitable material as desired. As some non-limiting examples, the organic substrate 1802 may be a printed circuit board, a flexible printed circuit board, and / or a laminate. Although not explicitly shown in FIG. 18 , any other suitable superconducting wiring, non-superconducting wiring, coaxial cable wiring, superconducting circuit structures, non-superconducting circuit structures, and / or dielectric materials / layers may be fabricated on the organic substrate 1802. Such other wiring / structures / layers have been omitted from FIG. 18 for ease of illustration and / or visual clarity.

[0125] In either case, as shown, interposer wafer 1702 can be bump bonded to organic substrate 1802. More specifically, a set of bump bonds 1804 can couple first surface 1704 of interposer wafer 1702 to organic substrate 1802. While FIG. 18 depicts set of bump bonds 1804 as including two bump bonds, this is merely a non-limiting example for ease of illustration. In various embodiments, set of bump bonds 1804 can include any suitable number of bump bonds (e.g., at least one bump bond) as desired. In various examples, as shown, each of set of bump bonds 1804 can be comprised of a solder bump sandwiched between two under-bump metallizations, like each of set of bump bonds 114 and / or like each of set of bump bonds 1710. 18 depicts each of the set of bump bonds 1804 as having the same shape, size, and / or composition as each of the set of bump bonds 114 and / or each of the set of bump bonds 1710, this is merely a non-limiting example for ease of illustration. In various cases, any of the set of bump bonds 1804 can have the same and / or different shape, size, and / or composition as any of the set of bump bonds 114 and / or any of the set of bump bonds 1710. In various embodiments, the set of bump bonds 1804 can be fabricated by any suitable micro- and / or nano-fabrication technique (e.g., photolithography, vapor deposition, etching, dual angle evaporation, electroplating) as desired. In various examples, the set of bump bonds 1804 may be fabricated at any suitable location and / or position between the first surface 1704 of the interposer wafer 1702 and the organic substrate 1802 (e.g., the location / position of the set of bump bonds 1804 between the first surface 1704 and the organic substrate 1802 depicted in FIG. 18 is merely a non-limiting example for illustrative purposes).

[0126] 17-18 depict a single instance of high density flip chip co-package 100 bump bonded to interposer wafer 1702, this is merely a non-limiting example for ease of illustration. In various embodiments, any suitable number of high density flip chip co-packages (e.g., two or more instances and / or copies of high density flip chip co-package 100) can be bump bonded to first side 1704 of interposer wafer 1702.

[0127] 19-20 show exemplary, non-limiting cross-sectional views illustrating how high-density flip-chip co-packages for superconducting qubits and parametric Josephson devices can be bonded to alternative interposers and / or organic substrates in accordance with one or more embodiments described herein.

[0128] Consider first cross-sectional view 1900 of FIG. 19 . In various embodiments, there may be interposer wafer 1902 and interposer wafer 1908 as shown. In various aspects, interposer wafer 1902 may have any suitable shape (e.g., rectangular, circular, triangular, hexagonal, irregular) and / or dimensions (e.g., length, width, thickness) as desired. Similarly, interposer wafer 1908 may have any suitable shape and / or dimensions as desired. In various examples, interposer wafer 1902 and interposer wafer 1908 may have the same and / or different shapes and / or the same and / or different dimensions. In either case, interposer wafer 1902 may be considered to have a first side 1904 and a second side 1906. Similarly, interposer wafer 1908 may be considered to have first side 1910 and second side 1912. Furthermore, in various aspects, interposer wafer 1902 and / or interposer wafer 1908 may be composed of any suitable quantum computing substrate material as desired (e.g., both may be made of silicon).

[0129] In various embodiments, a set of parametric Josephson devices 1914 may be fabricated on the first side 1904 of the interposer wafer 1902 as shown. While FIG. 19 depicts the set of parametric Josephson devices 1914 as including ten parametric Josephson devices, this is merely a non-limiting example for ease of illustration. In various cases, the set of parametric Josephson devices 1914 may include any suitable number of parametric Josephson devices (e.g., at least one parametric Josephson device) as desired. In various examples, one or more of the set of parametric Josephson devices 1914 may be a Josephson traveling-wave parametric amplifier, a Josephson parametric amplifier, a Josephson directional amplifier, a Josephson parametric converter, a Josephson circulator, a Josephson isolator, a traveling-wave frequency converter, a traveling-wave frequency isolator, any suitable combination and / or combinations thereof, and / or any other suitable type of parametric Josephson device. In various embodiments, the set of parametric Josephson devices 1914 may be fabricated on the first side 1904 of the interposer wafer 1902 by any suitable micro- and / or nano-fabrication techniques (e.g., photolithography, vapor deposition, etching, dual angle evaporation, electroplating) as desired. In various cases, the set of parametric Josephson devices 1914 may be fabricated at any suitable locations and / or positions on / along the first side 1904 of the interposer wafer 1902 (e.g., the locations / positions of the set of parametric Josephson devices 1914 on / along the first side 1904 depicted in FIG. 19 are merely non-limiting examples for illustrative purposes).

[0130] In various embodiments, the set of resonators 1916 can be fabricated on the first side 1910 of the interposer wafer 1908 as shown. While FIG. 19 depicts the set of resonators 1916 as including seven resonators, this is merely a non-limiting example for ease of illustration. In various cases, the set of resonators 1916 can include any suitable number of resonators (e.g., at least one resonator) as desired. In various examples, the set of resonators 1916 can include any suitable type and / or types of resonators (e.g., quantum readout resonators) exhibiting any suitable resonator architecture as desired. In various cases, the set of resonators 1916 can be fabricated on the first side 1910 of the interposer wafer 1908 by any suitable microfabrication and / or nanofabrication techniques (e.g., photolithography, deposition, etching, dual angle evaporation, electroplating) as desired. In various examples, the set of resonators 1916 may be fabricated at any suitable location and / or position on / along the first side 1910 of the interposer wafer 1908 (e.g., the locations / positions of the set of resonators 1916 on / along the first side 1910 depicted in FIG. 19 are merely non-limiting examples for illustrative purposes).

[0131] In various embodiments, as shown, the interposer wafer 1908 can include a set of through-substrate vias 1918 that can electrically couple / connect the first side 1910 to the second side 1912. While FIG. 19 depicts the set of through-substrate vias 1918 as including 12 through-substrate vias, this is merely a non-limiting example for ease of illustration. In various embodiments, the set of through-substrate vias 1918 can include any suitable number of through-substrate vias as desired (e.g., at least one through-substrate via). In various examples, the set of through-substrate vias 1918 can be comprised of any suitable superconducting material as desired. While FIG. 19 depicts each of the set of through-substrate vias 1918 as being made of the same material as one another, this is merely a non-limiting example for ease of illustration. In various cases, different ones of the set of through-substrate vias 1918 can be comprised of the same and / or different superconducting materials as one another. 19 depicts each of the sets of through-substrate vias 1918 as having the same shape and / or dimensions as one another, this is merely a non-limiting example for ease of illustration. In various embodiments, different ones of the sets of through-substrate vias 1918 can have the same and / or different shapes / dimensions as one another. In various cases, the sets of through-substrate vias 1918 can be fabricated between the first side 1910 and the second side 1912 of the interposer wafer 1908 by any suitable micro- and / or nano-fabrication techniques (e.g., photolithography, deposition, etching, dual angle evaporation, electroplating) as desired. In various examples, the set of through-substrate vias 1918 may be fabricated in any suitable location and / or position between the first side 1910 and the second side 1912 of the interposer wafer 1908 (e.g., the location / position of the set of through-substrate vias 1918 between the first side 1910 and the second side 1912 depicted in FIG. 19 is merely a non-limiting example for illustrative purposes).

[0132] In various embodiments, as shown, first side 1904 of interposer wafer 1902 can be coupled to second side 1912 of interposer wafer 1908 by a set of bump bonds 1920. While FIG. 19 depicts the set of bump bonds 1920 as including five bump bonds, this is merely a non-limiting example for ease of illustration. In various embodiments, the set of bump bonds 1920 can include any suitable number of bump bonds (e.g., at least one bump bond) as desired. In various examples, as shown, each of the set of bump bonds 1920 can be comprised of a solder bump sandwiched between two under-bump metallizations, similar to each of the set of bump bonds 114. Although FIG. 19 depicts each of the set of bump bonds 1920 as having the same shape, size, and / or composition as each of the set of bump bonds 114, this is merely a non-limiting example for ease of illustration. In various cases, any of the sets of bump bonds 1920 may have the same and / or different shape, size, and / or composition as any of the sets of bump bonds 114. Indeed, in some cases, the sets of bump bonds 114 may be physically smaller than each of the sets of bump bonds 1920, which may be beneficial to conserve space. In various examples, the sets of bump bonds 1920 may be manufactured by any suitable micro- and / or nano-fabrication techniques (e.g., photolithography, vapor deposition, etching, dual angle evaporation, electroplating, injection molding) as desired. In various cases, the set of bump bonds 1920 may be fabricated at any suitable location and / or position between the first side 1904 of the interposer wafer 1902 and the second side 1912 of the interposer wafer 1908 (e.g., the location / position of the set of bump bonds 1920 between the first side 1904 and the second side 1912 depicted in FIG. 19 is merely a non-limiting example for illustrative purposes).

[0133] Although not explicitly shown in FIG. 19 , any other suitable superconducting wiring, non-superconducting wiring, coaxial cable wiring, superconducting circuit structures, non-superconducting circuit structures, and / or dielectric materials / structures may be fabricated on the first side 1910 of interposer wafer 1908 as desired, on the second side 1912 of interposer wafer 1908 as desired, on the first side 1904 of interposer wafer 1902 as desired, on the second side 1906 of interposer wafer 1902 as desired, between the first side 1910 and second side 1912 of interposer wafer 1908 as desired, and / or between the first side 1904 and second side 1906 of interposer wafer 1902 as desired. Such other wiring and / or structures have been omitted from FIG. 19 for ease of illustration and / or visual clarity.

[0134] In various embodiments, as shown, the high-density flip chip copackage 100 can be bump bonded to the interposer wafer 1908. More specifically, a set of bump bonds 1922 can couple the first side 1910 of the interposer wafer 1908 to the first side 110 of the silicon wafer 104. While FIG. 19 depicts the set of bump bonds 1922 as including two bump bonds, this is merely a non-limiting example for ease of illustration. In various embodiments, the set of bump bonds 1922 can include any suitable number of bump bonds (e.g., at least one bump bond) as desired. In various examples, as shown, each of the set of bump bonds 1922 can be comprised of a solder bump sandwiched between two under-bump metallizations, like each of the set of bump bonds 114 and / or like each of the set of bump bonds 1920. 19 depicts each of the sets of bump bonds 1922 as having the same shape, size, and / or composition as each of the sets of bump bonds 114 and / or each of the sets of bump bonds 1920, this is merely a non-limiting example for ease of illustration. In various cases, any of the sets of bump bonds 1922 can have the same and / or different shape, size, and / or composition as any of the sets of bump bonds 114 and / or any of the sets of bump bonds 1920. Indeed, in some cases, the sets of bump bonds 114 can be physically smaller than each of the sets of bump bonds 1920 and / or each of the sets of bump bonds 1922, which can be beneficial to conserve space. In various embodiments, the sets of bump bonds 1922 can be fabricated by any suitable micro- and / or nano-fabrication techniques (e.g., photolithography, vapor deposition, etching, dual angle evaporation, electroplating) as desired.In various examples, the set of bump bonds 1922 may be fabricated at any suitable location and / or position between the first surface 110 of the silicon wafer 104 and the first surface 1910 of the interposer wafer 1908 (e.g., the location / position of the set of bump bonds 1922 between the first surface 110 and the first surface 1910 depicted in FIG. 19 is merely a non-limiting example for illustrative purposes).

[0135] In various examples, underfill 1924 can be injected between first side 1904 of interposer wafer 1902 and second side 1912 of interposer wafer 1908 such that underfill 1924 surrounds set of bump bonds 1920, surrounds / covers set of parametric Josephson devices 1914, and / or separates interposer wafer 1902 from interposer wafer 1908. In various aspects, underfill 1924 can be any suitable thermosetting epoxy (e.g., can include any suitable epoxy polymer in combination with any suitable amount of any suitable filler). In some cases, underfill 1924 can have the same and / or different composition as underfill 126. In some examples, the composition of underfill 1924 may be controlled so that the thermal expansion coefficient of underfill 1924 matches that of interposer wafer 1902 and / or interposer wafer 1908 (e.g., interposer wafer 1902 and interposer wafer 1908 may both be made of silicon and therefore have the same thermal expansion coefficient). In either case, underfill 1924 may function and / or act as a barrier layer to prevent and / or mitigate mechanical stress and / or chemical corrosion that the set of parametric Josephson devices 1914 would otherwise experience during subsequent fabrication processing.

[0136] Consider now the cross-sectional view 2000 of Figure 20. In various embodiments, as shown, an interposer wafer 1908 can be bump bonded to an organic substrate 1802 by a set of bump bonds 1804. While Figure 20 depicts each of the set of bump bonds 1804 as having the same shape, size, and / or composition as each of the set of bump bonds 114, each of the set of bump bonds 1920, and / or each of the set of bump bonds 1922, this is merely a non-limiting example for ease of illustration. In various cases, any of the set of bump bonds 1804 can have the same and / or different shape, size, and / or composition as any of the set of bump bonds 114, any of the set of bump bonds 1920, and / or any of the set of bump bonds 1922.

[0137] 19-20 depict a single instance of high density flip chip co-package 100 bump bonded to interposer wafer 1908, this is merely a non-limiting example for ease of illustration. In various embodiments, any suitable number of high density flip chip co-packages (e.g., two or more instances and / or copies of high density flip chip co-package 100) can be bump bonded to first side 1910 of interposer wafer 1908.

[0138] 21 shows a cross-sectional view of an exemplary, non-limiting high-density flip-chip co-package for superconducting qubits and parametric Josephson devices including a trimmable air bridge for frequency tuning, in accordance with one or more embodiments described herein. More specifically, FIG. 21 depicts high-density flip-chip co-package 2100, which may be considered an alternative to high-density flip-chip co-package 100.

[0139] In various embodiments, the silicon wafer 102, the silicon wafer 104, the set of bump bonds 114, the set of parametric Josephson devices 120, the set of through-substrate vias 122, the set of superconducting qubits 124, and / or the underfill 126 may be as described above. However, in various aspects, the segmented electrodes 2102 may be disposed on the second side 112 of the silicon wafer 104, and the hollow photoresist columns / pillars 2104 may prevent the underfill 126 from covering the segmented electrodes 2102. In particular, the segmented electrodes 2102 may include one or more air bridges that are laser trimmable to adjust the operating frequency of one or more of the set of superconducting qubits 124. Furthermore, the hollow photoresist columns / pillars 2104 may circumscribe the segmented electrodes 2102 and / or extend from the first side 106 of the silicon wafer 102 to the second side 112 of the silicon wafer 104. In various cases, the segmented electrodes 2102 and / or hollow photoresist columns / pillars 2104 may be fabricated by any suitable micro- and / or nano-fabrication technique (e.g., photolithography, deposition, etching, dual angle evaporation, electroplating) prior to the injection of the underfill 126. Thus, when the underfill 126 is injected between the silicon wafer 102 and the silicon wafer 104, the hollow photoresist columns / pillars 2104 may prevent the underfill 126 from covering the segmented electrodes 2102. Thus, the segmented electrodes 2102 may be trimmed by any suitable laser that can pass through the silicon wafer 102 (e.g., the wavelength of the laser may be controllably set to any suitable value at which the silicon wafer 102 behaves as transparent). Such laser trimming of the air bridges of the segmented electrodes 2102, which may correspondingly adjust the operating frequency of one or more of the sets of superconducting qubits 124, is more fully illustrated in FIGS. 22-23 .

[0140] While Figure 21 depicts a single segmented electrode 2102 as being disposed on the second side 112 of the silicon wafer 104, this is merely a non-limiting example for ease of illustration. In various cases, any suitable number of segmented electrodes can be fabricated on the second side 112 (and / or on the first side 110) of the silicon wafer 104. Similarly, while Figure 21 depicts a single hollow photoresist column / pillar 2104, this is merely a non-limiting example for ease of illustration. In various embodiments, any suitable number of hollow photoresist columns / pillars can be fabricated between the silicon wafer 104 and / or the silicon wafer 102.

[0141] 22-23 show exemplary, non-limiting cross-sectional views 2200 and 2300 illustrating how high-density flip-chip co-packages for superconducting qubits and parametric Josephson devices, including trimmable air bridges for frequency tuning, may be bonded to an interposer and / or organic substrate, in accordance with one or more embodiments described herein.

[0142] Consider first the cross-sectional view 2200 of FIG. 22 . In various embodiments, as shown, the interposer wafer 1702, the set of resonators 1708, the set of bump bonds 1710, the organic substrate 1802, and / or the set of bump bonds 1804 may be as described above. However, in various aspects, instead of the high-density flip-chip copackage 100, the high-density flip-chip copackage 2100 may be coupled to the interposer wafer 1702 by the set of bump bonds 1710. In such a case, the second side 108 of the silicon wafer 102 may be considered to face upward, as shown. Thus, in various examples, the laser 2202 may be directed downward toward the second side 108 of the silicon wafer 102. In various cases, the wavelength of the laser 2202 may be controllably set such that the laser 2202 may pass transparently through the silicon wafer 102. Thus, laser 2202 may strike one or more air bridges of segmented electrode 2102 and melt, cut, and / or otherwise trim it, thereby facilitating tuning of the set of superconducting qubits 124.

[0143] Consider now cross-sectional view 2300 of FIG. 23 . In various embodiments, as shown, interposer wafer 1902, interposer wafer 1908, set of resonators 1916, set of parametric Josephson devices 1914, set of through-substrate vias 1918, set of bump bonds 1920, set of bump bonds 1922, organic substrate 1802, and / or set of bump bonds 1804 may be as described above. However, in various aspects, instead of high-density flip-chip copackage 100, high-density flip-chip copackage 2100 may be coupled to interposer wafer 1908 by set of bump bonds 1922. In such cases, as shown, second side 108 of silicon wafer 102 may be considered to face upward. Thus, in various examples, laser 2202 may be directed downward toward second side 108 of silicon wafer 102. As mentioned above, the wavelength of laser 2202 can be controllably set such that laser 2202 can pass transparently through silicon wafer 102. Thus, laser 2202 can impinge on one or more air bridges of segmented electrode 2102, thereby facilitating tuning of a set of superconducting qubits 124.

[0144] 24-25 show cross-sectional views of another exemplary, non-limiting, high-density flip-chip co-package for superconducting qubits and parametric Josephson devices bonded to an interposer and / or organic substrate according to one or more embodiments described herein.

[0145] 24. As shown, there may be a structure 2400 that includes a silicon wafer 104, a set of through-substrate vias 122, and / or a set of superconducting qubits 124. As can be seen, structure 2400 may be considered equivalent to high-density flip-chip copackage 100, minus silicon wafer 102, minus set of parametric Josephson devices 120, minus set of bump bonds 114, and / or minus underfill 126.

[0146] Consider now block diagram 2500 of Figure 25. In various embodiments, as shown, interposer wafer 1902, interposer wafer 1908, set of resonators 1916, set of parametric Josephson devices 1914, set of through-substrate vias 1918, set of bump bonds 1920, set of bump bonds 1922, organic substrate 1802, and / or set of bump bonds 1804 may be as described above. However, in various aspects, instead of high-density flip-chip co-package 100, structure 2400 may be coupled to interposer wafer 1908 by set of bump bonds 1922. Similar to above, the underfill 1924 separating the interposer wafer 1902 from the interposer wafer 1908 can be considered a protective shield / barrier that eliminates and / or ameliorates excessive mechanical / chemical damage that the set of parametric Josephson devices 1914 would otherwise experience during subsequent fabrication processing (e.g., during bump bonding of the structure 2400 to the interposer wafer 1908).

[0147] FIG. 26 illustrates a block diagram of an exemplary, non-limiting method 2600 for facilitating high-density flip-chip co-packaging for superconducting qubits and parametric Josephson devices, according to one or more embodiments described herein.

[0148] In various embodiments, operation 2602 may include bonding a superconducting qubit wafer (e.g., 104) to a parametric Josephson wafer (e.g., 102) by one or more first bump bonds (e.g., 114).

[0149] In various aspects, operation 2604 may include injecting a first underfill (e.g., 126) between the superconducting qubit wafer and the parametric Josephson wafer such that the first underfill surrounds one or more bump bonds and / or surrounds / covers one or more parametric Josephson devices of the parametric Josephson wafer.

[0150] 26 , at least one first parametric Josephson device (e.g., 120) may be disposed on the first side (e.g., 106) of the parametric Josephson wafer, and / or at least one superconducting qubit (e.g., 124) including a Josephson junction may be disposed on the first side (e.g., 110) of the superconducting qubit wafer. In various cases, the superconducting qubit wafer may include at least one first through-substrate via (e.g., 122) electrically connecting the first side of the superconducting qubit wafer to the second side (e.g., 112) of the superconducting qubit wafer. In various embodiments, one or more first bump bonds may couple the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer.

[0151] 26 , method 2600 may further comprise: bonding an interposer wafer (e.g., 1702) to the superconducting qubit wafer by one or more second bump bonds (e.g., 1710), where at least one resonator (e.g., 1708) may be disposed on a first side (e.g., 1704) of the interposer wafer, and the one or more second bump bonds may bond the first side of the interposer wafer to the first side of the superconducting qubit wafer. In various cases, the first side of the interposer wafer may be bump bonded (e.g., by 1804) to an organic substrate (e.g., 1802), where the organic substrate may be a printed circuit board, a flexible printed circuit board, and / or a laminate.

[0152] 26 , method 2600 may further comprise bonding the first interposer wafer (e.g., 1902) to the second interposer wafer (e.g., 1908) by one or more second bump bonds (e.g., 1920); and injecting a second underfill (e.g., 1924) between the first interposer wafer and the second interposer wafer, such that the second underfill surrounds the one or more second bump bonds. In various aspects, at least one second parametric Josephson device (e.g., 1914) may be disposed on the first side (e.g., 1904) of the first interposer wafer, and / or at least one resonator (e.g., 1916) may be disposed on the first side (e.g., 1910) of the second interposer wafer. In various examples, at least one second through-substrate via (e.g., 1918) may electrically connect the first side of the second interposer wafer to the second side of the second interposer wafer (e.g., 1912), and one or more second bump bonds may couple the first side of the first interposer wafer to the second side of the second interposer wafer. In various cases, the first side of the superconducting qubit wafer may be bump-bonded to the first side of the second interposer wafer by one or more third bump bonds (e.g., 1922). In various examples, the first side of the second interposer wafer may be bump-bonded (e.g., by 1804) to an organic substrate (e.g., 1802), where the organic substrate may be a printed circuit board, a flexible printed circuit board, and / or a laminate.

[0153] 26 , at least one segmented electrode (e.g., 2102) corresponding to at least one superconducting qubit may be disposed on the second side of the superconducting qubit wafer, where the at least one segmented electrode may include at least one air bridge that is trimmable to adjust the operating frequency of the at least one superconducting qubit. In various cases, at least one hollow photoresist column (e.g., 2104) may extend from the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer to prevent the first underfill from covering the at least one air bridge.

[0154] Although not explicitly depicted in FIG. 26 , method 2600 may include: bonding another superconducting qubit wafer (e.g., another instance of 104) to another parametric Josephson wafer (e.g., another instance of 102) by one or more second bump bonds (e.g., another instance of 114); bonding another superconducting qubit wafer (e.g., another instance of 104) to another parametric Josephson wafer (e.g., another instance of 102) by one or more second bump bonds; bonding another superconducting qubit wafer (e.g., another instance of 126) to another parametric Josephson wafer (e.g., another instance of 126) by one or more second bump bonds; and bonding both the superconducting qubit wafer and the other superconducting qubit wafer to an interposer wafer (e.g., 1702 and / or 1908) by one or more third bump bonds (e.g., another example of 1710 or another example of 1922), where the interposer wafer may be bump bonded to an organic substrate (e.g., 1802).

[0155] Various embodiments described herein may provide a flip-chip package, where such a flip-chip package may comprise: a first wafer (e.g., 102) bump-bonded to a second wafer (e.g., 104), where the first wafer has one or more parametric Josephson devices (e.g., 120) and the second wafer has one or more superconducting qubits (e.g., 124); and an underfill (e.g., 126) separating the first wafer from the second wafer. In various cases, the underfill may protect and / or preserve the one or more parametric Josephson devices from mechanical and / or chemical damage that would otherwise occur during subsequent fabrication and / or processing of the one or more superconducting qubits.

[0156] In various embodiments, such a flip-chip package may further comprise: an interposer (e.g., 1702; or collectively 1902 and 1908) bump-bonded to both the second wafer and the organic substrate (e.g., 1802). In various examples, the interposer may have one or more resonators (e.g., 1708; or 1916). In various cases, the interposer may have a first interposer wafer (e.g., 1902) bump-bonded (e.g., by 1920) to a second interposer wafer (e.g., 1908), the first interposer wafer may include one or more other parametric Josephson devices (e.g., 1914), the second interposer wafer may include one or more resonators (e.g., 1916), where another underfill (e.g., 1924) may separate the first interposer wafer from the second interposer wafer, the second wafer may be bump-bonded (e.g., by 1922) to the second interposer wafer, and / or the another underfill may protect / preserve the one or more other parametric Josephson devices from mechanical and / or chemical damage.

[0157] Thus, the various embodiments described herein may be viewed as high-density flip-chip co-packages that can package both superconducting qubits and parametric Josephson devices without any and / or negligible mechanical / chemical degradation that plagues parametric Josephson devices, and without the excessive space consumption that plagues discrete packaging techniques. Such high-density flip-chip co-packages certainly constitute a concrete, tangible technological improvement in the field of qubits.

[0158] The disclosure herein describes non-limiting examples of various embodiments of the subject innovation. For ease of explanation and / or description, various portions of the disclosure herein utilize the term "each" when discussing various embodiments of the subject innovation. Such use of the term "each" is a non-limiting example. In other words, when the disclosure herein provides a description that applies to "each" of several particular objects and / or components, this should be understood as a non-limiting example of various embodiments of the subject innovation, and further, it should be understood that in various other embodiments of the subject innovation, such a description may apply to less than "each" of the particular objects and / or components.

[0159] The flowcharts in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments described herein. In this regard, each block in the flowcharts may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in the blocks may occur out of the order depicted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, depending on the functionality involved, or the blocks may in some cases be executed in the reverse order. It should also be noted that each block of the flowchart diagrams, and combinations of blocks in the flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or that executes a combination of dedicated hardware and computer instructions.

[0160] Additionally, the term "or" is intended to mean an inclusive "or," rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, under any of the above examples, "X employs A or B" is satisfied if X employs A; X employs B; or X employs both A and B. Furthermore, the articles "a" and "an," as used in the specification of the present subject matter and the accompanying drawings, should generally be construed to mean "one or more" unless otherwise specified or clear from the context that the singular form is intended. As used herein, the terms "example" and / or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0161] What has been described above includes merely examples of systems and computer-implemented methods. Of course, for purposes of describing the present disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "includes," "has," "possesses," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when employed as a transitional phrase in a claim.

[0162] The description of various embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a superconducting qubit wafer coupled to a parametric Josephson wafer by one or more first bump bonds; a first underfill surrounding the one or more first bump bonds; 1. A device comprising:

2. 10. The device of claim 1, wherein the first underfill is a composite material having an epoxy polymer and a filler, and the filler is at least one material selected from the group consisting of silicon dioxide, titanium dioxide, carbon nanotubes, carbon black, and graphene.

3. 10. The device of claim 1, wherein at least one first parametric Josephson device is disposed on a first side of the parametric Josephson wafer, at least one superconducting qubit is disposed on a first side of the superconducting qubit wafer, the superconducting qubit wafer including at least one first through-substrate via electrically connecting the first side of the superconducting qubit wafer to a second side of the superconducting qubit wafer, and the one or more first bump bonds bond the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer.

4. 4. The device of claim 3, wherein the at least one first parametric Josephson device comprises a Josephson parametric amplifier, a Josephson traveling wave parametric amplifier, a Josephson directional amplifier, a Josephson parametric transformer, a Josephson circulator, or a Josephson isolator.

5. an interposer wafer bump-bonded to the superconducting qubit wafer by one or more second bump bonds; at least one resonator is disposed on the first surface of the interposer wafer; The device of claim 3.

6. 6. The device of claim 5, wherein the one or more second bump bonds couple the first side of the interposer wafer to the first side of the superconducting qubit wafer.

7. 7. The device of claim 6, wherein the first surface of the interposer wafer is bump-bonded to an organic substrate, the organic substrate being selected from the group consisting of a printed circuit board, a flexible printed circuit board, and a laminate.

8. a first interposer wafer bump-bonded to a second interposer wafer by one or more second bump bonds; a second underfill surrounding the one or more second bump bonds; The device of claim 3 further comprising:

9. 9. The device of claim 8, wherein at least one second parametric Josephson device is disposed on the first surface of the first interposer wafer, and at least one resonator is disposed on the first surface of the second interposer wafer.

10. 10. The device of claim 9, wherein at least one second through-substrate via electrically connects the first surface of the second interposer wafer to the second surface of the second interposer wafer, and the one or more second bump bonds join the first surface of the first interposer wafer to the second surface of the second interposer wafer.

11. 11. The device of claim 10, wherein the first side of the superconducting qubit wafer is bump-bonded to the first side of the second interposer wafer with one or more third bump bonds, and the first side of the second interposer wafer is bump-bonded to an organic substrate, the organic substrate being selected from the group consisting of a printed circuit board, a flexible printed circuit board, and a laminate.

12. 4. The device of claim 3, wherein at least one segmented electrode corresponding to the at least one superconducting qubit is disposed on the second side of the superconducting qubit wafer, the at least one segmented electrode including at least one air bridge that is trimmable to adjust an operating frequency of the at least one superconducting qubit, and wherein at least one hollow photoresist column extends from the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer to prevent the first underfill from covering the at least one air bridge.

13. an interposer wafer; another superconducting qubit wafer coupled to another parametric Josephson wafer by one or more second bump bonds; a second underfill surrounding the one or more second bump bonds and surrounding one or more second parametric Josephson devices of the other parametric Josephson wafer; both the superconducting qubit wafer and the another superconducting qubit wafer are bump-bonded to the interposer wafer by one or more third bump bonds, and the interposer wafer is bump-bonded to an organic substrate; The device of claim 1 .

14. bonding the superconducting qubit wafer to the parametric Josephson wafer by one or more first bump bonds; injecting a first underfill between the superconducting qubit wafer and the parametric Josephson wafer such that the first underfill surrounds the one or more first bump bonds; A method for providing the above.

15. 15. The method of claim 14, wherein at least one first parametric Josephson device is disposed on a first side of the parametric Josephson wafer, at least one superconducting qubit is disposed on a first side of the superconducting qubit wafer, the superconducting qubit wafer including at least one first through-substrate via electrically connecting the first side of the superconducting qubit wafer to a second side of the superconducting qubit wafer, and the one or more first bump bonds bond the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer.

16. bonding the first interposer wafer to a second interposer wafer by one or more second bump bonds; injecting a second underfill between the first interposer wafer and the second interposer wafer such that the second underfill surrounds the one or more second bump bonds; The method of claim 15 further comprising:

17. 17. The method of claim 16, wherein at least one second parametric Josephson device is disposed on the first surface of the first interposer wafer and at least one resonator is disposed on the first surface of the second interposer wafer.

18. 18. The method of claim 17, wherein at least one second through-substrate via electrically connects the first side of the second interposer wafer to the second side of the second interposer wafer, the one or more second bump bonds bond the first side of the first interposer wafer to the second side of the second interposer wafer, the first side of the superconducting qubit wafer being bump-bonded to the first side of the second interposer wafer with one or more third bump bonds, and the first side of the second interposer wafer being bump-bonded to an organic substrate, the organic substrate being selected from the group consisting of a printed circuit board, a flexible printed circuit board, and a laminate.

19. 16. The method of claim 15, wherein at least one segmented electrode corresponding to the at least one superconducting qubit is disposed on the second side of the superconducting qubit wafer, the at least one segmented electrode including at least one air bridge that is trimmable to adjust an operating frequency of the at least one superconducting qubit, and wherein at least one hollow photoresist column extends from the first side of the parametric Josephson wafer to the second side of the superconducting qubit wafer to prevent the first underfill from covering the at least one air bridge.

20. bonding another superconducting qubit wafer to another parametric Josephson wafer by one or more second bump bonds; injecting a second underfill between the another superconducting qubit wafer and the another parametric Josephson wafer such that the second underfill surrounds the one or more second bump bonds and surrounds one or more second parametric Josephson devices of the another parametric Josephson wafer; bonding both the superconducting qubit wafer and the another superconducting qubit wafer to an interposer wafer by one or more third bump bonds; the interposer wafer is bump-bonded to an organic substrate; 15. The method of claim 14.

21. a first wafer bump-bonded to a second wafer, the first wafer having one or more parametric Josephson devices and the second wafer having one or more superconducting qubits; an underfill separating the first wafer from the second wafer; the one or more parametric Josephson devices are disposed between the underfill and the first wafer. Flip chip package.

Images