Communication apparatus

Abstract

To improve stability of communication control when noise is applied.SOLUTION: The forced bus-off circuit 21 measures and learns the delay time from the time when the transmission signal TX changes from the low level to the high level to the time when the signal level of the bus 3 changes from the low level to the high level. The forced feed-off circuit 21 compares the level represented by the transmission signal TX with the level represented by the reception signal RX output from the receiver circuit 7 at a predetermined timing determined according to the delay learning value that is the learning result of the delay time, and executes the forced turn-off operation at the first timing as usual when the levels are the same, and executes the forced turn-off operation at the second timing before the first timing when the levels are different. When noise is detected by the noise detecting circuit 14, the forced bus-off circuit 21 performs a forced turn-off operation at a third timing after the transmission signal TX changes from the low level to the high level and before the second timing.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a communication device used in a communication system in which one of a plurality of communication devices that transmit and receive data via a transmission path transmits data in synchronization with the communication of the other communication device. [Background technology]

[0002] Conventionally, a communication method such as CXPI, in which a slave transmits in synchronization with a master's communication, has been known as an in-vehicle communication method installed in a vehicle. CXPI is an abbreviation for Clock Extension Peripheral Interface. Patent Documents 1 and 2 disclose communication devices used in such communication. In the following, the technology disclosed in Patent Document 1 may be referred to as the first conventional technology, and the technology disclosed in Patent Document 2 may be referred to as the second conventional technology. In the following, the first conventional technology and the second conventional technology may be collectively referred to as the conventional technology.

[0003] Such a communication device includes a control circuit and a transceiver circuit. The control circuit generates a command signal that commands whether the signal level of the transmission path should be set to the dominant level or the inferior level when a dominant signal level on the transmission path is set to the dominant level and an inferior signal level on the transmission path is set to the inferior level. The transceiver circuit includes a switching element that can set the signal level of the transmission path to the dominant level, which is the dominant signal level on the transmission path, by turning it on, and a drive circuit that drives the switching element. The drive circuit includes an output buffer that receives a voltage for turning the switching element on or off and outputs an output voltage corresponding to the input voltage to a control terminal of the switching element, and a feedback circuit that feeds back the signal of the transmission path to the input of the output buffer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-114793 [Patent Document 2] Japanese Patent Application Publication No. 2018-201064 Summary of the Invention [Problem to be solved by the invention]

[0005] In a communication device with the above configuration, malfunction of the transceiver circuit due to immunity noise can be a problem, and various countermeasures have been considered. In the first prior art, a high-pass filter is used to separate high-frequency noise, so single-shot noise application does not cause problems. Note that in this specification, high-pass filter is sometimes abbreviated as HPF. However, in the first prior art, when high-frequency noise is continuously applied, such as in DPI and BCI tests, the noise waveform is almost completely passed through. As a result, the control node voltage is controlled using that noise waveform, making stable control of the bus waveform difficult. Note that DPI is an abbreviation for Direct Power Injection, and BCI is an abbreviation for Bulk Current Injection.

[0006] In the second prior art, the bus is normally controlled when the device outputs a dominant signal, but forced off control is performed when the device outputs a recessive signal. The timing at which the device outputs a dominant signal includes a slew rate generation period. The second prior art is equipped with a forced bus off circuit that can perform forced off operation to forcibly drive the switching element off regardless of the command signal, thereby realizing the forced off control described above.

[0007] However, while the second prior art employs forced-off control as a noise countermeasure, it does not consider the noise reduction circuit, which is typically used as a noise countermeasure, and is comprised of, for example, a low-pass filter, placed before the receiver circuit or monitor circuit, or the potential impact on other nodes that may result from the presence of the noise reduction circuit. Note that, in this specification, low-pass filter is sometimes abbreviated as LPF. Therefore, compared to the second prior art, a configuration that simply adds a noise reduction circuit before the comparator in the receiver circuit may prevent malfunctions in the device itself due to erroneous bus on, but this may result in a problem of normal communication not being established due to various circuit delays.

[0008] Furthermore, in receiver circuits and monitor circuits that do not have a noise reduction circuit in the upstream stage, chattering may occur regardless of whether noise is present or not. In such cases, it is possible that the measurement value may be erroneously learned. However, the second prior art does not take this into consideration. If the generation time of the next bus-off signal is advanced as a result of such erroneous learning, the bus waveform may become steeper, potentially causing emission noise problems. Furthermore, if the generation time of the next bus-off signal is delayed, a gap may be created in the timing at which the output circuit is erroneously turned on, increasing the possibility of communication problems. Furthermore, in the configuration of the second embodiment of the second prior art, the timer circuit does not operate unless the monitor circuit detects an intermediate voltage, which results in the problem of being unable to forcibly turn off the output circuit if it is erroneously turned on due to noise.

[0009] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a communication device that can improve the stability of communication control when noise is applied. [Means for solving the problem]

[0010] The communication device described in claim 1 is used in a communication system (1) in which one of a plurality of communication devices (2, 2a, 2b, 2c) transmits and receives data via a transmission path (3) in synchronization with the communication of the other communication devices, and includes a switching element (17, 17B), a control circuit (5), a drive circuit (18, 18A), a receiver circuit (7, 7A), and a noise detection circuit (14). In this case, a dominant signal level on the transmission path is set to a dominant level, and a subordinate signal level is set to a subordinate level. The switching element can set the signal level on the transmission path to the dominant level by turning on.

[0011] The control circuit controls the transmission and reception of the data and generates a command signal, which is a binary signal that commands whether the signal level of the transmission path should be the dominant level or the inferior level. The drive circuit turns on the switching element when the command signal is at a first level that commands the signal level of the transmission path to be the dominant level, and turns off the switching element when the command signal is at a second level that commands the signal level of the transmission path to be the inferior level. The receiver circuit receives data transmitted via the transmission path and outputs it to the control circuit as a received signal, which is a binary signal. The noise detection circuit detects noise superimposed on the transmission path.

[0012] The drive circuit includes an output buffer (19), a feedback circuit (20), and forced bus-off circuits (21, 21A, 21B). The output buffer receives a voltage for turning on or off the switching element, and outputs an output voltage corresponding to the input voltage to the control terminal of the switching element. The feedback circuit feeds back the signal on the transmission path to the input of the output buffer. The forced bus-off circuit can execute a forced-off operation to forcibly turn off the switching element regardless of the command signal.

[0013] The forced bus-off circuit measures and learns the delay time from when the command signal changes from the first level to the second level to when the signal level of the transmission path changes from the dominant level to the inferior level. The forced bus-off circuit compares the level represented by the command signal with the level represented by the received signal output from the receiver circuit at a predetermined timing determined according to a delay learning value that is the learning result of the delay time, and if the levels are the same, executes the forced bus-off operation at a first timing that is the normal timing, and if the levels are different, executes the forced bus-off operation at a second timing that is earlier than the first timing. If noise is detected by the noise detection circuit, the forced bus-off circuit executes the forced bus-off operation at a third timing that is after the command signal changes from the first level to the second level but earlier than the second timing.

[0014] According to the above configuration, when noise is superimposed on the transmission path, i.e., when noise is applied, the forced bus off circuit performs the forced off operation at a more appropriate timing than in the prior art. That is, with the above configuration, if no noise is detected and the level indicated by the received signal is as expected at a predetermined timing determined according to the delay learning value, the forced off operation is performed at a first timing, which is the normal timing. Also, with the above configuration, if no noise is detected and the level indicated by the received signal is different from the expected value at a predetermined timing determined according to the delay learning value, the forced off operation is performed at a second timing, which is earlier than the first timing.

[0015] Furthermore, if noise is detected, a forced-off operation is performed at a third timing, which is after the command signal changes from the first level to the second level and before the second timing, which is a predetermined timing determined according to the delay learning value, thereby increasing the margin to prevent further malfunctions. This configuration enables more stable communication control compared to conventional technology, even when noise of higher frequency or higher amplitude is applied. Therefore, the above configuration can improve the stability of communication control when noise is applied. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a communication system according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating a configuration of a communication device according to a first embodiment. [Figure 3] FIG. 1 is a diagram schematically illustrating a configuration of a transceiver circuit according to a first embodiment. [Figure 4] FIG. 1 is a diagram showing a specific configuration example of a driver circuit according to a first embodiment; [Figure 5] FIG. 1 is a timing chart illustrating the function of a forced bus-off circuit according to a first embodiment; [Figure 6] FIG. 1 is a diagram showing an example of a logic configuration of a forced-off control circuit according to a first embodiment; [Figure 7] FIG. 10 is a diagram showing an example of the operating waveforms of each part when the transmission signal TX according to the first embodiment changes from a low level to a high level and "1" is sampled normally. [Figure 8] 1 is a diagram showing an example of the operation waveforms of each part when the transmission signal TX according to the first embodiment changes from a low level to a high level and the bus waveform is distorted and the low width increases, or when "0" is erroneously sampled at the sampling timing. [Figure 9] FIG. 1 is a diagram showing an example of the operating waveforms of each part when a forced-off operation is executed during normal operation according to the first embodiment. [Figure 10]Timing chart No. 1 for explaining a specific example in which communication with other nodes is affected according to the first embodiment [Figure 11] Timing chart No. 2 for explaining a specific example in which communication with other nodes is affected according to the first embodiment [Figure 12] FIG. 10 is a diagram showing an example of operational waveforms of each unit when a forced-off operation is executed upon noise detection according to the first embodiment; [Figure 13] FIG. 2 is a diagram showing an example of the operating waveforms of each part when a forced-off operation is executed during normal operation according to the first embodiment. [Figure 14] FIG. 10 is a diagram schematically illustrating a configuration of a transceiver circuit according to a modified example. [Figure 15] FIG. 10 is a diagram showing a specific configuration example of a driver circuit according to a modified example. [Figure 16] FIG. 10 is a diagram illustrating an example of a flow of a series of processes executed by a forced-off control circuit according to a second embodiment. [Figure 17] FIG. 11 is a diagram showing an example of operational waveforms of each unit when a forced-off operation is performed when transitioning from a state in which noise is detected to a state in which noise is not detected according to the second embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, a number of embodiments of the present invention will be described with reference to the drawings. Note that substantially the same components in the respective embodiments are designated by the same reference numerals, and the description thereof will be omitted. (First embodiment) The first embodiment will be described below with reference to FIGS.

[0018] <Communication system configuration> The communication system 1 shown in Fig. 1 is used for control communication between multiple electronic control devices mounted on a vehicle, for example. The communication system 1 is configured such that multiple communication devices 2a, 2b, and 2c are connected via a bus 3 that corresponds to a transmission path. Hereinafter, the communication devices 2a, 2b, and 2c will be collectively referred to as the communication device 2 when there is no need to distinguish between them. In this case, the communication system 1 includes three communication devices 2, but may also include two communication devices 2, or four or more communication devices 2.

[0019] The multiple communication devices 2 are configured as semiconductor integrated circuits, or ICs, and transmit and receive data via a bus 3. In the communication system 1, one of the multiple communication devices 2, specifically communication device 2a, transmits data in synchronization with the communication of the other communication devices 2b and 2c. Hereinafter, communication device 2a will also be referred to as master 2m, and communication devices 2b and 2c will also be referred to as slaves 2s.

[0020] In the communication system 1, data is transmitted and received using CXPI communication. CXPI is an abbreviation for Clock Extension Peripheral Interface. In CXPI communication, the master 2m supplies a clock to the slave 2s via the bus 3, and the slave 2s performs communication synchronized with the clock supplied via the bus 3. In this case, the bus 3 is configured so that when a high-level signal and a low-level signal are simultaneously output from different communication devices 2, the signal level on the bus 3 becomes low, and bus arbitration is achieved using this function. That is, in this case, a low-level signal corresponds to a dominant level, which is a dominant signal level on the bus 3, and a high-level signal corresponds to a subordinate level, which is a subordinate signal level on the bus 3.

[0021] On the bus 3, a pulse width modulation signal, or PWM signal, is used as the transmission line code. The signal level changes from high to low at bit boundaries and from low to high midway between bits. Binary signals are expressed using two types of PWM signals with different duty cycles. PWM stands for Pulse Width Modulation. Hereinafter, the code with a relatively short low-level period will be referred to as the recessive code, and the code with a relatively long low-level period will be referred to as the dominant code. The recessive code corresponds to a logical value of 1, and the dominant code corresponds to a logical value of 0.

[0022] In this case, the recessive code is set to be low for the first 1 / 3 of the period of one bit and high for the next 2 / 3 of the period. In this case, the dominant code is set to be low for the first 2 / 3 of the period of one bit and high for the next 1 / 3 of the period. As a result, if a recessive code and a dominant code collide on bus 3, the dominant code will win the arbitration.

[0023] <Configuration of communication device> The master 2m and slave 2s have roughly the same configuration, although they differ in some respects, such as the presence or absence of a configuration for supplying a clock. That is, as shown in FIG. 2, the communication device 2 includes a transceiver circuit 4 and a control circuit 5. The transceiver circuit 4 includes a driver circuit 6 and a receiver circuit 7. The driver circuit 6 is supplied with a transmission signal TX output from the control circuit 5. The driver circuit 6 transmits data corresponding to the transmission signal TX via the bus 3. The receiver circuit 7 receives the data transmitted via the bus 3 and outputs it to the control circuit 5 as a reception signal RX, which is a binary signal.

[0024] The control circuit 5 controls the transmission and reception of data and is configured, for example, as a logic circuit. The control circuit 5 generates a transmission signal TX and outputs the transmission signal TX to the driver circuit 6. The transmission signal TX corresponds to a command signal that commands whether the signal level of the bus 3 should be low or high. In this case, the transmission signal TX is a binary signal, and when it is low, it commands the signal level of the bus 3 to be low, and when it is high, it commands the signal level of the bus 3 to be high. Furthermore, with respect to the transmission signal TX, a low level corresponds to a first level, and a high level corresponds to a second level. The control circuit 5 inputs a reception signal RX output from the receiver circuit 7 and performs predetermined processing based on the input reception signal RX.

[0025] <Transceiver circuit configuration> As shown in FIG. 3, the transceiver circuit 4 includes a driver circuit 6 and a receiver circuit 7, as well as a control logic 11, a noise elimination circuit 12, a noise detection circuit 13, and a noise sensing circuit 14. The control logic 11 is a logic circuit that functions as the control circuit 5 described above. The receiver circuit 7 includes a first receiver circuit 15 and a second receiver circuit 16. The noise elimination circuit 12 is inserted before the first receiver circuit 15 as a noise countermeasure. In other words, the first receiver circuit 15 is provided with the noise elimination circuit 12 before it to eliminate noise. The second receiver circuit 16 does not have the noise elimination circuit 12 before it. As shown in FIG. 6, both the first receiver circuit 15 and the second receiver circuit 16 can be configured using a comparator CMP.

[0026] In this case, the signal on the bus 3 is provided to one input terminal of the comparator CMP of the first receiver circuit 15 via the noise elimination circuit 12, and is also provided to one input terminal of the comparator CMP of the second receiver circuit 16. The noise elimination circuit 12 is configured, for example, with an LPF. The output signal of the noise elimination circuit 12 is a signal from which noise has been removed and which is delayed according to the time constant of the LPF, relative to the signal on the bus 3.

[0027] A threshold signal Sa is applied to the other input terminal of each comparator CMP of the first receiver circuit 15 and the second receiver circuit 16. The threshold signal Sa is a signal corresponding to a threshold for detecting an edge at which the signal level of the bus 3 inverts. In this case, the level of the threshold signal Sa changes according to the output signal of the comparator CMP. In other words, the comparator CMP functions as a hysteresis comparator.

[0028] With this configuration, the first receiver circuit 15 and the second receiver circuit 16 output a high-level signal when the signal level of the bus 3 is higher than the threshold value VIH, and output a low-level signal when the signal level of the bus 3 is lower than the threshold value VIL. The output signal of the first receiver circuit 15 is provided to the control logic 11 and the noise detection circuit 14 as the above-mentioned received signal RX. The output signal of the second receiver circuit 16 is provided to the noise detection circuit 14 as the above-mentioned received signal RX.

[0029] In this case, the reception signal RX output from the first receiver circuit 15 corresponds to the first reception signal, and is used for normal data reception operations by the control circuit 5 of the control logic 11, as well as for use in the noise detection circuit 14 and, further, in the forced bus-off circuit 21 described below. In addition, in this case, the reception signal RX output from the second receiver circuit 16 corresponds to the second reception signal, and is not used for normal data reception operations by the control circuit 5 of the control logic 11, but is used in the noise detection circuit 14 and, further, in the forced bus-off circuit 21.

[0030] The driver circuit 6 includes diodes D1 and D2, a resistor R1, a switching element 17, and a drive circuit 18. In the driver circuit 6, the cathode of the diode D1 is connected to the bus 3. The anode of the diode D1 is connected to a power supply line L1, to which a power supply voltage Va is supplied, via a pull-up resistor R1. The power supply voltage Va is a power supply voltage of the +B system generated from a power supply +B of a battery mounted on the vehicle.

[0031] The driver circuit 6 has an open-drain output circuit configuration to enable the bus arbitration described above. The switching element 17, which constitutes the output stage of the driver circuit 6, is an element that can set the signal level of the bus 3 to a low level when turned on, and is, for example, an N-channel MOS transistor. The drain of the switching element 17 is connected to the bus 3 via a diode D2 in the reverse direction, and its source is connected to ground, which is the reference potential of the circuit, 0 V. The driver circuit 6 receives a transmit signal TX provided by the control circuit 5 and an inverted transmit signal TX-bar. Note that in Figure 3 and other figures, the transmit signal TX-bar is indicated by adding a "-" above TX.

[0032] The drive circuit 18 drives the switching element 17 to be on while a low-level transmission signal TX is being provided, that is, when the transmission signal TX is at a first level that commands the signal level of the bus 3 to be set to a low level. The drive circuit 18 drives the switching element 17 to be off while a high-level transmission signal TX is being provided, that is, when the transmission signal TX is at a second level that commands the signal level of the bus 3 to be set to a high level.

[0033] The drive circuit 18 includes an output buffer 19, a feedback circuit 20, and a forced bus-off circuit 21. The output buffer 19 receives a voltage for turning on or off the switching element 17, and outputs an output voltage Vo corresponding to the input voltage Vi to the gate, which is the control terminal, of the switching element 17. The feedback circuit 20 is connected between the bus 3 and the input of the output buffer 19, and feeds back the signal of the bus 3 to the input of the output buffer 19. The feedback circuit 20 can be configured, for example, by a series circuit of a resistor and a capacitor.

[0034] The forced bus-off circuit 21 can execute a forced-off operation to forcibly drive off the switching element 17 regardless of the transmission signal TX. In this case, the forced bus-off circuit 21 can execute the forced-off operation regardless of the level of the transmission signal TX, but it is sufficient if the forced bus-off circuit 21 is configured to execute the forced-off operation at least while the transmission signal TX is at a high level.

[0035] The forced bus-off circuit 21 includes a first forced-off switch 22 connected between the input of the output buffer 19 and ground, which is a node supplied with 0 V, a voltage for driving the switching element 17 to turn off. The forced bus-off circuit 21 can additionally include a second forced-off switch 23 connected between the output of the output buffer 19 and ground, depending on the output capacity of the output buffer 19. In the forced bus-off circuit 21 configured as described above, a forced-off operation is executed by turning on the first forced-off switch 22, or by turning on both the first forced-off switch 22 and the second forced-off switch 23.

[0036] In this case, the control logic 11 functions as a forced-off control circuit 24 that, together with the first forced-off switch 22 and the second forced-off switch 23, constitutes the forced bus-off circuit 21. The on / off states of the first forced-off switch 22 and the second forced-off switch 23 are controlled by a binary forced-off signal Sb output from the forced-off control circuit 24. Specifically, the first forced-off switch 22 and the second forced-off switch 23 are turned off when the forced-off signal Sb is at a low level, and are turned on when the forced-off signal Sb is at a high level. In other words, the forced bus-off circuit 21 stops the forced-off operation when the forced-off signal Sb is at a low level, and performs the forced-off operation when the forced-off signal Sb is at a high level.

[0037] The noise detection circuit 14 is a circuit that detects noise superimposed on the bus 3, and includes a main detection circuit 25 and sub-detection circuits 26, 27, and 28. The signal Sc inside the output buffer 19 is input to the main detection circuit 25. The main detection circuit 25 detects noise superimposed on the bus 3 based on the noise superimposed on the signal Sc inside the output buffer 19. The main detection circuit 25 can be configured to count the signal Sc inside the output buffer 19 using an analog circuit.

[0038] The signal Sd output from the noise detection circuit 13 is input to the sub-detection circuit 26. The sub-detection circuit 26 detects noise superimposed on the bus 3 based on the output of the noise detection circuit 13. The noise detection circuit 13 is connected between the bus 3 and the input of the noise detection circuit 14, and is configured by a high-pass filter of any type, such as passive, active, digital, or analog. The sub-detection circuit 26 can be configured to count the signal Sd output from the noise detection circuit 13 using an analog circuit.

[0039] The output signal of the first receiver circuit 15 is input to the sub-detector circuit 27. The sub-detector circuit 27 detects noise superimposed on the bus 3 based on chattering in the first receiver circuit 15. The sub-detector circuit 27 can be configured to count the output signal of the first receiver circuit 15 using an analog circuit. The output signal of the second receiver circuit 16 is input to the sub-detector circuit 28. The sub-detector circuit 28 detects noise superimposed on the bus 3 based on chattering in the second receiver circuit 16. The sub-detector circuit 28 can be configured to count the output signal of the second receiver circuit 16 using an analog circuit.

[0040] The control logic 11 functions as sub-detection circuits 29 and 30, which are part of the noise detection circuit 14. The output signal of the first receiver circuit 15 is input to the sub-detection circuit 29. The sub-detection circuit 29 detects noise superimposed on the bus 3 based on chattering in the first receiver circuit 15. The sub-detection circuit 29 can be configured to count the output signal of the first receiver circuit 15 using a digital circuit. The output signal of the second receiver circuit 16 is input to the sub-detection circuit 30. The sub-detection circuit 30 detects noise superimposed on the bus 3 based on chattering in the second receiver circuit 16. The sub-detection circuit 30 can be configured to count the output signal of the second receiver circuit 16 using a digital circuit.

[0041] The noise detection circuit 14 may include, for example, an active filter, a digital filter using a DSP, etc. The digital filter may include an FIR filter, an IIR filter, an A / D converter, etc. Note that DSP is an abbreviation for Digital Signal Processor, FIR is an abbreviation for Finite Impulse Response, and IIR is an abbreviation for Infinite Impulse Response.

[0042] In the above configuration, each of the sub-detection circuits 26, 27, 28, 29, and 30 is configured so that an operation for detecting noise is enabled when noise is not detected by the main detection circuit 25. Note that each of the sub-detection circuits 26 to 30 may be configured so that an operation for detecting noise is always enabled. The noise detection circuit 14 outputs a noise detection signal Se representing the noise detection result to the control circuit 5 of the control logic 11. The noise detection signal Se is a binary signal that goes high when noise is detected.

[0043] <Specific configuration of the driver circuit> As a specific configuration of the driver circuit 6, for example, a configuration example as shown in Fig. 4 can be adopted. According to the configuration example shown in Fig. 4, the driver circuit 6 includes switches S1 and S2, current sources 41 and 42, etc. in addition to the configuration shown in Fig. 3. The switches S1 and S2 and the current sources 41 and 42 are included in the drive circuit 18.

[0044] One terminal of the switch S1 is connected to a power supply line L2 to which a power supply voltage Vb is supplied, and the other terminal is connected to a node N1 via a current source 41. The power supply voltage Vb is a power supply voltage of a system separate from the power supply voltage of the +B system, such as a 5V power supply system. The power supply voltage Vb may also be a power supply voltage of the +B system. One terminal of the switch S2 is connected to the node N1, and the other terminal is connected to ground via a current source 42. Both current sources 41 and 42 are constant current sources that output a constant current Icm.

[0045] The on / off state of the switch S1 is controlled by the transmission signal TX bar. Specifically, the switch S1 is turned on when the transmission signal TX bar is at a high level, and turned off when the transmission signal TX bar is at a low level. The on / off state of the switch S2 is controlled by the transmission signal TX. Specifically, the switch S2 is turned on when the transmission signal TX is at a high level, and turned off when the transmission signal TX is at a low level. In this way, the switches S1 and S2 are turned on and off in a complementary manner.

[0046] According to the above configuration, the voltage at node N1 becomes input voltage Vi, which is a voltage for turning on or off switching element 17. Node N1 is connected to the input of output buffer 19. A capacitor C1 and a resistor R2 are connected in series between the input of output buffer 19 and bus 3. The series circuit of capacitor C1 and resistor R2 forms feedback circuit 20. The output of output buffer 19 is connected to the gate, which is the control terminal, of switching element 17. As a result, output voltage Vo of output buffer 19 is applied to the gate of switching element 17.

[0047] A capacitor C2 and a resistor R3 are connected in series between ground and a node N2, which is the interconnection node of the resistor R2 and the capacitor C1 that make up the feedback circuit 20. The capacitor C2 and the resistor R3 form a noise detection circuit 13. The node N3, which is the interconnection node of the capacitor C2 and the resistor R3, serves as the output terminal of the noise detection circuit 13 and is connected to a noise sensing circuit 14.

[0048] The first forced-off switch 22 and the second forced-off switch 23 of the forced bus-off circuit 21 are both configured by, for example, N-channel MOS transistors. The drain of the first forced-off switch 22 is connected to the input of the output buffer 19, and its source is connected to ground. The drain of the second forced-off switch 23 is connected to the output of the output buffer 19, and its source is connected to ground. A forced-off signal Sb is supplied to each gate of the first forced-off switch 22 and the second forced-off switch 23.

[0049] The forced bus-off circuit 21 has the following function: The forced-off control circuit 24 measures and learns the delay time from when the transmission signal TX changes from low to high to when the signal level of the bus 3 changes from low to high. In this learning, the measurement of the time when the signal level of the bus 3 changes from low to high can be performed based on the output signal of the first receiver circuit 15 or the output signal of the second receiver circuit 16.

[0050] 5, the forced-off control circuit 24 compares the level of the transmission signal TX with the level of the reception signal RX output from the receiver circuit 7 at a predetermined time ta that is determined according to a delay learning value that is the result of learning the delay time. In this comparison, the reception signal RX output from the receiver circuit 7 may be the output signal of the first receiver circuit 15 or the output signal of the second receiver circuit 16. Note that FIG. 5 shows an example of the case where the above comparison is performed using the output signal of the second receiver circuit 16.

[0051] 5A, when the level of the output signal of the second receiver circuit 16 is high at time ta, that is, when the compared levels are the same, the forced-off control circuit 24 outputs a forced-off signal Sb so that the forced-off operation is performed at the first timing, which is the normal timing. The normal timing is any timing that does not affect the operation for generating the slew rate and satisfies the communication protocol.

[0052] 5B, when the level of the output signal of the second receiver circuit 16 is low at time ta, that is, when the compared levels are different, the forced-off control circuit 24 outputs the forced-off signal Sb so that the forced-off operation is performed at a second timing that is a timing before the first timing. The second timing can be a predetermined timing determined according to the delay learning value, for example. In this case, when the compared levels are different at time ta, the forced-off control circuit 24 outputs the forced-off signal Sb so that the forced-off operation is performed without considering the operation for generating a slew rate at that time ta.

[0053] 5(C), when noise is detected by the noise detection circuit 14, the forced-off control circuit 24 outputs a forced-off signal Sb so that a forced-off operation is performed at a third timing that is after the point in time when the transmission signal TX changes from low level to high level and before the second timing. The third timing can be, for example, a timing synchronized with the transmission signal TX, that is, the timing when the transmission signal TX changes from low level to high level.

[0054] When the forced-off control circuit 24 measures and learns the delay time, it learns only those delay time values ​​that fall within a predetermined appropriate learnable range, but does not learn values ​​that fall outside the learnable range.

[0055] To achieve this function, the forced-off control circuit 24 in the control logic 11 can employ a logic configuration such as that shown in Fig. 6. Note that Fig. 6 illustrates an example in which the delay time is learned using the output signal of the second receiver circuit 16, but a similar configuration can also be employed in the case in which the delay time is learned using the output signal of the first receiver circuit 15.

[0056] An example of the logic configuration of the forced-off control circuit 24 shown in Fig. 6 will be described below with reference to the timing charts of Fig. 7 and 8, which show the operating waveforms when the transmission signal TX changes from low to high. Note that Fig. 7 shows the case when there is no noise, that is, when "1" is sampled normally, while Fig. 8 shows the case when there is noise, that is, when the waveform of the bus 3 is distorted and the low width increases, or when "0" is erroneously sampled at the sampling timing.

[0057] The timer circuit 51 receives the transmission signal TX, the noise detection signal Se, and the signal Sf, which is the output signal of the comparator CMP of the second receiver circuit 16. The timer circuit 51 measures and learns the delay time based on the transmission signal TX and the signal Sf. The timer circuit 51 includes a counter that counts the period from time t1, which is the rising edge of the transmission signal TX, to time t2, which is the rising edge of the signal Sf. In the timer circuit 51, the count value obtained by counting the period by the counter becomes the period during which the transmission signal TX is at a high level, i.e., the learned value corresponding to the delay time Ta.

[0058] The timer circuit 51 repeatedly executes this counting operation and learns the delay time by averaging the multiple learned values ​​obtained thereby. In this case, not all learned values ​​are used for learning the delay time, but certain restrictions are imposed. First, the timer circuit 51 learns only those learned values ​​that fall within the aforementioned learnable range, and does not learn values ​​that fall outside the learnable range. Furthermore, the timer circuit 51 does not learn the delay time while the noise detection signal Se is at a high level, i.e., while noise is being detected. In other words, the timer circuit 51 does not use learned values ​​obtained during noise detection as learning targets.

[0059] The timer circuit 51 outputs the delayed learning value, which is the result of the learning described above, to the adder 52. The timer circuit 51 also outputs the count value of the counter at that time, i.e., the current count value, to the comparator 53. The adder 52 adds a variable constant α to the delayed learning value and outputs the addition result, "delayed learning value + α," to the comparator 53. α is a constant for determining the predetermined timing for the above-mentioned comparison, and is a variable constant so that it can be set to an optimal value. Note that α can also be set to zero.

[0060] The comparator 53 compares the "current count value" with the "delayed learning value + α" and outputs to the comparator 54 a signal Sg that rises when the two values ​​match, that is, at the predetermined timing, i.e., time t4 in FIG. 7, to which the comparator 54 is connected. The comparator 54 also receives the signal Sf. The comparator 54 samples the signal Sf at the sampling timing when the signal g rises, that is, time t3 in FIGS. 7 and 8. The comparator 54 compares the sampled value, that is, the level represented by the received signal output from the second receiver circuit 16, with an expected value, that is, the level represented by the transmitted signal TX.

[0061] If the level represented by the received signal differs from the expected value, the comparator 54 generates and outputs a signal Sh that changes from low to high at that point in time, that is, at time t5 in Figure 8. If the level represented by the received signal is the same as the expected value, the comparator 54 generates and outputs a constant low-level signal Sh. The normal signal generator 55 generates and outputs a signal Si that changes from low to high at the first timing described above.

[0062] The logic circuit 56 receives the signals Sh and Si, the noise detection signal Se, and the transmission signal TX. While the noise detection signal Se is at a low level, i.e., when there is no noise, the logic circuit 56 outputs a signal representing the logical sum of the signals Sh and Si as the forced-off signal Sb. Therefore, when the level of the received signal differs from the expected value, the forced-off signal Sb output from the logic circuit 56 becomes a signal representing the same logic as the signal Sh, i.e., the signal Sb indicated by the dashed-dotted line in FIG. 8 . Also, when the level of the received signal is the same as the expected value, the forced-off signal Sb becomes a signal representing the same logic as the signal Si, i.e., the signal Sb indicated by the dashed-dotted line in FIG. 7 . While the noise detection signal Se is at a high level, i.e., when there is noise, the forced-off signal Sb output from the logic circuit 56 becomes a signal representing the same logic as the transmission signal TX, i.e., the signal Sb indicated by the dashed-double-dot line in FIG. 8 .

[0063] Next, the forced bus off operation executed by the forced bus off circuit 21 having the above configuration will be described with reference to FIGS. [1] During normal operation During normal operation, that is, when a forced-off operation is performed when noise is not detected by the noise detection circuit 14, the operating waveforms of each part are, for example, as shown in Figure 9. In Figure 9, delay time d1 from time t12 when the output signal of the second receiver circuit 16 changes from high to low to time t13 when the output signal of the first receiver circuit 15 changes from high to low, and delay time d2 from time t16 when the output signal of the second receiver circuit 16 changes from low to high to time t18 when the output signal of the first receiver circuit 15 changes from low to high correspond to circuit delays in the noise removal circuit 12, etc. In Figure 9, each delay time is indicated by a solid black arrow.

[0064] 9, the delay time d3 from time t13 when the output signal of the first receiver circuit 15 changes from high level to low level to time t14 corresponds to the logic delay in the control logic 11, etc. Also, in Fig. 9, the delay time d4 from time t11 when the transmission signal TX changes from high level to low level to time t12 when the output signal of the second receiver circuit 16 changes from high level to low level corresponds to the circuit delay in the output buffer 19 and comparator CMP.

[0065] The forced bus-off circuit 21 constantly learns the delay time Ta from time t15 when the transmit signal TX changes from low to high, i.e., from the rising edge of the transmit signal TX, to time t16 when the output signal of the second receiver circuit 16 changes from low to high, i.e., the time up to the middle of the slew rate. At a predetermined timing, i.e., time t17 when the delay learned value (the result of the learning) or the delay learned value + α has elapsed from the rising edge of the transmit signal TX, the forced bus-off circuit 21 compares the expected transmission value, which is the level represented by the transmit signal TX, with the output value, which is the level represented by the output signal of the second receiver circuit 16.

[0066] 9, when the expected transmission value and the output value match, the forced bus-off circuit 21 outputs a forced-off signal Sb so that a forced-off operation is performed at a first timing, which is a normal timing that does not affect the generation of the slew rate. Note that "outputting the forced-off signal Sb" means that the forced-off signal Sb is changed from low level to high level. The first timing can be set, for example, to be the timing when a predetermined time has elapsed since time t14.

[0067] 9, when the expected transmission value and the output value do not match, the forced bus-off circuit 21 outputs a forced-off signal Sb so that a forced-off operation is performed even while the slew rate is being generated at a second timing, which is the point when the time of the delayed learning value or the delayed learning value + α has elapsed. Note that the expected transmission value and the output value may not match when either a foreign node, which is another communication device 2, outputs a logical value "0" or when the own node, which is this communication device 2, is turned on by mistake.

[0068] If the expected transmission value and the output value do not match and the local node is outputting a logical value of "1," the bus waveform, which is the signal waveform of bus 3, may change sharply when the forced-off signal Sb is output. However, in such a case, it is clear that the local node is performing a false-on operation as a result of the noise being applied, and although there is concern that the forced-off operation to avoid the false-on operation may worsen the emission noise, the malfunction caused by the inability to communicate normally may be a greater problem. Also, if the other node is outputting a logical value of "0," even if the local node is performing a forced-off operation, there will be no problem with the bus waveform because the other node is in control of the bus.

[0069] The second receiver circuit 16, which does not have a noise elimination circuit 12 in its upstream stage, is likely to experience chattering regardless of whether noise is present or not. However, the forced bus-off circuit 21 defines a learnable range for the learning value in the forced-off control circuit 24 within the control logic 11, and values ​​outside the learnable range are not considered for learning and are discarded. This means that even if chattering occurs, errors will not occur in learning the delay time, i.e., erroneous learning will not occur. Furthermore, the forced bus-off circuit 21 does not consider learned values ​​obtained during noise detection as learning targets and discards them, so erroneous learning due to the influence of noise will not occur.

[0070] In this case, the delay time is learned using the output signal of the second receiver circuit 16, but if communication with other nodes is not affected even if the timing of the forced-off operation is delayed due to a delay time in the noise removal circuit 12, the delay time can also be learned using the output signal of the first receiver circuit 15, which is provided in the preceding stage of the noise removal circuit 12. In this way, it becomes possible to omit the second receiver circuit 16, as in a modified example described later, which allows the circuit size and costs to be reduced accordingly.

[0071] Specific examples of the above-mentioned effects on communication with other nodes include the cases shown in Figures 10 and 11. In this case, it is assumed that the own node is the master and the other node is the slave, and there is a difference in filter delay time between the master and the slave. In Figures 10 and 11, SP represents the sampling timing, (M) represents the own node as the master, and (S) represents the other node as the slave.

[0072] 10, the presence of the noise elimination circuit 12 delays the timing of the forced-off operation of the node itself, which means that the forced-off control will not be able to keep up with the sampling timing of other nodes that do not have the noise elimination circuit 12, which could result in a logical value of "1" being changed to "0," i.e., erroneous sampling, which could result in a communication error. In contrast, according to this embodiment, as shown in FIG. 11, the forced-off timing control is performed with the filter delay advanced, so the above-mentioned problem of erroneous sampling does not occur.

[0073] [2] When noise is detected When noise is detected, that is, when a forced-off operation is executed when noise is detected by the noise detection circuit 14, the operating waveforms of each part are, for example, as shown in Fig. 12. For comparison, Fig. 13 shows an example of the operating waveforms of each part when a forced-off operation is executed during normal operation. As shown in Fig. 13, during normal operation, a forced-off signal Sb is output and the forced-off operation is executed at time t21, which is the first timing as usual, or at time t22, which is the second timing before the first timing.

[0074] 12, when noise is detected, after time t23, which is the rising edge of the transmission signal TX, a forced-off signal Sb is output at time t23, which is an example of an appropriate timing that is earlier than time t22, which is the second timing, and a forced-off operation is executed. This makes it possible to further secure a margin for false on due to noise. Note that the appropriate third timing may be determined within a range that satisfies the communication protocol, specifically, the low width time specifications for the logical values ​​"0" and "1." For example, a timing synchronized with the rising edge of the transmission signal TX may be adopted.

[0075] According to the present embodiment described above, the following effects can be obtained. According to the communication device 2, when noise is superimposed on the transmission path, i.e., when noise is applied, the forced bus off circuit 21 performs the forced off operation at a more appropriate timing than in the prior art. That is, in the configuration of this embodiment, if no noise is detected and the level indicated by the received signal RX is as expected at a predetermined timing determined according to the delay learning value, the forced off operation is performed at a first timing, which is the normal timing. Also, in the configuration of this embodiment, if no noise is detected and the level indicated by the received signal RX is different from the expected value at a predetermined timing determined according to the delay learning value, the forced off operation is performed at a second timing, which is earlier than the first timing.

[0076] Furthermore, in the configuration of this embodiment, if noise is detected, a forced-off operation is performed at a third timing, which is after the transmission signal TX changes from low to high and before the second timing, thereby increasing the margin to prevent further malfunctions. This configuration enables more stable communication control than conventional techniques, even when noise of higher frequency or amplitude is applied. Therefore, this embodiment can improve the stability of communication control when noise is applied.

[0077] In the configuration of this embodiment, the noise detection circuit 14 uses the HPF, chattering of the comparator CMP of the receiver circuit 7, and the like to detect noise, but these are used only for noise detection. In other words, the configuration of this embodiment does not use the noise waveform itself as a control signal, as in the first prior art. Furthermore, in the configuration of this embodiment, when noise is detected, logic control is performed to execute a forced-off operation at a third timing, which is earlier than the timing at which a normal forced-off operation is executed, so that no problems arise even when high-frequency noise is continuously applied.

[0078] Furthermore, in the configuration of this embodiment, unlike the second prior art, the timing for the forced OFF operation is not generated after the dominant control and the subsequent slew rate generation period end, but rather the delay time from the rising edge of the transmission signal TX to the rising edge of the output signal of the comparator CMP of the receiver circuit 7 is measured and learned in advance each time, and the level represented by the transmission signal TX and the level represented by the output signal of the receiver circuit 7 are compared at a time equal to the delay learning value or delay learning value + α, which is the result of this learning.

[0079] In the configuration of this embodiment, if the compared levels are different, a forced-off signal Sb is output so that a forced-off operation is performed at the timing of the comparison, and if the compared levels are the same, a forced-off signal Sb is output so that a forced-off operation is performed at a normal timing with sufficient margin for slew rate generation. With this configuration, if the switching element 17 is erroneously turned on, it is possible to resolve the erroneous turn-on of the switching element 17 at an earlier timing than in the second prior art, and normal communication can be maintained.

[0080] In this embodiment, the forced bus-off operation is described using the example of outputting a logical value of "1," but this operation can also be performed when outputting a logical value of "0." Normally, it is sufficient to consider the case where a false ON operation occurs when outputting a logical value of "1," causing the logical value to change to "0." Therefore, the forced bus-off circuit 21 only needs to be configured to be able to perform the forced bus-off operation at least while the transmission signal TX is at a high level.

[0081] The receiver circuit 7 includes a first receiver circuit 15 with a noise elimination circuit 12 provided upstream thereof, but there is concern that the delay time due to the noise elimination circuit 12 may cause problems in communication. Therefore, in this embodiment, the receiver circuit 7 includes a second receiver circuit 16 without a noise elimination circuit 12 provided upstream thereof, and the delay time is measured and learned using the output signal of the second receiver circuit 16. This configuration makes it possible to generate the forced-off signal Sb without being affected by the delay time due to the noise elimination circuit 12, thereby preventing erroneous sampling of other nodes.

[0082] Because the second receiver circuit 16 does not have a noise reduction circuit 12 upstream, learning using the output signal of the second receiver circuit 16 may result in erroneous learning due to chattering caused by noise, as in the second prior art. However, in this embodiment, when measuring and learning the delay time, the forced bus-off circuit 21 learns only those delay time values ​​within a learnable range, which is an appropriate range, but discards those values ​​outside the learnable range. This configuration prevents the forced-off signal Sb from being generated using an incorrect delay learning value, thereby preventing problems such as a bus waveform that changes suddenly and causes problems with emission noise or a gap timing that causes the switching element 17 to turn on erroneously.

[0083] According to the communication device 2 of this embodiment, by performing the forced-off operation described above, the false-on tolerance of the transceiver circuit 4 can be improved and erroneous sampling of other nodes can be prevented. As a result, high noise resistance can be ensured while maintaining good adaptability to communication protocols. Furthermore, according to the communication device 2 of this embodiment, the forced-off operation described above does not affect the communication waveform during normal operation, so emission noise can be suppressed. As such, this embodiment can solve various problems that occurred in the prior art.

[0084] The forced bus-off circuit 21 includes a first forced-off switch 22 connected to the input side of the output buffer 19, and can additionally include a second forced-off switch 23 connected to the output side of the output buffer 19 depending on the output capacity of the output buffer 19. With this configuration, even if the sink capacity of the output buffer 19 is not sufficient to forcibly drive the switching element 17 to OFF, it is possible to reliably execute the forced-off operation, and the various effects described above can be reliably obtained.

[0085] The noise detection circuit 14 includes a main detection circuit 25 that detects noise superimposed on the bus 3 based on noise superimposed on the signal in the output buffer 19. The amplitude of noise coming from the bus 3 is relatively large, for example, about 40 Vp-p to 80 Vp-p. Therefore, in a configuration in which noise is detected based on the signal on the bus 3, it becomes necessary to increase the withstand voltage of the circuit elements that make up the circuit, which may result in an increase in the circuit size. In contrast, according to the main detection circuit 25 of this embodiment, the signal in the output buffer 19 has a smaller amplitude than the signal on the bus 3, so it is possible to use elements with a relatively low withstand voltage as the circuit elements that make up the circuit, thereby keeping the circuit size small.

[0086] The noise detection circuit 14 includes a main detection circuit 25 as well as a plurality of sub-detection circuits 26-30, which are configured to enable operation for detecting noise when noise is not detected by the main detection circuit 25. This configuration makes it possible to detect noise more reliably, and ultimately enables accurate control of switching the execution timing of the forced-off operation based on whether or not noise is detected.

[0087] <Modifications of the Transceiver Circuit Configuration> The configuration of the transceiver circuit 4 is not limited to the configuration shown in Fig. 3, but may be a modified configuration such as that shown in Fig. 14. In the modified transceiver circuit 4A shown in Fig. 14, the receiver circuit 7A differs from the receiver circuit 7 of the transceiver circuit 4 in that the second receiver circuit 16 is omitted.

[0088] In the transceiver circuit 4A, the driver circuit 6A differs from the driver circuit 6 of the transceiver circuit 4 in that it includes a driver circuit 18A instead of the driver circuit 18. The driver circuit 18A differs from the driver circuit 18 in that it includes a forced bus-off circuit 21A instead of the forced bus-off circuit 21. The forced bus-off circuit 21A differs from the forced bus-off circuit 21 in that the second forced-off switch 23 is omitted.

[0089] <Modifications regarding specific configurations of driver circuits> The specific configuration of the driver circuit 6 is not limited to the example configuration shown in Fig. 4, but may also be a modified configuration as shown in Fig. 15. In the modified driver circuit 6B shown in Fig. 15, the switching element 17B is an NPN bipolar transistor. The driver circuit 6B differs from the driver circuit 6 in that it includes a forced bus-off circuit 21B instead of the forced bus-off circuit 21.

[0090] The forced bus-off circuit 21B differs from the forced bus-off circuit 21 in that it includes a first forced-off switch 22B and a second forced-off switch 23 instead of the first forced-off switch 22 and the second forced-off switch 23, and in that it also includes resistors R11 and R12. The first forced-off switch 22B and the second forced-off switch 23B are both configured using NPN-type bipolar transistors. A forced-off signal Sb is applied to the bases of the first forced-off switch 22B and the second forced-off switch 23B via resistors R11 and R12, respectively.

[0091] (Second embodiment) A second embodiment in which the control content by the forced bus off circuit 21 is modified from that of the first embodiment will be described below with reference to Figures 16 and 17. In this case, the circuit configuration of the forced bus off circuit 21 is the same as that of the first embodiment, so its description will be omitted and the drawings of the first embodiment will be referred to as necessary.

[0092] In this embodiment, the forced-off control circuit 24 of the forced bus-off circuit 21 is configured to transition to a noise-detected state in which a forced-off operation is executed at a third timing due to noise detection by the noise detection circuit 14, and then transition to a noise-undetected state in which a forced-off operation is executed at a first timing or a second timing if noise detection by the noise detection circuit 14 is not performed for a certain period of time. Furthermore, when transitioning from the noise-detected state to the noise-undetected state, the forced-off control circuit 24 of the forced bus-off circuit 21 is configured to delay the timing of executing the forced-off operation by a predetermined rate.

[0093] Next, a specific example of control by the forced bus off circuit 21 configured as described above will be described with reference to the flowchart of Fig. 16 and the timing chart of Fig. 17. The series of processes shown in the flowchart of Fig. 16 are started when noise is not detected by the noise detection circuit 14, that is, when noise is not detected. In step S101, the low width of the logical value "1" is measured based on the received signal output from the receiver circuit 7, and the measured value a is stored.

[0094] In step S102, it is determined whether noise has been detected by the noise detection circuit 14, that is, whether the state is one in which noise is detected or not. If the state is one in which noise is detected, step S102 results in "YES" and the process proceeds to step S103. In step S103, a forced-off signal Sb is output so that a forced-off operation is performed at a third timing, specifically, at a timing synchronized with the rising edge of the transmission signal TX. In FIG. 16, this forced-off operation is referred to as a third forced-off operation.

[0095] After step S103 is executed, the process returns to step S102. Here, this processing flow, that is, the processing flow of "YES in step S102 → step S103", is referred to as the "α-1 path". On the other hand, if the state is one in which noise is not detected, the result is "NO" in step S102, and the process proceeds to step S104. In step S104, it is determined whether the level represented by the received signal output from the receiver circuit 7 is the same as the level represented by the transmitted signal TX, that is, whether the level represented by the received signal is as expected.

[0096] If the level represented by the received signal is different from the expected value, step S104 results in "NO" and the process proceeds to step S105. In step S105, a forced-off signal Sb is output so that a forced-off operation is performed at the second timing, specifically, at that time. In FIG. 16, this forced-off operation is referred to as a second forced-off operation. After step S105 is performed, the process returns to step S102. Here, this processing flow, i.e., the processing flow of "NO in step S102 → NO in step S104 → step S105", is referred to as the "α-2 path."

[0097] On the other hand, if the level represented by the received signal is the same as the expected value, the result in step S104 is "YES" and the process proceeds to step S106. In step S106, the low width of the logical value "1" is measured based on the received signal output from the receiver circuit 7, and the measured value b is stored. After step S106 is executed, the process proceeds to step S107, where it is determined whether the measured value b of the low width of the logical value "1" is within a predetermined range, specifically, whether the following formula (1) is satisfied. b≧a±c% …(1)

[0098] If the measured value b is within the specified range, the result in step S107 is "YES" and the process proceeds to step S108. In step S108, the forced-off control value that determines the timing for outputting the forced-off signal Sb, i.e., the rising timing of the forced-off signal Sb, is set to a new value obtained by adding d% to the current value, and the forced-off signal Sb is output so that the forced-off operation is performed at a timing based on the new value. Note that d is set to a value that satisfies, for example, "less than b + 6% @ 1 Tbit." After step S108 is executed, the process returns to step S106.

[0099] On the other hand, if the measured value b is outside the specified range, the result in step S107 is "NO" and the process proceeds to step S109. In step S109, a forced-off signal Sb is output so that a forced-off operation is performed at a first timing, specifically, at the normal timing. Note that in FIG. 16, this forced-off operation is referred to as a first forced-off operation. After step S109 is performed, the process returns to step S101.

[0100] Here, this processing flow, i.e., "YES in step S104 → step S106 → step S107 → step S108 or S109," will be referred to as the "β path." In this case, the "β path" is a path that occurs during normal operation or after the "α-1 path" or "α-2 path."

[0101] By executing this series of processes, the state when noise is detected transitions to the state when noise is not detected as follows. That is, as illustrated in Fig. 17, in the state when noise is detected, the forced-off signal Sb is output so that the forced-off operation is performed in synchronization with the rising timing of the transmission signal TX. Thereafter, when transitioning from the state when noise is detected to the state when noise is not detected, the forced-off signal Sb is output so that the timing at which the forced-off signal Sb is output, i.e., the rising timing of the forced-off signal Sb, is delayed by +d%. Note that in Fig. 17, the state when noise is detected is referred to as "noise detected," and the state when noise is not detected is referred to as "no noise detected."

[0102] According to the present embodiment described above, the following effects can be obtained. That is, if the row width control when noise is detected is applied as it is when noise is not detected, the row width will increase suddenly all at once, which may result in erroneous sampling in other nodes, where a logical value "1" is mistakenly sampled as a logical value "0." Therefore, in this embodiment, when transitioning from a state when noise is detected to a state when noise is not detected, the timing of executing the forced-off operation is controlled to be delayed by a predetermined rate. In this way, the row width will not increase suddenly all at once, and as a result, erroneous sampling in other nodes can be prevented.

[0103] (Other embodiments) The present invention is not limited to the embodiments described above and illustrated in the drawings, but can be modified, combined, or expanded as desired without departing from the spirit of the invention. The numerical values ​​and the like shown in the above embodiments are examples and are not limited to these.

[0104] The present invention is not limited to the communication device 2 performing CXPI communication exemplified in each of the above embodiments, but can be applied to communication devices in general used in a communication system in which one of a plurality of communication devices that transmits and receives data via a transmission path transmits in synchronization with the communication of another communication device. For example, the present invention can also be applied to a communication device that performs LIN communication. LIN is an abbreviation for Local Interconnect Network.

[0105] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0106] 1...communication system, 2, 2a, 2b, 2c, 3...bus, 4, 4A...transceiver circuit, 6, 6A, 6B...driver circuit, 7, 7A...receiver circuit, 5...control circuit, 13...noise detection circuit, 14...noise detection circuit, 15...first receiver circuit, 16...second receiver circuit, 17, 17B...switching element, 18, 18A...driver circuit, 19...output buffer, 20...feedback circuit, 21, 21A...forced bus off circuit, 22, 22B...first forced off switch, 23, 23B...second forced off switch, 25...main detection circuit, 26...sub detection circuit, 27, 28, 29, 30...sub detection circuit.

Claims

1. A communication device used in a communication system (1) in which one of a plurality of communication devices (2, 2a, 2b, 2c) that transmits and receives data via a transmission path (3) transmits data in synchronization with the communication of the other communication device, When the dominant signal level on the transmission path is defined as the dominant level and the inferior signal level is defined as the inferior level, a switching element (17, 17B) that can set the signal level of the transmission path to the dominant level by turning it on; a control circuit (5) for controlling the transmission and reception of the data and generating a command signal which is a binary signal for commanding whether the signal level of the transmission path is to be the dominant level or the inferior level; a drive circuit (18, 18A) that turns on the switching element when the command signal is at a first level that commands the signal level of the transmission path to be the dominant level, and turns off the switching element when the command signal is at a second level that commands the signal level of the transmission path to be the inferior level; a receiver circuit (7, 7A) that receives data transmitted via the transmission line and outputs the data to the control circuit as a binary received signal; a noise detection circuit (14) for detecting noise superimposed on the transmission path; Equipped with The drive circuit an output buffer (19) that receives a voltage for turning on or off the switching element and outputs an output voltage corresponding to the input voltage to a control terminal of the switching element; a feedback circuit (20) that feeds back a signal on the transmission line to the input of the output buffer; a forced bus-off circuit (21, 21A, 21B) capable of executing a forced-off operation for forcibly driving off the switching element regardless of the command signal; Equipped with The forced bus off circuit measuring and learning a delay time from when the command signal changes from the first level to the second level to when the signal level of the transmission path changes from the dominant level to the inferior level; comparing a level represented by the command signal with a level represented by the received signal output from the receiver circuit at a predetermined timing determined according to a delay learning value that is a result of learning the delay time; If the levels are the same, the forced-off operation is performed at a first timing, which is the normal timing; If the levels are different, the forced-off operation is performed at a second timing that is a timing before the first timing; When noise is detected by the noise detection circuit, the communication device executes the forced-off operation at a third timing that is after the point in time when the command signal changes from the first level to the second level and before the second timing.

2. The forced bus off circuit a first forced-off switch (22, 22B) connected between the input of the output buffer and a node to which a voltage for turning off the switching element is applied; A second forced-off switch (23, 23B) may be additionally provided, which is connected between the output of the output buffer and a node to which a voltage for turning off the switching element is applied according to the output capability of the output buffer, 2. The communication device according to claim 1, wherein the forced-off operation is executed by turning on the first forced-off switch or by turning on both the first forced-off switch and the second forced-off switch.

3. The receiver circuit includes a first receiver circuit (15) provided with a noise removal circuit (12) for removing noise on its upstream side, and a second receiver circuit (16) not provided with the noise removal circuit on its upstream side, a first reception signal output from the first receiver circuit is used for a normal data reception operation by the control circuit; 2. The communication device according to claim 1, wherein the second received signal output from the second receiver circuit is used in the forced bus-off circuit.

4. 2. The communication device according to claim 1, wherein the forced bus-off circuit is capable of executing the forced bus-off operation at least during a period in which the command signal is at the second level.

5. The forced bus off circuit When measuring and learning the delay time, values ​​of the measured delay time that are within a learnable range, which is a predetermined appropriate range, are the subject of learning, and values ​​outside the learnable range are not the subject of learning. The communication device described in claim 1.

6. 2. The communication device according to claim 1, wherein the forced bus-off circuit is configured to transition to a noise-detected state in which the forced bus-off operation is executed at the third timing when noise is detected by the noise detection circuit, and then transition to a noise-non-detected state in which the forced bus-off operation is executed at the first timing or the second timing when noise detection by the noise detection circuit is not performed for a certain period of time.

7. 7. The communication device according to claim 6, wherein the forced bus-off circuit controls the timing of executing the forced bus-off operation to be delayed by a predetermined rate when transitioning from the noise-detected state to the noise-non-detected state.

8. 2. The communication device according to claim 1, wherein the noise detection circuit includes a main detection circuit (25) that detects noise superimposed on the transmission path based on noise superimposed on the signal in the output buffer.

9. 9. The communication device according to claim 8, wherein the noise detection circuit includes a sub-detection circuit (26) that detects noise superimposed on the transmission path based on the output of a noise detection circuit (13) configured by any form of high-pass filter.

10. 9. The communication device according to claim 8, wherein the noise detection circuit includes sub-detection circuits (27, 28, 29, 30) that detect noise superimposed on the transmission path based on chattering in the receiver circuit.

11. 11. The communication device according to claim 9, wherein the sub-detection circuit is configured to enable an operation for detecting noise when noise is not detected by the main detection circuit.

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