Light emitting display device

Abstract

An object of one embodiment of the present invention is to provide a light-emitting display apparatus including a thin film transistor.SOLUTION: The display device includes a plurality of pixels each including a thin film transistor and a light-emitting device, the pixels are electrically connected to first wirings functioning as scan lines, the thin film transistor includes an oxide-semiconductor layer provided over the first wirings with a gate insulating film interposed therebetween, the oxide-semiconductor layer is provided so as to protrude from a region where the first wirings are provided, and the light-emitting device and the oxide-semiconductor layer are provided so as to overlap with each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a light-emitting display device and to an electronic device equipped with the light-emitting display device. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are , amorphous silicon, and polycrystalline silicon. Thin film transistors using silicon have low field effect mobility, but are suitable for enlarging the area of ​​glass substrates. On the other hand, thin film transistors using crystalline silicon have high field effect mobility. However, a crystallization process such as laser annealing is required, and enlarging the glass substrate is essential. However, it has the characteristic of not being adaptable.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-G Thin film transistors were fabricated using a-Zn-O oxide semiconductors, and used as switches in light-emitting display devices. Patent Document 1 discloses a technique used in a switching element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-31750 Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors that use oxide semiconductors for the channel region are made of amorphous silicon. The field-effect mobility is higher than that of thin film transistors using the same in the panel region. A pixel having a thin film transistor formed using such an oxide semiconductor is used in an EL display. It is expected to be applied to light-emitting display devices such as 3D displays and 4k2k displays. In light-emitting display devices with added value, such as (a), the area per pixel becomes smaller. While this is expected, a light-emitting display device having pixels with an improved aperture ratio is desired.

[0006] Therefore, the present invention provides a pixel having a thin film transistor using an oxide semiconductor. An object of the present invention is to provide a light-emitting display device that can improve the brightness. [Means for solving the problem]

[0007] One embodiment of the present invention includes a plurality of pixels each having a thin film transistor and a light-emitting element. The thin film transistor is electrically connected to a first wiring that functions as a scan line. an oxide semiconductor layer provided on a wiring of the first gate electrode via a gate insulating film, The light-emitting element and the oxide semiconductor layer are provided so as to extend beyond the region where the first wiring is provided. and are provided so as to overlap each other.

[0008] One embodiment of the present invention includes a plurality of pixels each having a thin film transistor and a light-emitting element. , electrically connected to a first wiring functioning as a scanning line and a second wiring functioning as a signal line. The thin film transistor is formed on an oxide film provided on the first wiring via a gate insulating film. The oxide semiconductor layer is provided so as to extend beyond the region where the first wiring is provided. The second wiring extends on the gate insulating film on the first wiring and is connected to the oxide semiconductor layer. The light-emitting display device has a light-emitting element and an oxide semiconductor layer overlapping each other.

[0009] One embodiment of the present invention includes a plurality of pixels each having a thin film transistor and a light-emitting element. , electrically connected to a first wiring functioning as a scanning line and a second wiring functioning as a signal line. The thin film transistor is formed on an oxide film provided on the first wiring via a gate insulating film. The oxide semiconductor layer is provided so as to extend beyond the region where the first wiring is provided. The second wiring is formed on the gate insulating film on the first wiring and on the interlayer insulating layer on the gate insulating film. The light emitting element and the oxide semiconductor layer are overlapped with each other. It is a light-emitting display device.

[0010] One embodiment of the present invention is a semiconductor device including a first thin film transistor, a second thin film transistor, and a light-emitting element. The pixel has a plurality of pixels each having a first wiring functioning as a scanning line and a second wiring functioning as a signal line. The first thin film transistor is electrically connected to a second wiring that functions as a gate electrode. an oxide semiconductor layer provided on the first substrate with a gate insulating film interposed therebetween, The second wiring is provided so as to extend beyond the area where the line is provided, and the second wiring is a gate insulating layer on the first wiring. The insulating film extends on the oxide semiconductor layer and contacts the oxide semiconductor layer. The insulating film also contacts the oxide semiconductor layer. The third wiring for electrically connecting the first thin film transistor and the second thin film transistor is The light emitting element and the oxide semiconductor layer are overlapped. This is a light-emitting display device that is provided in a folded state.

[0011] One embodiment of the present invention includes a plurality of pixels each having a thin film transistor and a light-emitting element. , electrically connected to a first wiring functioning as a scanning line and a second wiring functioning as a signal line. The thin film transistor is formed on an oxide film provided on the first wiring via a gate insulating film. The oxide semiconductor layer is provided so as to extend beyond the region where the first wiring is provided. The second wiring is formed on the gate insulating film on the first wiring and on the interlayer insulating layer on the gate insulating film. The first thin film transistor is formed on the oxide semiconductor layer. The third wiring for electrically connecting the first thin film transistor to the second thin film transistor is formed on the first wiring. and a light emitting element, the light emitting element being provided extending on the gate insulating film and the interlayer insulating layer on the gate insulating film. and an oxide semiconductor layer are provided so as to overlap each other. [Effects of the Invention]

[0012] When manufacturing a pixel having a thin film transistor using an oxide semiconductor, it is necessary to improve the aperture ratio. Therefore, a light-emitting display device having a high-definition display portion can be provided. [Brief explanation of the drawings]

[0013] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a light-emitting display device. [Figure 2] 1 is a cross-sectional view illustrating a light-emitting display device. [Figure 3] 1A and 1B are top views illustrating a light-emitting display device. [Figure 4] 1A and 1B are a top view and a cross-sectional view illustrating a light-emitting display device. [Figure 5] 1A and 1B are top views illustrating a light-emitting display device. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a light-emitting display device. [Figure 7] FIG. 1 is a circuit diagram illustrating a light-emitting display device. [Figure 8] FIG. 1 is a circuit diagram illustrating a light-emitting display device. [Figure 9] 1 is a cross-sectional view illustrating a light-emitting display device. [Figure 10] 1A and 1B are diagrams illustrating electronic devices. [Figure 11] 1A and 1B are diagrams illustrating electronic devices. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a light-emitting display device. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in the following manner. It should be noted that the present invention is not limited to the following description. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. and the repeated explanation will be omitted.

[0015] In each drawing described in this specification, the size of each component, the thickness of a layer, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0016] In this specification, terms such as first, second, and third are used to avoid confusion of components. It is not a numerical limitation. For example, "first" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0017] (Embodiment 1) In this embodiment, as an example, a thin film transistor (hereinafter also referred to as a TFT) and the T A pixel having a light-emitting element connected to an FT will be shown and a light-emitting display device will be described. The pixel refers to each element provided in each pixel of the display device, such as a thin film transistor, a light emitting element, and a group of elements that are composed of elements for controlling the display by electrical signals such as wiring. The pixel may include a color filter, etc., and one pixel may It may be one color element whose brightness can be controlled. In the case of a color display device consisting of a R pixel, a G pixel, and a B pixel, the smallest unit of the image is It is composed of three pixels, and an image can be obtained by using multiple pixels. become.

[0018] The light-emitting element has a structure in which a light-emitting layer is provided between a pair of electrodes (anode and cathode), and In this specification, one electrode of the light-emitting element is shown in FIG. When referring to an element, it may also be called a light-emitting element.

[0019] When we say that A and B are connected, we mean that A and B are electrically connected. This includes the case where A and B are directly connected, and the case where A and B are directly connected. Specifically, the object is a transistor or other switch. A and B are connected via a switching element, and when the switching element is turned on, A and When A and B are connected via a resistor element, and both ends of the resistor element When the potential difference generated at the terminals is small enough not to affect the operation of the circuit including A and B, However, when considering circuit operation, it is acceptable to regard the part between A and B as the same node. This represents the case where the

[0020] FIG. 1(A) shows a top view of a pixel. Note that the structure of the TFT shown in FIG. 1(A) is a bottom gate type. The gate structure is on the opposite side of the oxide semiconductor layer that becomes the channel region from the wiring that becomes the gate. The so-called inverted staggered type has wiring layers that become the source and drain electrodes of the TFT on the side. This shows the configuration of

[0021] The pixel 100 shown in FIG. 1A includes a first wiring 101A functioning as a scan line, a second wiring 101B functioning as a signal line, and a third wiring 101C functioning as a signal line. The second wiring 102A, the first oxide semiconductor layer 103A, and the second oxide semiconductor layer 1(A), a power supply line 104A, a capacitance electrode 101B, and a light emitting element 105. The pixel 100 shown in FIG. 1 has a first oxide semiconductor layer 103A and a capacitance electrode 101B electrically connected to each other. A third wiring 102B for connection is provided, and a first thin film transistor 107A is provided. The pixel 100 shown in FIG. 1A includes a second oxide semiconductor layer 103B and a light-emitting element 10 5, and a fourth wiring 104B for electrically connecting the second thin film transistor 10 7B is formed.

[0022] First wiring 101A, second wiring 102A, third wiring 102B, fourth wiring 104B, The first oxide semiconductor layer 103A, the second oxide semiconductor layer 103B, the power supply line 104A, and A partition wall 106 is provided on the capacitance electrode 101B to separate the light emitting elements into pixels. The light emitting element 105 connected to the fourth wiring 104B is provided inside the partition wall 106. This becomes the case.

[0023] The first wiring 101A also functions as a gate of the first thin film transistor 107A. The capacitor electrode 101B is connected to the gate of the second thin film transistor 107B and one of the capacitor elements. The second wiring 102A also functions as an electrode of the first thin film transistor. It is also a wiring that functions as one of the source electrode or drain electrode of 107A. The line 102B is connected to the other of the source electrode or the drain electrode of the first thin film transistor 107A. The power supply line 104A is also a wiring that functions as a The wiring that functions as one of the source electrode or drain electrode and the other electrode of the capacitor element may also be The fourth wiring 104B is connected to the source electrode or drain of the second thin film transistor 107B. It also functions as the other of the in-electrodes.

[0024] The first wiring 101A and the capacitance electrode 101B are provided from the same layer, and the second wiring 102 A, a third wiring 102B, a power supply line 104A, and a fourth wiring 104B are provided from the same layer. The power supply line 104A and the capacitance electrode 101B are provided so as to overlap each other. This forms a storage capacitor for the thin film transistor 107B.

[0025] The first oxide semiconductor layer 103A of the first thin film transistor 107A is The first oxide semiconductor layer is provided on the wiring 101A via a gate insulating film (not shown). The conductor layer 103A is provided in the region where the first wiring 101A is provided and extends beyond the partition wall 106. It is being done.

[0026] Note that A protrudes from B when looking at the top view of stacked A and B. This means that the ends of A and B do not coincide, and A extends outward from the end of B.

[0027] In addition to the first thin film transistor 107A and the second thin film transistor 107B, a plurality of The first thin film transistor 107A may be a thin film transistor. The first thin film transistor 107A has a function of selecting a pixel having the first thin film transistor 107A. The second thin film transistor 107B is also called a select transistor. The transistor 107B has a function of controlling the current flowing to the light emitting element 105 of the pixel. , also called a drive transistor.

[0028] Also, in Figure 1(B), the cross sections between the dashed lines A-A', B-B', and C-C' in Figure 1(A) are shown. In the cross-sectional structure shown in FIG. 1B, a base film 111 is formed on a substrate 111. A first wiring 101A, which is a gate, and a capacitance electrode 101B are provided via 12. A gate insulating film 113 is provided so as to cover the first wiring 101A and the capacitance electrode 101B. On the gate insulating film 113, a first oxide semiconductor layer 103A, a second oxide semiconductor layer 103B, a A conductor layer 103B is provided on the first oxide semiconductor layer 103A. 102A, a third wiring 102B, and a power supply line 104A are provided on the second oxide semiconductor layer 103B. A fourth wiring 104B is provided. The compound semiconductor layer 103B, the second wiring 102A, the third wiring 102B, the power supply line 104A, and An oxide insulating layer 114 functioning as a passivation film is formed on the fourth wiring 104B. The first wiring 101A, the second wiring 102A, the third wiring 102B, the fourth wiring 102B, The wiring 104B, the first oxide semiconductor layer 103A, the second oxide semiconductor layer 103B, the power supply A partition wall 106 is provided on the oxide insulating layer 114 on the line 104A and the capacitor electrode 101B. An opening is formed in the oxide insulating layer 114 on the fourth wiring 104B. In the opening, the electrode of the light emitting element 105 is connected to the fourth wiring 104B. The third wiring 102B and the capacitance electrode 101B are connected to each other along the dashed line BB'. The connection is made through an opening formed in 113.

[0029] The pixels shown in FIGS. 1A and 1B are a plurality of pixels 701 on a substrate 700 shown in FIG. In FIG. 7, the pixel section 7 is arranged on the substrate 700. 7 shows a configuration including a scanning line driver circuit 702, a scanning line driver circuit 703, and a signal line driver circuit 704. The pixel 701 is supplied with a first wiring 101A connected to a scanning line driving circuit 703. The scanning signal determines whether each row is in a selected state or a non-selected state. The pixel 701 selected by the signal is connected to the second wiring 704. 102A supplies the video voltage (also called image signal, video signal, or video data) The pixel 701 is connected to a power supply circuit 705 provided outside the substrate 700. The power supply line 104A is connected to the power supply line 104B.

[0030] In FIG. 7, a scanning line driver circuit 703 and a signal line driver circuit 704 are provided on a substrate 700. However, either the scanning line driver circuit 703 or the signal line driver circuit 704 The pixel portion 702 may be provided on the substrate 700. Alternatively, only the pixel portion 702 may be provided on the substrate 700. 7, the power supply circuit 705 may be provided outside the substrate 700. However, a configuration in which the light emitting element is provided on the substrate 700 may also be used.

[0031] In FIG. 7, a pixel section 702 has a plurality of pixels 701 arranged in a matrix (stripe arrangement). It should be noted that the pixels 701 do not necessarily have to be arranged in a matrix. For example, the pixels 701 may be arranged in a delta arrangement or a Bayer arrangement. The display method in the element section 702 is either the progressive method or the interlace method. In addition, the color elements controlled by pixels when displaying colors are RGB ( It is not limited to three colors (R is red, G is green, B is blue), but may be more than three, for example, RGBW ( W is white), or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may differ for each dot of the color element.

[0032] In FIG. 7, a first wiring 101A, a second wiring 102A, and a power supply line 104A are connected to the pixel. The numbers are shown according to the row and column directions. 2A and the power supply line 104A are connected to the sub-pixels (also called sub-pixels or sub-sub-pixels) that make up the pixel. The number of lines may be increased depending on the number of lines, or the number of transistors in a pixel. The first wiring 101A, the second wiring 102A, and the power supply line 104A are shared between the pixels. The element 701 may be driven.

[0033] In FIG. 1A, the shape of the TFT is shown as if the second wiring 102A is rectangular. However, the shape of the third wiring 102B is such that it surrounds the third wiring 102B (specifically, U-shaped or C-shaped), The area of ​​the region where carriers move may be increased to increase the amount of current that flows.

[0034] The width of the first wiring 101A other than the region that will become the first thin film transistor 107A is By reducing the width of the first wiring, the pixel The aperture ratio can be improved.

[0035] The aperture ratio represents the area through which light passes per unit area. When the area occupied by the non-transmitting material becomes larger, the aperture ratio decreases and the area occupied by the light-transmitting material becomes larger. The larger the area occupied, the higher the aperture ratio. To prevent wiring or the like that does not transmit light from overlapping the area occupied by the light emitting element to be provided; Reducing the size of the thin film transistors leads to an improvement in the aperture ratio.

[0036] The thin film transistor has at least three regions including a gate, a drain, and a source. An element having terminals, and a channel region between a drain region and a source region, A current can be passed through the drain region, the channel region, and the source region. The source and drain vary depending on the transistor structure and operating conditions, so it is difficult to know which is which. It is difficult to determine whether the source or drain is the source or drain. The region that functions as a gate may not be called a source or drain. For example, they may be written as the first terminal and the second terminal. These may be referred to as the first electrode and the second electrode, or as the first region and the second region. There are cases where this happens.

[0037] Next, the method for manufacturing a pixel will be explained based on the top view and cross-sectional view shown in Figure 1(A) and (B). 2 will be used to explain.

[0038] First, a glass substrate can be used as the light-transmitting substrate 111. Preventing diffusion of impurities from the substrate 111 or ensuring close contact with each element provided on the substrate 111 The structure shown here is one in which a base film 112 is provided to improve the performance. There is no need to set up a

[0039] Next, a conductive layer is formed on the entire surface of the substrate 111, and then a first photolithography process is performed. A resist mask is formed, and unnecessary portions are removed by etching to form the first wiring 101A. At this time, at least the first wiring 101A and the capacitance electrode 101B are formed. The end of O1B is etched to have a tapered shape.

[0040] The first wiring 101A and the capacitance electrode 101B are made of aluminum (Al), copper (Cu), or the like. It is desirable to form it with a low-resistance conductive material, but aluminum alone has poor heat resistance and is prone to corrosion. Therefore, it is formed in combination with a heat-resistant conductive material. Materials include titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (M o), chromium (Cr), neodymium (Nd), scandium (Sc), or or an alloy containing the above elements as components, or an alloy of a combination of the above elements, or It is formed from nitrides containing the elements.

[0041] In addition, the wiring and the like that constitute the TFT can be formed using inkjet or printing methods. These allow fabrication at room temperature, in low vacuum, or on large substrates. Since it can be manufactured without using a photomask, the transistor layout can be It can be easily changed. Furthermore, since there is no need to use resist, the material cost is low. This reduces the number of processes. In addition, resist masks can be formed using inkjet or printing methods. Resist can be formed only in the required areas using inkjet or printing methods. By forming a resist mask by exposure and development, it is possible to This allows for lower costs.

[0042] In addition, a multi-tone mask is used to create a resist mask having regions of multiple thicknesses (typically two types). A block may be formed, and wiring and the like may be formed.

[0043] Next, an insulating film (hereinafter referred to as a gate insulating film 11) is formed on the first wiring 101A and the capacitance electrode 101B. The gate insulating film 113 is formed by sputtering or the like.

[0044] For example, the gate insulating film 113 is formed using a silicon oxide film by a sputtering method. Of course, the gate insulating film 113 is not limited to such a silicon oxide film, and may be a nitride oxide film. Other insulating films such as silicon dioxide film, silicon nitride film, aluminum oxide film, and tantalum oxide film The insulating film may be formed as a single layer or a laminated structure made of these materials.

[0045] Before forming an oxide semiconductor film, a reverse sintering process was performed in which argon gas was introduced to generate plasma. It is preferable to remove dust adhering to the surface of the gate insulating film 113 by sputtering. Instead of the argon atmosphere, nitrogen, helium, etc. may be used. It may be carried out in an atmosphere containing oxygen, N2O, etc. Also, in an argon atmosphere, Cl2 Alternatively, the reaction may be carried out in an atmosphere containing CF4 or the like.

[0046] Next, an oxide semiconductor is deposited on the gate insulating film 113 by plasma treatment of the surface of the gate insulating film 113. After the treatment, the oxide semiconductor is deposited without being exposed to the air. This results in a higher field-effect transport rate compared to silicon-based semiconductor materials such as amorphous silicon. The oxide semiconductor can be, for example, zinc oxide (ZnO), oxide Tin oxide (SnO2) can also be used. In addition, adding In or Ga to ZnO It is also possible to do so.

[0047] InMO3(ZnO) as an oxide semiconductor x A thin film expressed as (x>0) can be used. M can be gallium (Ga), iron (Fe), nickel (Ni), manganese (M n) and cobalt (Co). M can be Ga, or it can be any of the above other than Ga, such as Ga and Ni or Ga and Fe. In some cases, a metal element is contained. In addition, in the above oxide semiconductor, the metal contained as M is In addition to the transition metal elements, Fe, Ni and other transition metal elements, or the oxides of these transition metals, may be present as impurity elements. For example, the oxide semiconductor layer is made of In-Ga-Zn-O. A membrane can be used.

[0048] Oxide semiconductor (InMO3(ZnO) x (x>0) film) as In-Ga-Zn-O system film Instead of InMO3(ZnO), M can be another metal element. x (x>0) membrane may be used In addition to the above, oxide semiconductors include In-Sn-Zn-O, In-Al-Z nO system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system , In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn-O series, A Zn—O-based oxide semiconductor can be used.

[0049] The oxide semiconductor used is In-Ga-Zn-O. The target is a2O3:ZnO=1:1:1. The distance between the substrate and the target is Distance 100 mm, pressure 0.6 Pa, direct current (DC) power 0.5 kW, oxygen (oxygen flow rate 1 When a pulsed direct current (DC) power supply is used, the film is formed in a 00% atmosphere. This reduces the amount of powdery material (also called particles or dust) that gets into the film, and the film thickness distribution becomes uniform. preferable.

[0050] The oxide semiconductor film was formed in the same chamber as the previous reverse sputtering. Alternatively, the film may be formed in a chamber different from the chamber in which the previous reverse sputtering was performed.

[0051] The sputtering method uses RF sputtering, which uses a high frequency power supply, and DC sputtering. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which applies a bias pulse. The sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used when:

[0052] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0053] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0054] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0055] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C or higher and lower than 750°C, preferably 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. In this case, the heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is protected from exposure to the atmosphere, preventing water and hydrogen from re-entering the oxide semiconductor layer. In this embodiment, a process for dehydrating or dehydrogenating an oxide semiconductor layer is performed. From the heating temperature T, use the same furnace to a temperature that is high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the temperature T. Dehydration or dehydrogenation under a rare gas (helium, neon, argon, etc.) atmosphere is not possible. Do the following.

[0056] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. A rare gas such as argon or nitrogen, which hardly reacts with the material to be treated by heat treatment. An inert gas is used.

[0057] The oxide semiconductor layer is subjected to a heat treatment at a temperature of 400°C or higher and lower than 750°C. This dehydration and dehydrogenation of the carbon dioxide prevents subsequent re-impregnation with water (H2O).

[0058] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0059] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, In some cases, the film crystallizes to become a microcrystalline or polycrystalline film. For example, if the crystallization rate is 90% or more, In some cases, the oxide semiconductor film is microcrystalline, or 80% or more of the crystallinity is high. Depending on the conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be obtained. It may also be a conductive film.

[0060] The oxide semiconductor layer becomes oxygen-deficient after the first heat treatment for dehydration or dehydrogenation. The oxide semiconductor layer after the first heat treatment has a lower resistance than the oxide semiconductor film immediately after deposition. The carrier concentration is also increased, preferably to 1×10 18 / cm 3 have a carrier concentration of This becomes an oxide semiconductor layer.

[0061] Next, a second photolithography step is performed to form a resist mask and etch the The unnecessary portions are removed by the method, and the first oxide semiconductor layer 103A and the second oxide semiconductor layer 103B are formed of oxide semiconductor. The oxide semiconductor layer 103B is formed. The first heat treatment on the semiconductor layer 103B is performed on the oxide semiconductor layer 103B before it is processed into the island-shaped oxide semiconductor layer. The etching can be performed on a conductive film. Dry etching is used. The cross section at this stage is shown in Figure 2(A).

[0062] After the gate insulating film 113 is formed, the gate insulating film 113 is coated with a capacitor as shown in FIG. An opening 121 reaching the capacitance electrode 101B is formed, and a wiring to be formed later and the capacitance electrode are connected. It may be possible to do so.

[0063] Next, a conductive film made of a metal material is formed on the oxide semiconductor layer by sputtering or vacuum deposition. The conductive film material is an element selected from Al, Cr, Ta, Ti, Mo, and W, or Examples include alloys containing the above elements or alloys that combine the above elements. In addition, when heat treatment is performed at 200 to 600°C, the conductive film must be heat-resistant enough to withstand this heat treatment. It is preferable to use aluminum alone, which has problems such as poor heat resistance and susceptibility to corrosion. Therefore, it is formed by combining it with a heat-resistant conductive material. Heat-resistant conductive material combined with Al Titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo ), chromium (Cr), neodymium (Nd), Sc (scandium), or is an alloy containing the above elements, an alloy combining the above elements, or It is formed from nitrides containing elements.

[0064] Here, the conductive film has a single-layer structure of a titanium film. The conductive film may also have a two-layer structure. Alternatively, a titanium film may be laminated on an aluminum film. An aluminum film containing Nd (Al-Nd) is layered on top of the Ti film, and then The conductive film may be a single layer of aluminum film containing silicon. It may also have a layered structure.

[0065] Next, a third photolithography process is performed to form a resist mask and then etching is performed. The unnecessary portions are removed to leave the second wiring 102A, the third wiring 102B, and the power supply wiring 102B, which are made of a conductive film. The fourth wiring 104A and the fourth wiring 104B are formed. For example, ammonia hydrogen peroxide (31% by weight hydrogen peroxide) is used. Wet etching using hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2 The conductive film of the Ti film is etched to form the second wiring 102A, the third wiring 102B, the power supply The first oxide semiconductor layer 1 is selectively etched by selectively etching the fourth wiring 104A and the fourth wiring 104B. Therefore, the second oxide semiconductor layer 103A and the second oxide semiconductor layer 103B can remain.

[0066] In addition, depending on the etching conditions, the oxide semiconductor The exposed areas of the layer may be etched, in which case the second wiring 102A and the third wiring The first oxide semiconductor layer 103A in the region sandwiched between the wirings 102B is formed on the first wiring 101A. In this case, the oxide semiconductor layer in the region overlapping with the second wiring 102A and the third wiring 102B is thicker than that in the region overlapping with the second wiring 102A and the third wiring 102B. In addition, the thickness of the second oxide film in the region sandwiched between the power supply line 104A and the fourth wiring 104B is reduced. The compound semiconductor layer 103B is connected to the power supply line 104A and the fourth wiring 104B on the capacitance electrode 101B. The oxide semiconductor layer has a smaller thickness than that of the oxide semiconductor layer in the region overlapping with the oxide semiconductor layer.

[0067] Next, the gate insulating film 113, the first oxide semiconductor layer 103A, the second oxide semiconductor layer 1 03B, the second wiring 102A, the third wiring 102B, the power supply line 104A, and the fourth wiring 104 An oxide insulating layer 114 is formed on the first oxide semiconductor layer 103A and the second oxide semiconductor layer 103B. A part of the second oxide semiconductor layer 103B is in contact with the oxide insulating layer 114. A region of the first oxide semiconductor layer 103A that overlaps with the first wiring 101A with the insulating film 113 sandwiched therebetween. The region of the second oxide semiconductor layer 103B that overlaps with the capacitor electrode 101B is a channel formation region. It becomes an area.

[0068] The oxide insulating layer 114 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating layer can be formed by any suitable method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer. In this embodiment mode, a silicon oxide film is formed as the oxide insulating layer by a sputtering method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. In this embodiment, the substrate temperature is set to 100° C. The silicon oxide film is formed by sputtering in a rare gas (typically argon) atmosphere. In air, oxygen, or a mixture of rare gas (typically argon) and oxygen, The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used under an oxygen and rare gas atmosphere. A silicon oxide film can be formed by sputtering. The oxide insulating layer formed in contact with the body layer is resistant to moisture, hydrogen ions, and OH - Contains impurities such as First, an inorganic insulating film is used to block these substances from entering from the outside, typically an oxide film. A silicon film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxide nitride film, or the like is used. Note that the oxide insulating layer formed by sputtering is particularly dense, and impurities may be introduced into the adjacent layer. It can be used as a single layer as a protective film to suppress the diffusion phenomenon. Using a target doped with phosphorus (P) or boron (B), phosphorus (P) or boron (B) is doped into the oxide insulating layer. B) can also be added.

[0069] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity 0 The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering, and the film thickness is 300 nm.

[0070] Note that the oxide insulating layer 114 is provided over and in contact with a region that serves as a channel formation region of the oxide semiconductor layer. It also functions as a channel protection layer.

[0071] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 300°C or lower) is performed. 50°C or less) may be carried out in an inert gas atmosphere or a nitrogen gas atmosphere. A second heat treatment is carried out at 250° C. for 1 hour in a nitrogen atmosphere. The first oxide semiconductor layer 103A and a part of the second oxide semiconductor layer 103B are oxide insulating layers. It is heated in contact with 114.

[0072] The first oxide semiconductor layer 103A whose resistance is reduced by the first heat treatment and the second oxide semiconductor layer When the second heat treatment is performed on the oxide insulating layer 114 while the oxide insulating layer 103B is in contact with the oxide insulating layer 114, The region in contact with the insulating layer 114 becomes oxygen-excessive. The first oxide semiconductor layer 103A and the second oxide semiconductor layer 103B are in contact with the oxide insulating layer 114. In the depth direction of the first oxide semiconductor layer 103A and the second oxide semiconductor layer 103B, Make it I-type (high resistance).

[0073] Next, an opening 122 is formed in the oxide insulating layer 114 by a fourth photolithography process. The cross section at this stage is shown in Figure 2(B).

[0074] Next, a light-transmitting conductive film is formed to connect to the fourth wiring 104B. The conductive film material having this property is indium oxide (In2O3) or indium oxide silicon oxide. SnO2 alloys (In2O3-SnO2, abbreviated as ITO) are deposited by sputtering or vacuum deposition. Another material for the transparent conductive film is Al-Zn containing nitrogen. -O type film, that is, Al-Zn-ON type film, Zn-O type film containing nitrogen, and nitrogen-free The composition ratio of zinc in the Al-Zn-ON film may be (atomic %) is 47 atomic % or less, and is larger than the aluminum composition ratio (atomic %) in the film. The aluminum composition ratio (atomic %) in the film is greater than the nitrogen composition ratio (atomic %) in the film. Etching of such materials is done with a hydrochloric acid-based solution. Etching tends to leave residue, so indium oxide is used to improve etching processability. A zinc oxide alloy (In2O3-ZnO) may also be used.

[0075] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0076] Next, a fifth photolithography step is performed to form a resist mask and then to perform etching. The unnecessary part is removed to form one electrode of the light emitting element. The structure has a light-emitting layer between the electrodes (electrode and cathode), and the element constituting the light-emitting layer is stacked on the electrode. Therefore, one electrode of the light emitting element is called a light emitting element 105 .

[0077] Next, the first wiring 101A, the second wiring 102A, the third wiring 102B, the fourth wiring 1 04B, the first oxide semiconductor layer 103A, the second oxide semiconductor layer 103B, and the power supply line 104 A partition wall 106 is provided on the capacitor electrode 101B to separate the light emitting elements into pixels. The light emitting element 105 connected to the fourth wiring 104B is provided inside the partition wall 106. The cross section at this stage is shown in Figure 2(C).

[0078] Thus, the first thin film transistor 107A and the second thin film transistor 107B are Then, these are arranged in a matrix corresponding to each pixel. By arranging the electrodes to form a pixel portion, an active matrix light emitting display device is manufactured. It is possible.

[0079] The advantages of the configuration of this embodiment described with reference to FIGS. 1 and 2 will be explained with reference to FIGS. 3(A) and 3(B). A detailed explanation will be given below.

[0080] 3A and 3B are enlarged views of the oxide semiconductor layer and its vicinity in the top view of FIG. 1A. In addition, the width of the first oxide semiconductor layer 103A in FIG. 3A (W1 in FIG. 3A) The enlarged view shows the width of the first oxide semiconductor layer 103A in FIG. 3B ( This corresponds to the figure shown as W2).

[0081] In the top view of the pixel in FIG. 1A in this embodiment, as shown in FIGS. Then, the first wiring 101A is formed on the first wiring 101A without branching the wiring from the first wiring 101A. The oxide semiconductor layer 103A is provided. The second wiring 102A and the third wiring 102B are formed in the oxide semiconductor layer. A channel region formed between the first wiring 101A and the wiring 102B is located in the overlapping region on the first wiring 101A. The first oxide semiconductor layer 103A has a channel region that is irradiated with light. Therefore, the first wiring 101A is branched off from the first wiring 101A. It was necessary to ensure reliable light blocking using wiring, which was also a factor in reducing the aperture ratio of the pixels. An oxide semiconductor layer is provided so as to overlap on the first wiring 101A, which is the configuration of the embodiment, By not forming a wiring branched from the first wiring 101A, it is possible to improve the aperture ratio. Cut.

[0082] In addition, a light-transmitting oxide semiconductor layer is used as a semiconductor layer of a thin film transistor. As a result, the oxide semiconductor layer is positioned slightly away from the area where it overlaps with the first wiring 101A, rather than the designed position. Even if the light emitting element 105 overlaps the light emitting element 105, the aperture ratio can be reduced. The display can be performed without any problem.

[0083] By forming an oxide semiconductor layer with a pattern larger than the specified size, it is possible to Even if the oxide semiconductor layer is formed at a slightly misaligned location, it may cause malfunction and a decrease in aperture ratio. Therefore, it is possible to provide a good display without any problem. This makes it easier to manufacture substrates, and can improve yields.

[0084] Next, a storage capacitance is reduced by using a thin film transistor using an oxide semiconductor layer. An example of a specific top view when performing this is shown.

[0085] In a thin film transistor having an oxide semiconductor, a gate is connected to the gate electrode to turn the transistor off. The current that flows through the transistor when a voltage is applied (hereinafter referred to as leakage current) is 0.1 pA. While thin-film transistors with amorphous silicon have a current of several hundred nA or less, Therefore, in a thin film transistor having an oxide semiconductor, it is necessary to reduce the storage capacitance. That is, in a pixel provided with a thin film transistor having an oxide semiconductor, The pixel has a smaller area than the pixel in which a thin film transistor having amorphous silicon is provided. This allows for greater freedom in layout.

[0086] Thin film transistors having an oxide semiconductor layer have an extremely small leakage current, so they can be used as storage capacitors. It is also possible to omit the storage capacitor. The diagram is shown in FIGS. 12(A) and 12(B). The top view of the pixel shown in FIG. 12(A) is similar to that described above. This corresponds to the top view of FIG. 1(A) with the capacitance lines omitted. As can be seen from the top view shown in FIG. 12(B) and the cross-sectional view shown in FIG. 12(C), the thin film having the oxide semiconductor layer By using a transistor, the third wiring 10 The routing of 2B etc. can be shortened and the aperture ratio can be improved.

[0087] As described above, by using the structure described in this embodiment, a thin film using an oxide semiconductor When manufacturing a pixel having a film transistor, the aperture ratio can be improved. As a result, a light-emitting display device having a high-definition display portion can be provided.

[0088] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0089] (Embodiment 2) An example of configuring pixels of a display device having a TFT configuration different from that of the above embodiment will be described below.

[0090] A top view of a pixel having a structure different from that of Embodiment 1 is shown in FIG. The TFT structure shown in Figure 1 is a bottom gate structure, and the channel is On the opposite side of the oxide semiconductor layer that will become the gate region, A so-called inverted staggered structure having line layers is shown.

[0091] The pixel 400 shown in FIG. 4A includes a first wiring 401A functioning as a scan line, a second wiring 401B functioning as a signal line, and a third wiring 401C functioning as a signal line. The second wiring 402A, the first oxide semiconductor layer 403A, and the second oxide semiconductor layer 403B, a power supply line 404A, a capacitance electrode 401B, and a light emitting element 405. A third wiring 40 for electrically connecting the oxide semiconductor layer 403A and the capacitor electrode 401B. 2B, forming a first thin film transistor 407A. A fourth wiring 404B is provided for electrically connecting the layer 403B and the light emitting element 405. The second thin film transistor 407B is formed. 2A, a third wiring 402B, a fourth wiring 404B, a first oxide semiconductor layer 403A, a second A light-emitting element is provided on the oxide semiconductor layer 403B, the power supply line 404A, and the capacitor electrode 401B. A partition wall 406 is provided to separate each pixel. The fourth wiring 4 is provided inside the partition wall 406. A light emitting element 405 connected to the light emitting element 04B is provided.

[0092] The first wiring 401A also functions as a gate of the first thin film transistor 407A. The capacitor electrode 401B is connected to the gate of the second thin film transistor 407B and one of the storage capacitors. The second wiring 402A also functions as an electrode for the first thin film transistor. It also functions as one of the source electrode and the drain electrode of the transistor 407A. The third wiring 402B is connected to the source electrode or drain electrode of the first thin film transistor 407A. The power supply line 404A is also a wiring that functions as the other of the first and second thin film transistors 407. A semiconductor device that functions as one of the source electrode or drain electrode of B and the other electrode of the storage capacitor. The fourth wiring 404B is also a source electrode of the second thin film transistor 407B. is also a wiring that functions as the other of the drain electrodes.

[0093] The first wiring 401A and the capacitance electrode 401B are provided from the same layer, and the second wiring 402 A, a third wiring 402B, a power supply line 404A, and a fourth wiring 404B are provided from the same layer. The power supply line 404A and the capacitance electrode 401B are provided so as to overlap each other. The first thin film transistor 407B forms a storage capacitor. The first oxide semiconductor layer 403A of the first wiring 401A is formed on the gate insulating film 401B. The first oxide semiconductor layer 403A is provided via a first wiring 40 1A and the partition wall 406 are provided so as to extend beyond the area where they are provided.

[0094] Also, in FIG. 4(B), the cross sections between the dashed lines A-A', B-B', and C-C' in FIG. 4(A) are shown. In the cross-sectional structure shown in FIG. 4B, a base film 411 is formed on a substrate 411. 12, a first wiring 401A which is a gate and a capacitance electrode 401B are provided. A gate insulating film 413 is provided so as to cover the first wiring 401A and the capacitance electrode 401B. On the gate insulating film 413, a first oxide semiconductor layer 403A, a second oxide semiconductor layer 403B, a A conductor layer 403B is provided on the first oxide semiconductor layer 403A. 402A, a third wiring 402B, and a power supply line 404A are provided on the second oxide semiconductor layer 403B. A fourth wiring 404B is provided. The compound semiconductor layer 403B, the second wiring 402A, the third wiring 402B, the power supply line 404A, and An oxide insulating layer 414 functioning as a passivation film is formed on the fourth wiring 404B. The first wiring 401A, the second wiring 402A, the third wiring 402B, the fourth wiring 402B, The wiring 404B, the first oxide semiconductor layer 403A, the second oxide semiconductor layer 403B, the power supply A partition wall 406 is provided on the oxide insulating layer 414 on the line 404A and the capacitor electrode 401B. An opening is formed in the oxide insulating layer 414 on the fourth wiring 404B. In the opening, the electrode of the light emitting element 405 is connected to the fourth wiring 404B. The third wiring 402B and the capacitance electrode 401B are connected to each other along the dashed line BB'. The connection is made through an opening formed in 413.

[0095] The pixels shown in FIGS. 4A and 4B are the same as those described in FIGS. 1A and 1B of the first embodiment. Similarly, a plurality of pixels 701 arranged in a matrix on a substrate 700 in FIG. The explanation regarding FIG. 7 is the same as that in the first embodiment.

[0096] The cross-sectional view shown in FIG. 4(B) is the same as the cross-sectional view shown in FIG. 1(B). The method is the same as that explained in FIG. 2 in the first embodiment.

[0097] The advantages of the configuration of this embodiment described with reference to FIGS. 4(A) and 4(B) are shown in FIGS. 5(A) and 5(B). ) will be used for detailed explanation.

[0098] 5A and 5B are enlarged views of the oxide semiconductor layer and its vicinity in the top view of FIG. 4A. In addition, the width of the first oxide semiconductor layer 403A in FIG. 5A (W1 in FIG. 5A) The enlarged view shows the width of the first oxide semiconductor layer 403A in FIG. 5B ( This corresponds to the figure shown as W2).

[0099] In the top view of the pixel in FIG. 4A in this embodiment, as shown in FIGS. Then, the first wiring 401A is connected to the first wiring 401A without branching the wiring from the first wiring 401A. An oxide semiconductor layer 403A is provided. The second wiring 402A and the third wiring 403B are formed in the oxide semiconductor layer. A channel region formed between the first wiring 402B and the first wiring 401A is located in the overlapping region. In addition, in this embodiment, the first oxide semiconductor layer 403A is formed A second wiring 402A and a third wiring 402B extend on the gate insulating film on the wiring 401A. You will come into contact with.

[0100] The first oxide semiconductor layer 403A has a channel region that is irradiated with light, and the TFT characteristics are varied. Therefore, the wiring branched from the first wiring 401A is used to ensure light blocking. This is a factor that reduces the aperture ratio of the pixel. An oxide semiconductor layer is provided over and overlaps with the first wiring 401A. A structure in which no branched wiring is formed, and a structure in which a gate insulating film is extended on the first wiring 401A The second wiring 402A and the third wiring 402B are in contact with the first oxide semiconductor layer 403A. This configuration can improve the aperture ratio.

[0101] In addition, a light-transmitting oxide semiconductor layer is used as a semiconductor layer of a thin film transistor. As a result, the oxide semiconductor layer is positioned slightly away from the area where it overlaps with the first wiring 401A, rather than the designed position. Even if the light emitting element 405 overlaps the light emitting element 405, the aperture ratio can be reduced. The display can be performed without any problem.

[0102] The second wiring 402A and the third wiring 402B extending over the first wiring 401A shown in FIG. 4(A) are The line 402B may be provided so as to overlap the first line 401A. The third wiring 402A and the third wiring 402B may be routed in a meandering manner. Alternatively, the wiring may be arranged in a straight line.

[0103] By forming an oxide semiconductor layer with a pattern larger than the specified size, it is possible to Even if the oxide semiconductor layer is formed at a position that is out of alignment, there is no problem of malfunction and a decrease in aperture ratio. Therefore, a good display can be achieved without any problem. This makes it easier to produce risk substrates, which can lead to improved yields.

[0104] As described above, by using the structure described in this embodiment, a thin film using an oxide semiconductor When manufacturing a pixel having a film transistor, the aperture ratio can be improved. As a result, a light-emitting display device having a high-definition display portion can be provided.

[0105] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0106] (Embodiment 3) An example of configuring pixels of a display device having a TFT configuration different from that of the above embodiment will be described below.

[0107] A top view and a cross-sectional view of a pixel different from the configuration of Embodiment 2 are shown in FIGS. 6A and 6B. The structure of the top view shown in FIG. 6(A) is the same as that shown in FIG. 4(A), and therefore will not be explained here. The structure of the cross-sectional view shown in FIG. 6(B) is different from the structure of the cross-sectional view shown in FIG. 4(B). The point is that an interlayer insulating layer 601A is provided between the first wiring 401A and the second wiring 402A. and an interlayer insulating layer 601 between the first wiring 401A and the third wiring 402B. B is provided.

[0108] A second wiring 402A and a third wiring 402B are provided extending on the first wiring 401A. In this case, depending on the film thickness of the gate insulating film 413, the first wiring 401A and the second wiring 402A , between the first wiring 401A and the third wiring 402B, and between the first wiring 401A and the power supply line 4 Therefore, as shown in Figure 6(B), a parasitic capacitance is generated between the insulating layer and the By providing the insulating layer 601A and the interlayer insulating layer 601B, the parasitic capacitance is reduced, and malfunctions and other defects are prevented. can be reduced.

[0109] As described above, by using the structure described in this embodiment, a thin film using an oxide semiconductor When manufacturing a pixel having a film transistor, the aperture ratio can be improved. In this embodiment, in addition to the configuration of the second embodiment, it is possible to reduce the parasitic capacitance. Therefore, the light emitting display device has a high-definition display portion and is capable of reducing malfunctions. It is possible.

[0110] (Fourth embodiment) In this embodiment mode, a structure of a light-emitting element that is a display element will be described.

[0111] FIG. 9 shows one mode of a cross-sectional structure of a light-emitting element connected to a thin film transistor. The light-emitting element is composed of a first electrode 911, an EL layer 913 having a light-emitting layer, a second electrode 914, and a One of the first electrode 911 and the second electrode 914 serves as an anode. The light-emitting element functions as a cathode and the other functions as a positive electrode. The electrons injected from the first electrode of the light-emitting element are recombined in the light-emitting layer included in the EL layer, and emit light. The electrode 911 is connected to the thin film transistor 107B formed on the substrate 111. The first electrode 911 and one of the electrodes that will be the source or drain of the film transistor 107B are covered. The partition wall 106 is provided so as to form a hole. An L layer 913 is provided, and a second electrode 914 is provided so as to cover the EL layer 913 and the partition wall 106. Note that this embodiment mode uses the thin film transistor described in Embodiment Mode 1. In this case, the thin film transistor described in other embodiments can be used.

[0112] The first electrode 911 or the second electrode 914 is made of a metal, an alloy, or an electrically conductive compound. and form.

[0113] For example, the first electrode 911 or the second electrode 914 has a large work function (a work function of 4. 0 eV or more) metals, alloys, electrically conductive compounds, etc. can be used. Indium Tin Oxide (ITO), silicon or oxide Indium oxide-tin oxide and indium oxide-zinc oxide (IZO:In Tungsten oxide and zinc oxide are used in oxide coatings. The conductive metal oxide layer has optical transparency, such as IWZO.

[0114] In addition, the first electrode 911 or the second electrode 914 has a small work function (typically, (function is 3.8 eV or less) metals, alloys, electrically conductive compounds, etc. can be used. Specifically, elements in Groups 1 and 2 of the periodic table, such as lithium and cesium, Alkali metals and alkaline earth metals such as magnesium, calcium, and strontium metals and alloys containing these (aluminum, magnesium-silver alloy, aluminum and lithium alloys), rare earth metals such as europium and ytterbium, and Alloys, etc.

[0115] Alkali metals, alkaline earth metals, and alloys containing these metals can be deposited by vacuum deposition, sputtering, etc. In addition, silver paste or the like is ejected and printed by the inkjet method. The first electrode 911 and the second electrode 914 may be formed as a single layer. It is also possible to form the film by laminating the film.

[0116] In order to extract light emitted from the EL layer to the outside, the first electrode 911 or the second electrode 91 Either one or both of the first electrode and the second electrode are formed to transmit light emitted from the EL layer. If only 911 is an electrode having light transmissivity, light passes through the first electrode as shown by the arrow 900. The signal is output from the substrate 111 at a brightness corresponding to the video signal input from the signal line through the electrode 911. In addition, when only the second electrode 914 is an electrode having light transmissivity, the light is transmitted through the second electrode The light is taken out from the sealing substrate 916 side at a brightness according to the video signal input from the signal line through 914. Both the first electrode 911 and the second electrode 914 are light-transmitting electrodes. In this case, light passes through the first electrode 911 and the second electrode 914 and is converted into a video signal input from a signal line. The light is extracted from both the substrate 111 side and the sealing substrate 916 side at a luminance corresponding to the signal.

[0117] The light-transmitting electrode is formed using, for example, a light-transmitting conductive metal oxide. Alternatively, silver, aluminum, or the like is formed to a thickness of several nm to several tens of nm. a thin metal layer such as silver or aluminum and a transparent conductive metal oxide layer It may also have a laminated structure.

[0118] Either the first electrode 911 or the second electrode 914, which functions as an anode, has a large work function. It is preferable to use metals, alloys, electrically conductive compounds, etc. (work function 4.0 eV or more) The other of the first electrode 911 and the second electrode 914, which function as a cathode, has a work function of It is preferable to use metals, alloys, electrically conductive compounds, etc. with small work functions (3.8 eV or less). Typically, alkali metals, alkaline earth metals, and alloys and compounds containing these metals are preferred. , as well as transition metals including rare earth metals.

[0119] The EL layer 913 has a light-emitting layer. In addition to the light-emitting layer, the EL layer 913 also has a hole injection layer. The hole transport layer may be connected to the anode and the light emitting layer. The hole injection layer is provided between the anode and the light emitting layer, or between the anode and the hole transport layer. On the other hand, the electron transport layer is provided between the cathode and the light emitting layer. The layer is provided between the cathode and the light-emitting layer, or between the cathode and the electron transport layer. It is not necessary to provide all of the layers, the hole transport layer, the electron transport layer, and the electron injection layer, and it is possible to provide only the layers as required. It may be selected and provided depending on the function, etc.

[0120] The light-emitting layer contains a light-emitting substance. Examples of the light-emitting substance include fluorescent substances that emit fluorescence. Compounds and phosphorescent compounds that emit phosphorescence can be used.

[0121] The light-emitting layer can be formed by dispersing a light-emitting substance in a host material. When the luminescent layer is formed by dispersing the luminescent materials in a substrate, concentration quenching occurs, which causes a quenching reaction between the luminescent materials. This can suppress the phenomenon of crystallization.

[0122] When the luminescent substance is a fluorescent compound, the host material has a higher singlet excitation than the fluorescent compound. It is possible to use a substance with a large energy (energy difference between the ground state and the singlet excited state) In the case of a phosphorescent compound, it is preferable that the host material has a triplet excitation property rather than a phosphorescent compound. It is possible to use a substance with a large energy (energy difference between the ground state and the triplet excited state) preferable.

[0123] The light-emitting substance dispersed in the host material may be the phosphorescent compound or the fluorescent compound described above. A mixture can be used.

[0124] The light-emitting layer may contain two or more host materials and a light-emitting substance. Two or more types of host materials and two or more types of luminescent materials may be used. Two or more kinds of luminescent substances may be used.

[0125] In addition, a layer containing a substance with high hole transporting properties and a substance showing electron accepting properties is used as the hole injecting layer. The layer containing a substance having a high hole transporting property and a substance having an electron accepting property can be formed by It has a high hole density and excellent hole injection properties. A layer containing a material having the above structure is used as a hole injection layer in contact with an electrode functioning as an anode. Therefore, regardless of the work function of the electrode material that functions as the anode, various metals, alloys, and Conductive compounds and mixtures thereof can be used.

[0126] The light-emitting layer, hole injection layer, hole transport layer, electron transport layer and electron injection layer can be formed by vapor deposition, coating or the like. It can be formed more easily.

[0127] In addition, a passivation layer 915 is formed on the second electrode 914 and the partition wall 106 by sputtering. The passivation layer 915 may be formed by a method such as a CVD method. This reduces the deterioration of the light emitting element due to the intrusion of moisture and oxygen into the light emitting element. The space between the passivation layer 915 and the sealing substrate 916 is filled with nitrogen, and a desiccant is also added. Alternatively, a light-transmitting layer may be disposed between the passivation layer 915 and the sealing substrate 916. Alternatively, the porous layer may be filled with an organic resin having high water absorption properties.

[0128] When the light emitting element emits white light, a color filter or a color conversion layer is formed on the substrate 11. 1 or the sealing substrate 916, full color display can be performed.

[0129] In order to enhance contrast, a polarizing plate or a circular polarizing plate is provided on the substrate 111 or the sealing substrate 916. A plate may be provided.

[0130] In the pixel of this embodiment, by combining the configurations of the above embodiments, When manufacturing a pixel having a thin film transistor using an oxide semiconductor, it is necessary to improve the aperture ratio. This can be achieved.

[0131] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh.

[0132] (Embodiment 5) In this embodiment mode, a circuit configuration of a pixel that can be applied to a light-emitting display device will be described.

[0133] 8 is a diagram showing an example of a pixel configuration that can be applied to a light-emitting display device. a first thin film transistor 801, a second thin film transistor 802, a capacitor element 803, a light-emitting element The gate of the first thin film transistor 801 is electrically connected to the first wiring 805. The first terminal of the first thin film transistor 801 is electrically connected to the second wiring 806. The second terminal of the first thin film transistor 801 is connected to the first electrode of the capacitor 803. and the gate of the second thin film transistor 802. The electrode is electrically connected to a power supply line 807. A first terminal of the second thin film transistor 802 is electrically connected to a power supply line 807. A second terminal of the second thin film transistor 802 is It is electrically connected to one electrode of the light-emitting element 804 .

[0134] The first wiring 805 has the same function as the first wiring 101A described in the first embodiment. The second wiring 806 is similar to the second wiring 10 described in the first embodiment. The power supply line 807 has the same function as that of the power supply line 2A described in the first embodiment. The structure of the light emitting element 804 is the same as that of the light emitting element 104A described in the fourth embodiment. The configuration is the same as that of the light-emitting element described above.

[0135] In the pixel of this embodiment, by combining the configurations of the above embodiments, When manufacturing pixels equipped with thin film transistors using nitride semiconductors, it is necessary to improve the aperture ratio. It is possible.

[0136] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0137] (Sixth embodiment) In this embodiment mode, an electronic device including the light-emitting display device described in the above embodiment mode will be described. An example will be described.

[0138] FIG. 10A shows a portable gaming machine, which includes a housing 9630, a display unit 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, recording medium reading unit 9672, etc. The portable gaming machine shown in FIG. 10(A) can be used to play a program or data recorded on a recording medium. It also has the function of reading out data and displaying it on the display, and of sharing information with other portable gaming machines via wireless communication. The portable gaming machine shown in FIG. 10(A) has the following functions. The functions are not limited to these, and various functions can be provided.

[0139] FIG. 10B shows a digital camera, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, connection terminal 9636, shutter button 9676, image receiving unit 9677 , etc. The digital camera with a television receiving function shown in FIG. 10(B) can have: Functions for taking still images, shooting videos, and automatically or manually correcting captured images Function, function to acquire various information from the antenna, image taken or acquired from the antenna It has the function of saving the captured information, displaying the captured image or the information obtained from the antenna on the display. It should be noted that the digital camera with television reception function shown in FIG. The functions of the mobile camera are not limited to these, and the mobile camera may have a variety of functions.

[0140] FIG. 10C shows a television receiver, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, etc. A television receiver has the functions of processing television radio waves and converting them into image signals, It has functions such as converting signals suitable for display and converting the frame frequency of image signals. It should be noted that the functions of the television receiver shown in FIG. 10(C) are not limited to these. It can have a variety of functions.

[0141] FIG. 11A shows a computer, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, external connection ports 9680, pointing devices The computer shown in FIG. 11(A) can store various information. (still images, videos, text images, etc.) on the display, Functions for controlling processing by means of wireless or wired communication, the ability to connect to various computer networks using the communication function, It can have a function to transmit or receive data, etc. The functions possessed by the computer are not limited to these, and the computer may have a variety of functions.

[0142] Next, FIG. 11B shows a mobile phone, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, a microphone 9638, etc. The mobile phone shown in has the function of displaying various information (still images, videos, text images, etc.), Functions for displaying the calendar, date, time, etc. on the display, and for operating or It has the function of editing, the function of controlling the processing by various software (programs), etc. The functions of the mobile phone shown in FIG. 11(B) are not limited to these. It can have a variety of functions.

[0143] Next, FIG. 11C shows an electronic paper (also called an E-book), which includes a housing 9630, a display The electronic pen 9630 shown in FIG. The user can display various information (still images, videos, text images, etc.), a calendar, , the function to display the date or time on the display unit, and the function to operate or edit the information displayed on the display unit Functions such as the ability to control processing using various software (programs) The functions of the electronic paper shown in FIG. 11(C) are not limited to these. It can have a variety of functions.

[0144] The electronic device described in this embodiment has a plurality of pixels constituting a display unit, each of which has an aperture ratio It is possible to improve the

[0145] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0146] 100 pixels 103 Oxide semiconductor layer 105 Light-emitting element 106 Bulkhead 111 Substrate 112 Base film 113 Gate insulating film 114 Oxide insulating layer 121 Opening 122 Opening 400 pixels 405 Light-emitting element 406 Bulkhead 411 Substrate 412 Base film 413 Gate insulating film 414 Oxide insulating layer 700 boards 701 pixels 702 pixel section 703 Scanning line driving circuit 704 Signal Line Driver Circuit 705 Power supply circuit 800 pixels 801 Thin Film Transistor 802 Thin Film Transistor 803 Capacitor 804 Light-emitting element 805 Wiring 806 Wiring 807 Power line 900 Arrow direction 911 Electrode 912 Bulkhead 913 EL layer 914 Electrode 915 Passivation Layer 916 Sealing substrate 101A wiring 101B Capacitive electrode 102A wiring 102B wiring 103A Oxide semiconductor layer 103B Oxide semiconductor layer 104A power line 104B wiring 107A Thin-film transistor 107B Thin-film transistor 401A Wiring 401B Capacitive electrode 402A Wiring 402B wiring 403A Oxide semiconductor layer 403B Oxide semiconductor layer 404A power line 404B wiring 407A Thin Film Transistor 407B Thin Film Transistor 601A Interlayer insulation layer 601B Interlayer insulation layer 9630 chassis 9631 Display section 9633 Speaker 9635 Operation Key 9636 Connection terminal 9638 Microphone 9672 Recording medium reading unit 9676 Shutter button 9677 Image receiving unit 9680 External connection port 9681 Pointing Device

Claims

1. A first wiring having a region extending in a first direction in a plan view and functioning as a scanning line, A second wiring having a region extending in a second direction that intersects the first direction in a plan view, and having the function of a signal line, A third wiring having a region extending in the second direction in a plan view and functioning as a power line, A first light-emitting element included in the first pixel, The first transistor included in the first pixel, The second transistor included in the first pixel, A second light-emitting element included in a second pixel adjacent to the first pixel, It has a partition wall having a first opening that overlaps with the first light-emitting element and a second opening that overlaps with the second light-emitting element, The source and drain of the first transistor are electrically connected to the gate of the second transistor. The source and drain of the first transistor are electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first wiring, One of the sources and drains of the second transistor is electrically connected to the first light-emitting element. The source and drain of the second transistor are electrically connected to the third wiring. In a plan view, the first oxide semiconductor layer having the channel formation region of the first transistor has a region that overlaps with the second opening. The channel length direction of the first transistor is along the first direction, The channel length direction of the second transistor is along the direction of the second direction, The channel length of the second transistor is greater than the channel length of the first transistor. In a plan view, the first opening has a portion having a first width along the first direction, a portion having a second width along the first direction, and a portion having a third width along the first direction. The second width is smaller than the first width and smaller than the third width. In a plan view, the portion having the first width, the portion having the second width, and the portion having the third width are arranged in this order in the second direction. Light-emitting display device.

2. A first wiring having a region extending in a first direction in a plan view and functioning as a scanning line, A second wiring having a region extending in a second direction that intersects the first direction in a plan view, and having the function of a signal line, A third wiring having a region extending in the second direction in a plan view and functioning as a power line, A first light-emitting element included in the first pixel, The first transistor included in the first pixel, The second transistor included in the first pixel, A second light-emitting element included in a second pixel adjacent to the first pixel, It has a partition wall having a first opening that overlaps with the first light-emitting element and a second opening that overlaps with the second light-emitting element, The source and drain of the first transistor are electrically connected to the gate of the second transistor. The source and drain of the first transistor are electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first wiring, One of the sources and drains of the second transistor is electrically connected to the first light-emitting element. The source and drain of the second transistor are electrically connected to the third wiring. In a plan view, the first oxide semiconductor layer having the channel formation region of the first transistor has a region that overlaps with the second opening. The channel length direction of the first transistor is along the first direction, The channel length direction of the second transistor is along the direction of the second direction, The channel length of the second transistor is greater than the channel length of the first transistor. In a plan view, the first opening has a portion having a first width along the first direction, a portion having a second width along the first direction, and a portion having a third width along the first direction. The second width is smaller than the first width and smaller than the third width. In a plan view, the portion having the first width, the portion having the second width, and the portion having the third width are arranged in this order in the second direction. In a plan view, the region where the first conductive layer, which functions as either the source electrode or the drain electrode of the second transistor, and the first electrode of the first light-emitting element are in contact with each other is aligned with the portion having the second width along the first direction. Light-emitting display device.

3. A first wiring having a region extending in a first direction in a plan view and functioning as a scanning line, A second wiring having a region extending in a second direction that intersects the first direction in a plan view, and having the function of a signal line, A third wiring having a region extending in the second direction in a plan view and functioning as a power line, A first light-emitting element included in the first pixel, The first transistor included in the first pixel, The second transistor included in the first pixel, A second light-emitting element included in a second pixel adjacent to the first pixel, It has a partition wall having a first opening that overlaps with the first light-emitting element and a second opening that overlaps with the second light-emitting element, The source and drain of the first transistor are electrically connected to the gate of the second transistor. The source and drain of the first transistor are electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first wiring, One of the sources and drains of the second transistor is electrically connected to the first light-emitting element. The source and drain of the second transistor are electrically connected to the third wiring. In a plan view, the first oxide semiconductor layer having the channel formation region of the first transistor has a region that overlaps with the second opening. The channel length direction of the first transistor is along the first direction, The channel length direction of the second transistor is along the direction of the second direction, The channel length of the second transistor is greater than the channel length of the first transistor. In a plan view, the first opening has a portion having a first width along the first direction, a portion having a second width along the first direction, and a portion having a third width along the first direction. The second width is smaller than the first width and smaller than the third width. In a plan view, the portion having the first width, the portion having the second width, and the portion having the third width are arranged in this order in the second direction. In a plan view, the region where the first conductive layer, which functions as either the source electrode or the drain electrode of the second transistor, and the first electrode of the first light-emitting element are in contact with each other is aligned with the portion having the second width along the first direction. In a plan view, the second conductive layer having the function of the gate electrode of the second transistor has a first region having a fourth width along the first direction, a second region having a fifth width along the first direction, and a third region having a sixth width along the first direction. The fifth width is greater than the fourth width and greater than the sixth width. In a plan view, the first region, the second region, and the third region are arranged in this order in the second direction. The second region overlaps with the channel formation region of the second transistor. Light-emitting display device.

4. A first wiring having a region extending in a first direction in a plan view and functioning as a scanning line, A second wiring having a region extending in a second direction that intersects the first direction in a plan view, and having the function of a signal line, A third wiring having a region extending in the second direction in a plan view and functioning as a power line, A first light-emitting element included in the first pixel, The first transistor included in the first pixel, The second transistor included in the first pixel, A second light-emitting element included in a second pixel adjacent to the first pixel, It has a partition wall having a first opening that overlaps with the first light-emitting element and a second opening that overlaps with the second light-emitting element, The source and drain of the first transistor are electrically connected to the gate of the second transistor. The source and drain of the first transistor are electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first wiring, One of the sources and drains of the second transistor is electrically connected to the first light-emitting element. The source and drain of the second transistor are electrically connected to the third wiring. In a plan view, the first oxide semiconductor layer having the channel formation region of the first transistor has a region that overlaps with the second opening. The channel length direction of the first transistor is along the first direction, The channel length direction of the second transistor is along the direction of the second direction, The channel length of the second transistor is greater than the channel length of the first transistor. In a plan view, the first opening has a portion having a first width along the first direction, a portion having a second width along the first direction, and a portion having a third width along the first direction. The second width is smaller than the first width and smaller than the third width. In a plan view, the portion having the first width, the portion having the second width, and the portion having the third width are arranged in this order in the second direction. In a plan view, the region in which the first conductive layer, which functions as either the source electrode or the drain electrode of the second transistor, and the first electrode of the first light-emitting element are in contact with each other does not overlap with the second oxide semiconductor layer having the channel-forming region of the second transistor. Light-emitting display device.

5. A first wiring having a region extending in a first direction in a plan view and functioning as a scanning line, A second wiring having a region extending in a second direction that intersects the first direction in a plan view, and having the function of a signal line, A third wiring having a region extending in the second direction in a plan view and functioning as a power line, A first light-emitting element included in the first pixel, The first transistor included in the first pixel, The second transistor included in the first pixel, A second light-emitting element included in a second pixel adjacent to the first pixel, It has a partition wall having a first opening that overlaps with the first light-emitting element and a second opening that overlaps with the second light-emitting element, The source and drain of the first transistor are electrically connected to the gate of the second transistor. The source and drain of the first transistor are electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first wiring, One of the sources and drains of the second transistor is electrically connected to the first light-emitting element. The source and drain of the second transistor are electrically connected to the third wiring. In a plan view, the first oxide semiconductor layer having the channel formation region of the first transistor has a region that overlaps with the second opening. The channel length direction of the first transistor is along the first direction, The channel length direction of the second transistor is along the direction of the second direction, The channel length of the second transistor is greater than the channel length of the first transistor. In a plan view, the first opening has a portion having a first width along the first direction, a portion having a second width along the first direction, and a portion having a third width along the first direction. The second width is smaller than the first width and smaller than the third width. In a plan view, the portion having the first width, the portion having the second width, and the portion having the third width are arranged in this order in the second direction. In a plan view, the region in which the first conductive layer, which functions as either the source electrode or the drain electrode of the second transistor, and the first electrode of the first light-emitting element are in contact with each other is aligned with the portion having the second width along the first direction, and does not overlap with the second oxide semiconductor layer having the channel-forming region of the second transistor. Light-emitting display device.

6. A first wiring having a region extending in a first direction in a plan view and functioning as a scanning line, A second wiring having a region extending in a second direction that intersects the first direction in a plan view, and having the function of a signal line, A third wiring having a region extending in the second direction in a plan view and functioning as a power line, A first light-emitting element included in the first pixel, The first transistor included in the first pixel, The second transistor included in the first pixel, A second light-emitting element included in a second pixel adjacent to the first pixel, It has a partition wall having a first opening that overlaps with the first light-emitting element and a second opening that overlaps with the second light-emitting element, The source and drain of the first transistor are electrically connected to the gate of the second transistor. The source and drain of the first transistor are electrically connected to the second wiring. The gate of the first transistor is electrically connected to the first wiring, One of the sources and drains of the second transistor is electrically connected to the first light-emitting element. The source and drain of the second transistor are electrically connected to the third wiring. In a plan view, the first oxide semiconductor layer having the channel formation region of the first transistor has a region that overlaps with the second opening. The channel length direction of the first transistor is along the first direction, The channel length direction of the second transistor is along the direction of the second direction, The channel length of the second transistor is greater than the channel length of the first transistor. In a plan view, the first opening has a portion having a first width along the first direction, a portion having a second width along the first direction, and a portion having a third width along the first direction. The second width is smaller than the first width and smaller than the third width. In a plan view, the portion having the first width, the portion having the second width, and the portion having the third width are arranged in this order in the second direction. In a plan view, the region in which the first conductive layer, which functions as either the source electrode or the drain electrode of the second transistor, and the first electrode of the first light-emitting element are in contact with each other is aligned with the portion having the second width along the first direction, and does not overlap with the second oxide semiconductor layer having the channel-forming region of the second transistor. In a plan view, the second conductive layer having the function of the gate electrode of the second transistor has a first region having a fourth width along the first direction, a second region having a fifth width along the first direction, and a third region having a sixth width along the first direction. The fifth width is greater than the fourth width and greater than the sixth width. In a plan view, the first region, the second region, and the third region are arranged in this order in the second direction. The second region overlaps with the channel formation region of the second transistor. Light-emitting display device.

7. In any one of claims 4 to 6, In a plan view, the second oxide semiconductor layer has a region that does not overlap with the first aperture. Light-emitting display device.

8. In any one of claims 1 to 7, The partition wall has a region that covers the end of the first electrode of the first light-emitting element. Light-emitting display device.

9. In any one of claims 1 to 8, The first oxide semiconductor layer has a region that overlaps with the first electrode of the first light-emitting element. Light-emitting display device.

Images