Voltage monitoring circuit

Abstract

To provide a voltage monitoring circuit capable of determining a plurality of voltage states with a small circuit area.SOLUTION: The voltage monitoring circuit 100 determines which of a plurality of states divided by three or more voltage levels the input voltage Vmon to be monitored is included in. The first variable voltage source 104 generates a first threshold voltage Vth1. The second variable voltage source 108 generates a second threshold voltage Vth2. The first comparator 102 compares the voltage Vmon with the first threshold voltage Vth1, and generates a first detection signal DET1 indicating the comparison result. The second comparator 106 compares the voltage Vmon with the second threshold voltage Vth2, and generates a second detection signal DET2 indicating the comparison result. In accordance with the first detection signal DET1 and the second detection signal DET2, the controller 120 generates a state determination signal STATE indicating the state of the detection voltage Vmon, and controls the first variable voltage source 104 and the second variable voltage source 108.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a voltage monitoring circuit. [Background technology]

[0002] In semiconductor integrated circuits, voltage comparisons are performed using voltage comparators to detect overvoltage and undervoltage conditions in monitored voltages such as power supply voltages. For example, to determine whether the monitored voltage is in one of five states separated by four voltage levels, four voltage comparators are required.

[0003] Furthermore, if the output of the voltage comparator is processed as is, it becomes susceptible to noise and other influences, so the output of the voltage comparator may be delayed by a debounce timer. In this case, a debounce timer is required depending on the number of voltage comparators, which increases the circuit area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-71392

[0005] [overview] The present disclosure has been made in light of the above circumstances, and one of its exemplary purposes is to provide a voltage monitoring circuit that can determine a plurality of voltage states with a small circuit area.

[0006] A voltage monitoring circuit according to an embodiment of the present disclosure determines which of a plurality of states, separated by three or more voltage levels, a monitored input voltage falls within. The voltage monitoring circuit includes a first variable voltage source that generates a first threshold voltage, a second variable voltage source that generates a second threshold voltage, a first comparator that compares the input voltage with the first threshold voltage and generates a first detection signal indicative of the comparison result, a second comparator that compares the input voltage with the second threshold voltage and generates a second detection signal indicative of the comparison result, and a controller that generates a state determination signal indicative of the state of the input voltage in response to the first detection signal and the second detection signal, and controls the first variable voltage source and the second variable voltage source.

[0007] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a semiconductor integrated circuit including a voltage monitoring circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of voltage monitoring. [Figure 3] FIG. 3 is a block diagram of a voltage monitoring circuit according to a comparative technique. [Figure 4] FIG. 4 is a circuit block diagram of a voltage monitoring circuit according to an embodiment. [Figure 5] FIG. 5 is a diagram illustrating the threshold voltage control according to the first embodiment. [Figure 6] FIG. 6 is a diagram illustrating the threshold voltage control according to the second embodiment. [Figure 7] FIG. 7 is a block diagram of a voltage monitoring circuit according to the second embodiment. [Figure 8] FIG. 8 is a circuit diagram of a voltage monitoring circuit according to a third embodiment. [Figure 9] FIG. 9 is a diagram illustrating threshold voltage control according to the third embodiment. [Figure 10] FIG. 10 is a circuit diagram of a voltage monitoring circuit according to a fourth embodiment.

[0009] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] A voltage monitoring circuit according to one embodiment determines which of a plurality of states, separated by three or more voltage levels, a monitored input voltage falls within. The voltage monitoring circuit includes a first variable voltage source that generates a first threshold voltage, a second variable voltage source that generates a second threshold voltage, a first comparator that compares the input voltage with the first threshold voltage and generates a first detection signal indicative of the comparison result, a second comparator that compares the input voltage with the second threshold voltage and generates a second detection signal indicative of the comparison result, and a controller that generates a state determination signal indicative of the state of the input voltage in response to the first detection signal and the second detection signal, and controls the first variable voltage source and the second variable voltage source.

[0011] In a voltage monitoring circuit, the threshold voltages to be compared with the input voltage to be monitored are two on either side of the voltage to be monitored. Therefore, by providing two voltage comparison circuits and changing the threshold levels of the two voltage comparison circuits depending on the state of the input voltage, it is possible to detect transitions in the input voltage state. This configuration eliminates the need for a comparator for each threshold level, thereby reducing the circuit area.

[0012] In one embodiment, the controller may fix the first threshold voltage and change the second threshold voltage to cross the first threshold voltage when the first detection signal changes, and may fix the second threshold voltage and change the first threshold voltage to cross the second threshold voltage when the second detection signal changes.

[0013] In one embodiment, the number of the plurality of voltage levels is four, and they are called the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level in order from top to bottom. The controller is capable of switching between a first state in which the first threshold voltage is assigned the second voltage level and the second threshold voltage is assigned the third voltage level, a second state in which the first threshold voltage is assigned the second voltage level and the second threshold voltage is assigned the first voltage level, and a third state in which the first threshold voltage is assigned the fourth voltage level and the second threshold voltage is assigned the third voltage level. In the first state, the first comparing unit The first comparator may assert the first detection signal when the input voltage becomes lower than the first threshold voltage in the first state, or the second comparator may assert the second detection signal when the input voltage becomes higher than the second threshold voltage in the second state, or when the input voltage becomes lower than the second threshold voltage in the first state, and the controller may transition to the second state when the first detection signal is asserted in the first state, transition to the first state when the first detection signal is negated in the second state, transition to the third state when the second detection signal is asserted in the first state, and transition to the first state when the second detection signal is negated in the third state.

[0014] In one embodiment, the controller shifts the first threshold voltage after a predetermined time has elapsed since the transition of the first detection signal to provide hysteresis to the first comparison unit, and shifts the second threshold voltage after a predetermined time has elapsed since the transition of the second detection signal to provide hysteresis to the second comparison unit.

[0015] In one embodiment, the controller may update the determination of the input voltage after a predetermined time has elapsed since the transition of the first sensed signal and after a predetermined time has elapsed since the transition of the second sensed signal.

[0016] In one embodiment, the controller may include a first debounce timer that generates a first debounce signal that is asserted a predetermined time after a transition of the first detection signal, and a second debounce timer that generates a second debounce signal that is asserted a predetermined time after a transition of the second detection signal.

[0017] In one embodiment, the controller may update the determination of the input voltage in response to the first debounce signal and the second debounce signal.

[0018] In one embodiment, the controller may change the first threshold voltage and the second threshold voltage in conjunction with each other in the same direction.

[0019] In one embodiment, the controller may vary the first threshold voltage and the second threshold voltage in conjunction with the result of determining the state of the input voltage.

[0020] In one embodiment, the controller may include a state machine.

[0021] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0022] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0023] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0024] (Embodiment) 1 is a block diagram of a semiconductor integrated circuit 200 including a voltage monitoring circuit 100 according to an embodiment. The semiconductor integrated circuit 200 is, for example, a power management circuit (PMIC), and includes one or more power supply circuits 210.

[0025] The voltage monitoring circuit 100 monitors the internal voltage of the semiconductor integrated circuit 200 and determines the state of the voltage Vmon to be monitored. For example, the voltage Vmon to be monitored may be the input voltage Vin or the output voltage Vout of the power supply circuit 210, or may be an internal voltage of the power supply circuit 210, or a voltage generated by a circuit other than the power supply circuit 210.

[0026] 2 is a diagram illustrating an example of voltage monitoring. In this example, five states are determined according to the voltage level of the monitored voltage Vmon: overvoltage protection (OVP) state, overvoltage warning (OVW) state, normal state, undervoltage warning (UVW) state, and undervoltage protection (UVP) state.

[0027] The relationship between each state and the voltage range is as follows: Overvoltage protection (OVP) status OVP_Vth <Vmon Overvoltage warning (OVW) status OVW_Vth <Vmon<OVP_Vth Normal state UVW_Vth <Vmon<OVW_Vth Low voltage warning (UVW) state UVP_Vth <Vmon<UVW_Vth Undervoltage protection (UVP) status Vmon <UVP_Vth

[0028] That is, the voltage Vmon is compared with four threshold voltages OVP_Vth, OVW_Vth, UVW_Vth, and UVP_Vth. Each threshold may have hysteresis.

[0029] The OVP detection signal indicates the result of comparing the voltage Vmon with the threshold voltage OVP_Vth, and is asserted (for example, high) when Vmon>OVP_Vth.

[0030] The OVW detection signal indicates the result of comparison between the voltage Vmon and the threshold voltage OVW_Vth, and is asserted (for example, high) when Vmon>OVW_Vth.

[0031] The UVW detection signal indicates the result of comparing the voltage Vmon with the threshold voltage UVW_Vth. <UVW_Vthのときアサート(たとえばハイ)となる。

[0032] The UVP detection signal indicates the result of comparing the voltage Vmon with the threshold voltage UVP_Vth. <UVP_Vthのときアサート(たとえばハイ)となる。

[0033] When all detection signals are negated, it is in a normal state. When the OVP detection signal is asserted, it is in an overvoltage protection state (OVP). When the OVW detection signal is asserted and the OVP detection signal is negated, it is in an overvoltage warning state (OVW).

[0034] When the UVP detection signal is asserted, it is in the undervoltage protection (UVP) state. When the UVW detection signal is asserted and the UVP detection signal is negated, it is in the undervoltage warning (UVW) state.

[0035] Before describing the voltage monitoring circuit 100 according to the embodiment, a comparison technique will be described.

[0036] 3 is a block diagram of a voltage monitoring circuit 100R according to a comparative technique. The voltage monitoring circuit 100R includes four voltage comparators COMP1 to COMP4 and a logic circuit 110R.

[0037] The four voltage comparators COMP1 to COMP4 correspond to the four threshold voltages OVP_Vth, OVW_Vth, UVW_Vth, and UVP_Vth, and each comparator compares the voltage Vmon with the corresponding threshold voltage.

[0038] The logic circuit 110R determines the state of the voltage Vmon based on the detection signals OVP, OVW, UVW, and UVP that are outputs from the four comparators COMP1 to COMP4.

[0039] The logic circuit 110R includes interface circuits 112_1 to 112_4 and a determination unit 114.

[0040] The interface circuits 112_1 to 112_4 correspond to the four comparators COMP1 to COMP4. Each interface circuit 112_j (j=1, 2, 3, 4) receives a detection signal output from the corresponding comparator COMPj and synchronizes it with a clock signal. The interface circuit 112 may also include a debounce timer.

[0041] The determining unit 114 determines the states OVP, OVW, UVW, and UVP of the input voltage Vmon based on the detection signals processed by the interface circuits 112_1 to 112_4, and generates a state determination signal STATE indicating the determination result.

[0042] 3 requires a voltage comparator for each threshold voltage, resulting in a large circuit area. Furthermore, an interface circuit 112 is also required for each threshold voltage, resulting in a large circuit area. In particular, if the interface circuit 112 includes a debounce timer, the area becomes even larger.

[0043] 4 is a circuit block diagram of a voltage monitoring circuit 100 according to an embodiment. The voltage monitoring circuit 100 determines which of a plurality of states, separated by three or more (N) voltage levels, a voltage to be monitored (hereinafter referred to as an input voltage) Vmon belongs to.

[0044] The voltage monitoring circuit 100 includes a first comparing unit 102 , a first variable voltage source 104 , a second comparing unit 106 , a second variable voltage source 108 , and a controller 120 .

[0045] The first variable voltage source 104 generates a first threshold voltage Vth1 that can take on a plurality of voltage levels, and the second variable voltage source 108 generates a second threshold voltage Vth2 that can take on a plurality of voltage levels.

[0046] The first comparing unit 102 compares the input voltage Vmon with a first threshold voltage Vth1 and generates a first detection signal DET1 indicative of the comparison result. The second comparing unit 106 compares the input voltage Vmon with a second threshold voltage Vth2 and generates a second detection signal DET2 indicative of the comparison result.

[0047] The controller 120 generates a state determination signal STATE indicating the state of the input voltage Vmon in response to the first detection signal DET1 generated by the first comparing section 102 and the second detection signal DET2 generated by the second comparing section 106. The controller 120 also controls the first variable voltage source 104 and the second variable voltage source 108 based on the first detection signal DET1 and the second detection signal DET2 to switch the voltage levels of the first threshold voltage Vth1 and the second threshold voltage Vth2.

[0048] The above is the basic configuration of the voltage monitoring circuit 100. While the comparative technology requires N voltage comparators, this configuration uses two voltage comparison circuits while switching the threshold voltage, making it possible to determine four or more states. This allows the circuit area and power consumption of the voltage monitoring circuit 100 to be reduced compared to the comparative technology.

[0049] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 4 or that are derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0050] Several examples of controlling the threshold voltages of the two voltage comparators will be described below.

[0051] Example 1 5 is a diagram illustrating threshold voltage control according to the first embodiment. In the first embodiment, the number N of threshold levels is 4, and the voltage monitoring circuit 100 determines which of five states the input voltage Vmon is in. Note that the number of threshold levels N is not limited to 4, and may be 3 or more.

[0052] The relationship between each state and the voltage range is the same as that of the comparative technology in FIG. 3, and is as follows: Overvoltage protection (OVP) status OVP_Vth <Vmon Overvoltage warning (OVW) status OVW_Vth <Vmon<OVP_Vth Normal state UVW_Vth <Vmon<OVW_Vth Low voltage warning (UVW) state UVP_Vth <Vmon<UVW_Vth Undervoltage protection (UVP) status Vmon <UVP_Vth

[0053] The four threshold levels OVP_Vth, OVW_Vth, UVW_Vth, and UVP_Vth are also referred to as a first voltage level, a second voltage level, a third voltage level, and a fourth level, in order from highest to lowest.

[0054] When the first detection signal DET1 changes, the controller 120 fixes the first threshold voltage Vth1 and changes the second threshold voltage Vth2 so as to cross the first threshold voltage Vth1. When the second detection signal DET2 changes, the controller 120 fixes the second threshold voltage Vth2 and changes the first threshold voltage Vth1 so as to cross the second threshold voltage Vth2.

[0055] The controller 120 switches the threshold voltage setting between three states, a first state φ1 to a third state φ3.

[0056] First state φ1 First threshold voltage Vth1=Second voltage level OVW_Vth Second threshold voltage Vth2=Third voltage level UVW_Vth

[0057] Second state φ2 First threshold voltage Vth1=Second voltage level OVW_Vth Second threshold voltage Vth2=First voltage level OVP_Vth

[0058] Third state φ3 First threshold voltage Vth1=Fourth voltage level UVP_Vth Second threshold voltage Vth2=Third voltage level UVW_Vth

[0059] The first comparing unit 102 asserts (e.g., outputs high) the first detection signal DET1 when the input voltage Vmon becomes higher than the first threshold voltage Vth1 (OVW_Vth) in the first state φ1, or when the input voltage Vmon becomes lower than the first threshold voltage Vth1 (UVP_Vth) in the third state φ3.

[0060] The second comparing unit 106 asserts the second detection signal DET2 (e.g., high output) when the input voltage Vmon becomes higher than the second threshold voltage Vth2 (OVP_Vth) in the second state φ2, or when the input voltage Vmon becomes lower than the second threshold voltage Vth2 (UVW_Vth) in the first state φ1.

[0061] When the first detection signal DET1 is asserted in the first state φ1, the controller 120 switches to the second state φ2.

[0062] When the first detection signal DET1 is negated (outputs low) in the second state φ2, the controller 120 switches to the first state φ1.

[0063] When the second detection signal DET2 is asserted in the first state φ1, the controller 120 switches to the third state φ3.

[0064] When the second detection signal DET2 is negated in the third state φ3, the controller 120 switches to the first state φ1.

[0065] According to the control of Example 1, the threshold voltages Vth1 and Vth2 are appropriately controlled in accordance with the first detection signal DET1 and the second detection signal DET2, and the state of the input voltage Vmon can be determined based on the first detection signal DET1 and the second detection signal DET2.

[0066] Example 2 6 is a diagram illustrating threshold voltage control according to Example 2. In Example 2, the number N of threshold levels is also 4, and the voltage monitoring circuit 100 determines which of five states the input voltage Vmon is in.

[0067] In the second embodiment, hysteresis is provided to each of the first threshold voltage Vth1 and the second threshold voltage Vth2.

[0068] The controller 120 shifts the first threshold voltage Vth1 by the hysteresis width Vhys after a predetermined time τd has elapsed since the transition of the first detection signal DET1. Similarly, the controller 120 shifts the second threshold voltage Vth2 by the hysteresis width Vhys after a predetermined time τd has elapsed since the transition of the second detection signal DET2. This sets hysteresis in each of the first comparing unit 102 and the second comparing unit 106. The hysteresis width Vhys may differ for each voltage level.

[0069] Furthermore, the controller 120 updates the determination result of the state of the input voltage Vmon after a predetermined time τd has elapsed since the transition of the first detection signal DET1 and the second detection signal DET2.

[0070] 7 is a block diagram of a voltage monitoring circuit 100A according to Example 2. The voltage monitoring circuit 100A includes a first comparing unit 102, a first variable voltage source 104, a second comparing unit 106, a second variable voltage source 108, and a controller 120A.

[0071] The first variable voltage source 104 is configured to be able to select the first threshold voltage Vth1 from two voltage levels: the second voltage level OVW_Vth and the fourth voltage level UVP_Vth. As described above, the second voltage level OVW_Vth and the fourth voltage level UVP_Vth have hysteresis, and therefore the voltage levels OVW_Vth and UVP_Vth can each take two voltage levels separated by a hysteresis width Vhys.

[0072] The first variable voltage source 104 includes a digitally controllable voltage source 105 and multiplexers MUX1 to MUX3. The voltage source 105 generates a first threshold voltage Vth1 according to a first control code VC1. The voltage source 105 may be a digital potentiometer that divides a reference voltage at a voltage division ratio according to the control code VC1. Alternatively, the voltage source 105 may be a D / A converter.

[0073] The first control code VC1 is generated by multiplexers MUX1 to MUX3. The multiplexer MUX1 selects one of two codes OVW_Vth and UVP_Vth in response to a first selection signal SEL1 generated by the controller 120A.

[0074] The multiplexer MUX2 selects one of two codes OVW_Vthh and OVW_Vthl in response to an OVW_DET signal that is asserted (1) in an overvoltage warning (OVW) state. The two codes OVW_Vthh and OVW_Vthl have values ​​separated by a hysteresis width Vhys.

[0075] The multiplexer MUX3 selects one of two codes UVP_Vthh and UVP_Vthl in response to a UVP_DET signal that is asserted (1) in an undervoltage protection (UVP) state. The two codes UVP_Vthh and UVP_Vthl have values ​​separated by a hysteresis width Vhys.

[0076] The second variable voltage source 108 is configured to be able to select the second threshold voltage Vth2 from two levels: a first voltage level OVP_Vth and a third voltage level UVW_Vth. As described above, the first voltage level OVP_Vth and the third voltage level UVW_Vth have hysteresis, and therefore the voltage levels OVP_Vth and UVW_Vth can each take on two voltage levels separated by a hysteresis width Vhys.

[0077] The second variable voltage source 108 has the same configuration as the first variable voltage source 104, and includes a digitally controllable voltage source 109 and multiplexers MUX4 to MUX6. The voltage source 109 generates a second threshold voltage Vth2 according to a second control code VC2.

[0078] The second control code VC2 is generated by multiplexers MUX4 to MUX6. The multiplexer MUX4 selects one of the two codes OVP_Vth and UVW_Vth in response to a second selection signal SEL2 generated by the controller 120A.

[0079] A multiplexer MUX5 selects one of two codes, OVP_Vthh and OVP_Vthl, in response to an OVP_DET signal that is asserted (1) in an overvoltage protection (OVP) state. The two codes, OVP_Vthh and OVP_Vthl, have values ​​separated by a hysteresis width, Vhys.

[0080] The multiplexer MUX6 selects one of two codes UVW_Vthh and UVW_Vthl in response to the UVW_DET signal, which is asserted (1) in the undervoltage warning (UVW) state. The two codes UVW_Vthh and UVW_Vthl have values ​​separated by a hysteresis width Vhys.

[0081] The controller 120A is a digital logic circuit that performs signal processing in synchronization with a clock signal CLK, and includes a first interface circuit 122, a second interface circuit 124, a first debounce timer 126, a second debounce timer 128, a first threshold control unit 130, a second threshold control unit 132, and a judgment unit 134.

[0082] The controller 120A generates a determination signal STATE indicating the state of the input voltage Vmon based on the first detection signal DET1 and the second detection signal DET2. The state determination signal STATE includes four detection signals: OVP_DET, OVW_DET, UVW_DET, and UVP_DET. The OVP_DET signal is asserted in the OVP state, and the OVW_DET signal is asserted in either the OVW state or the OVP state. The UVP_DET signal is asserted in the UVP state, and the UVW_DET signal is asserted in either the UVW state or the UVP state.

[0083] Furthermore, the controller 120A generates a first selection signal SEL1 that specifies the first threshold voltage Vth1 and a second selection signal SEL2 that specifies the second threshold voltage Vth2 based on the first detection signal DET1 and the second detection signal DET2.

[0084] The first interface circuit 122 retimes the first detection signal DET1 using the clock signal CLK, detects a transition of the first detection signal DET1, and generates a first transition detection pulse P1 indicating the occurrence of a transition.

[0085] The second interface circuit 124 retimes the second detection signal DET2 using the clock signal CLK, detects a transition of the second detection signal DET2, and generates a second transition detection pulse P2 indicating the occurrence of a transition.

[0086] The first debounce timer 126 asserts an output signal (first debounce signal) S1 after a predetermined time τd has elapsed since the generation of the first transition detection pulse P1. The first debounce timer 126 may include a counter circuit that starts a counting operation when triggered by the generation of the first transition detection pulse P1, and a comparator that compares the count value of the counter circuit with a threshold value and asserts the first debounce signal S1 when the count value reaches the threshold value.

[0087] The second debounce timer 128 asserts an output signal (second debounce signal) S2 after a predetermined time τd has elapsed since the second transition detection pulse P2 was generated. The second debounce timer 128 can be configured in the same manner as the first debounce timer 126.

[0088] The second transition detection pulse P2 and the second selection signal SEL2 are supplied to the first threshold control unit 130. When the second transition detection pulse P2 is generated while the second selection signal SEL2 is 0, the first threshold control unit 130 inverts the first selection signal SEL1.

[0089] The first transition detection pulse P1 and the first selection signal SEL1 are supplied to the second threshold control unit 132. When the first transition detection pulse P1 is generated while the first selection signal SEL1 is 1, the second threshold control unit 132 inverts the second selection signal SEL2.

[0090] The determination unit 134 generates a state determination signal STATE indicating the state of the input voltage Vmon based on the first debounce signal S1, the second debounce signal S2, the first selection signal SEL1, and the second selection signal SEL2.

[0091] The above is the configuration of the voltage monitoring circuit 100 A. This voltage monitoring circuit 100 A can realize the control of the threshold voltage described with reference to FIG.

[0092] Example 3 Fig. 8 is a circuit diagram of a voltage monitoring circuit 100B according to the third embodiment. Fig. 9 is a diagram illustrating threshold voltage control according to the third embodiment.

[0093] In the third embodiment, the number N of threshold levels is also four, and the voltage monitoring circuit 100 determines which of the five states the input voltage Vmon is in.

[0094] In the third embodiment, the controller 120B changes the first threshold voltage Vth1 and the second threshold voltage Vth2 in the same direction in conjunction with the result of determining the state of the input voltage Vmon.

[0095] The threshold voltages Vth1 and Vth2 in each state are controlled as follows. Overvoltage protection (OVP) status, overvoltage warning (OVW) status Vth1=OVW_Vth Vth2=OVP_Vth

[0096] Normal state Vth1=UVW_Vth Vth2=OVW_Vth

[0097] Low voltage warning (UVW) state, low voltage protection (UVP) state Vth1=UVP_Vth Vth2=UVW_Vth

[0098] The controller 120B may perform hysteresis control on each of the threshold voltages OVP_Vth, OVW_Vth, UVW_Vth, and UVP_Vth. In this case, the threshold voltages Vth1 and Vth2 in each state correspond to each other as follows:

[0099] Overvoltage protection (OVP) status Vth1=OVW_Vthl Vth2=OVP_Vthl

[0100] Overvoltage warning (OVW) condition Vth1=OVW_Vthl Vth2=OVP_Vthh

[0101] Normal state Vth1=UVW_Vthl Vth2=OVW_Vthh

[0102] Low Voltage Warning (UVW) condition Vth1=UVP_Vthl Vth2=UVW_Vthh

[0103] Undervoltage Protection (UVP) status Vth1=UVP_Vthh Vth2=UVW_Vthh

[0104] The first variable voltage source 104 includes a digitally controllable voltage source 105 and a multiplexer MUX7. The multiplexer MUX7 selects one of a plurality of control codes according to a selection signal SEL1. The selection signal SEL1 indicates whether the current input voltage Vmon is OVP, OVW, NORMAL, UVW, or UVP.

[0105] The second variable voltage source 108 has a configuration similar to that of the first variable voltage source 104, and includes a voltage source 109 and a multiplexer MUX8. The multiplexer MUX8 selects one of a plurality of control codes according to a selection signal SEL2. The selection signal SEL2 indicates whether the current input voltage Vmon is OVP, OVW, NORMAL, UVW, or UVP.

[0106] The controller 120B includes a first interface circuit 122, a second interface circuit 124, a first debounce timer 126, a second debounce timer 128, and a determination unit 134B.

[0107] The determination unit 134B includes a state machine 136. The state machine 136 has five states: OVP, OVW, NORMAL, UVW, and UVP, and transitions between states in response to the first debounce signal S1 and the second debounce signal S2.

[0108] The determination unit 134B outputs a state determination signal STATE according to the state of the state machine 136. The determination unit 134B also generates selection signals SEL1 and SEL2 according to the state of the state machine 136.

[0109] The above is the configuration of the voltage monitoring circuit 100B.

[0110] According to the third embodiment, four or more states can be determined by using the two comparators 102 and 106 while switching between the threshold voltages Vth1 and Vth2. This reduces the circuit area and power consumption of the voltage monitoring circuit 100A compared to the comparative technology.

[0111] Example 4 10 is a circuit diagram of a voltage monitoring circuit 100C according to Example 4. In Example 4, the number N of threshold levels is 2, and the voltage monitoring circuit 100C determines which of three states the input voltage Vmon is in.

[0112] The relationship between each state and the voltage range is the same as in the comparative technology, and is as follows: Overvoltage protection (OVP) status OVP_Vth <Vmon Normal state UVP_Vth <Vmon<OVP_Vth Undervoltage protection (UVP) status Vmon <UVP_Vth

[0113] The voltage monitoring circuit 100C includes a first voltage comparator COMP1, a second comparator COMP2, and a controller 120C. The controller 120C includes a debounce timer 140 and a determination unit 134C. The debounce timer 140 is shared by the two comparators COMP1 and COMP2, and asserts an output S0 after a predetermined time has elapsed when one of the detection signals DET1 and DET2 transitions. The determination unit 134C generates a state determination signal STATE based on the detection signals DET1 and DET2 and the output S0 of the debounce timer 140.

[0114] According to this configuration, the circuit area can be reduced by sharing the debounce timer.

[0115] Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0116] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0117] (Item 1) A voltage monitoring circuit that determines whether an input voltage to be monitored is in one of a plurality of states separated by three or more voltage levels, a first variable voltage source that generates a first threshold voltage; a second variable voltage source that generates a second threshold voltage; a first comparing unit that compares the input voltage with the first threshold voltage and generates a first detection signal indicative of a comparison result; a second comparing unit that compares the input voltage with the second threshold voltage and generates a second detection signal indicative of the comparison result; a controller that generates a state determination signal indicating a state of the input voltage in response to the first detection signal and the second detection signal, and controls the first variable voltage source and the second variable voltage source; A voltage monitoring circuit comprising:

[0118] (Item 2) The controller When the first detection signal changes, the first threshold voltage is fixed, and the second threshold voltage is changed so as to cross the first threshold voltage; 2. The voltage monitoring circuit according to item 1, wherein when the second detection signal changes, the second threshold voltage is fixed and the first threshold voltage is changed so as to cross the second threshold voltage.

[0119] (Item 3) The number of the plurality of voltage levels is four, and when the voltage levels are called the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level from top to bottom, The controller a first state that assigns the second voltage level to the first threshold voltage and the third voltage level to the second threshold voltage; a second state that assigns the second voltage level to the first threshold voltage and the first voltage level to the second threshold voltage; a third state in which the first threshold voltage is assigned the fourth voltage level and the second threshold voltage is assigned the third voltage level; It is possible to switch between the first comparing unit asserts the first detection signal when the input voltage becomes higher than the first threshold voltage in the first state or when the input voltage becomes lower than the first threshold voltage in the third state; the second comparing unit asserts the second detection signal when the input voltage becomes higher than the second threshold voltage in the second state or when the input voltage becomes lower than the second threshold voltage in the first state; The controller When the first detection signal is asserted in the first state, the transition to the second state occurs; When the first detection signal is negated in the second state, the transition to the first state is made; When the second detection signal is asserted in the first state, the state transitions to the third state; 3. The voltage monitoring circuit according to claim 1, wherein when the second detection signal is negated in the third state, the voltage monitoring circuit transitions to the first state.

[0120] (Item 4) the controller shifts the first threshold voltage to provide hysteresis to the first comparison unit after a predetermined time has elapsed since the transition of the first detection signal; 4. The voltage monitoring circuit according to any one of items 1 to 3, wherein the second threshold voltage is shifted to provide hysteresis to the second comparing unit after the predetermined time has elapsed since the transition of the second detection signal.

[0121] (Item 5) 5. The voltage monitoring circuit according to item 4, wherein the controller updates the judgment result of the input voltage after the predetermined time has elapsed since the transition of the first detection signal and after the predetermined time has elapsed since the transition of the second detection signal.

[0122] (Item 6) The controller a first debounce timer that generates a first debounce signal that is asserted after the predetermined time has elapsed since the transition of the first detection signal; a second debounce timer that generates a second debounce signal that is asserted after the predetermined time has elapsed since the transition of the second detection signal; 5. The voltage monitoring circuit of item 4, comprising:

[0123] (Item 7) 7. The voltage monitoring circuit of claim 6, wherein the controller updates the input voltage determination result in response to the first debounce signal and the second debounce signal.

[0124] (Item 8) 2. The voltage monitoring circuit of claim 1, wherein the controller changes the first threshold voltage and the second threshold voltage in a coordinated manner in the same direction.

[0125] (Item 9) 6. The voltage monitoring circuit according to item 5, wherein the controller changes the first threshold voltage and the second threshold voltage in conjunction with the determination result of the state of the input voltage.

[0126] (Item 10) Item 9. The voltage monitoring circuit of item 8, wherein the controller includes a state machine. [Explanation of symbols]

[0127] 100 Voltage Monitoring Circuit 102 First comparison section 104 First variable voltage source 105 Voltage Source 106 Second Comparison Section 108 Second variable voltage source 109 Voltage Source 110R Logic Circuit 112 Interface Circuit 114 Judgment section 120 Controller 122 First interface circuit 124 Second Interface Circuit 126 1st Debounce Timer 128 Second Debounce Timer 130 First threshold control section 132 Second threshold control section 134 Judgment section 136 State Machine 140 Debounce Timer 200 Semiconductor Integrated Circuits 210 Power supply circuit

Claims

1. 1. A voltage monitoring circuit that determines whether an input voltage to be monitored is in one of a plurality of states separated by three or more voltage levels, a first variable voltage source that generates a first threshold voltage; a second variable voltage source that generates a second threshold voltage; a first comparison unit that compares the input voltage with the first threshold voltage and generates a first detection signal indicative of a comparison result; a second comparison unit that compares the input voltage with the second threshold voltage and generates a second detection signal indicative of a comparison result; a controller that generates a state determination signal indicating a state of the input voltage in response to the first detection signal and the second detection signal, and controls the first variable voltage source and the second variable voltage source; A voltage monitoring circuit comprising:

2. The controller When the first detection signal changes, the first threshold voltage is fixed, and the second threshold voltage is changed so as to cross the first threshold voltage; 2. The voltage monitoring circuit according to claim 1, wherein when said second detection signal changes, said second threshold voltage is fixed, and said first threshold voltage is changed so as to cross said second threshold voltage.

3. The number of the plurality of voltage levels is four, and when the voltage levels are called the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level from top to bottom, The controller a first state that assigns the second voltage level to the first threshold voltage and the third voltage level to the second threshold voltage; a second state that assigns the second voltage level to the first threshold voltage and the first voltage level to the second threshold voltage; a third state that assigns the fourth voltage level to the first threshold voltage and the third voltage level to the second threshold voltage; It is possible to switch between the first comparing unit asserts the first detection signal when the input voltage becomes higher than the first threshold voltage in the first state or when the input voltage becomes lower than the first threshold voltage in the third state; the second comparing unit asserts the second detection signal when the input voltage becomes higher than the second threshold voltage in the second state or when the input voltage becomes lower than the second threshold voltage in the first state; The controller When the first detection signal is asserted in the first state, the state transitions to the second state; When the first detection signal is negated in the second state, the state transitions to the first state; When the second detection signal is asserted in the first state, the state transitions to the third state; 3. The voltage monitoring circuit according to claim 1, wherein when the second detection signal is negated in the third state, the voltage monitoring circuit transitions to the first state.

4. the controller shifts the first threshold voltage to provide hysteresis to the first comparison unit after a predetermined time has elapsed since the transition of the first detection signal; 3. The voltage monitoring circuit according to claim 1, wherein the second threshold voltage is shifted to provide hysteresis to the second comparing section after the predetermined time has elapsed since the transition of the second detection signal.

5. 5. The voltage monitoring circuit according to claim 4, wherein the controller updates the determination result of the input voltage after the predetermined time has elapsed since the transition of the first detection signal and after the predetermined time has elapsed since the transition of the second detection signal.

6. The controller a first debounce timer that generates a first debounce signal that is asserted after the predetermined time has elapsed since the transition of the first detection signal; a second debounce timer that generates a second debounce signal that is asserted after the predetermined time has elapsed since the transition of the second detection signal; 5. The voltage monitoring circuit of claim 4, comprising:

7. 7. The voltage monitoring circuit of claim 6, wherein the controller updates the input voltage determination result in response to the first debounce signal and the second debounce signal.

8. 2. The voltage monitoring circuit according to claim 1, wherein said controller changes said first threshold voltage and said second threshold voltage in a coordinated manner in the same direction.

9. 6. The voltage monitoring circuit according to claim 5, wherein the controller changes the first threshold voltage and the second threshold voltage in conjunction with a result of determining the state of the input voltage.

10. The voltage monitoring circuit of claim 8 , wherein the controller includes a state machine.

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