Acoustic wave device and wafer manufacturing method

Abstract

In an acoustic wave device, the amount of material used for forming a high acoustic velocity layer can be appropriately minimized, and the support substrate and the high acoustic velocity layer can be integrated without any problems. [Solution] The device mainly comprises a device chip 2 having a high acoustic velocity layer 4 formed on a support substrate 3 and a piezoelectric layer 5 formed on the high acoustic velocity layer 4, with a circuit pattern 6 formed on the piezoelectric layer 5, including a resonator 7 that excites a predetermined surface wave. The high acoustic velocity layer 4 is configured to have a bulk wave acoustic velocity faster than the bulk wave acoustic velocity of the piezoelectric layer 5, and has a thickness that is at least twice the wavelength of the surface wave. The thermal expansion coefficient of the glass that makes up the support substrate 3 from the softening point temperature to room temperature is set to be within ±3% of the thermal expansion coefficient of the material that makes up the high acoustic velocity layer 4.

Description

[Technical Field]

[0001] The present invention relates to an acoustic wave device suitable for use as a frequency filter in mobile communication devices and the like, and to an improvement in a method for manufacturing a wafer thereof. [Background technology]

[0002] Patent Document 1 discloses an acoustic wave device having a structure in which a spinel substrate serving as a high acoustic velocity layer is formed on a silicon substrate serving as a support substrate, and a piezoelectric layer is formed on this spinel substrate. In this case, the SH waves are reflected by the spinel substrate and confined in the piezoelectric layer, thereby imparting desired characteristics to the acoustic wave device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-216414 Summary of the Invention [Problem to be solved by the invention]

[0004] The main problem that this invention aims to solve is to provide an acoustic wave device that is mainly composed of a device chip in which a high acoustic velocity layer is formed on a support substrate and a piezoelectric layer is formed on this high acoustic velocity layer, and that has a structure that allows the support substrate and the high acoustic velocity layer to be integrated without any problems while appropriately minimizing the amount of material used to make the relatively expensive high acoustic velocity layer. [Means for solving the problem]

[0005] In order to achieve the above object, from a first viewpoint, the present invention provides an acoustic wave device that is mainly composed of a device chip having a glass support substrate, a high acoustic velocity layer formed on the support substrate, and a piezoelectric layer formed on the high acoustic velocity layer, and that has a circuit pattern formed on the piezoelectric layer of the device chip, the circuit pattern including a resonator that excites a predetermined surface wave, the high acoustic velocity layer is configured to have a bulk wave acoustic velocity faster than the bulk wave acoustic velocity of the piezoelectric layer, and has a thickness that is at least twice the wavelength of the surface wave; Moreover, the thermal expansion coefficient of the glass from the softening point temperature to room temperature is set to be within a range of ±3% of the thermal expansion coefficient of the material constituting the high sound velocity layer.

[0006] In one embodiment of the first aspect of the invention, the high sound velocity layer is made of spinel.

[0007] In order to achieve the above object, from a second aspect, the present invention provides a wafer manufacturing method, comprising the steps of: A method for manufacturing a wafer having a base plate portion that serves as the support substrate, a middle layer plate portion that serves as the high acoustic velocity layer, and a surface layer plate portion that serves as the piezoelectric layer, a cutting step of cutting the middle layer plate portion from an ingot made of a material constituting the high sonic velocity layer; a bonding step of bonding the base plate portion and the middle plate portion together, In the bonding step, the base plate portion is heated to a softening point temperature, and then the middle layer plate portion is superimposed on the base plate portion and pressed against the base plate portion.

[0008] In one embodiment of the invention according to the second aspect, the surface roughness Ra of the intermediate plate portion on the side to be bonded to the base plate portion is set to 0.5 to 5 μm.

[0009] In order to achieve the above object, from a third viewpoint, the present invention provides an acoustic wave device that is mainly composed of a device chip having a glass support substrate, a first high acoustic velocity layer formed on one surface of the support substrate, a piezoelectric layer formed on the first high acoustic velocity layer, and a second high acoustic velocity layer formed on the other surface of the support substrate, and that has a circuit pattern formed on the piezoelectric layer of the device chip, the circuit pattern including a resonator that excites a predetermined surface wave, The first high acoustic velocity layer and the second high acoustic velocity layer are each made of the same material having a bulk wave acoustic velocity faster than the bulk wave acoustic velocity of the piezoelectric layer, The surface wave is configured to have the same thickness that is at least twice the wavelength of the surface wave, Furthermore, the thermal expansion coefficient of the glass from the softening point temperature to room temperature is set to be within a range of ±6% of the thermal expansion coefficient of the material constituting the first high acoustic velocity layer and the second high acoustic velocity layer.

[0010] In one embodiment of the invention according to the third aspect, the first high sonic velocity layer and the second high sonic velocity layer are made of spinel.

[0011] In order to achieve the above object, from a fourth aspect, the present invention provides a wafer manufacturing method, comprising: a wafer to be the device chip constituting the acoustic wave device according to the third aspect, the wafer comprising: A method for manufacturing a wafer having a base plate portion that becomes the support substrate, a first intermediate plate portion that becomes the first high acoustic velocity layer, a second intermediate plate portion that becomes the second high acoustic velocity layer, and a surface plate portion that becomes the piezoelectric layer, a cutting step of cutting the first intermediate layer plate portion and the second high sonic velocity layer from an ingot made of a material constituting the first high sonic velocity layer and the second high sonic velocity layer; a bonding step of bonding the second intermediate plate portion to one surface of the base plate portion and bonding the second intermediate plate portion to the other surface of the base plate, In the bonding process, the base plate portion is heated to its softening point temperature, and then the three portions are overlapped and pressed together so that the base plate portion is positioned between the first intermediate layer plate portion and the second intermediate layer plate portion.

[0012] In one embodiment of the invention according to the fourth aspect, the surface roughness Ra of the intermediate plate portion on the side to be bonded to the base plate portion is set to 0.5 to 5 μm. [Effects of the Invention]

[0013] According to this invention, in an acoustic wave device mainly composed of a device chip in which the high acoustic velocity layer (first high acoustic velocity layer in the inventions relating to the third and fourth aspects) is formed on the support substrate and a piezoelectric layer is formed on this high acoustic velocity layer (first high acoustic velocity layer in the inventions relating to the third and fourth aspects), it is possible to provide a structure in which the support substrate and the high acoustic velocity layer (first high acoustic velocity layer and second high acoustic velocity layer in the inventions relating to the third and fourth aspects) can be integrated without any problems while appropriately minimizing the amount of material used to form the relatively expensive high acoustic velocity layer (first high acoustic velocity layer and second high acoustic velocity layer in the inventions relating to the third and fourth aspects). [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view of an acoustic wave device according to a first example. [Figure 2] FIG. 2 is a diagram showing an example of a configuration of a resonator formed on the functional surface of a device chip that constitutes the acoustic wave device. [Figure 3] FIG. 3 is a configuration diagram showing an example of a circuit formed on a device chip that constitutes the acoustic wave device. [Figure 4] FIG. 4 is a cross-sectional view of an acoustic wave device according to a second example. [Figure 5] FIG. 5 is a cross-sectional view showing one step in the manufacturing process of a wafer that becomes the device chips that make up the first and second examples. [Figure 6]FIG. 6 is a cross-sectional view showing a step in the manufacturing process of wafers that will become device chips constituting the first and second examples, which is the next step after FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a step in the manufacturing process of wafers that will become device chips constituting the first and second examples, which is the next step after FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a step in the manufacturing process of wafers that will become device chips constituting the first and second examples, which is the next step after FIG. [Figure 9] FIG. 9 is a cross-sectional view showing a step in the manufacturing process of wafers that will become device chips constituting the first and second examples, which is the step that follows that of FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a step in the manufacturing process of wafers that will become device chips constituting the first and second examples, which is the next step after FIG. [Figure 11] FIG. 11 is a cross-sectional view of a wafer that will become the device chips constituting the first and second examples, which will be the next step after that shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view showing the state in which a circuit pattern is formed on the wafer of FIG. [Figure 13] FIG. 13 is a cross-sectional view showing the wafer of FIG. 12 on which the circuit pattern is formed, diced into individual pieces. [Figure 14] FIG. 14 is a cross-sectional view of an acoustic wave device according to a third example. [Figure 15] FIG. 15 is a cross-sectional view of an acoustic wave device according to a fourth example. [Figure 16] FIG. 16 is a cross-sectional view showing one step in the manufacturing process of a wafer that becomes the device chips that constitute the third and fourth examples. [Figure 17] FIG. 17 is a cross-sectional view showing a step in the manufacturing process of wafers that will become device chips constituting the third and fourth examples, which is the step that follows that of FIG. [Figure 18]FIG. 18 is a cross-sectional structural view showing one step in the manufacturing process of wafers that will become device chips constituting the third and fourth examples, which is the next step after FIG. [Figure 19] FIG. 19 is a cross-sectional structural view showing one step in the manufacturing process of wafers that will become device chips constituting the third and fourth examples, which is the next step after FIG. [Figure 20] FIG. 20 is a cross-sectional structural view showing one step in the manufacturing process of wafers that will become device chips constituting the third and fourth examples, which is the next step after FIG. [Figure 21] FIG. 21 is a cross-sectional view showing a step in the manufacturing process of wafers that will become device chips constituting the third and fourth examples, which is the next step after that shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view of a wafer that will become the device chips that make up the third and fourth examples. [Figure 23] FIG. 23 is a cross-sectional view showing the state in which a circuit pattern is formed on the wafer of FIG. [Figure 24] FIG. 24 is a cross-sectional view showing the wafer of FIG. 22 on which the circuit pattern is formed, diced into individual pieces. DETAILED DESCRIPTION OF THE INVENTION

[0015] 1 to 24, exemplary embodiments of the present invention will be described. An acoustic wave device 1 according to this embodiment is suitable for use as a frequency filter in a mobile communication device or the like.

[0016] (Example 1) FIG. 1 shows a first example of such an acoustic wave device 1. As shown in FIG. The acoustic wave device 1 of the first example is mainly composed of a device chip 2. The device chip 2 includes a support substrate 3, a high acoustic velocity layer 4, and a piezoelectric layer 5. The device chip 2 has a flat hexahedral shape with a functional surface 2a formed from the surface of the piezoelectric layer 5, a back surface 2b opposite to the functional surface 2a, and four side surfaces 2c extending between the functional surface 2a and the back surface 2b. In the first example, the back surface 2b is formed from the surface of the support substrate 3 opposite to the side on which the high acoustic velocity layer 4 is formed.

[0017] The support substrate 3 is made of glass. The high acoustic velocity layer 4 is formed on the support substrate 3. The piezoelectric layer 5 is formed on the high acoustic velocity layer 4. A circuit pattern 6 including a resonator that excites a predetermined surface wave (SH wave) is formed on the piezoelectric layer 5 (on the functional surface 2a).

[0018] The circuit pattern 6 includes a plurality of resonators 7, a plurality of bump receiving portions 8, inter-resonator wiring (not shown) connecting the resonators 7 to each other, and external connection wiring (not shown) connecting the resonators 7 to the bump receiving portions 8. The circuit pattern 6 is typically formed on the piezoelectric layer 5 using a conductive metal film formed by photolithography.

[0019] The first example is an acoustic wave device 1 with a CSP (Chip Size Package) structure. In Fig. 1, reference numeral 9 denotes a package substrate, reference numeral 9a denotes a mounting surface of the package substrate 9, reference numeral 9b denotes a pad on the package substrate 9 side, reference numeral 9c denotes an external output pad formed on the back surface of the package substrate 9 opposite the mounting surface 9a, reference numeral 10 denotes a sealing resin, reference numeral 11 denotes a bump, and reference numeral 12 denotes an internal space. The device chip 2 is mounted on the package substrate 9 with the functional surface 2 a facing the mounting surface of the package substrate 9 . By welding the bumps 11 formed on the bump receiving portions 8 to the pads 9b, the circuit on the device chip 2 side and the circuit on the package substrate 9 side are electrically connected. Between the functional surface 2a and the mounting surface 9a, a gap is formed that is equal to the thickness of the bump receiving portion 8, the bump 11, and the pad 9b. The sealing resin 10 is made of insulating resin and covers the entire back surface 2b of the device chip 2 opposite the functional surface 2a and the side surface 2c of the device chip 2, and also extends partly between the functional surface 2a and the mounting surface 9a directly below the side surface 2c, thereby forming the internal space 12.

[0020] The high acoustic velocity layer 4 is configured to have a bulk wave acoustic velocity faster than the bulk wave acoustic velocity of the piezoelectric layer 5, and has a thickness that is at least twice the wavelength of the surface wave. For example, when the wavelength of the surface wave is 4 μm, the thickness of the high acoustic velocity layer 4 is set to 8 μm or more. The high acoustic velocity layer 4 is preferably made of spinel.

[0021] On the other hand, the support substrate 3 is made of glass whose thermal expansion coefficient from the softening point temperature of the glass to room temperature is within ±3% of the thermal expansion coefficient of the material constituting the high acoustic velocity layer 4. Typically, when the high sound velocity layer 4 is made of spinel, the thermal expansion coefficient of spinel is 7.4×10 -6 / K, the glass is typically made of borosilicate glass, phosphosilicate glass, or borophosphosilicate glass (BPSG), and its thermal expansion coefficient is 7.2 × 10 -6 / K to 7.6×10 -6 Make it so that it is / K. The thermal expansion coefficient can be adjusted by adjusting the boron (B) content in the borosilicate glass, the phosphorus (P) content in the phosphosilicate glass, and the boron and phosphorus contents in the borophosphosilicate glass.

[0022] The surface of the high acoustic velocity layer 4 that comes into contact with the support substrate 3 (the bonding side, which will be described later) is a rough surface r with a surface roughness Ra of 0.5 to 5 μm. The rough surface r is formed by forming countless recesses and countless protrusions on the surface of the high sound velocity layer 4 so that the protrusions are located substantially between the recesses and the recesses are located between the protrusions. As shown in FIG. 1, the constituent material of the support substrate 3 fills the recesses of the rough surface r without leaving any gaps, and the protrusions of the rough surface r bite into the support substrate 3.

[0023] If the thickness of the high acoustic velocity layer 4 is at least twice the wavelength of the surface wave, it is recognized that the surface wave can be reflected and confined within the piezoelectric layer 5. This makes it possible to impart desired characteristics to the acoustic wave device 1. Furthermore, by making the high acoustic velocity layer 4 have the above-mentioned minimum thickness and supporting the high acoustic velocity layer 4 having such a thickness by the support substrate 3, it is possible to minimize the amount of material used to make the high acoustic velocity layer 4, which is relatively expensive among the materials making up the device chip 2, while ensuring the desired characteristics. Furthermore, by setting the thermal expansion coefficient of the glass constituting the support substrate 3 to within ±3% of the thermal expansion coefficient of the material constituting the high acoustic velocity layer 4, it is possible to effectively prevent warping of the device chip 2 that may occur due to heat generated when the acoustic wave device 1 is operated, and warping of the wafer 19 described below that may occur during the manufacturing process of the device chip 2 described below.

[0024] The piezoelectric layer 5 is typically made of a piezoelectric material such as lithium tantalate or lithium niobate.

[0025] Typically, the device chip 2 is configured as a rectangular plate with a side length of 0.5 to 1 mm and a thickness of 0.15 to 0.2 mm, and when viewed from a direction perpendicular to the functional surface 2a, the outline of the functional surface 2a is rectangular. The piezoelectric layer 5 typically has a thickness of 0.2 to 2 μm. The high sound velocity layer 4 typically has a thickness of 2 to 20 μm. The support substrate 3 typically has a thickness of 100 to 200 μm. In each figure, the thickness of the components is exaggerated to make the configuration of the acoustic wave device 1 easier to understand.

[0026] The resonator 7 is formed by a conductive metal layer formed on the functional surface 2a. FIG. 2 shows an example of the configuration of one resonator 7. The resonator 7 has an IDT electrode 7a and a reflector 7b formed on either side of the IDT electrode 7a. The IDT electrode 7a is composed of an electrode pair, and each electrode pair has multiple electrode fingers 7c arranged in parallel so that their length direction intersects the propagation direction x of the acoustic wave that is the main mode, and connected by a busbar 7d at one end of the electrode fingers. The reflector 7b has multiple electrode fingers 7e arranged in parallel so that their length direction intersects the propagation direction x of the acoustic wave, and connected by a busbar 7f at the ends thereof.

[0027] Figure 3 shows the concept of an example of a circuit provided on one device chip 2. Reference numeral 70 denotes resonators 7a connected in series between input and output ports, reference numeral 71 denotes resonators 7a connected in parallel between input and output ports, and reference numeral 13 denotes a ground. The number and arrangement of the resonators 7a can be changed as needed. In other words, a ladder-type filter is configured using the circuit in Figure 3.

[0028] (Example 2) FIG. 4 shows a second example of such an acoustic wave device 1. In FIG. The acoustic wave device 1 of the second example is also mainly composed of a device chip 2. The second example is an acoustic wave device 1 having a WLP (Wafer Level Package) structure. In FIG. 4, reference numeral 14 denotes a support layer, reference numeral 15 denotes a cover layer, reference numeral 16 denotes a via, reference numeral 17 denotes an in-via wiring, and reference numeral 18 denotes a bump. The support layer 14 is made of an insulating resin and is formed so as to surround the region on the functional surface 2a where the resonator 7 is formed. The cover layer 15 is made of insulating resin and is supported on the support layer 14. The cover layer 15 cooperates with the functional surface 2a and the support layer 14 to form an internal space 12 facing the resonator 7. The vias 16 penetrate the support layer 14 and the cover layer 15 in the area outside the internal space 12, and the external connection pads 8 on the functional surface 2a are located at their bottoms. The via wiring 17 is made of a conductive metal filled in the vias 16, and has its inner end connected to the external connection pads 8 and its outer end connected to the bumps 18. The second example is designed to be mounted on a module substrate or the like using the bumps 18.

[0029] The remaining configuration of the device chip 2 constituting this second example is substantially identical to that of the device chip 2 constituting the first example, and therefore the same reference numerals as those used in the first example are used in Figure 4 and their explanations are omitted.

[0030] (Method for manufacturing wafer 19 to be device chip 2 according to first and second examples) The wafer 19 that becomes the device chip 2 that constitutes the acoustic wave device 1 of the first and second examples can be manufactured appropriately and rationally by a manufacturing method that includes the following steps.

[0031] As shown in FIG. 11, the wafer 19 has a base plate portion 20 that becomes the support substrate 3, a middle layer plate portion 21 that becomes the high acoustic velocity layer 4, and a surface layer plate portion 22 that becomes the piezoelectric layer 5.

[0032] Cutting step: An ingot (not shown) made of the material that will form the high sound velocity layer 4 is prepared. When the high sound velocity layer 4 is made of spinel, the ingot is in the form of a rod made of spinel. Then, the ingot is cut in a direction perpendicular to its central axis, and the disk-shaped middle layer plate portion 21 is cut out from the ingot (FIG. 5). Typically, the middle layer plate portion 21 is cut out from the ingot to have a thickness of 50 μm to 100 μm. The cutout is performed so that the surface of the middle layer plate portion 21 has a rough surface r with a surface roughness Ra of 0.5 to 5 μm. Prior to the lamination process, the middle layer plate portion 21 is cleaned to remove dust d and the like generated during the cutting process from its surface (FIGS. 5 and 6).

[0033] Bonding process: As shown in Figure 7, one surface of one base plate portion 20 and one surface of one middle plate portion 21 are stacked and set between a pair of holders H that constitute the bonding device, with one surface facing each other. The base plate portion 20 is typically prepared to have an area substantially equal to that of the middle layer plate portion 21 and a thickness of 100 to 200 μm, and is heated to its softening point temperature prior to the setting. Next, the laminating device is operated to narrow the distance between the pair of holders H, and the workpiece having the intermediate layer plate portion 21 superimposed on the base plate portion 20 is pressed with a predetermined force. By such heating and pressing, the contact interface between the base plate portion 20 and the middle layer plate portion 21 is shaped to have a surface shape that imitates the rough surface r of the middle layer plate portion 21, which has a surface roughness Ra of 0.5 to 5 μm, and is complementary to the rough surface r of the middle layer plate portion 21, thereby firmly integrating the base plate portion 20 and the middle layer plate portion 21 (Figure 8).

[0034] 9, after the bonding step, the surface of the middle layer plate 21 opposite to the contact interface with the base plate 20 is ground, and this surface is typically polished to a mirror finish by CMP. Because the rigidity of the workpiece is increased by the base plate 20, the workpiece can be handled in the same way as a regular wafer.

[0035] Formation process of piezoelectric layer 5: As shown in Figure 10, after the grinding process, the surface plate portion 22 is placed on top of the middle layer plate portion 21 so that the other surface of the mirror-finished middle layer plate portion 21 faces one surface of the similarly mirror-finished surface plate portion 22, and the other surface of the middle layer plate portion 21 and one surface of the surface plate portion 22 are directly bonded. Thereafter, the surface plate portion 22 is ground until it has a predetermined thickness, thereby obtaining a wafer 19 that will become the device chip 2 (FIG. 11).

[0036] On the surface plate portion 22 of the wafer 19 obtained in this manner, the circuit pattern 6 is formed for each region that will become one device chip 2 (FIG. 12). Thereafter, the other surface of the base plate portion 20 is back-ground as required, and then the wafer 19 is diced, thereby producing a plurality of the device chips 2 from one wafer 19 (FIG. 13).

[0037] (Example 3) FIG. 14 shows a third example of such an acoustic wave device 1. In FIG. The acoustic wave device 1 of the third example is mainly composed of a device chip 2. The device chip 2 includes a support substrate 3, a first high acoustic velocity layer 4a, a second high acoustic velocity layer 4b, and a piezoelectric layer 5. The device chip 2 has a flat hexahedral shape with a functional surface 2a formed from the surface of the piezoelectric layer 5, a back surface 2b opposite to the functional surface 2a, and four side surfaces 2c extending between the functional surface 2a and the back surface 2b. In the third example, the back surface 2b is formed from the surface of the second high acoustic velocity layer 4b opposite to the bonding side with the support substrate 3.

[0038] The support substrate 3 is made of glass. The first high acoustic velocity layer 4 a is formed on one surface of the support substrate 3 . The second high acoustic velocity layer 4 b is formed on the other surface of the support substrate 3 . The piezoelectric layer 5 is formed on the first high acoustic velocity layer 4a. A circuit pattern 6 including a resonator 7 (see FIG. 2) that excites a predetermined surface wave (SH wave) is formed on the piezoelectric layer 5 (on the functional surface 2a).

[0039] The circuit pattern 6 includes a plurality of resonators 7, a plurality of bump receiving portions 8, inter-resonator wiring (not shown) connecting the resonators 7 to each other, and external connection wiring (not shown) connecting the resonators 7 to the bump receiving portions 8. The circuit pattern 6 is typically formed on the piezoelectric layer 5 using a conductive metal film formed by photolithography.

[0040] The third example is an acoustic wave device 1 having a CSP (Chip Size Package) structure. In Fig. 14, reference numeral 9 denotes a package substrate, reference numeral 9a denotes a mounting surface of the package substrate 9, reference numeral 9b denotes a pad on the package substrate 9 side, reference numeral 9c denotes an external output pad formed on the back surface of the package substrate 9 opposite the mounting surface 9a, reference numeral 10 denotes a sealing resin, reference numeral 11 denotes a bump, and reference numeral 12 denotes an internal space. The device chip 2 is mounted on the package substrate 9 with the functional surface 2 a facing the mounting surface of the package substrate 9 . By welding the bumps 11 formed on the bump receiving portions 8 to the pads 9b, the circuit on the device chip 2 side and the circuit on the package substrate 9 side are electrically connected. Between the functional surface 2a and the mounting surface 9a, a gap is formed that is equal to the thickness of the bump receiving portion 8, the bump 11, and the pad 9b. The sealing resin 10 is made of insulating resin and covers the entire back surface 2b of the device chip 2 opposite the functional surface 2a and the side surface 2c of the device chip 2, and also extends partly between the functional surface 2a and the mounting surface 9a directly below the side surface 2c, thereby forming the internal space 12.

[0041] The first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b are each configured to have a bulk wave acoustic velocity faster than the bulk wave acoustic velocity of the piezoelectric layer 5, and have a thickness that is at least twice the wavelength of the surface wave. For example, when the wavelength of the surface wave is 4 μm, the thickness of the first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b is set to 8 μm or more. The first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b are preferably made of spinel.

[0042] On the other hand, the support substrate 3 is made of glass whose thermal expansion coefficient from the softening point temperature of the glass to room temperature is within a range of ±6% of the thermal expansion coefficient of the material constituting the first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b. Typically, when the high sound velocity layer 4 is made of spinel, the thermal expansion coefficient of spinel is 7.4×10 -6 / K, the glass is typically made of borosilicate glass, phosphosilicate glass, or borophosphosilicate glass (BPSG), and its thermal expansion coefficient is 7.0 × 10 -6 / K to 7.8 × 10 -6 Make it so that it is / K. The thermal expansion coefficient can be adjusted by adjusting the boron (B) content in the borosilicate glass, the phosphorus (P) content in the phosphosilicate glass, and the boron and phosphorus contents in the borophosphosilicate glass.

[0043] The surfaces of the first and second high acoustic velocity layers 4a and 4b that come into contact with the support substrate 3 (the bonding side, which will be described later) are roughened surfaces r with a surface roughness Ra of 0.5 to 5 μm. The rough surface r is formed by forming countless recesses and countless protrusions on the surfaces of the first high sound velocity layer 4a and the second high sound velocity layer 4b so that the protrusions are located substantially between the recesses and the recesses are located between the protrusions. As shown in FIG. 14, the constituent material of the support substrate 3 fills the recesses of the rough surface r without leaving any gaps, and the protrusions of the rough surface r bite into the support substrate 3.

[0044] If the thickness of the first high acoustic velocity layer 4a is at least twice the wavelength of the surface wave, it is recognized that the surface wave can be reflected and confined within the piezoelectric layer 5. This makes it possible to impart desired characteristics to the acoustic wave device 1. Furthermore, by making the first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b have the minimum thickness described above and supporting the high acoustic velocity layer 4 having such a thickness by the support substrate 3, it is possible to minimize the amount of material used to make the first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b, which are relatively expensive among the materials that make up the device chip 2, while ensuring the desired characteristics. Furthermore, by setting the thermal expansion coefficient of the glass constituting the support substrate 3 to within ±6% of the thermal expansion coefficient of the material constituting the first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b, it is possible to effectively prevent warping of the device chip 2 that may occur due to heat generation when the acoustic wave device 1 is operated, and warping of the wafer 19 described below that may occur during the manufacturing process of the device chip 2 described below. In particular, in this third example, a first high acoustic velocity layer 4a is formed on one side of the support substrate 3, and a second high acoustic velocity layer 4b is formed on the other side of the support substrate 3. Therefore, when a force that causes warping as indicated by symbol w1 in FIG. 14 is applied to one side of the support substrate 3 due to the difference in thermal expansion coefficients, a force that causes warping in the opposite direction to the force as indicated by symbol w2 in FIG. 14 is applied to the other side of the support substrate 3, thereby making it possible to more effectively prevent the warping. Alternatively, when a force that causes warping as indicated by symbol w3 in FIG. 14 is applied to one surface of the support substrate 3 due to the difference in thermal expansion coefficient, the warping can be more effectively prevented by applying a force that causes warping in the opposite direction to the above force as indicated by symbol w4 in FIG. 14 to the other surface of the support substrate 3.

[0045] As a result, in this third example, unlike the first example, the thermal expansion coefficient of the glass constituting the support substrate 3 can be within a range of ±6% of the thermal expansion coefficient of the material constituting the first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b without any problems.

[0046] The piezoelectric layer 5 is typically made of a piezoelectric material such as lithium tantalate or lithium niobate.

[0047] Typically, the device chip 2 is configured as a rectangular plate with a side length of 0.5 to 1 mm and a thickness of 0.15 to 0.2 mm, and when viewed from a direction perpendicular to the functional surface 2a, the outline of the functional surface 2a is rectangular. The piezoelectric layer 5 typically has a thickness of 0.2 to 2 μm. The first high acoustic velocity layer 4a and the second high acoustic velocity layer 4b typically have a thickness of 2 to 20 μm. The support substrate 3 typically has a thickness of 100 to 200 μm. In each drawing, the thickness of the components of the acoustic wave device 1 is exaggerated to make it easier to understand the configuration of the device.

[0048] (Example 4) FIG. 15 shows a fourth example of such an acoustic wave device 1. In FIG. The acoustic wave device 1 of the fourth example is also mainly composed of a device chip 2. The fourth example is an acoustic wave device 1 having a WLP (Wafer Level Package) structure. In FIG. 15, reference numeral 14 denotes a support layer, reference numeral 15 denotes a cover layer, reference numeral 16 denotes a via, reference numeral 17 denotes an in-via wiring, and reference numeral 18 denotes a bump. The support layer 14 is made of an insulating resin and is formed so as to surround the region on the functional surface 2a where the resonator 7 is formed. The cover layer 15 is made of insulating resin and is supported on the support layer 14. The cover layer 15 cooperates with the functional surface 2a and the support layer 14 to form an internal space 12 facing the resonator 7. The vias 16 penetrate the support layer 14 and the cover layer 15 in the area outside the internal space 12, and the external connection pads 8 on the functional surface 2a are located at their bottoms. The via wiring 17 is made of a conductive metal filled in the vias 16, and has its inner end connected to the external connection pads 8 and its outer end connected to the bumps 18. The fourth example is designed to be mounted on a module substrate or the like using the bumps 18.

[0049] The remaining configuration of the device chip 2 constituting this fourth example is substantially identical to that of the device chip 2 constituting the third example, and therefore the same reference numerals as those used in the third example are used in Figure 15 and their explanations are omitted.

[0050] (Method for manufacturing wafer 19 to be device chip 2 according to third and fourth examples) The wafer 19 that becomes the device chip 2 that constitutes the acoustic wave device 1 of the third and fourth examples can be appropriately and rationally manufactured by a manufacturing method that includes the following steps.

[0051] As shown in Figure 22, such a wafer 19 has a base plate portion 20 that becomes the support substrate 3, a first intermediate layer plate portion 21a that becomes the first high acoustic velocity layer 4a, a second intermediate layer plate portion 21b that becomes the second high acoustic velocity layer 4b, and a surface layer plate portion 22 that becomes the piezoelectric layer 5.

[0052] Cutting step: An ingot (not shown) made of the material that will form the first high sound velocity layer 4a and the second high sound velocity layer 4b is prepared. When the first high sonic velocity layer 4a and the second high sonic velocity layer 4b are made of spinel, the ingot is in the form of a rod made of spinel. Then, the ingot is cut in a direction perpendicular to its central axis, and the disk-shaped first intermediate layer plate portion 21a and second intermediate layer plate portion 21b are cut out from the ingot (FIG. 16). Typically, the first intermediate layer plate portion 21a and the second intermediate layer plate portion 21b are cut out from the ingot to have a thickness of 50 μm to 100 μm. The surfaces of the first intermediate plate portion 21a and the second intermediate plate portion 21b are cut out so as to have a rough surface r with a surface roughness Ra of 0.5 to 5 μm. The first intermediate plate portion 21a and the second intermediate plate portion 21b are prepared to have substantially the same thickness. Prior to the lamination process, the middle layer plate portion 21 is cleaned to remove dust d and the like generated during the cutting process from its surface (FIGS. 16 and 17).

[0053] Bonding process: As shown in Figure 18, the base plate portion 20 is stacked and set between a pair of holders H that constitute the bonding device, with one surface of the base plate portion 20 facing one surface of the first intermediate plate portion 21a and the other surface of the base plate portion 20 facing one surface of the second intermediate plate portion 21b. The base plate portion 20 is typically prepared to have an area substantially equal to that of the first intermediate layer plate portion 21a and the second intermediate layer plate portion 21b and a thickness of 100 to 200 μm, and is heated to its softening point temperature prior to the setting. Next, the bonding device is operated to narrow the distance between the pair of holders H, and the workpiece (workpiece) having the first intermediate layer plate portion 21a and the second intermediate layer plate portion 21b superimposed on the base plate portion 20 is pressed with a predetermined force. That is, in the bonding process, the base plate portion 20 is heated to its softening point temperature, and then the three are overlapped and pressed together so that the base plate portion 20 is positioned between the first intermediate layer plate portion 21a and the second intermediate layer plate portion 21b. By such heating and pressing, the contact interface between the base plate portion 20 and the first intermediate layer plate portion 21a is shaped to have a surface shape that imitates the rough surface r of the first intermediate layer plate portion 21a, which has a surface roughness Ra of 0.5 to 5 μm, and is complementary to the rough surface r of the first intermediate layer plate portion 21a, thereby firmly integrating the base plate portion 20 and the first intermediate layer plate portion 21a (Figure 19). At the same time, by the heating and pressing, the contact interface between the base plate portion 20 and the second intermediate layer plate portion 21b is shaped to have a surface shape that imitates the rough surface r of the second intermediate layer plate portion 21b, which has a surface roughness Ra of 0.5 to 5 μm, and is complementary to the rough surface r of the second intermediate layer plate portion 21b, thereby firmly integrating the base plate portion 20 and the second intermediate layer plate portion 21b (Figure 19).

[0054] 20, after the bonding step, the surface of the first intermediate layer plate portion 21a opposite to the contact interface with the base plate portion 20 is ground, and this surface is mirror-finished, typically by CMP. At the same time, the surface of the second intermediate layer plate portion 21b opposite to the contact interface with the base plate portion 20 is ground, and this surface is mirror-finished, typically by CMP. Since the rigidity of the processing object is increased by the base plate portion 20, the processing object can be handled in the same way as a general wafer 19.

[0055] Formation process of piezoelectric layer 5: As shown in Figure 21, after the grinding process, the surface plate portion 22 is placed on the first intermediate layer plate portion 21a so that the other surface of the mirror-finished first intermediate layer plate portion 21a faces one surface of the surface plate portion 22 which has also been mirror-finished, and the other surface of the first intermediate layer plate portion 21a and one surface of the surface plate portion 22 are directly bonded. Thereafter, the surface plate portion 22 is ground until it has a predetermined thickness, thereby obtaining a wafer 19 that will become the device chip 2 (FIG. 22).

[0056] On the surface plate portion 22 of the wafer 19 obtained in this manner, the circuit pattern 6 is formed for each region that will become one device chip 2 (FIG. 23). Thereafter, the wafer 19 is diced to produce a plurality of device chips 2 from one wafer 19 (FIG. 24).

[0057] It should be noted that the present invention is not limited to the above-described embodiments, but includes all embodiments that can achieve the object of the present invention. [Explanation of symbols]

[0058] x Propagation direction d Dust H Holder r Rough surface 1. Acoustic wave devices 2. Device chip 2a Functional aspect 2b Back 2c side 3 Support substrate 4 High-sonic layer 4a 1st high-sonic layer 4b 2nd high-sonic layer 5 Piezoelectric layer 6 Circuit Pattern 7, 70, 71 resonator 7a IDT electrode 7b reflector 7c electrode finger 7d busbar 7e electrode finger 7F bus bar 8 Bump receiving part 9 Package substrate 9a Mounting surface 9b pad 9c External output pad 10 Sealing resin 11 Bump 12 Interior Space 13 Grand 14 Support layer 15 Cover Layer 16 Via 17 Via in wiring 18 Bump 19 wafers 20 Base plate 21 Middle plate part 21a 1st middle plate section 21b 2nd middle plate section 22 Surface plate part

Claims

1. An acoustic wave device comprising a device chip as a main body, the device chip having a glass support substrate, a high acoustic velocity layer formed on the support substrate, and a piezoelectric layer formed on the high acoustic velocity layer, and a circuit pattern including a resonator that excites a predetermined surface wave is formed on the piezoelectric layer of the device chip, the high acoustic velocity layer is configured to have a bulk wave acoustic velocity that is faster than the bulk wave acoustic velocity of the piezoelectric layer, and has a thickness that is at least twice the wavelength of the surface wave; Furthermore, the thermal expansion coefficient of the glass from the softening point temperature to room temperature is set to be within a range of ±3% of the thermal expansion coefficient of the material constituting the high acoustic velocity layer.

2. The acoustic wave device according to claim 1 , wherein the high acoustic velocity layer is made of spinel.

3. 3. A wafer that becomes the device chip that constitutes the acoustic wave device according to claim 1 or 2, A method for manufacturing a wafer having a base plate portion that serves as the support substrate, a middle layer plate portion that serves as the high acoustic velocity layer, and a surface layer plate portion that serves as the piezoelectric layer, a cutting step of cutting the middle layer plate portion from an ingot made of a material constituting the high sonic velocity layer; a bonding step of bonding the base plate portion and the middle plate portion together, In the bonding step, the base plate portion is heated to a softening point temperature, and then the middle layer plate portion is superimposed on the base plate portion and pressed against the base plate portion.

4. 4. The method for manufacturing a wafer according to claim 3, wherein the surface roughness Ra of the intermediate plate portion on the side to be bonded to the base plate portion is set to 0.5 to 5 [mu]m.

5. An acoustic wave device mainly comprising a device chip having a glass support substrate, a first high acoustic velocity layer formed on one surface of the support substrate, a piezoelectric layer formed on the first high acoustic velocity layer, and a second high acoustic velocity layer formed on the other surface of the support substrate, wherein a circuit pattern including a resonator that excites a predetermined surface wave is formed on the piezoelectric layer of the device chip, The first high acoustic velocity layer and the second high acoustic velocity layer are each made of the same material having a bulk wave acoustic velocity faster than the bulk wave acoustic velocity of the piezoelectric layer, The surface wave is configured to have the same thickness that is at least twice the wavelength of the surface wave, Furthermore, the thermal expansion coefficient of the glass from the softening point temperature to room temperature is set to be within a range of ±6% of the thermal expansion coefficient of the material constituting the first high acoustic velocity layer and the second high acoustic velocity layer.

6. The acoustic wave device according to claim 5 , wherein the first high acoustic velocity layer and the second high acoustic velocity layer are made of spinel.

7. A wafer that becomes the device chip that constitutes the acoustic wave device according to claim 5 or 6, A method for manufacturing a wafer having a base plate portion that serves as the support substrate, a first intermediate plate portion that serves as the first high acoustic velocity layer, a second intermediate plate portion that serves as the second high acoustic velocity layer, and a surface plate portion that serves as the piezoelectric layer, a cutting step of cutting the first intermediate layer plate portion and the second high sonic velocity layer from an ingot made of material constituting the first high sonic velocity layer and the second high sonic velocity layer; a bonding step of bonding the second intermediate plate portion to one surface of the base plate portion and bonding the second intermediate plate portion to the other surface of the base plate, A wafer manufacturing method in which, in the bonding process, the base plate portion is heated to its softening point temperature, and then the three portions are overlapped and pressed together so that the base plate portion is positioned between the first intermediate layer plate portion and the second intermediate layer plate portion.

8. 8. The method for manufacturing a wafer according to claim 7, wherein the surface roughness Ra of the intermediate plate portion on the side to be bonded to the base plate portion is set to 0.5 to 5 [mu]m.

Images