Method for manufacturing a composite substrate, composite substrate, and elastic wave element

Abstract

To suppress the reflection of bulk waves from the bonding interface of the silicon substrate while preventing slippage from occurring from the back side during heat treatment. [Solution] A method for manufacturing a composite substrate comprises the steps of: preparing a piezoelectric substrate; preparing a silicon substrate whose surface roughness is smaller than that of the back surface; making the surface of the silicon substrate a non-bonding surface; bonding the back surface of the silicon substrate and the piezoelectric substrate directly or via a bonding layer; and thinning the piezoelectric substrate.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a composite substrate, a composite substrate, and an elastic wave element. [Background technology]

[0002] In recent years, piezoelectric materials such as lithium niobate (hereinafter also referred to as "LN") and lithium tantalate (hereinafter also referred to as "LT") have been used as materials for elastic wave elements (hereinafter also referred to as "elastic wave devices") such as SAW (Surface Acoustic Wave) filters and thin-film resonators. Furthermore, piezoelectric substrates made from these piezoelectric materials are bonded to support substrates such as silicon, quartz glass, crystal, and borosilicate glass, which have a smaller coefficient of thermal expansion than the piezoelectric substrate, to form composite substrates which are then used as substrates for elastic wave devices such as SAW filters and thin-film resonators. By bonding the piezoelectric substrate to a support substrate with a smaller coefficient of thermal expansion than the piezoelectric substrate in this way, changes in the size of the composite substrate when the temperature changes are suppressed, thereby suppressing changes in the frequency characteristics of the elastic wave device.

[0003] Patent Document 1 discloses a method for manufacturing a composite substrate in which a silicon substrate with an interstitial oxygen concentration of 2 to 10 ppm is used as a support substrate, this silicon substrate is bonded to a piezoelectric substrate, and then the piezoelectric substrate is thinned. It is stated that this method allows high resistance to be maintained even after a heat treatment process at 300°C.

[0004] Patent Document 2 discloses a composite substrate in which the piezoelectric substrate is 5 to 100 μm thick, the support substrate is made of silicon with a resistivity of 2000 Ω·cm or more, and both surface layers are oxidized to a thickness of 0.1 to 20 μm. It is stated that this allows for a composite substrate with less warping when subjected to temperature changes and excellent heat resistance.

[0005] In Patent Document 3, the bonding layer provided between the support substrate and the piezoelectric substrate is made of Si (1-x) O xA composite substrate having a composition of (0.008 ≤ x ≤ 0.408) is disclosed. It is stated that this allows for increased bonding strength while improving the insulating properties of the bonding layer. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2018-117030 [Patent Document 2] Japanese Patent Publication No. 2005-347295 [Patent Document 3] Patent No. 6375471 [Overview of the project] [Problems that the invention aims to solve]

[0007] Furthermore, the disclosures in the above-mentioned prior art documents are incorporated into this book by reference. The following analysis was conducted by the inventors.

[0008] Incidentally, in composite substrates of piezoelectric substrates and silicon substrates, the difference in thermal expansion coefficients is very large. Therefore, if heat treatment is performed during device formation after bonding the substrates together, the bonding surfaces of the silicon substrate and piezoelectric substrate may peel off.

[0009] In addition, in elastic wave devices manufactured using such composite substrates, the reflection of bulk waves from the bonding interface of the silicon substrate sometimes degraded the device characteristics.

[0010] The object of the present invention is to provide a method for manufacturing a composite substrate, a composite substrate, and an elastic wave device that contribute to suppressing slippage from the back side during heat treatment while suppressing reflection of bulk waves from the bonding interface of the silicon substrate, in view of the above-mentioned problems. [Means for solving the problem]

[0011] To solve the above problems, the present invention provides a method for manufacturing a composite substrate, comprising the steps of: preparing a piezoelectric substrate; preparing a silicon substrate whose surface roughness is smaller than that of the back surface; making the surface of the silicon substrate a non-bonding surface; bonding the back surface of the silicon substrate and the piezoelectric substrate directly or via a bonding layer; and thinning the piezoelectric substrate.

[0012] In the present invention's method for manufacturing a composite substrate, a silicon substrate with a surface roughness smaller than that of the back surface is used, and the back surface of the silicon substrate with greater roughness is used as the bonding surface. This allows for the suppression of bulk reflected waves from the bonding interface of the silicon substrate during the manufacturing of elastic wave devices with a simple configuration. Furthermore, by using the surface of the silicon substrate with even less roughness as the non-bonding surface and the back surface of the composite substrate, slippage from the back surface during the device formation heat treatment can be suppressed.

[0013] During the bonding process, the surface roughness Rms of the silicon substrate is smaller than that of the back surface of the silicon substrate, and it is preferable that the surface roughness Rms of the silicon substrate is 0.05 to 0.5 nm. Furthermore, during the bonding process, it is preferable that the back surface roughness Rms of the silicon substrate is 0.2 to 5.0 nm.

[0014] It is preferable to further include a bonding layer formation step in which a bonding layer is formed on the surface of the silicon substrate before the bonding step. Furthermore, it is preferable that the bonding layer includes one or more layers selected from a silicon oxide film layer, a silicon nitride film layer, an amorphous silicon layer, a polysilicon layer, an organic adhesive layer, a titanium layer, and a titanium oxide film layer.

[0015] Preferably, the back surface of the silicon substrate is supported by a susceptor, and the silicon substrate is further subjected to a heat treatment step in which it is heated at a predetermined heating rate, held at a maximum temperature of 1100°C to 1400°C for a predetermined time, and cooled at a predetermined cooling rate. Preferably, the heat treatment step is a rapid heating and cooling heat treatment performed in an oxygen atmosphere (hereinafter, rapid heating and cooling heat treatment will also be referred to as "RTP", and in particular, rapid heating and cooling heat treatment in an oxygen atmosphere will also be referred to as "RTO"), the oxygen partial pressure is 1 to 100%, the maximum temperature is 1300°C or higher, and the predetermined period is 1 to 60 s. The heat treatment step may also be a batch heat treatment in which the predetermined heating rate is 1 to 20°C / min, the predetermined cooling rate is 1 to 20°C / min, and the maximum temperature is held at 1100°C to 1250°C for 0.5 to 20 hours. This is because making it easier for oxygen precipitation nuclei and oxygen precipitates to grow makes it more difficult for slips to extend.

[0016] The aforementioned silicon substrate is sliced ​​from a vacancy-rich silicon single crystal manufactured by the Czochralski method, with an interstitial oxygen concentration of 2.0E17 to 1.3E18 atoms / cm³. 3 It is preferable that the silicon substrate is sliced ​​from a vacancy-rich (V-rich) silicon single crystal produced by the Czochralski method, thereby increasing productivity and facilitating the formation of oxygen nuclei and oxygen precipitates. In addition, the interstitial oxygen concentration is 2E17~1.3E18 atoms / cm³. 3 By doing so, the oxygen concentration can be increased relatively compared to the FZ substrate, thereby increasing the strength of the silicon substrate itself and making it easier for oxygen nuclei and oxygen precipitates to grow during device heat treatment, which makes it difficult for slip to elongate. It is preferable that the heat treatment process be carried out in a non-oxidizing atmosphere.

[0017] The heat treatment process is preferably a batch heat treatment in which the predetermined heating rate is 1 to 20 °C / min, the predetermined cooling rate is 1 to 20 °C / min, and the maximum temperature reached is maintained at 1100 °C or higher and 1250 °C or lower for 0.5 to 20 hours. When the predetermined heating rate is 1 to 20 °C / min, the predetermined cooling rate is 1 to 20 °C / min, and the maximum temperature reached is maintained at 1100 °C or higher and 1250 °C or lower for 0.5 to 20 hours, a relatively high-temperature heat treatment process is performed for a long time, so a large number of oxygen precipitates are formed. In addition, oxygen precipitate nuclei and oxygen precipitates are formed to be relatively large in size compared to RTP, which is a short-time heat treatment process. Therefore, even if slip occurs, the elongation of the slip can be suppressed by the oxygen precipitates. Note that it is preferable that the silicon substrate is not polished after the heat treatment process and before the thinning process.

[0018] In order to solve the above problems, the composite substrate of the present invention has a silicon substrate and a piezoelectric substrate, the silicon substrate and the piezoelectric substrate are joined via a joining layer, the joining layer includes at least a silicon oxide film layer, the silicon substrate is rich in vacancies, and the inter-lattice oxygen concentration of the bulk layer is 2.0E17~1.3E18atoms / cm 3 and is characterized in that the roughness on the joining surface side of the silicon substrate is larger than the roughness on the non-joining surface side.

[0019] The silicon substrate is sliced from a vacancy-rich silicon single crystal produced by the Czochralski method, and the inter-lattice oxygen concentration is 2.0E17~1.3E18atoms / cm 3 is preferable. The silicon substrate is sliced from a vacancy-rich (V-rich) silicon single crystal produced by the Czochralski method, so that oxygen precipitate nuclei and oxygen precipitates can be easily formed while increasing productivity. In addition, the inter-lattice oxygen concentration is 2E17~1.3E18atoms / cm 3By assuming this, the oxygen concentration can be relatively increased compared to the FZ substrate, enhancing the strength of the silicon substrate itself and making it easier for oxygen precipitation nuclei and oxygen precipitates to grow during device heat treatment, thereby making it difficult for slips to elongate.

[0020] Preferably, the silicon substrate has a DZ layer on the bonding surface side and a bulk layer with oxygen precipitates formed on the non-bonding surface side. Also, the roughness Rms on the bonding surface side of the silicon substrate may be 0.2 to 5.0 nm, and the roughness Rms on the non-bonding surface side may be 0.05 to 0.5 nm. <000​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Figure 6 is a flowchart showing the manufacturing method of the composite substrate according to Embodiment 2. [Modes for carrying out the invention]

[0024] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the embodiments described below. In each drawing, the same or corresponding elements are appropriately denoted by the same reference numerals. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from those of reality. Even between drawings, there may be parts where the dimensional relationships and ratios differ from each other.

[0025] (Embodiment 1) Figure 1 is a schematic cross-sectional view showing an example of a composite substrate according to Embodiment 1 of the present invention. As shown in Figure 1, the composite substrate 5 is manufactured by bonding a piezoelectric substrate 1 and a silicon substrate 2, which is a support substrate having a smaller coefficient of thermal expansion, via an insulating bonding layer 3. With this configuration, when stress is generated in the piezoelectric substrate 1 and the silicon substrate 2 in response to temperature changes, the thermal expansion of the piezoelectric substrate 1 can be suppressed, thereby improving the frequency-temperature characteristics compared to a piezoelectric substrate alone.

[0026] The composite substrate 5 can be manufactured, for example, by forming an oxide film on one or both of the piezoelectric substrate 1 and the silicon substrate 2, bonding them together, and applying a load to create a bond. The bonding layer 3 may include one or more layers from among a silicon oxide layer, a silicon nitride layer, an amorphous silicon layer, a polysilicon layer, an organic adhesive layer, a titanium layer, and a titanium oxide layer, and may also be a multilayer structure. The thickness of the bonding layer 3 is preferably 0.05 μm to 50 μm. If it is thinner than 0.05 μm, the effect of reducing the warping of the composite substrate is small, and if it is thicker than 50 μm, cracks may occur in the piezoelectric substrate 1, which is undesirable. In addition, the adhesive strength may be enhanced by hydrophilizing the surface with an ammonia / hydrogen peroxide aqueous solution or by plasma activation treatment. The size of the substrate is not particularly limited; for example, substrates with diameters of 125 mm, 150 mm, or 200 mm may be used, or they may be larger or smaller.

[0027] In this embodiment, the piezoelectric substrate 1 has a thickness of 0.5 to 150 μm. Although it varies depending on the application, the thickness of the piezoelectric substrate 1 is preferably 30 to 120 μm, and more preferably 50 to 100 μm. Furthermore, if it is a composite substrate 5 used in high-frequency acoustic wave devices, the thickness of the piezoelectric substrate 1 is preferably 0.5 to 10 μm, and more preferably 0.5 to 3.0 μm. To make the thickness of the piezoelectric substrate 1 the desired value above, for example, the piezoelectric substrate 1 can be ground and polished after the composite substrate is formed. Note that if the thickness of the piezoelectric substrate 1 is thinner than 0.5 μm, cracks may occur due to processing distortion caused by polishing, which is undesirable. Also, if it is thicker than 150 μm, the piezoelectric substrate may crack when the composite substrate 5 is heat-treated during device formation, which is undesirable. Furthermore, the piezoelectric substrate 1 may be thinned using a so-called ion implantation separation method. Ion implantation separation is a method in which light element ions such as hydrogen and helium are implanted at a predetermined depth in an active layer wafer to form an ion-implanted layer, the active layer wafer is then bonded to a support substrate wafer, and subsequently the active layer wafer is peeled off at the ion-implanted layer to reduce its thickness.

[0028] The piezoelectric substrate 1 may be made of any piezoelectric crystal material, but lithium tantalate or lithium niobate is desirable because they have a large electromechanical coupling coefficient, enabling the production of an elastic wave device with a wide bandwidth as a frequency selection filter and low insertion loss. Regarding the substrate orientation, it can be appropriately selected according to the type of piezoelectric crystal material and the application of the elastic wave device, such as 36° rotated Y-cut, 41° rotated Y-cut, 45° rotated Y-cut, etc.

[0029] For the support substrate, a silicon substrate 2 is used which is heated at a predetermined heating rate, heat-treated at a maximum temperature of 1100°C or higher and 1400°C or lower for a predetermined time, and cooled at a predetermined cooling rate, thereby forming oxygen precipitation nuclei and oxygen precipitates 4. In this specification, those with a size less than 1 nm are referred to as oxygen precipitation nuclei, and those with a size of 1 nm or more are referred to as oxygen precipitates.

[0030] The thickness of the silicon substrate 2 is preferably 50 to 500 μm. The silicon substrate 2 has a smaller thermal expansion coefficient than the piezoelectric substrate 1 and is also suitable for mass production. Regarding the resistivity of the silicon substrate 2, it is preferably a high resistivity, preferably 1000 Ω·cm or more, and more preferably 4000 Ω·cm or more. The silicon substrate of this embodiment is manufactured using the Czochralski method (hereinafter also referred to as the "CZ method") and is preferably a silicon substrate sliced from a so-called vacancy-rich (V-rich: Vacancy dominant) silicon single crystal. Also, the inter-lattice oxygen concentration of the silicon substrate 2 before heat treatment is preferably 2.0E17 to 1.3E18 atoms / cm 3 is preferable, and more preferably 5.0E17 to 9.0E17 atoms / cm 3 is even more preferable.

[0031] Note that a polysilicon layer may be formed on the silicon substrate 2 as a charge trap layer. In this embodiment, the silicon substrate with the polysilicon layer formed is also simply referred to as the "silicon substrate" and is included in the silicon substrate.

[0032] In this embodiment, the silicon substrate 2 has oxygen precipitates 4 with a size of 20 nm or less, at a concentration of 1.0E2 particles / cm². 3 The above findings are present in bulk layer 7. The size and density of these oxygen precipitates were measured using transmission electron microscopy (TEM).

[0033] In this embodiment, the silicon substrate 2 after the heat treatment process has a surface roughness smaller than the back surface roughness. After the heat treatment process, it is desirable that the surface roughness Rms of the silicon substrate 2 is 0.05 to 0.5 nm and the back surface roughness is 0.2 to 5.0 nm. In this embodiment, the side held by the susceptor during the heat treatment process is considered the back surface, and the side opposite to the side held by the susceptor is considered the front surface.

[0034] After forming a bonding layer on the rougher back surface of the silicon substrate 2, the silicon substrate 2 and the piezoelectric substrate 1 are bonded via the bonding layer 3. In this embodiment, the composite substrate 5 is configured such that a DZ layer 6 is located on the side that bonds with the bonding layer 3 (the piezoelectric substrate side), and a bulk layer 7 with oxygen precipitation nuclei and oxygen precipitates 4 is located on the side that does not bond with the bonding layer 3 (the side opposite to the piezoelectric substrate side). With this configuration, a simple structure can be used to suppress bulk reflected waves from the bonding interface of the silicon substrate 2 during elastic wave device manufacturing, suppress slip from the back surface during device formation heat treatment, and even if slip occurs in the silicon substrate 2, the oxygen precipitates can suppress the extension of the slip.

[0035] In this embodiment, the silicon substrate 2 is configured such that a DZ layer 6 is located on the side that is bonded to the bonding layer 3 (piezoelectric substrate side), and a bulk layer with oxygen precipitation nuclei and oxygen precipitates 4 is located on the side that is not bonded to the bonding layer 3 (opposite side from the piezoelectric substrate side). This configuration enhances the bonding strength between the piezoelectric substrate 1 and the silicon substrate 2, while suppressing the extension of slip even if slip occurs in the silicon substrate 2 during the device formation heat treatment, thanks to the oxygen precipitates 4. In particular, since it is undesirable for slip to extend to the bonding surface, causing cracks or delamination at the bonding surface, this configuration allows for focused suppression of slip extension near the bonding surface.

[0036] Alternatively, the DZ layer 6 may be located on the side that does not bond with the bonding layer 3 (opposite the piezoelectric substrate side), and the bulk layer 7, on which oxygen precipitation nuclei and oxygen precipitates 4 are formed, may be located on the side that bonds with the bonding layer 3 (piezoelectric substrate side). With this configuration, even if slip occurs near the bonding surface of the silicon substrate 2, it is possible to suppress the extension of the slip to the bonding surface. In particular, since it is undesirable for the slip to extend to the bonding surface, as this can cause cracks or delamination at the bonding surface, the above configuration can be used to specifically suppress the extension of slip near the bonding surface.

[0037] Figure 2 is a flowchart showing the manufacturing method of the composite substrate according to Embodiment 1. As shown in Figure 2, the manufacturing method of the composite substrate according to Embodiment 1 includes a step of preparing a silicon substrate (S1), a heat treatment step (S2), a bonding layer formation step (S3), a step of preparing a piezoelectric substrate (S4), a bonding step (S5), and a thinning step (S6).

[0038] In the step of preparing the silicon substrate 2 (S1), a silicon substrate 2 to be used as a support substrate for the composite substrate is prepared. The thickness of the silicon substrate 2 is preferably 50 to 500 μm. The silicon substrate can be sliced ​​from a silicon single crystal manufactured by the well-known FZ method or CZ method, but it is preferable to use a silicon substrate sliced ​​from a silicon single crystal manufactured using the CZ method. Furthermore, in the crystal pulling process, the silicon single crystal is pulled such that the main plane of the silicon single crystal has an inclination angle of 0.2° to 1.0° with respect to the {110} plane. Alternatively, the pulled silicon single crystal ingot with the {110} as the main plane may be ground at its outer circumference to achieve an inclination angle of 0.2° to 1.0° with respect to the {110} plane. Furthermore, the interstitial oxygen concentration of the silicon substrate 2 before heat treatment is 2.0E17 to 1.3E18 atoms / cm³. 3 This is preferable, with a concentration of 5.0°E17 to 9.0°E17 atoms / cm². 3 It would be even more desirable if that were the case.

[0039] In the heat treatment step (S2), the silicon substrate 2 is subjected to a heat treatment in which the temperature is raised at a predetermined rate, the maximum temperature reached is between 1100°C and 1400°C and held for a predetermined time, and the temperature is cooled at a predetermined rate. Here, it is preferable to perform a batch heat treatment in which the predetermined rate of raising the temperature is 1 to 20°C / min, the predetermined rate of cooling is 1 to 20°C / min, and the maximum temperature reached is between 1100°C and 1250°C and held for 0.5 to 20 hours. Through this heat treatment step (S2), oxygen precipitation nuclei and oxygen precipitates are formed on the silicon substrate 2.

[0040] In the bonding layer formation step (S3), a bonding layer 3 is formed on the surface of the silicon substrate 2. The bonding layer 3 includes one or more layers from among a silicon oxide layer, a silicon nitride layer, an amorphous silicon layer, a polysilicon layer, an organic adhesive layer, a titanium layer, and a titanium oxide layer, and may also be a multilayer structure including multiple layers. The thickness of the bonding layer is preferably 0.05 μm to 50 μm.

[0041] In the step of preparing the piezoelectric substrate 1 (S4), the piezoelectric substrate 1 to be used in the composite substrate 5 is prepared. As mentioned above, the piezoelectric substrate 1 can be any material made of piezoelectric crystalline material. The thickness of the piezoelectric substrate is preferably 30 to 120 μm, and more preferably 50 to 100 μm. Furthermore, if it is a composite substrate used in a high-frequency elastic wave device, the thickness of the piezoelectric substrate 1 is preferably 0.5 to 10 μm, and more preferably 0.5 to 3.0 μm. The piezoelectric substrate 1 can be prepared after being appropriately processed according to the application of the composite substrate.

[0042] In the bonding process (S5), the piezoelectric substrate 1 and the silicon substrate 2 are bonded together via the bonding layer 3 by applying a load. Heat may be applied during bonding. Alternatively, plasma treatment may be performed before bonding. Subsequently, in the thinning process (S6), both sides of the composite substrate 5 are polished to obtain the desired thickness of the piezoelectric substrate 1 and the silicon substrate 2. After double-sided polishing, single-sided polishing may be performed to obtain the desired thickness of the piezoelectric substrate and the silicon substrate.

[0043] Figure 3 is a schematic diagram showing a batch-type heat treatment apparatus used in the heat treatment process of Embodiment 1. As shown in Figure 3, the batch-type heat treatment apparatus 10 has a heat treatment board 11, and multiple silicon substrates are housed in the batch-type heat treatment apparatus 10 with multiple silicon substrates stored on the heat treatment board 11. The batch-type heat treatment apparatus 10 is provided with a heat treatment gas inlet 12, and the heat treatment gas is introduced into the reaction chamber of the batch-type heat treatment apparatus 10 to heat-treat the silicon substrates.

[0044] Figure 4 is a schematic diagram showing the heat treatment process in the heat treatment step of Embodiment 1. The heat treatment step of Embodiment 1 is a batch heat treatment under an Ar atmosphere. The heat treatment atmosphere may be a non-oxidizing atmosphere such as Ar or nitrogen, or an oxygen atmosphere.

[0045] In the heat treatment process of Embodiment 1, a silicon substrate 2 sliced ​​from a void-rich silicon single crystal ingot grown by the CZ method is subjected to a heat treatment as shown in Figure 4, in which the temperature is raised from T2 to T1 at a predetermined heating rate, held at the highest temperature T1 from t1 to t2 for a time t3, and then cooled from T1 to T2 at a predetermined heating rate.

[0046] In the case of batch heat treatment, as in Embodiment 1, the heating rate is preferably 1 to 20°C / min, and more preferably 5 to 15°C / min. Similarly, the cooling rate is preferably 1 to 20°C / min, and more preferably 5 to 15°C / min. The maximum temperature T1 is preferably between 1100°C and 1250°C, and more preferably between 1150°C and 1250°C. Furthermore, the holding time t3 at the maximum temperature is preferably 0.5 to 20 hours. However, from the viewpoint of productivity, it is even more desirable to hold it for 0.5 to 10 hours.

[0047] As a result of the batch heat treatment described above, a DZ layer 6 and a bulk layer 7 are formed on the silicon substrate 2, and the bulk layer contains oxygen precipitates of 20 nm or less in size at a rate of 1.0E4 to 1.0E11 particles / cm². 3 Furthermore, by using a non-oxidizing Ar atmosphere, oxygen precipitation nuclei 4 are formed in the bulk layer 7, while the interstitial oxygen concentration of the DZ layer 6 is significantly reduced compared to the bulk layer 7, reaching 4.0E14~6.0E17 atoms / cm². 3 This can be achieved. Therefore, with the composite substrate 5 using the silicon substrate of this embodiment, it is possible to suppress the extension of slip while suppressing the decrease in resistivity due to thermal donors.

[0048] The heat treatment process may also be a rapid temperature rise and fall treatment. In addition to O2 gas, argon gas, nitrogen gas, or a mixture of O2 gas and argon gas with a partial pressure of 1 to less than 100% may be used as the atmospheric gas. The following describes the case where the heat treatment process is a rapid temperature rise and fall treatment (RTO) using O2 gas.

[0049] Figure 5 is a schematic diagram of a rapid heating and cooling treatment apparatus used for heat treatment. As shown in Figure 5, the rapid heating and cooling treatment apparatus 20 comprises a chamber (reaction tube) 21 equipped with an atmosphere gas inlet 20a and an atmosphere gas outlet 20b, a plurality of lamps 30 spaced apart at the top of the chamber 21, and a substrate support section 40 that supports a silicon substrate 2 in the reaction space 25 within the chamber 21. Although not shown, it also includes a rotating means for rotating the silicon substrate 2 around its central axis at a predetermined speed.

[0050] The substrate support section 40 includes a ring 22 that supports the outer periphery of the silicon substrate 2 and a stage 40a that supports the ring 22. The chamber 21 is made of, for example, quartz. The lamp 30 is made of, for example, a halogen lamp. The stage 40a is made of, for example, quartz. This rapid heating and cooling heat treatment apparatus 20 can uniformly heat and treat the entire silicon substrate 2 with a heating and cooling temperature gradient of 10 to 300°C / second.

[0051] Here, the heat treatment process in the heat treatment step will be explained with reference to Figure 4.

[0052] In this heat treatment process, a silicon substrate is placed in a chamber maintained at a desired temperature T2 (for example, 500°C). Then, O2 gas is introduced into the chamber 21 as the atmospheric gas from the atmospheric gas inlet 20a.

[0053] Next, the silicon substrate 2 is heated by the lamp 30 and rapidly heated at a predetermined heating rate until it reaches a maximum temperature T1 between 1100°C and 1400°C. At this point, the silicon substrate 2 is controlled to be held at the maximum temperature T1 for a predetermined time (t3). After holding the silicon substrate 2 at the maximum temperature T1 for the predetermined time, it is cooled down to T2 at a predetermined cooling rate, and the RTO is terminated.

[0054] In this embodiment, O2 gas was used as an example of the atmospheric gas, but argon gas, nitrogen gas, or a gas mixed with argon gas with a partial pressure of 1 to less than 100% may also be used.

[0055] Furthermore, while the maximum temperature T1 of this embodiment may be between 1100°C and 1400°C, it is preferable that it be above 1300°C, and more preferably between 1300°C and 1350°C. The holding time is preferably between 1 and 60 seconds, and more preferably between 5 and 30 seconds. The heating rate is preferably between 5 and 150°C / min, and more preferably between 10 and 80°C / min. Similarly, the cooling rate is preferably between 5 and 150°C / min, and more preferably between 10 and 80°C / min.

[0056] This heat treatment process forms a silicon oxide film on the silicon substrate 2, and also creates oxygen precipitates with a size of 20 nm or less at a rate of 1.0E2 to 1.0E4 particles / cm² in the bulk layer. 3 A layer is formed. At the same time, numerous oxygen precipitation nuclei are also formed. Compared to batch annealing, fewer oxygen precipitates are formed, which is due to the very fast heating and cooling rates and the short holding time at the highest temperature. These oxygen precipitates grow even at the relatively low temperature heat treatment during device formation, and suppress the extension of slip even if slip occurs in the silicon substrate 2. In addition, by using the silicon oxide film formed in an oxygen atmosphere as the bonding layer, the heat treatment process and the bonding layer formation process can be performed simultaneously, and the bonding strength can be improved.

[0057] Furthermore, a two-stage heat treatment process may be used as part of the heat treatment. While RTP can be performed after RTP, or batch annealing can be performed after batch annealing, it is desirable to include at least one batch annealing stage. This is because including at least one batch annealing stage results in larger and denser oxygen precipitates. A two-stage heat treatment of RTP followed by batch annealing is particularly desirable because it allows the oxygen nuclei formed during RTP to grow into oxygen precipitates during the subsequent batch annealing.

[0058] (Embodiment 2) Embodiment 2 is characterized by bonding the piezoelectric substrate 1 to the back side of the silicon substrate 2, which has a rougher surface, without heat treatment of the silicon substrate 2 to form oxygen deposition nuclei or oxygen precipitates, as in Embodiment 1. Furthermore, the piezoelectric substrate 1 is thinned by ion implantation in the piezoelectric substrate 1 in an implantation process and peeling from the ion implanted surface. Other aspects are substantially the same as Embodiment 1, so their descriptions are omitted.

[0059] Figure 6 is a flowchart showing the manufacturing method of the composite substrate according to this embodiment. As shown in Figure 6, the manufacturing method of the composite substrate according to this embodiment includes a step of preparing a silicon substrate 2 (S7), a double-sided polishing step (S8), a bonding layer formation step (S9), a step of preparing a piezoelectric substrate (S10), an implantation step (S11), a bonding step (S12), and a thinning step (S13).

[0060] The steps of preparing the silicon substrate 2 (S7), forming the bonding layer (S10), and preparing the piezoelectric substrate (S11) are the same as in Embodiment 1, so their explanation will be omitted.

[0061] In the double-sided polishing process (S9) of this embodiment, after preparing the silicon substrate 2, double-sided polishing is performed. During double-sided polishing, the surface that contacts the upper polishing plate is called the front surface, and the surface that contacts the lower polishing plate is called the back surface. In the double-sided polishing process of this embodiment, by using different polishing cloths for the upper and lower polishing plates, the surface roughness Rms is made smaller than that of the back surface. More specifically, it is desirable to have a surface roughness Rms of 0.05 to 0.5 nm for the silicon substrate and a back surface roughness of 0.2 to 5.0 nm.

[0062] In this silicon substrate 2, where the surface roughness Rms is smaller on the front surface than on the back surface, a bonding layer 3 is formed on the rougher back surface, and then the silicon substrate 2 and the piezoelectric substrate 1 are bonded via the bonding layer 3. In this embodiment, the composite substrate is configured such that the rougher back surface is located on the side that bonds with the bonding layer 2 (the side with the piezoelectric substrate 1), and the surface with less roughness is located on the side that does not bond with the bonding layer 3 (the side opposite to the piezoelectric substrate 1). With this configuration, it is possible to suppress bulk reflected waves from the bonding interface of the silicon substrate during elastic wave device manufacturing with a simple configuration, while also suppressing slip from the back surface during the device formation heat treatment.

[0063] In the implantation process (S12), ions are implanted into the piezoelectric substrate 1 to pre-form an embrittlement layer at a predetermined depth on the piezoelectric substrate 1. In the thinning process (S14), which will be described later, the piezoelectric substrate is thinned after being bonded using this embrittlement layer.

[0064] In the bonding process (S13), the piezoelectric substrate 1 and the silicon substrate are bonded together by applying a load via the bonding layer 3. In the thinning process (S14), the piezoelectric substrate is thinned by peeling off the brittle layer that was previously formed to a predetermined depth in the implantation process (S10) in order to achieve the desired thickness of the piezoelectric substrate 1 and the silicon substrate 2.

[0065] By adopting this configuration, a step-terrace structure can be formed on the bonding surface of the silicon substrate 2, and the strength of the bonding surface can be increased by setting the terrace width to an appropriate length.

[0066] (Examples) Here, we will explain the verification experiment of the effectiveness of implementing the present invention. In this verification experiment, a 36° rotated Y-cut lithium tantalate substrate was used as the piezoelectric substrate 1, and a silicon substrate 2 manufactured by the CZ method with a (100) plane as the main surface and a resistivity of approximately 1500 Ω·cm was used as the bonding layer 3, and an SiO2 film obtained by thermal oxidation of the silicon substrate 2 was used. Both the piezoelectric substrate 1 and the silicon substrate 2 were 150 mm in diameter. Furthermore, the surface roughness, back surface roughness, and heat treatment conditions of the silicon substrate 2 in each example were as shown in Table 1 below, and the composite substrate 5 in each example was manufactured according to the manufacturing flow shown in Figure 2. (Comparative example) As a comparative example, a composite substrate 5 is formed by bonding a silicon substrate 2 and a piezoelectric substrate 1, similar to the above embodiment, via a bonding layer 3. However, while the back side is used as the bonding surface in the embodiment, the back side is used as the bonding surface in the comparative example. The surface roughness, back surface roughness, and heat treatment conditions of the silicon substrate 2 for each comparative example are as shown in Table 1 below.

[0067] In this verification experiment, slip evaluation and device characteristics evaluation were performed using composite substrates 5 of each example and comparative example shown in Table 1. In this verification experiment, all comparative examples were experimented with the front side as the bonding surface, and all examples were experimented with the back side as the bonding surface. For slip evaluation, a heat treatment was repeated seven times in which the substrate was heated to 300°C, held at 300°C for 60 seconds, and then cooled to 30°C, and it was observed whether slip occurred from the back side (five composite substrates 5 were used for each condition in each example and comparative example). The evaluation criteria for slip evaluation are as follows. For device characteristics evaluation, an IDT (comb-tooth) electrode was formed on the composite substrate to form a SAW filter, and the frequency characteristics were measured with an RF probe. The obtained frequency characteristics were evaluated as follows: ○ Good, △ Slightly poor, × Poor. Batch annealing was performed in an oxygen atmosphere under three conditions: oxygen partial pressure of 1%, 5%, and 100%, and in an Ar atmosphere under four conditions. The heating rate and cooling rate were both set to 3°C / min. <Slip evaluation> ○: No slip △: Slips occur rarely. ×: Slip occurred

[0068] [Table 1]

[0069] As described above, the composite substrate 5 (Examples 1-10), configured such that the rougher back surface is located on the side that bonds with the bonding layer 2 (the piezoelectric substrate 1 side), and the smoother front surface is located on the side that does not bond with the bonding layer 3 (the side opposite to the piezoelectric substrate 1 side), obtained good results in both slip evaluation and device characteristics, as shown in Table 1. This confirmed that the composite substrate 5 of Examples 1-10 can suppress slip from the back surface while suppressing bulk reflected waves from the bonding interface of the silicon substrate 2.

[0070] On the other hand, in composite substrates 5 (Comparative Examples 1-4) configured such that the back surface, which is a rougher surface, is located on the side not bonded to the bonding layer 2 (opposite side to the piezoelectric substrate 1), and the front surface, which is a smoother surface, is located on the side bonded to the bonding layer 3 (piezoelectric substrate 1 side), both slip evaluation and device characteristics were poor or slightly poor, as shown in Table 1, and no good results were obtained.

[0071] Although the present invention has been described above based on embodiments, the present invention is not limited to the above embodiments. For example, the composite substrates of Embodiments 1 and 2 of the present invention can be suitably applied to acoustic wave devices such as surface acoustic wave devices, Lamb wave elements, and thin-film resonators, or to optical devices such as optical switching elements and wavelength conversion elements. [Explanation of symbols]

[0072] 1. Piezoelectric substrate 2. Silicon substrate 2a Polysilicon layer 3 Bonding layer 3a Organic adhesive layer 3b Silicon oxide layer 4. Oxygen precipitation nuclei and oxygen precipitates 10 Batch-type heat treatment equipment 11 Heat treatment boards 12. Inlet for heat treatment gas 20 Rapid heating and cooling heat treatment apparatus 20a Atmospheric gas inlet 20b Atmospheric gas outlet 21 Chambers 22 rings 25 Reaction space 30 lamps 40 Substrate support section 40a Stage

Claims

1. The process of preparing a piezoelectric substrate, A process to prepare a silicon substrate in which the surface roughness is smaller than the back surface roughness, The surface of the silicon substrate is a non-bonding surface, and the back surface of the silicon substrate and the piezoelectric substrate are bonded together either directly or via a bonding layer in a bonding step. A thinning step for thinning the piezoelectric substrate, A method for manufacturing a composite substrate, characterized by having the following features.

2. The method for manufacturing a composite substrate according to claim 1, characterized in that, during the bonding process, the surface of the silicon substrate has a roughness Rms smaller than the back surface of the silicon substrate, and the surface roughness Rms of the silicon substrate is 0.05 to 0.5 nm.

3. The method for manufacturing a composite substrate according to claim 1, characterized in that, during the bonding process, the back surface roughness Rms of the silicon substrate is 0.2 to 5.0 nm.

4. The method for manufacturing a composite substrate according to claim 1, further comprising a bonding layer formation step of forming a bonding layer on the surface of the silicon substrate before the bonding step.

5. The method for manufacturing a composite substrate according to claim 4, characterized in that the bonding layer includes one or more layers selected from a silicon oxide film layer, a silicon nitride film layer, an amorphous silicon layer, a polysilicon layer, an organic adhesive layer, a titanium layer, and a titanium oxide film layer.

6. The back surface of the silicon substrate is supported by a susceptor. The method for manufacturing a composite substrate according to claim 1, further comprising a heat treatment step of heating the silicon substrate at a predetermined heating rate, holding it at a maximum temperature of 1100°C or higher and 1400°C or lower for a predetermined time, and then cooling it at a predetermined cooling rate.

7. The silicon substrate is sliced ​​from a vacancy-rich silicon single crystal produced by the Czochralski method, with an interstitial oxygen concentration of 2.0E17 to 1.3E18 atoms / cm³. 3 The method for manufacturing a composite substrate according to claim 6, characterized in that it is the same.

8. The method for manufacturing a composite substrate according to claim 6, characterized in that the heat treatment step is performed under a non-oxidizing atmosphere.

9. The method for manufacturing a composite substrate according to claim 6, characterized in that the heat treatment step is a batch heat treatment in which the predetermined heating rate is 1 to 20°C / min, the predetermined cooling rate is 1 to 20°C / min, and the maximum temperature reached is 1100°C or higher and 1250°C or lower, and the temperature is held at that temperature for 0.5 to 20 hours.

10. The method for manufacturing a composite substrate according to claim 1, characterized in that the silicon substrate is not polished after the heat treatment step and before the thinning step.

11. It has a silicon substrate and a piezoelectric substrate, The silicon substrate and the piezoelectric substrate are joined together via a bonding layer. The bonding layer includes at least a silicon oxide film layer, The silicon substrate is pore-rich, and the interstitial oxygen concentration of the bulk layer is 2.0E17 to 1.3E18 atoms / cm³. 3 And, A composite substrate characterized in that the roughness of the bonding surface side of the silicon substrate is greater than the roughness of the non-bonding surface side.

12. The composite substrate according to claim 11, characterized in that the silicon substrate has a DZ layer on the bonding surface side and a bulk layer on the non-bonding surface side in which oxygen precipitates are formed.

13. The composite substrate according to claim 11, characterized in that the roughness Rms on the bonding surface side of the silicon substrate is 0.2 to 5.0 nm, and the roughness Rms on the non-bonding surface side is 0.05 to 0.5 nm.

14. An elastic wave device comprising a composite substrate according to any one of claims 11 to 13, and an electrode provided on the piezoelectric substrate.

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