Indication device

Abstract

To provide a display device that can suppress long-term deterioration in reliability. [Solution] The display device includes a transistor connected to the third node, a transistor connected between the third node and the fourth node having a gate electrode connected to the second node, a transistor connected between the second node and the fourth node, a transistor connected between the initialization voltage line and the third node, a transistor connected between the fourth node and the fifth node, a transistor connected between the reference voltage power line and the first node, a transistor connected between the reference voltage line and the third node, a transistor connected between the power line and the fifth node, a capacitive element connected between the first node and the second node, a capacitive element connected between the first node and the third node, and a light-emitting element connected to the fifth node.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device.

Background Art

[0002] In recent years, display devices including light-emitting elements have been mounted on televisions, smartphones, etc. and have become widespread. For example, a display device includes a plurality of pixels and a control circuit for driving the plurality of pixels. Each of the plurality of pixels includes a plurality of transistors, a capacitive element, and a light-emitting element. The light-emitting element is an element that emits light by a self-emission method. For example, it is a light-emitting diode (LED), a micro light-emitting diode (micro LED), or an organic electroluminescence (EL) element. The control circuit in the display device can supply a voltage to each of the plurality of pixels and cause a current corresponding to the supplied voltage to flow through the light-emitting element included in each of the plurality of pixels. Each of the light-emitting elements emits light with a luminance corresponding to the current flowing through the light-emitting element, and a pixel including the light-emitting element can display an image with a gradation corresponding to the luminance.

[0003] For example, Non-Patent Document 1 discloses an active matrix organic light-emitting diode display device (AMOLED). A pixel in the display device described in Non-Patent Document 1 includes seven transistors (T1 to T7), two capacitive elements (CVdt, CVth) connected in series, and one light-emitting element (Pix.OLED). Further, the driving method of the display device described in Non-Patent Document 1 includes a program period (Programming phase) in which a driving voltage Vdd is supplied to a connection point (N2) of two capacitive elements by transistor T5 or T6, and acquisition of image data (Vdt refresh) and detection of a threshold voltage (Vth detection) are independently executed.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

[0005] For example, if a large voltage, such as a drive voltage, is applied to a capacitive element, the load on the element increases, which may impair the long-term reliability of the element. Furthermore, in recent years, display devices including light-emitting elements have been required to drive at higher speeds to accommodate high resolution, large screens, or high frequencies. Moreover, when display devices including light-emitting elements support high resolution, large screens, or high frequencies, the power consumption of such devices is expected to increase, and therefore, it is required to suppress the increase in power consumption of such devices.

[0006] In view of these challenges, one embodiment of the present invention aims to provide a display device capable of suppressing long-term reliability degradation. Another embodiment of the present invention aims to provide a display device capable of high-speed operation. Yet another embodiment of the present invention aims to provide a display device capable of suppressing increased power consumption. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention is a display device including a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, wherein each of the plurality of pixels has a first transistor electrically connected between an image data signal line to which a data voltage is supplied and a sixth node, and a gate electrode electrically connected to a second node, and a second transistor electrically connected between a third node and a fourth node electrically connected to the sixth node, and a third transistor electrically connected between the second node and the fourth node to which switching is controlled using a second control signal, and a fourth transistor electrically connected between an initialization voltage power line to which an initialization voltage is supplied and a third node to which switching is controlled using a second control signal, and a fourth control signal The device includes: a fifth transistor whose switching is controlled using a signal and is electrically connected between the fourth node and the fifth node; a sixth transistor whose switching is controlled using a fifth control signal and is electrically connected between a reference voltage power line supplied with a reference voltage and the first node; a seventh transistor whose switching is controlled using a sixth control signal and is electrically connected between a reference voltage line supplied with a reference voltage and the third node; an eighth transistor whose switching is controlled using a fifth control signal and is electrically connected between a power line supplied with a constant voltage and the fifth node; a first capacitive element electrically connected between the first node and the second node; a second capacitive element electrically connected between the first node and the sixth node; and a light-emitting element electrically connected between the power line and the fifth node.

[0008] A display device according to one embodiment of the present invention is a display device including a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, wherein each of the plurality of pixels has a first transistor electrically connected between a second node and an image data signal line to which a data voltage is supplied and whose switching is controlled using a first control signal, and a gate electrode electrically connected to the second node, and a second transistor electrically connected between a third node and a fourth node, a third transistor electrically connected between a second node and a fourth node to which switching is controlled using a second control signal, and whose switching is controlled using a third control signal, and whose switching is controlled between a third node and an initialization voltage power supply line to which an initialization voltage is supplied, and a fifth transistor electrically connected between a fourth node and a fifth node to which switching is controlled using a fourth control signal. The device includes a transistor, a sixth transistor whose switching is controlled using a fifth control signal and which is electrically connected between a reference voltage power line supplied with a reference voltage and the first node, a seventh transistor whose switching is controlled using a fourth control signal and which is electrically connected between a reference voltage line supplied with a reference voltage and the third node, an eighth transistor whose switching is controlled using a fifth control signal and which is electrically connected between a power line supplied with a constant voltage and the fifth node, a ninth transistor whose switching is controlled using a second control signal and which is electrically connected between a reset voltage power line supplied with a reset voltage and the fourth node, a second capacitive element electrically connected between the first node and the second node, a first capacitive element electrically connected between the first node and the third node, and a light-emitting element electrically connected between the power line and the fifth node. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram showing the configuration of a display device according to the first embodiment of the present invention. [Figure 2]This is a schematic diagram showing the input signals to the pixel circuit according to the first embodiment of the present invention. [Figure 3] This is a circuit diagram showing the configuration of a pixel circuit according to one embodiment of the present invention. [Figure 4] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 5] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 6] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 7] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 8] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 9] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 10] This is an end view showing the end face cut along A1-A2 in the layout shown in Figure 9. [Figure 11] This is an end view showing the end face cut along B1-B2 in the layout shown in Figure 9. [Figure 12] This is an end view showing the end face cut along C1-C2 in the layout shown in Figure 9. [Figure 13] This is a sequence diagram showing a method for manufacturing a display device according to the first embodiment of the present invention. [Figure 14] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 15] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 16] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 17] This is a plot diagram showing the relationship between potential difference and capacitance value according to the first embodiment of the present invention. [Figure 18] This is a schematic diagram showing the configuration of a display device according to the second embodiment of the present invention. [Figure 19]It is a block diagram showing the configuration of a control circuit according to a second embodiment of the present invention. [Figure 20] It is a circuit diagram showing the circuit configuration of a scan driver according to a second embodiment of the present invention. [Figure 21] It is a schematic diagram showing an input signal to a pixel circuit according to a second embodiment of the present invention. [Figure 22] It is a circuit diagram showing the configuration of a pixel circuit according to a second embodiment of the present invention. [Figure 23] It is a timing chart of a display device according to a second embodiment of the present invention. [Figure 24] It is a timing chart of a display device according to a second embodiment of the present invention. [Figure 25] It is a timing chart of a control circuit according to a second embodiment of the present invention. [Figure 26] There is a timing chart of a pixel circuit according to a second embodiment of the present invention. [Figure 27] It is a timing chart of a pixel circuit according to a second embodiment of the present invention. [Figure 28] There is a timing chart of a pixel circuit according to a second embodiment of the present invention. [Figure 29] It is a schematic diagram showing the configuration of a display device according to a third embodiment of the present invention. [Figure 30] It is a schematic diagram showing an input signal to a pixel circuit according to a third embodiment of the present invention. [Figure 31] It is a circuit diagram showing the configuration of a pixel circuit according to a third embodiment of the present invention. [Figure 32] It is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 33] It is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 34] There is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 35] It is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 36]This is a schematic diagram showing the input signals to the pixel circuit according to the fourth embodiment of the present invention. [Figure 37] This is a circuit diagram showing the configuration of a pixel circuit according to a fourth embodiment of the present invention. [Figure 38] This is a timing chart of a display device according to the fourth embodiment of the present invention. [Figure 39] This is a timing chart of a pixel circuit according to the fourth embodiment of the present invention. [Figure 40] This is a timing chart of a pixel circuit according to the fourth embodiment of the present invention. [Figure 41] This is a timing chart of a pixel circuit according to the fourth embodiment of the present invention. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms, and is not limited to the embodiments described below. In addition, the drawings may schematically represent the width, thickness, shape, and configuration of each part compared to the actual embodiments in order to make the explanation clearer, but these are merely examples and do not limit the interpretation of the present invention. The letters "1st" and "2nd" attached to each element are convenient indicators used to distinguish each element and have no further meaning unless otherwise specified.

[0011] Furthermore, in this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Moreover, these expressions do not exclude cases where α includes other elements.

[0012] In the specification of this application, when the terms "identical" and "identical" are used, the terms "identical" and "identical" may include errors within the scope of the design.

[0013] For example, one embodiment of the present invention is a display device that uses an EL element as a self-emissive light-emitting element. For example, a display device that uses an EL element may be called a self-emissive display device, an EL display device, or the like.

[0014] [1. First Embodiment] [1-1. Overview of the display device 10] Referring to Figure 1, an overview of the display device 10 according to the first embodiment will be described. Figure 1 is a schematic diagram showing the configuration of the display device 10. The configuration of the display device 10 shown in Figure 1 is an example, and the configuration of the display device 10 is not limited to the configuration shown in Figure 1.

[0015] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC200), and an IC chip 110. The display device 10 also includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0016] In the display area 22, multiple pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. A pixel 180 is the smallest unit that constitutes a part of the image displayed in the display area 22. Each of the multiple pixels 180 may correspond to, for example, a sub-pixel R, sub-pixel G, and sub-pixel B. Three sub-pixels may form one pixel. There are no restrictions on the arrangement of the pixels 180, and the arrangement of multiple pixels 180 may be, for example, a stripe arrangement. The arrangement of the display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0017] Sub-pixels R, G, and B are configured to display images of different colors from each other. For example, each of sub-pixels R, G, and B includes a light-emitting element containing a light-emitting layer that emits red, green, and blue light, respectively. By supplying an arbitrary voltage or current to each of the three sub-pixels, the display device 10 can display an image.

[0018] The peripheral area 24 is provided with an IC chip 110 and two control circuits 120. The two control circuits 120 are located on the left and right sides of the display area 22. The IC chip 110 is connected to the terminal section 150 using connection wires 341. Each of the two control circuits 120 is connected to the IC chip 110 using connection wires 342. The peripheral area 24 is sometimes called the frame area. The connection wire 341 may be referred to as a connection wire 341 on its own, or as a bundle of multiple connection wires 341. Similarly to the connection wire 341, the connection wire 342 may be referred to as a connection wire 342 on its own, or as a bundle of multiple connection wires 342.

[0019] The terminal area 26 is provided with a terminal section 150 and an FPC 200 electrically connected to the terminal section 150. The terminal area 26 is the area opposite to the area where the display area 22 is provided, along the first direction D1, relative to the peripheral area 24.

[0020] The FPC200 is connected to an external device (not shown) outside the display device 10. The display device 10 is connected to the external device via the FPC200 and terminals 150 connected to the FPC. Control signals and voltages are transmitted from the external device to the display device 10 via the FPC200 and terminals 150 connected to the FPC. The display device 10 uses the received control signals and voltages from the external device to drive each pixel 180 provided on the display device 10. As a result, the display device 10 can display an image in the display area 22.

[0021] The IC chip 110 supplies signals, voltages, etc., to drive each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via the FPC 200, terminal section 150, and connecting wiring 341.

[0022] Each of the IC chip 110 and the two control circuits 120 may be referred to as a control circuit individually, and a group of circuits including part or all of each of the IC chip 110 and the two control circuits 120 may also be referred to as a control circuit.

[0023] [1-2. Configuration of IC chip 110] Referring to Figure 1, the outline of the IC chip 110 will be described. The IC chip 110 is located adjacent to the display area 22 along a first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0024] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on ON and OFF signals supplied to the selection signal. The selection circuit is selected by the ON signal supplied to the selection signal and supplies an image data signal SL(m), including the data signal VDATA, to the image data signal line 321 and the pixels 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to the IC chip 110 via the FPC 200 and the terminal section 150 connected to the FPC. For example, the data signal VDATA (image data signal SL(m)) includes a data voltage between voltage VSIGL (see Figure 5) and voltage VSIGH (see Figure 5). Voltage VSIGH is greater than voltage VSIGL. Voltage VSIGL is sometimes called the first voltage, and voltage VSIGH is sometimes called the second voltage.

[0025] For example, the ON signal is a signal containing a voltage that conducts the selection circuit (switch), and the OFF signal is a signal containing a voltage that disconnects the selection circuit (switch). In the present invention, the ON signal may be a high-level voltage (potential) (High, HI) and the OFF signal may be a low-level voltage (potential) (Low, LO), or the ON signal may be a low-level voltage (potential) (Low, LO) and the OFF signal may be a high-level voltage (potential) (High, HI). The high-level voltage is greater than (higher than) the low-level voltage. In one example of the display device according to one embodiment of this specification, the ON signal is a high-level voltage and the OFF signal is a low-level voltage.

[0026] [1-3. Configuration of Control Circuit 120] Referring to Figure 1, the control circuit 120 will be outlined. Two control circuits 120 are located adjacent to each other on both sides of the display area 22 along a second direction D2. Scan signal lines 330, 331, 332, 333, and 334 extend from the control circuits 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. As an example, each scan signal line of the display device 10 shown in Figure 1 is connected to both of the two control circuits 120. Each scan signal line may be connected to one of the two control circuits 120. That is, the nth scan signal line may be electrically connected to the control circuit 120 on the right side of the display area 22 along the second direction D2, and the (n+1)th scan signal line may be electrically connected to the control circuit 120 on the left side of the display area 22 along the second direction D2. The numerical value n is a positive integer.

[0027] The control circuit 120 includes a shift register circuit 130 and a scan driver circuit 160. For example, the control circuit 120 is a gate driver and receives control signals including a clock signal, a start pulse, and multiple enable signals, as well as voltages such as the drive voltage VDDEL (see Figure 2) and the reference voltage VSSEL (see Figure 2). The control circuit 120 can sequentially select scan lines based on the input of control signals and power supply.

[0028] The shift register circuit 130 is electrically connected to the scan driver circuit 160. The shift register circuit 130 includes multiple shift registers (not shown). The shift register circuit 130 is supplied with the above-mentioned multiple control signals via multiple connection lines 342, the drive voltage VDDEL is supplied via the drive power line PVDD (see Figure 2), and the reference voltage VSSEL is supplied via the reference voltage line PVSS (see Figure 2). Based on the above-mentioned multiple control signals, the shift register circuit 130 generates multiple output signals (not shown) that are shifted at different timings and outputs them sequentially to the scan driver circuit 160.

[0029] The scan driver circuit 160 includes multiple scan drivers. For example, multiple output signals are supplied to the multiple scan drivers from the shift register circuit 130, and the above-mentioned multiple enable signals are supplied from the IC chip 110 via multiple connection lines 342, the drive voltage VDDEL is supplied via the drive power line PVDD, and the reference voltage VSSEL is supplied via the reference voltage line PVSS. Based on the multiple output signals and the multiple enable signals, the multiple scan drivers sequentially supply scan signals with different timings (for example, the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n)), and the fifth scan signal SC5(n)) to each scan signal line, and also drive the pixels 180 (pixel circuit 181) electrically connected to each scan signal line. For example, the fourth scan signal SC4(n) and the scan signal line 333 to which the fourth scan signal SC4(n) is supplied are so-called scan signals and scan signal lines.

[0030] [1-4. 180-pixel configuration] Referring to Figures 1 to 3, the overview of the pixel 180 and pixel circuit 181 will be explained. Figure 2 is a schematic diagram showing the input signals to the pixel circuit 181 included in the pixel 180. Figure 3 is a circuit diagram showing the configuration of the pixel circuit 181. Figures 2 and 3 show the configuration of the pixel circuit 181 of the pixel 180 shown in Figure 1 as an example. The configuration of the pixel 180 and pixel circuit 181 is not limited to the configurations shown in Figures 1 to 3. Configurations identical or similar to those in Figure 1 will be explained as necessary.

[0031] Pixel circuit 181 is a circuit for driving pixel 180. The pixel circuits of sub-pixels R, G, and B included in pixel 180 are the same as those of pixel circuit 181, but the color of light emitted by the light-emitting OLED differs. In the following explanation, a light-emitting OLED that emits red light will be described as an example.

[0032] As shown in Figure 2, the pixel circuit 181 is supplied with image data signal SL(m), a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), a reference voltage VREF, and an initialization voltage VINI. In addition, the pixel circuit 181 is supplied with a drive voltage VDDEL and a reference voltage VSSEL as a power supply to drive the pixel 180. For example, the reference voltage VREF, initialization voltage VINI, drive voltage VDDEL, and reference voltage VSSEL may be constant voltages, or they may be variable voltages that fluctuate according to the timing of each signal.

[0033] The first scan signal SC1(n) is supplied to scan signal line 330, the second scan signal SC2(n) is supplied to scan signal line 331, the third scan signal SC3(n) is supplied to scan signal line 332, the fourth scan signal SC4(n) is supplied to scan signal line 333, and the fifth scan signal SC5(n) is supplied to scan signal line 334. The first scan signal SC1(n) also functions as the seventh scan signal SC7(n), which will be described later. The first scan signal SC1(n) may be called the second control signal, the second scan signal SC2(n) may be called the fourth control signal, the third scan signal SC3(n) may be called the fifth control signal, the fourth scan signal SC4(n) may be called the first control signal, and the fifth scan signal SC5(n) may be called the sixth control signal.

[0034] Furthermore, the reference voltage VREF is supplied to the reference voltage power line SVR, the initialization voltage VINI is supplied to the initialization voltage power line SVI, the drive voltage VDDEL is supplied to the drive power line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. For example, each of the reference voltage power line SVR, initialization voltage power line SVI, drive power line PVDD, and reference voltage line PVSS is electrically connected to a different connection wiring 342. Alternatively, each of the reference voltage power line SVR, initialization voltage power line SVI, drive power line PVDD, and reference voltage line PVSS may be connected to a different connection wiring 342.

[0035] For example, the reference voltage VREF, initialization voltage VINI, drive voltage VDDEL, and reference voltage VSSEL are supplied to the IC chip 110 from an external device via the FPC 200, terminal section 150, and connection wiring 341. Also, for example, the reference voltage VREF, initialization voltage VINI, drive voltage VDDEL, and reference voltage VSSEL are supplied from the IC chip 110 to multiple pixels 180 (pixel circuits 181) via connection wiring 342, precharge voltage power line SVP, reference voltage power line SVR, initialization voltage power line SVI, drive power line PVDD, and reference voltage line PVSS. Although not shown in the diagram, the reference voltage VREF, initialization voltage VINI, drive voltage VDDEL, and reference voltage VSSEL may be connected from an external device via the FPC 200, terminal section 150, and connection wiring 341, without going through the IC chip 110 and connection wiring 342, to the reference voltage power line SVR, initialization voltage power line SVI, drive power line PVDD, and reference voltage line PVSS, and may be supplied to multiple pixels 180 (pixel circuit 181). For example, the reference voltage VREF, initialization voltage VINI, and reference voltage VSSEL are smaller than the drive voltage VDDEL.

[0036] As shown in Figure 3, the system includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a capacitive element CV, a capacitive element CD, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source electrode and drain electrode) consisting of a first electrode and a second electrode. Each of the capacitive element CV, the capacitive element CD, and the light-emitting element OLED has a pair of electrodes consisting of a first electrode and a second electrode. Note that the capacitive element CV may be called the first capacitive element, and the capacitive element CD may be called the second capacitive element.

[0037] For example, the first transistor T1 is a selection transistor. The first transistor T1 has the function of supplying the image data signal SL(m) to the sixth node N6. Since the sixth node N6 of the pixel circuit 181 is connected to the third node N3, the first transistor T1 also has the function of supplying the image data signal SL(m) to the third node N3.

[0038] For example, the second transistor T2 is a drive transistor. Between the gate electrode 622 and the first electrode (source) 624 of the second transistor T2, a threshold voltage VTH is acquired based on the initialization voltage VINI, and the acquired threshold voltage VTH is applied to the capacitive element CV, thereby performing the operation of acquiring and saving the threshold voltage VTH. Furthermore, the second transistor T2 controls the amount of current flowing from the drive power line PVDD to the light-emitting element OLED based on the gate voltage (voltage between the gate electrode 622 and the first electrode (source) 624) which has been corrected for variations in the threshold voltage VTH, and the input image data signal SL(m). In other words, the second transistor T2 has the function of supplying current to the light-emitting element OLED from the drive voltage VDDEL according to the display gradation (brightness), thereby causing the light-emitting element OLED to emit light.

[0039] The third transistor T3 conducts the second node N2 and the fourth node N4, making the potential difference between the gate electrode 622 of the second transistor T2 and the second electrode 626 0V. When the threshold voltage VTH is acquired, it transmits the decrease in drain potential (potential at node N4) due to discharge to the gate (node ​​N2), and plays a role in stopping the discharge when Vgs (the difference between the gate potential and the source potential (potential difference)) reaches the threshold voltage Vth.

[0040] The fourth transistor T4 has the function of supplying the initialization voltage VINI to the third node N3 (sixth node N6) by conducting the initialization voltage power line SVI to the third node N3, thereby initializing the third node N3 (sixth node N6).

[0041] The fifth transistor T5 has the function of making the fourth node N4 (the second electrode 626 of the second transistor T2) and the fifth node N5 (the first electrode 32 of the light-emitting element OLED) electrically conductive.

[0042] The sixth transistor T6 connects the first node N1 to the reference voltage power line SVR, supplying the reference voltage power line SVR to the first node N1, and has the function of fixing the potential of the first node N1 when the threshold voltage VTH is acquired and when the image data signal SL(m) is written.

[0043] The seventh transistor T7 has the function of connecting the third node N3 (the sixth node N6) with the reference voltage line PVSS, thereby supplying the reference voltage VSSEL to the third node N3.

[0044] The eighth transistor T8 has the function of making the first electrode 32 and the second electrode 34 of the light-emitting element OLED conduction, thereby making the potential difference between the electrodes of the light-emitting element OLED zero and suppressing the emission of light from the light-emitting element OLED during periods other than the light emission period, and the function of supplying the drive voltage VDDEL to the source and drain electrodes (i.e., node N4) of the second transistor T2 via the fifth transistor T5 during the initialization period before the threshold voltage VTH acquisition operation.

[0045] As will be explained in more detail later, the capacitive element CV has the function of holding (storing) the charge corresponding to the threshold voltage VTH of the second transistor T2.

[0046] The capacitive element CD has the function of holding (storing) a charge corresponding to the data voltage (voltage between voltage VSIGL (see Figure 39) and voltage VSIGH (see Figure 39)) contained in the image data signal SL(m) supplied to the third node N3 (sixth node N6).

[0047] The light-emitting OLED has diode characteristics and functions to emit light based on the current flowing through it. The current flowing through the light-emitting OLED is the drain current (current Ion) of the second transistor T2. The first electrode 32 of the light-emitting OLED is the cathode electrode, and the second electrode 34 of the light-emitting OLED is the anode electrode.

[0048] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the third node N3 (sixth node N6), the first electrode 624 of the second transistor T2, the second electrode 646 of the fourth transistor T4, and the second electrode 54 of the capacitive element CD. The scan signal line 333 is supplied with a fourth scan signal SC4(n). The switching of the first transistor T1 is controlled using the fourth scan signal SC4(n). In other words, the conduction state (on state) and non-conduction state (off state) of the first transistor T1 are controlled by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 is in a non-conducting state. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 is in a conducting state.

[0049] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, the first electrode 42 of the capacitive element CV, and the first electrode 634 of the third transistor T3. The second electrode 626 is electrically connected to the fourth node N4, the second electrode 636 of the third transistor T3, and the first electrode 654 of the fifth transistor T5. The threshold voltage of the second transistor T2 is the threshold voltage VTH. The second transistor T2 controls the amount of current flowing through the light-emitting element OLED according to the potential difference Vgs between the voltage supplied to the gate electrode 622 (second node N2) and the voltage supplied to the first electrode 624 (third node N3), and the potential difference Vds between the second electrode 626 (fourth node N4) and the first electrode 624. For example, if the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is less than the threshold voltage VTH, the second transistor T2 becomes non-conductive, and no current flows to the light-emitting element OLED, so pixel 180 displays black. For example, if the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is greater than or equal to the threshold voltage VTH, and the potential difference Vds between the voltage supplied to the fourth node N4 and the voltage supplied to the third node N3 is greater than 0V, the second transistor T2 becomes conductive, and the current flowing to the light-emitting element OLED is controlled according to the magnitude of the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, based on the display gradation, and the light-emitting element OLED emits light at a brightness based on the display gradation.

[0050] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 330. The scan signal line 330 is supplied with a first scan signal SC1(n). The switching of the third transistor T3 is controlled using the first scan signal SC1(n). In other words, the third transistor T3 is controlled to be either conducting (on) or not conducting (off) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in a non-conducting state, and when the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in a conducting state.

[0051] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 330. The first electrode 644 is electrically connected to the initialization voltage power line SVI. The switching of the fourth transistor T4 is controlled using the first scan signal SC1(n). In other words, the conduction state (on state) and non-conduction state (off state) of the fourth transistor T4 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the fourth transistor T4 is in a non-conducting state, and when the signal supplied to the scan signal line 330 is HI, the fourth transistor T4 is in a conduction state.

[0052] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 331. The second electrode 656 is electrically connected to the first electrode 32 of the light-emitting element OLED and the first electrode 684 of the eighth transistor T8. The scan signal line 331 is supplied with a second scan signal SC2(n). The switching of the fifth transistor T5 is controlled using the second scan signal SC2(n). In other words, the fifth transistor T5 is controlled to be in a conduction state (on state) or a non-conduction state (off state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fifth transistor T5 is in a non-conduction state, and when the signal supplied to the second scan signal SC2(n) is HI, the fifth transistor T5 is in a conduction state.

[0053] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 332. The first electrode 664 is electrically connected to the reference voltage power line SVR. The second electrode 666 is electrically connected to the first node N1, the second electrode 44 of the capacitance element CV, and the first electrode 52 of the capacitance element CD. The scan signal line 332 is supplied with a third scan signal SC3(n). The switching of the sixth transistor T6 is controlled using the third scan signal SC3(n). In other words, the conduction state (on state) and non-conduction state (off state) of the sixth transistor T6 are controlled by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the sixth transistor T6 is in a non-conducting state, and when the signal supplied to the third scan signal SC3(n) is HI, the sixth transistor T6 is in a conducting state.

[0054] The seventh transistor T7 includes a gate electrode 6·BR>V2, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 334. The first electrode 674 is electrically connected to the reference voltage line PVSS. The scan signal line 334 is supplied with the fifth scan signal SC5(n). The switching of the seventh transistor T7 is controlled using the fifth scan signal SC5(n). In other words, the seventh transistor T7 is controlled to be either conducting (on) or not conducting (off) by the fifth scan signal SC5(n). When the signal supplied to the fifth scan signal SC5(n) is LO, the seventh transistor T7 is in a non-conducting state, and when the signal supplied to the fifth scan signal SC5(n) is HI, the seventh transistor T7 is in a conducting state.

[0055] The eighth transistor T8 includes a gate electrode 682, a first electrode 684, and a second electrode 686. The gate electrode 682 is electrically connected to the scan signal line 332 and the gate electrode 662 of the sixth transistor T6. The second electrode 686 is electrically connected to the second electrode 34 of the light-emitting element OLED and the drive power line PVDD. As described above, the scan signal line 332 is supplied with the third scan signal SC3(n). The switching of the eighth transistor T8 is controlled using the third scan signal SC3(n). In other words, the eighth transistor T8 is controlled to be either conducting (on) or not conducting (off) by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the eighth transistor T8 is in a non-conducting state, and when the signal supplied to the third scan signal SC3(n) is HI, the eighth transistor T8 is in a conducting state.

[0056] As will be explained in more detail later, the capacitive element CV has the function of holding (storing) the charge corresponding to the threshold voltage VTH of the second transistor T2.

[0057] The capacitive element CD has the function of holding (storing) a charge corresponding to the data voltage (voltage between voltage VSIGL (see Figure 5) and voltage VSIGH (see Figure 5)) contained in the image data signal SL(m) supplied to the first node N1.

[0058] The first electrode 32 of the light-emitting OLED is the cathode electrode, and the second electrode 34 of the light-emitting OLED is the anode electrode.

[0059] For example, the conduction state of a transistor in the display device 10 indicates that the source electrode and drain electrode of the transistor are conducting, and the transistor is ON. The non-conducting state of a transistor in the display device 10 indicates that the source electrode and drain electrode of the transistor are not conducting, and the transistor is OFF. In each transistor, the source electrode and drain electrode may be swapped depending on the voltage or potential supplied to each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is OFF, a small current may flow, such as leakage current.

[0060] Each transistor shown in Figure 3 is an n-channel field-effect transistor, and its channel region contains a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties. For example, crystalline silicon can be used as the channel region containing a Group 14 element. The crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. Also, for example, a metal oxide exhibiting semiconductor properties can be used as the oxide exhibiting semiconductor properties. As an example, an oxide semiconductor containing two or more metals, including indium (In), can be used as the metal oxide exhibiting semiconductor properties. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanides may be used as the metal oxide exhibiting semiconductor properties. Furthermore, the metal oxide exhibiting semiconductor properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline materials.

[0061] For example, each transistor in the display device 10 is formed using a thin-film transistor (TFT). The channel region of each transistor may be formed using single-crystal silicon such as a silicon wafer or SOI substrate. Furthermore, if the display device 10 includes both a transistor containing a group 14 element in its channel region and a transistor containing an oxide exhibiting semiconductor properties in its channel region, the manufacturing method of the display device 10 includes forming a semiconductor layer containing a group 14 element and forming a semiconductor layer containing an oxide exhibiting semiconductor properties (e.g., an oxide semiconductor layer). Depending on the application and specifications, the transistor configuration, the connection of the holding capacitance, the power supply voltage, etc., of the display device 10 may be appropriately adapted.

[0062] For example, the leakage current of a transistor made of a metal oxide with semiconductor properties is extremely small. Therefore, when using a transistor made of a metal oxide with semiconductor properties, the charge corresponding to the voltage (potential) written to the capacitive element is less likely to escape from the capacitive element. As a result, by using a transistor made of a metal oxide with semiconductor properties, it becomes possible to retain the charge written to the capacitive element for a long time. Also, under the same conditions for the gate-source voltage (potential difference between the gate electrode and the source electrode (Vgs)) and the source-drain voltage (for example, the potential difference between the source electrode and the drain electrode (Vds)), the drain current of a transistor made of a metal oxide with semiconductor properties may be greater than the drain current of a transistor made of crystalline silicon (for example, low-temperature polysilicon (LTPS)). As a result, under the same conditions for the drain current, the gate-source voltage and source-drain voltage of a transistor made of a metal oxide with semiconductor properties can be made smaller than those of a transistor made of crystalline silicon. Therefore, by using a transistor made of a metal oxide with semiconductor properties, the power consumption of the display device 10 can be suppressed.

[0063] [1-5. Method for driving the display device 10] The driving method of the display device 10 will be explained with reference to Figures 4 to 8. Figures 4 to 8 are schematic diagrams showing the timing chart of the display device 10. Configurations identical or similar to those in Figures 1 to 3 will be explained as necessary.

[0064] In each embodiment, the horizontal axis of the timing chart represents time. In addition, in the image data signal SL(m) including the data signal VDATA in each embodiment, as an example, the data signal VDATA supplied to the selected pixel (pixel circuit) is shown by a diagonal line as a data voltage between VSIGL and VSIGH, while the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is omitted and shown by a solid line. In reality, in each embodiment, the image data signal SL(m) including the data signal VDATA also continuously or intermittently supplies the voltage of the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit).

[0065] For example, the frequency used to drive the display device 10 is 60Hz, and one frame (1FRAME) is driven at 60Hz. For example, Figure 4 shows the current frame (KthFRAME), a portion of the frame immediately preceding it (K-1stFRAME), and a portion of the frame immediately following it (K+1stFRAME). Figures 5 to 8 show the emission period PEM of the frame immediately preceding it (K-1stFRAME), the period PIN, period PVH, period PWR, and period PEM of the current frame (KthFRAME), and the period PIN, period PVH, period PWR, and period PEM of the frame immediately following it. Figures 5 to 8 also show one horizontal period (horizontal period HRP) for a single pixel 180 (pixel circuit 181).

[0066] First, with reference to Figure 4, an overview of the driving method of the display device 10 will be explained. As shown in Figure 4, the driving method of the display device 10 includes at least an initialization period PIN (period PIN), a threshold voltage acquisition and holding period PVH (period PVH), and a write period PWR (period PWR) within one frame. In the pixel 180 (pixel circuit 181) included in the display device 10, period PWR is executed after period PVH. Furthermore, after the light emission period PEM of the frame immediately preceding the current frame, the period PIN, period PVH, and period PWR of the current frame are executed, and after the light emission period PEM of the current frame, the period PIN, period PVH, and period PWR of the frame immediately following the current frame are executed.

[0067] Period PIN is the period for initializing the second node, the third node N3 (sixth node N6), and the fourth node N4. Period PVH is the period during which the threshold voltage of the second transistor T2 is obtained by performing an operation to make the potential difference Vgs of the second transistor T2 equal to the threshold voltage, and a charge equivalent to the threshold voltage is held in the second node N2 (first electrode 42 of the capacitive element CV). Period PWR is the period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181). That is, period PWR is the period during which the data voltage is supplied to the sixth node N6 (second electrode 54 of the capacitive element CD), and a charge equivalent to the data voltage is held. Furthermore, the light emission period PEM is the period during which the pixel 180 emits light based on the written data voltage and the obtained threshold voltage of the second transistor T2 (threshold voltage correction).

[0068] Next, with reference to Figures 4 to 8, a specific method for driving the pixels 180 (pixel circuit 181) of the display device 10 will be explained.

[0069] Pixel 180 (pixel circuit 181) is input to a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), an image data signal SL(m) including the data signal VDATA, an initialization voltage VINI, and a reference voltage VREF. For example, pixel 180 (pixel circuit 181) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180 (pixel circuit 181) according to the timing of each signal. The same operation is performed for all pixels 180 (pixel circuits 181), and based on the image data signal SL(m) input to all pixels 180 (pixel circuits 181), the image of the current frame corresponding to 1 FRAME is displayed in the display area 22 of the display device 10.

[0070] For example, the voltage (potential) supplied to each signal and each node during each period of each frame in the timing charts shown in Figures 4 to 8 is shown in Table 1.

[0071] [Table 1]

[0072] For example, as shown in Table 1, when the voltage VSIGH is 4V, pixel 180 supplied with the voltage VSIGH does not emit light and appears black. Also, for example, when the voltage VSIGL is 0V, pixel 180 supplied with the voltage VSIGL emits light and produces white color. For example, the threshold voltage VTH of the second transistor T2 is 1V, the voltage VH(HI) is 8V, the voltage VL(LO) is -5V, the initialization voltage VINI is 3V, the reference voltage VREF is 2V, the drive voltage VDDEL is 6V, the reference voltage VSSEL is -2V, the voltage VM is 5V, and the voltage VN is -5V. That is, the reference voltage VREF is different from the initialization voltage VINI, and both the reference voltage VREF and the initialization voltage VINI are greater than the reference voltage VSSEL and less than the drive voltage VDDEL.

[0073] [1-5-1. First example of a method for driving the display device 10] Referring to Figure 5 and Table 1, a first example of a driving method for the display device 10 will be described. The driving method shown in the first example includes the following: Pixel 180 (pixel circuit 181) displays a white image based on the voltage VSIGH of the data signal VDATA in the frame immediately preceding the current frame (KthFRAME) (K-1stFRAME); and then Pixel 180 (pixel circuit 181) displays a black image based on the voltage VSIGL of the data signal VDATA in the KthFRAME. In other words, the driving method shown in the first example includes displaying images of different colors in consecutive frames.

[0074] For each period, an image data signal SL(m) containing the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data (analog voltage) containing a voltage between VSIGL and VSIGH. For example, during the PWR period, a selection signal (not shown in the figure) is used to select a voltage between VSIGL and VSIGH, and this voltage is supplied to the image data signal SL(m). For example, during periods other than the PWR period, the data signal VDATA is supplied to a pixel other than the selected pixel 180 (pixel circuit 181).

[0075] The light emission period PEM of the K-1stFRAME is the period during which pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs of the second transistor T2 ((voltage supplied to the second node N2 (voltage V(N2)) - (voltage supplied to the third node N3 (voltage V(N3)))). For example, pixel 180 (pixel circuit 181) emits red light, and three pixels using a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180 emit white light.

[0076] For example, during the light emission period PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA to all pixels except the selected pixel 180 (pixel circuit 181). The first scan signal SC1(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, while the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are in the off state, while the fifth transistor T5 and the seventh transistor T7 are in the on state. Also, for example, the voltage held at the third node N3 (sixth node N6) is voltage Vnd (-2V), the voltage held at the second node N2 is voltage Vnq (2V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the ON state, and a current Ion based on the potential difference Vgs and potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the K-1stFRAME can be flowed from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. The voltage held at the first node N1 is 0V due to capacitive coupling by the capacitive elements CV and CD. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels using a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180 emit white light.

[0077] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to all pixels except the selected pixel 180 (pixel circuit 181). Initially, the fifth scan signal SC5(n) changes from a HI state to a LO state. When the fifth scan signal SC5(n) is supplied with LO, the third scan signal SC3(n) changes from a LO state to a HI state. When the third scan signal SC3(n) is supplied with HI, the first scan signal SC1(n) changes from a LO state to a HI state. The second scan signal SC2(n) is supplied with HI, and the fourth scan signal SC4(n) is supplied with LO.

[0078] As a result, during the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the seventh transistor T7 switches from the ON state to the OFF state, and the current Ion stops flowing from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. The sixth transistor T6 and the eighth transistor T8 switch from the OFF state to the ON state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, the light emission of the light-emitting element OLED stops, and the voltage supplied to the first node N1 rises from 0V towards voltage Vnq (reference voltage VREF, 2V) until it reaches voltage Vnq. The third transistor T3 turns from the off state to the on state, the fifth transistor T5 remains on, the first transistor T1 remains off, the second node N2 and the fourth node N4 become conductive, and a voltage Vnr (drive voltage VDDEL, 6V) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). Also, the fourth transistor T4 turns from the off state to the on state, and a voltage Vnp (initialization voltage VINI, 3V) is supplied to the third node N3 (first electrode 624 of the second transistor T2) and the sixth node N6 (second electrode 616 of the first transistor T1). The potential difference Vgs is 3V (6V-3V), and the second transistor T2 is on.

[0079] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, the first node N1 is initialized with the reference voltage VREF, and the third node N3 (sixth node N6) is initialized with the initialization voltage VINI.

[0080] During period PVH, following period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA that is supplied to all pixels except the selected pixel 180 (pixel circuit 181). The second scan signal SC2(n) changes from a HI state to a LO state. The other scan signals remain in the same state as during period PIN. The fifth transistor T5 changes from an ON state to an OFF state, and the other transistors remain in the same state as during period PIN.

[0081] As a result, during period PVH, the first node N1 maintains voltage Vnq, and the third node N3 (sixth node N6) maintains voltage Vnp. The second transistor T2 is in the ON state, electrode Ion flows, and the first node N1 maintains voltage Vnq, and the third node N3 (sixth node N6) maintains voltage Vnp. Also, the fifth transistor T5 is in the OFF state, so the voltage supplied to the second node N2 and the fourth node N4 is released and gradually decreases (discharges) from voltage Vnr. When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) reaches the threshold voltage VTH, the second transistor T2 turns OFF. At this time, the voltage supplied to the second node N2 and the fourth node N4 is voltage Vnl, for example, 4V. In reality, the threshold voltage VTH varies during manufacturing, for example, 3.8V or 4.1V. The threshold voltage VTH is obtained through operations during the period PVH, and correction is applied using the obtained threshold voltage VTH.

[0082] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0083] During the period between period PVH and period PWR, or during period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGH (4V). Initially, the first scan signal SC1(n) changes from a HI state to a LO state. When the first scan signal SC1(n) is supplied with LO, the fourth scan signal SC4(n) changes from a LO state to a HI state. The third scan signal SC3(n) is supplied with HI, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with LO. The first transistor T1 changes from an off state to an on state, and the third transistor T3 and the fourth transistor T4 change from an on state to an off state. The other transistors remain in the same state as during period PVH. The voltage supplied to the second node N2 remains at voltage Vnl (e.g., 4V), and the voltage supplied to the first node N1 remains at voltage Vnq (reference voltage VREF, 2V). The voltage supplied to the third node N3 (sixth node N6) gradually increases from voltage Vnp to voltage Vnl (voltage VSIGH, e.g., 4V). At this time, the capacitive element CD maintains the potential difference (-2V relative to the sixth node N6) by holding a charge corresponding to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and Vnl (voltage VSIGH, e.g., 4V) supplied to the third node N3 (sixth node N6). In other words, the potential difference Vgs is 0V.

[0084] As described above, during the PWR period, the data signal VDATA is written to pixel 180 (pixel circuit 181). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0085] During the period following the PWR, the fourth scan signal SC4(n) changes from a HI state to a LO state. When the fourth scan signal SC4(n) is supplied with LO, the third scan signal SC3(n) changes from a HI state to a LO state. When the third scan signal SC3(n) is supplied with LO, the fifth scan signal SC5(n) changes from a LO state to a HI state. The first transistor T1, the sixth transistor T6, and the eighth transistor T8 change from the ON state to the OFF state, and the seventh transistor T7 changes from the OFF state to the ON state. The other scan signals and other transistors remain in the same state as during the PWR. The voltage supplied to the second node N2 and the voltage supplied to the third node N3 (sixth node N6) drop from voltage Vnl to voltage Vnd (-2V). That is, the potential difference Vgs is maintained at 0V. At this time, the voltage supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, drops from voltage Vnq to voltage Vnt (-4V).

[0086] In the KthFRAME emission period PEM that follows the KthFRAME period PWR, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA to all pixels except the selected pixel 180 (pixel circuit 181). Also, the second scan signal SC2(n) changes from a state where LO is supplied to a state where HI is supplied. Therefore, the fifth transistor T5 changes from the off state to the on state. Other scan signals and other transistors remain in the same state as in the KthFRAME period PWR. With the fifth transistor T5 turned on, the first electrode 32 of the light-emitting element OLED conducts with the second electrode 626 of the second transistor T2 (fourth node N4). The potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (initialization voltage VINI (3V) - voltage of data signal VDATA (voltage VSIGH, 4V) + threshold voltage VTH (1V) = 0V). Pixel 180 (pixel circuit 181) whose data signal VDATA contains the voltage VSIGH has a potential difference Vgs of 0V, and the second transistor T2 is in the off state, so no Ion flows through the drain electrode. Therefore, the light-emitting element OLED does not emit light. As a result, the red-emitting pixel 180 (pixel circuit 181) becomes black. Similarly, the blue-emitting pixel 180 and the green-emitting pixel 180 also do not emit light, so the three pixels using the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 all become black.

[0087] The display device 10 allows each node to be controlled independently. Furthermore, the display device 10 includes a configuration in which the first node N1, the second node N2, the third node N3 (the sixth node N6), the capacitive element CV, and the capacitive element CD are not directly connected to the light-emitting element OLED. Additionally, the voltages supplied to the first node N1, the second node N2, the third node N3 (the sixth node N6), the capacitive element CV, and the capacitive element CD are constant voltages such as the drive voltage VDDEL, the initialization voltage VINI, the reference voltage VREF, or the data signal VDATA. Therefore, for example, charge redistribution does not occur between the first node N1, the second node N2, and the third node N3 (the sixth node N6) and the parasitic capacitance added to the capacitive element CD, the capacitive element CV, and the light-emitting element OLED. As a result, the display device 10 can suppress fluctuations in the voltages of the first node N1, the second node N2, and the third node N3 (the sixth node N6) due to charge redistribution. Furthermore, the acquisition of the threshold voltage VTH during the period PVH is performed using the initialization voltage VINI supplied to the third node N3 as the reference voltage. As a result, the display device 10 can acquire the threshold voltage VTH in a state that is less affected by potential fluctuations due to the drive voltage VDDEL. Therefore, the display device 10 can suppress the decrease in holding potential due to charge redistribution and acquire the threshold voltage quickly and accurately. Consequently, it can accurately store and retain the data signal VDATA voltage (potential difference) with the threshold voltage corrected and supply it to the potential difference Vgs of the second transistor T2, thereby obtaining high brightness and high quality display.

[0088] Furthermore, the display device 10 has a reference voltage VREF that is different from the initialization voltage VINI. The reference voltage VREF is an intermediate voltage (intermediate voltage, intermediate potential) between the voltages VSIGH and VSIGL. As a result, the potential difference between the voltage supplied to the first electrode 52 of the capacitive element CD and the voltage supplied to the second electrode 54 is the same as the potential difference between the voltage supplied to the first electrode 42 of the capacitive element CV and the voltage supplied to the second electrode 44. Therefore, the potential difference of the capacitive element CD in the display device 10 can be suppressed from being significantly different from the potential difference of the capacitive element CV. In other words, the display device 10 can distribute the voltage applied to the capacitive elements CD and CV, thereby reducing the load on the capacitive elements CD and CV, and suppressing a decrease in the breakdown voltage of the capacitive elements CD and CV. In addition, because the display device 10 can suppress a decrease in the breakdown voltage of the capacitive elements CD and CV, the insulating film used to form the capacitive elements CD and CV can be made thinner. Therefore, in the display device 10, the area required for the capacitive elements CD and CV can be reduced, so that sufficient capacitance can be secured even when the pixel area is small.

[0089] [1-5-2. Second example of a method for driving the display device 10] Referring to Figure 6, a second example of the driving method for the pixel circuit 181 will be described. The driving method shown in the second example includes the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the frame immediately preceding the current frame (KthFRAME) (K-1stFRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the KthFRAME as well. In other words, the driving method shown in the second example includes displaying images of the same color (white) in consecutive frames. Configurations identical or similar to those in Figures 1 to 5 will be described as necessary.

[0090] The voltages (potentials) of each node during the light emission period PEM of the K-1thFRAME to the period PVH of the KthFRAME, and during the period between the KthFRAME's period PVH and the KthFRAME's period PWR, are the same as those described in "1-5-1. First Example of Driving Method of Display Device 10". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "First Example of Driving Method of Display Device 10". Therefore, configurations similar to those described in "First Example of Driving Method of Display Device 10" will be explained as needed. Note that during the KthFRAME's period PWR, the image data signal SL(m) is supplied with a data signal VDATA including VSIGL(0V) corresponding to white, and during periods other than the KthFRAME's period PWR, the same data signal VDATA as described in "1-5-1. First Example of Driving Method of Display Device 10" is supplied.

[0091] In the K-1stFRAME's light emission period PEM, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," the pixel 180 (pixel circuit 181) emits red light, and three pixels, consisting of a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180, emit white light.

[0092] In the KthFRAME period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, the first node N1 is initialized with the reference voltage VREF, and the third node N3 (sixth node N6) is initialized with the initialization voltage VINI, similar to the configuration described in "1-5-1. First example of driving method of display device 10".

[0093] During the period PVH following the period PIN, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, similar to the configuration described in "1-5-1. First Example of Driving Method of Display Device 10," and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0094] During the period between period PVH and period PWR, or during period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the second node N2 maintains a voltage Vnl (e.g., 4V), and the voltage supplied to the first node N1 maintains a voltage Vnq (reference voltage VREF, 2V). The voltage supplied to the third node N3 (sixth node N6) gradually decreases from a voltage Vnp (initialization voltage VINI, 3V) to 0V (voltage VSIGL). At this time, the capacitive element CD maintains the potential difference (2V with respect to the sixth node N6) by holding a charge equivalent to the potential difference between the voltage Vnq (reference voltage VREF, 2V) supplied to the first node N1 and the 0V (voltage VSIGL) supplied to the third node N3 (sixth node N6). Furthermore, the capacitive element CV maintains a potential difference (2V relative to the first node N1) by holding a charge equivalent to the potential difference between the voltage Vnl (e.g., 4V) supplied to the second node N2 and the voltage Vnq (reference voltage VREF, 2V) supplied to the first node N1. That is, the potential difference Vgs is 4V, which is the sum of the potential differences held by the capacitive elements CD and CV. For example, if the threshold voltage VTH fluctuates and the voltage Vnl supplied to the second node N2 becomes 3.9V, then the potential difference Vgs will be 3.9V (Vgs = (Vnl(3.9V) - VREF(2V)) + (VREF(2V) - VSIL(0V))).

[0095] As described above, during the PWR period, the data signal VDATA is written to pixel 180 (pixel circuit 181). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0096] During the period following the PWR period, the fifth scan signal SC5(n) is supplied with a HI signal, which causes the seventh transistor T7 to switch from the off state to the on state. As a result, the third node N3 (sixth node N6) is connected to the reference voltage VSSEL, and the voltage supplied to the third node N3 (sixth node N6) drops from 0V to Vnd (-2V). Consequently, the voltage at the second node N2, which is capacitively coupled by capacitive elements CV and CD, drops from Vnl to Vnq (2V). That is, the potential difference Vgs is maintained at 4V. At this time, the voltage supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, drops from Vnq to 0V.

[0097] In the KthFRAME emission period PEM that follows the KthFRAME period PWR, the potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (reference voltage VREF(2V) - voltage included in the data signal VDATA (voltage VSIGL, 0V) + (initialization voltage VINI(3V) + threshold voltage VTH(1V) - reference voltage VREF(2V) = 4V). That is, based on the data signal VDATA and the corrected threshold voltage, pixel 180 (pixel circuit 181) displays an image. This is possible. When the data signal VDATA includes the voltage VSIGL, the potential difference Vgs is 4V and the second transistor T2 is ON, so current Ion flows from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 each emit light, and the three pixels using the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 will produce white light.

[0098] The second example of the driving method for the display device 10 produces the same effects as those described in "1-5-1. First Example of Driving Method for the Display Device 10".

[0099] [1-5-3. Third example of a method for driving the display device 10] Referring to Figure 7, a third example of the driving method for the display device 10 will be described. The driving method shown in the third example includes the following: after the pixel 180 (pixel circuit 181) displays a black image based on the voltage VSIGL included in the data signal VDATA in the frame immediately preceding the current frame (KthFRAME) (K-1stFRAME), the pixel 180 (pixel circuit 181) also displays a black image based on the voltage VSIGH included in the data signal VDATA in the KthFRAME. In other words, the driving method shown in the third example includes displaying images of the same color (black) in consecutive frames. Configurations identical or similar to those in Figures 1 to 6 will be described as necessary. Configurations identical or similar to those in Figures 1 to 6 will be described as necessary.

[0100] The voltages (potentials) of each node during the KthFRAME period PVH to the KthFRAM light emission period PEM are the same as those described in "1-5-1. First Example of Driving Method for Display Device 10". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "1-5-1. First Example of Driving Method for Display Device 10". Therefore, configurations similar to those described in "1-5-1. First Example of Driving Method for Display Device 10" will be explained as needed.

[0101] In the K-1stFRAME's light emission period PEM, for example, the voltage held at the first node N1 is Vnt (-4V). Also, the voltage supplied to the second node N2 and the voltage held at the third node N3 is Vnd (-2V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, no ion flows through the drain electrode, and the light-emitting element OLED does not emit light.

[0102] As a result, the red-emitting pixel 180 (pixel circuit 181) becomes black. Similarly, the blue-emitting pixel 180 and the green-emitting pixel 180 also do not emit light, so the three pixels using the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 become black.

[0103] During the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, the sixth transistor T6 and the eighth transistor T8 switch from the off state to the on state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, the light emission of the light-emitting element OLED stops, and the voltage supplied to the first node N1 rises from voltage Vnt (-4V) towards voltage Vnq (reference voltage VREF, 2V) until it reaches voltage Vnq. The third transistor T3 turns from the off state to the on state, the fifth transistor T5 remains on, the first transistor T1 remains off, the second node N2 and the fourth node N4 become conductive, and a voltage Vnr (drive voltage VDDEL, 6V) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). Also, the fourth transistor T4 turns from the off state to the on state, and a voltage Vnp (initialization voltage VINI, 3V) is supplied to the third node N3 (first electrode 624 of the second transistor T2) and the sixth node N6 (second electrode 616 of the first transistor T1). The potential difference Vgs is 3V (6V-3V), and the second transistor T2 is on.

[0104] As described above, in the same configuration as described in "1-5-1. First Example of Driving Method for Display Device 10", in the period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, and the first node N1 is initialized with the reference voltage VREF. Further initialization occurs, and the third node N3 (sixth node N6) is initialized by the initialization voltage VINI.

[0105] In the period PVH following period PIN, similar to the configuration described in "1-5-1. First Example of Driving Method of Display Device 10," the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0106] In the PWR period following the PVH period, the data signal VDATA is written to the pixel 180 (pixel circuit 181), similar to the configuration described in "1-5-1. First Example of Driving Method of Display Device 10". In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0107] During the period following the PWR period, and during the PEM period of the KthFRAME that follows the PWR period, the pixel circuit 181 operates in the same manner as described in "1-5-1. First Example of Driving Method of Display Device 10," with a potential difference Vgs of 0V and the second transistor T2 in the off state. As a result, no ion flows through the drain electrode, and the light-emitting element OLED does not emit light. Consequently, the three pixels, consisting of the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180, appear black.

[0108] The third example of the driving method for the display device 10 produces the same effects as those described in "1-5-1. First Example of Driving Method for the Display Device 10".

[0109] [1-5-4. Fourth example of a method for driving the display device 10] Referring to Figure 8, a fourth example of the driving method for the display device 10 will be described. The driving method shown in the fourth example includes the following: after a pixel 180 (pixel circuit 181) displays a black image based on the voltage VSIGL of the data signal VDATA in the frame immediately preceding the current frame (KthFRAME) (K-1stFRAME), the pixel 180 (pixel circuit 181) displays a white image based on the voltage VSIGH of the data signal VDATA in the KthFRAME. In other words, the driving method shown in the fourth example includes displaying images of different colors in consecutive frames. Configurations identical or similar to those in Figures 1 to 7 will be described as necessary.

[0110] The voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor during the light emission period PEM of the K-1stFRAME to the light emission period PVH of the KthFRAME are the same as those described in "1-5-3. Third Example of Driving Method of Display Device 10". Furthermore, the voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor during the period after the light emission period PVH of the KthFRAME to the light emission period PEM are the same as those described in "1-5-2. Second Example of Driving Method of Display Device 10". Therefore, further explanation is omitted here.

[0111] The fourth example of the driving method for the display device 10 produces the same effects as those described in "1-5-1. First Example of Driving Method for the Display Device 10".

[0112] [1-6. Edge structure of 180 pixels] The end face structure of pixel 180 will be described with reference to Figures 9-12. Figure 9 is a layout diagram of pixel 180. Figure 10 is an end face view showing the end face cut along A1-A2 in the layout shown in Figure 9. Figure 11 is an end face view showing the end face cut along B1-B2 in the layout shown in Figure 9. Figure 12 is an end face view showing the end face cut along C1-C2 in the layout shown in Figure 9. The layout of pixel 180 shown in Figure 9 and the end faces of pixel 180 shown in Figures 10-12 are examples, and the planar layout and end faces of pixel 180 are not limited to the examples shown in Figures 9-12. Configurations identical or similar to those in Figures 1-8 will be described as necessary.

[0113] Note that the end face of the pixel 180 shown in Figures 11 and 12 omits the upper layer (opposite side of the substrate 101) above the insulating layer 141 along the D3 direction.

[0114] Furthermore, the end face of the pixel 180 shown in Figure 10 is an example of an end face of the pixel 180, and is the end face along the functional layer 148, the second wiring 140C, the contact hole opening for the cathode electrode 147, the second contact hole opening 138H, the first wiring 132K, the first contact hole opening 135J, and the semiconductor layer 122D. The end face of the pixel 180 shown in Figure 11 is an example of an end face of the pixel 180, and is the end face along the first wiring 132G, the first contact hole opening 135H, the semiconductor layer 122A, the second wiring 140A, the organic insulating film opening for the capacitive element CS 138A, the gate wiring 127A, and the first wiring 132E. The end face of the pixel 180 shown in Figure 12 is an example of an end face of the pixel 180, and is the end face along the first wiring 132E, the first contact hole opening 135C, the gate wiring 127A, the first contact hole opening 135B, the semiconductor layer 122C, the gate wiring 127B, the second wiring 140B, the first wiring 132F, and the first contact hole opening 135A.

[0115] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via a base layer 121. The semiconductor layer 122 includes a semiconductor layer 122A, which includes a channel region 123 (see Figure 14) and an impurity region 124A (see Figure 14). The semiconductor layer 122 also includes semiconductor layers 122D and 122C. For example, the impurity region is called the source region or drain region. Also, for example, a second transistor T2 includes semiconductor layer 122A, and a first electrode 624 and a second electrode 626 include impurity region 124A. In other words, semiconductor layer 122A includes the channel region of the second transistor T2.

[0116] Similar to semiconductor layer 122A, the third transistor T3 includes semiconductor layer 122C, and the first electrode 634 and the second electrode 636 include impurity regions. In other words, semiconductor layer 122C includes the channel region of the third transistor T3. Also, the fifth transistor T5 includes semiconductor layer 122D, and the first electrode 654 and the second electrode 656 include impurity regions, and the eighth transistor T8 includes semiconductor layer 122D, and the first electrode 684 and the second electrode 686 include impurity regions. In other words, semiconductor layer 122D includes the channel region of the fifth transistor T5 and the channel region of the eighth transistor T8. That is, semiconductor layer 122D serves as both the channel region of the fifth transistor T5 and the channel region of the eighth transistor T8.

[0117] On the semiconductor layer 122, a gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are provided in this order. The conductive layer 126 includes gate wiring 127A (gate electrode 622) and gate wiring 127B (scan signal line 330, gate electrode 632). The conductive layer 132 includes the first wiring 132K, the first wiring 132G, the first wiring 132E (first electrode 42), and the first wiring 132F. The region where the conductive layer 126 and the semiconductor layer 122 overlap is the channel region. In other words, the region where the gate electrode of each transistor and the semiconductor layer overlap is the channel region.

[0118] Each transistor in the pixel 180 is formed using a semiconductor layer 122 (channel region 123 and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (for example, gate wiring 127A).

[0119] First contact hole openings 135J, 135H, 135B, and 135A that reach the semiconductor layer 122 penetrate the gate insulating layer 125 and the insulating layer 128 and are provided in the gate insulating layer 125 and the insulating layer 128. For example, the first contact hole opening 135J exposes the semiconductor layer 122D (e.g., the second electrode 626 and the first electrode 684), and the first wiring 132K is electrically connected to the semiconductor layer 122D by the first contact hole opening 135J. Also, the first contact hole opening 135H exposes the semiconductor layer 122A (e.g., the second electrode 626), and the first wiring 132G is electrically connected to the semiconductor layer 122A by the first contact hole opening 135H. The first contact hole opening 135C exposes the conductive layer 126 (gate wiring 127A), and the first contact hole opening 135B exposes the semiconductor layer 122 (semiconductor layer 122C). The first wiring 132E is electrically connected to the gate wiring 127A by the first contact hole opening 135C, and the first wiring 132E is electrically connected to the semiconductor layer 122D by the first contact hole opening 135B. That is, an opening reaching the conductive layer 126 or the semiconductor layer 122 may be provided in the insulating layer 128. Alternatively, the first contact hole opening 135A exposes the semiconductor layer 122C (for example, the second electrode 636), and the first wiring 132F is electrically connected to the semiconductor layer 122C by the first contact hole opening 135A.

[0120] The insulating layer 131 is provided so as to cover the conductive layer 132 and the insulating layer 131 over which the conductive layer 132 is not exposed. The insulating layer 136 is provided so as to cover the insulating layer 131.

[0121] A second contact hole opening is provided in the insulating layer 131 and the insulating layer 136. For example, the second contact hole opening includes a second contact hole opening 138H. Also, an organic insulating film opening 138A for the capacitive element CS is provided in the insulating layer 136. A conductive layer 139 is provided on the insulating layer 136, in the organic insulating film opening 138A for the capacitive element CS and the second contact hole opening 138H. The conductive layer 139 includes the second wiring 140C (first electrode 32), the second wiring 140A (first electrode 52 and second electrode 44), and the second wiring 140B. The second contact hole opening 138H exposes the first wiring 132K. The second contact hole opening 138H electrically connects the second wiring 140C (first electrode 32) and the first wiring 132K. The opening 138A of the organic insulating film for the capacitive element exposes the insulating layer 131. For example, the capacitive element CV is formed using the insulating layer 131 as the dielectric and a first wiring 132E (first electrode 42) and a second wiring 140A (first electrode 52 and second electrode 44), while the capacitive element CD is formed using the insulating layer 131 as the dielectric and a first wiring 132H (second electrode 54) and a second wiring 140A (first electrode 52 and second electrode 44). For example, the second wiring 140A also serves as a pixel electrode. Although not shown in the figures, for example, the second contact hole opening 138 exposes a portion of the multiple terminals (not shown) included in the terminal portion 150. The exposed portion of the terminals is electrically connected to the FPC 200 using a conductive film such as an anisotropic conductive film (not shown). Furthermore, pixel electrodes are provided independently for each pixel.

[0122] The insulating layer 141 is provided so as to cover the conductive layer 139.

[0123] The base layer 121, semiconductor layer 122, gate insulating layer 125, conductive layer 126, insulating layer 128, conductive layer 132, insulating layer 131, insulating layer 136, conductive layer 139, and insulating layer 141 are collectively referred to as the array section 170.

[0124] Next, the layer above the insulating layer 141 will be described. A contact hole opening 147 for the cathode electrode is provided in the insulating layer 141. The contact hole opening 147 for the cathode electrode exposes the conductive layer 139 (for example, the second wiring 140C).

[0125] The cathode electrode 143 is provided so as to cover the exposed conductive layer 139, the contact hole opening 147 for the cathode electrode, and the insulating layer 141. The functional layer 148 is provided on top of the cathode electrode 143. The common electrode 149 is provided on top of the functional layer 148 so as to cover the functional layer 148. The common electrode 149 is electrically connected to the cathode electrode (the first electrode 32 of the light-emitting OLED). Here, the light-emitting OLED is composed of the cathode electrode 143, the functional layer 148, and the common electrode 149 (anode electrode).

[0126] The configuration of the functional layer 148 can be selected as appropriate. For example, the functional layer 148 can be composed of a combination of a carrier injection layer, a carrier transport layer, an emission layer, a carrier blocking layer, an exciton blocking layer, and so on. For example, the functional layer 148 shown in Figure 9 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (electron) injection and transport layer, the second layer 145 is an emission layer, and the third layer 146 is a carrier (hole) injection and transport layer. For example, the functional layer 148 can be provided independently for each pixel, similar to the pixel electrodes.

[0127] A sealing film 165 is provided on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed to cover at least the display area 22. A cover film 158 is placed on the second inorganic insulating layer 156.

[0128] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146 included in the functional layer 148, as well as the common electrode 149, are not placed on top of the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 are placed on top of the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED and each transistor from outside the display device 10.

[0129] Common metallic materials are used for conductive layers 126, 132, 139, and the common electrode 149. For example, common metallic materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.

[0130] For example, the semiconductor layer 122 may contain crystalline silicon, or it may contain a metal oxide.

[0131] The materials forming the base layer 121, gate insulating layer 125, insulating layer 131, first inorganic insulating layer 152, and second inorganic insulating layer 156 can be general insulating materials. For example, silicon oxide (SiO₂) can be used as these insulating layers. x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride (SiN x O y Inorganic insulating layers such as ) are used.

[0132] The materials forming the insulating layer 128, insulating layer 136, insulating layer 141, and organic insulating layer 154 can be, for example, organic compound materials with excellent surface flatness. The insulating layer 128, insulating layer 136, and insulating layer 141 are sometimes referred to as organic insulating layers.

[0133] [1-7. Method for manufacturing the display device 10] The manufacturing method of the display device 10 (pixels 180) will be described with reference to Figures 9 and 13 to 16. Figure 13 is a sequence diagram showing the manufacturing method of the display device 10. Configurations identical or similar to those in Figures 1 to 12 will be described as necessary. The manufacturing method shown in Figure 13 includes, as an example, an oxide semiconductor layer formed using an oxide semiconductor.

[0134] As shown in Figures 10 to 12, when the manufacturing of the display device 10 (pixels 180) begins, the underlayer 121 is formed on the first surface 101A of the substrate 101.

[0135] As shown in Figure 9, Figure 13, or Figure 14, the semiconductor layer 122 is formed on the base layer 121 (step 10 (S10) in Figure 13). The semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, 122D, 122E, and 122F. Semiconductor layer 122A serves as both the semiconductor layer for the second transistor T2 and the semiconductor layer for the fourth transistor T4. Semiconductor layer 122B is the semiconductor layer for the first transistor T1. Semiconductor layer 122C is the semiconductor layer for the third transistor T3. Semiconductor layer 122D serves as both the semiconductor layer for the fifth transistor T5 and the semiconductor layer for the eighth transistor T8. Semiconductor layer 122E is the semiconductor layer for the sixth transistor T6. Semiconductor layer 122F is the semiconductor layer for the seventh transistor T7. In other words, semiconductor layer 122A includes the channel region of the second transistor T2 and the channel region of the fourth transistor T4, semiconductor layer 122B includes the channel region of the first transistor T1, semiconductor layer 122C includes the channel region of the third transistor T3, semiconductor layer 122D includes the channel region of the fifth transistor T5 and the channel region of the eighth transistor T8, semiconductor layer 122E includes the channel region of the sixth transistor T6, and semiconductor layer 122F includes the channel region of the seventh transistor T7.

[0136] The gate insulating layer 125 (Figures 10-12) is formed on top of the semiconductor layer 122 and on top of the underlayer 121 on which the semiconductor layer 122 is not formed (step 12 (S12) in Figure 13).

[0137] A conductive layer 126 (Figures 10-12) is formed on the gate insulating layer 125 (step 13(S13) in Figure 13). As shown in Figure 9, Figure 13, or Figure 14, the conductive layer 126 includes gate wiring 127A (gate electrode 622), gate wiring 127B (scan signal line 330), gate wiring 127C (scan signal line 331), gate wiring 127D (scan signal line 332), gate wiring 127E (scan signal line 333), gate wiring 127F (scan signal line 334), and gate wiring 127G (reference voltage power line SVR). Gate wiring 127B (scan signal line 330) includes gate electrodes 632 and 642, gate wiring 127C (scan signal line 331) includes gate electrode 652, gate wiring 127D (scan signal line 332) includes gate electrodes 662 and 682, gate wiring 127E (scan signal line 333) includes gate electrode 612, and gate wiring 127F (scan signal line 334) includes gate electrode 672.

[0138] The region where the gate electrode 622 and semiconductor layer 122A of the second transistor T2 overlap is the channel region 123, and the channel region 123 corresponds to the channel length of the second transistor T2. Similarly to the second transistor T2, the region where the gate electrode 612 and semiconductor layer 122B of the first transistor T1 overlap is the channel region of the first transistor T1 and corresponds to its channel length. For transistors other than the second transistor T2 and the first transistor T1, similar to the second transistor T2, the region where the gate electrode and semiconductor layer overlap is the channel region of the transistor and corresponds to its channel length.

[0139] As shown in Figure 14, in plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. That is, the channel length of the second transistor T2 is longer than the channel length of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. Since the second transistor T2 operates in the saturation region, it is necessary to suppress the kink effect. Furthermore, the resistance of the second transistor T2 to hot carriers must be higher than that of the other transistors in pixel 180. To suppress the kink effect and ensure reliability (hot carrier resistance), the channel length of the second transistor T2 is longer than the channel lengths of the other transistors in pixel 180.

[0140] An insulating layer 128 (Figures 10-12) is formed on top of the conductive layer 126 and on top of the gate insulating layer 125 on which the conductive layer 126 is not formed (step 14 (S14) in Figure 13).

[0141] As shown in Figure 9, Figure 13, or Figure 14, the first contact hole openings 135A to 135O are opened (step 15 (S15) in Figure 13). Each opening opens the gate insulating layer 125 and the insulating layer 128, exposing the wiring, semiconductor layer, or electrode corresponding to each opening. For example, the first contact hole opening 135A exposes the semiconductor layer 122C, and the first contact hole opening 135C exposes the gate wiring 127A. The other openings also expose the wiring, semiconductor layer, or electrode corresponding to each.

[0142] A conductive layer 132 (Figures 10-12) is formed on the insulating layer 128 (step 16(S16) in Figure 13). As shown in Figure 9, Figure 13, or Figure 15, the conductive layer 132 includes a first wiring 132A (drive power line PVDD), a first wiring 132B (initialization voltage power line SVI), a first wiring 132C (image data signal line 321), a first wiring 132D (reference voltage line PVSS), a first wiring 132E (first electrode 42), a first wiring 132F, a first wiring 132G, a first wiring 132H (second electrode 54), a first wiring 132I, a first wiring 132J, a first wiring 132K, and a first wiring 132L.

[0143] As shown in Figure 15, in a plan view, for example, the first wiring 132B is electrically connected to the second transistor T4 via the first contact hole opening 135E, and the first wiring 132C is electrically connected to the first transistor T1 via the first contact hole opening 135F. The first wiring 132D is electrically connected to the seventh transistor T7 via the first contact hole opening 135M. The first wiring 132E is electrically connected to the gate wiring 127A via the first contact hole opening 135C and also electrically connected to the third transistor T3 via the first contact hole opening 135B. The other first wirings are also electrically connected to the gate wiring or transistors (semiconductor layer 122) via their respective openings.

[0144] Furthermore, as shown in Figure 15, the first wiring 132E (first electrode 42), gate wiring 127A (gate electrode 622), and semiconductor layer 122A (channel region 123) are superimposed. That is, the channel region and gate electrode 622 of the second transistor T2 are superimposed on the first electrode 42 of the capacitive element CV. Also, the first electrode 42 and the first wiring 132H (second electrode 54) are arranged adjacent to each other on the gate electrode 622.

[0145] An insulating layer 131 (Figures 10-12) is formed on top of the conductive layer 132 and on top of the insulating layer 128 on which the conductive layer 132 is not formed (step 17 (S17) in Figure 13).

[0146] As shown in Figure 9, Figure 13, or Figure 15, the second contact hole openings 138C to 138H are opened (step 18 (S18) in Figure 13). Each opening opens the insulating layer 131, exposing the wiring, semiconductor layer, or electrode corresponding to each opening.

[0147] An insulating layer 136 (organic insulating layer) (Figures 10-12) is formed on top of the insulating layer 131 (step 19 (S19) in Figure 13).

[0148] As shown in Figure 9, Figure 13, or Figure 15, the insulating layer 136 (organic insulating layer) is opened (step 20 (S20) in Figure 13). In the opening of S20, the organic insulating film openings 138A and 138B for the capacitive element are opened. Also, in the opening of S20, the second contact hole openings 138C to 138H are opened, similar to the opening in S18. That is, the second contact hole openings 138C to 138H are opened twice. Each opening opens the insulating layer 136, exposing the insulating layer, wiring, or electrode corresponding to each opening. For example, the organic insulating film opening 138A for the capacitive element removes only the insulating layer 136 on the first wiring 132E (first electrode 42), exposing the insulating layer 131. On the other hand, in the organic insulating film opening 138B for the capacitive element, only the insulating layer 136 on the first wiring 132H (second electrode 54) is removed, exposing the first wiring 132H. In the other openings, the corresponding insulating layer, wiring, or electrode is also exposed.

[0149] A conductive layer 139 (Figures 10-12) is formed on the insulating layer 136, on the insulating layer 131 exposed by the organic insulating film opening 138A for the capacitive element, and on the insulating layer 131 exposed by the organic insulating film opening 138B for the capacitive element (step 21 (S21) in Figure 13). As shown in Figure 9 or Figure 16, the conductive layer 139 includes a second wiring 140A (first electrode 52 and second electrode 44), a second wiring 140B, a second wiring 140C (first electrode 32), a second wiring 140D, and a second wiring 140E (reference voltage power line SVR).

[0150] As shown in Figure 16, in a plan view, the second wiring 140A (first electrode 52 and second electrode 44) is electrically connected to the sixth transistor T6 via the second contact hole opening 138I, the first wiring 132I, and the first contact hole opening 135N. The second wiring 140C is electrically connected to the first wiring 132K, the fifth transistor T5, and the eighth transistor T8 via the second contact hole opening 138H and the first contact hole opening 135J. The second wiring 140E is electrically connected to the first wiring 132J, the sixth transistor T6, and the gate wiring 127G via the second contact hole opening 138G and the first contact hole opening 135P. The other second wirings are also electrically connected to the first wiring, gate wiring, or transistor (semiconductor layer 122) via their respective openings.

[0151] Furthermore, as shown in Figure 16, the second wiring 140A (first electrode 52 and second electrode 44), the first wiring 132E (first electrode 42), the gate electrode 622, and the semiconductor layer 122A (channel region 123) are superimposed. That is, the second transistor T2 is superimposed on the capacitive element CV. Also, the first electrode 42 and the first wiring 132H (second electrode 54) are arranged adjacent to each other on the gate electrode 622. That is, the capacitive element CV and the capacitive element CD are arranged adjacent to each other.

[0152] An insulating layer 141 (organic insulating layer) (Figures 10 to 12) is formed on top of the conductive layer 139 and on top of the insulating layer 136 on which the conductive layer 139 is not formed (step 22 (S22) in Figure 13).

[0153] As shown in Figures 9 and 10, the insulating layer 141 (organic insulating layer) is opened (step 23 (S23) in Figure 13). In the opening in S23, a contact hole opening portion 147A for the cathode electrode is opened. The contact hole opening portion 147A for the cathode electrode removes the insulating layer 141 on the second wiring 140C, exposing the second wiring 140C. The contact hole opening portion 147A for the cathode electrode is sometimes called an organic insulating layer opening. Note that, as shown in Figures 9 and 10, the contact hole opening portion 147A for the cathode electrode is superimposed on the second wiring 140C in a plan view.

[0154] The cathode electrode 143 is provided on the exposed second wiring 140C, on the contact hole opening 147A for the cathode electrode, and on the insulating layer 141. A functional layer 148 is provided on the cathode electrode 143 (Figure 10). A common electrode 149 is provided on the functional layer 148 (step 24 (S24) in Figure 13). For example, the cathode electrode 143 and functional layer 148 are provided for each pixel, and the common electrode 149 is provided so as to overlap the display area 22.

[0155] After S24, the sealing film 165 and the cover film 158 are placed on the common electrode 149 in that order (Figure 10).

[0156] With the above steps completed, the manufacturing of the display device 10 (180 pixels) is finished.

[0157] [1-8. Relationship between potential difference and capacitance value] Referring to Figure 17, the relationship between the absolute value of the potential difference (potential difference Vcv) between the voltage supplied to the first electrode 42 and the voltage supplied to the second electrode 44 of the capacitive element CV and the capacitance value Ccvv of the capacitive element CV, and the relationship between the potential difference Vcv and the capacitance value Ccdv of the capacitive element CD will be explained.

[0158] Ideally, the capacitance values ​​Ccvv and Ccdv are estimated such that the absolute value of the potential difference between the electrodes of the capacitive element CV is the same as the absolute value of the potential difference between the electrodes of the capacitive element CD, and the breakdown voltages of the capacitive elements CV and CD are the same or approximately the same. At this time, the second electrode 44 and the first electrode 52 are electrically connected to the first node N1 and a reference voltage VREF (2V) is supplied.

[0159] For example, the ratio of the leakage charge (leakage current) of the capacitive element CV and the capacitive element CD is 2:3, the amount of charge Qcv that the capacitive element CV can hold is 440 fC, and the amount of charge Qcd that the capacitive element CD can hold is 660 fC. Also, for example, the second electrode 54 is supplied with a maximum voltage VSIGL (4V), and the potential difference between the electrodes of the capacitive element CD (the potential difference between the voltage supplied to the first electrode 52 and the voltage supplied to the second electrode 54) is a potential difference Vcd (4V - potential difference Vcv).

[0160] As shown in Figure 17, for example, when the potential difference Vcv is 2.2V, the required capacitance value Ccvv is 200fF. In this case, the potential difference Vcd is 1.8V (4V-2.2V), and the capacitance value Ccdv is 370fF. For example, to quickly acquire the threshold voltage VTH, it is desirable to estimate the capacitance value Ccvv to be smaller than the capacitance value Ccdv.

[0161] As described above, the relationship between the potential difference Vcv and the capacitance value Ccvv, and the relationship between the potential difference Vcd and the capacitance value Ccdv can be estimated, and the estimated capacitance values ​​Ccvv and Ccdv can be used for design.

[0162] Furthermore, by using the estimated capacitance values ​​Ccvv and Ccdv, it is possible to balance the required breakdown voltages for the capacitance elements CV and CD, and to acquire the threshold voltage VTH at high speed.

[0163] [2. Second Embodiment] The display device 20 according to the second embodiment will be described with reference to Figures 18 to 28. Figure 18 is a schematic diagram showing the configuration of the display device 20. Figure 19 is a schematic diagram showing the configuration of the control circuit 120A according to the second embodiment, and Figure 20 is a circuit diagram showing the configuration of the scan driver 160A(n) according to the second embodiment. Figure 21 is a schematic diagram showing the input signals to the pixel 180A (pixel circuit 181A) according to the second embodiment, and Figure 22 is a circuit diagram showing the configuration of the pixel circuit 181A. Figures 23, 25 to 28 are timing charts of the display device 20, and Figure 24 is a timing chart of the control circuit 120A. Configurations identical or similar to those in Figures 1 to 17 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0164] The display device 20 includes a control circuit 120A, a pixel 180A, and a pixel circuit 181A. Specifically, the display device 20 includes the configurations shown in (1) to (6) below. The configurations shown in (1) to (6) mainly differ from the configuration of the display device 10 according to the first embodiment. (1) The control circuit 120 of the display device 10 according to the first embodiment has a configuration and function in which the control circuit 120 is replaced by the control circuit 120A, and the configuration and function related to the control circuit 120A are different from the configuration and function related to the control circuit 120. (2) The electrical connection between the control circuit 120A and the pixel 180A (pixel circuit 181A) is different from the electrical connection between the control circuit 120 and the pixel 180 (pixel circuit 181). (3) The first scan signal SC1(n) also serves as the scan signal SC3(n). That is, the display device 20 does not include the scan signal SC3(n) or the scan signal line 332 to which the scan signal SC3(n) is supplied. (4) Pixel 180A (pixel circuit 181A) includes a ninth transistor T9. The ninth transistor T9 is electrically connected between the sixth node N6 and the third node N3, and the gate electrode 692 of the ninth transistor T9 is electrically connected to the scan signal line 334. (5) The method for driving the display device 20 includes executing the period PWR and the period PVH in parallel. (6) The method for driving the display device 20 includes executing the period PIN and the period PWR in parallel.

[0165] Configurations of the display device 20 other than those shown in (1) to (6), and configurations of the display device 20 other than those related to those shown in (1) to (6), are the same as those of the display device 10 according to the first embodiment. When describing the configuration and functions of the display device 20, configurations and functions similar to those of the display device 10 will be described as necessary.

[0166] [2-1. Configuration of Control Circuit 120A] Refer to Figures 18 to 20 to explain the overview of the control circuit 120A.

[0167] As shown in Figure 18, the two control circuits 120A are located adjacent to each other on both sides of the display area 22 along the second direction D2 of the display area 22. Scan signal lines 330, 331, 333, and 334 extend from the control circuits 120A along the second direction D2 and connect to a plurality of pixels 180 arranged along the second direction D2.

[0168] As shown in Figure 19, the control circuit 120A includes a shift register circuit 130A and a plurality of scan drivers 160A(n). For example, the control circuit 120A is a gate driver. The numerical value n is a positive integer. For example, the control circuit 120A receives control signals such as a clock signal CLK, a start pulse STV, enable signals EN1 to EN6, and voltages such as a drive voltage VDDEL and a reference voltage VSSEL. The control circuit 120A can sequentially select scan lines based on the input of control signals and power supply.

[0169] The shift register circuit 130A is electrically connected to multiple scan drivers 160A(n). The shift register circuit 130A includes multiple shift registers (e.g., shift registers 111 and 112). The shift register circuit 130A is supplied with a clock signal CLK, a start pulse STV, etc. via multiple connection lines 342, a drive voltage VDDEL is supplied via the drive power line PVDD, and a reference voltage VSSEL is supplied via the reference voltage line PVSS. Based on control signals such as the clock signal CLK and the start pulse STV, the shift register circuit 130A generates multiple output signals (output signal SR1, output signal SR2, etc.) that are shifted at different timings and outputs them sequentially to multiple scan drivers (e.g., scan driver 160A(1), scan driver 160A(2), etc.).

[0170] For example, shift register 111 is electrically connected to shift register 112. Shift register 111 is electrically connected to scan driver 160A(1) and supplies output signal SR1 to input terminal IN1 of scan driver 160A(1). Shift register 112 is electrically connected to scan driver 160A(2) and supplies output signal SR2 to input terminal IN1 of scan driver 160A(2).

[0171] Each scan driver 160A(n) has seven input terminals (input terminals IN1 to IN7) and nine output terminals (output terminals OUT1 to OUT9). Multiple scan drivers 160A(n) are supplied with enable signals EN1 to EN6 from the IC chip 110 via multiple connection lines 342, a drive voltage VDDEL is supplied via the drive power line PVDD, and a reference voltage VSSEL is supplied via the reference voltage line PVSS. Based on the aforementioned multiple output signals and enable signals EN1 to EN6, each scan driver 160A(n) sequentially supplies scan signals with different timings (for example, the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n)) to each scan signal line, and also drives the pixels 180A (pixel circuit 181A) that are electrically connected to each scan signal line.

[0172] For example, as shown in Figure 20, the scan driver 160A(n) includes inverter circuits INV1 to INV5 and six transmission gate TMGs. Each of the six transmission gate TMGs includes a switch SW and a transistor TR1. The switch SW has a configuration in which an n-channel field-effect transistor and a p-channel field-effect transistor are electrically connected. Transistor TR1 is electrically connected to inverter circuit INV3, reference voltage line PVSS, p-channel field-effect transistor and the corresponding output terminal (transmission gate TMG). Inverter circuit INV1 is electrically connected to input terminal IN1 and inverter circuit INV2. Inverter circuit INV2 is electrically connected to output terminal OUT1, inverter circuit INV3, and switch SW (n-channel field-effect transistor) in one of the six transmission gate TMGs. Inverter circuit INV3 is electrically connected to inverter circuit INV4, switch SW (p-channel field-effect transistor) in one of the six transmission gate TMGs, and output terminal OUT3. Inverter circuit INV4 is electrically connected to inverter circuit INV5, and inverter circuit INV5 is electrically connected to output terminal OUT2. The six transmission gate TMGs are electrically connected one-to-one to input terminals IN2 to IN7, and also electrically connected one-to-one to output terminals OUT4 to IN9. Specifically, the transmission gate TMG electrically connected to input terminal IN2 is electrically connected to output terminal OUT4, the transmission gate TMG electrically connected to input terminal IN3 is electrically connected to output terminal OUT5, the transmission gate TMG electrically connected to input terminal IN4 is electrically connected to output terminal OUT6, the transmission gate TMG electrically connected to input terminal IN5 is electrically connected to output terminal OUT7, the transmission gate TMG electrically connected to input terminal IN6 is electrically connected to output terminal OUT8, and the transmission gate TMG electrically connected to input terminal IN7 is electrically connected to output terminal OUT9.

[0173] For example, as shown in Figures 18 and 19, scan signals SC1(n), SC2(n), and SC5(n) are input every k rows. The scan signal lines 330 from row n to row k are electrically connected along the second direction D2. Similarly to scan signal lines 330, scan signal lines 331 from row n to row k are electrically connected, and scan signal lines 334 from row n to row k are electrically connected. That is, multiple pixels 180A (pixel circuits 181A) electrically connected to scan signal lines 330, 331, and 334 from row n to row k receive scan signal SC1(n) supplied to the common scan signal line 330 at the same timing, scan signal SC2(n) supplied to the common scan signal line 331 at the same timing, and scan signal SC5(n) supplied to the common scan signal line 334 at the same timing.

[0174] For example, as shown in Figures 18 and 19, the scan signal SC4(n) is input for each row. That is, multiple pixels 180A (pixel circuit 181A) electrically connected to the scan signal line 333 of the nth row receive the scan signal SC4(n) supplied to the scan signal line 333 of the nth row. Similarly, multiple pixels 180A (pixel circuit 181A) electrically connected to the scan signal line 333 of the (n+1)th row receive the scan signal SC4(n+1) supplied to the scan signal line 333 of the (n+1)th row, and multiple pixels 180A (pixel circuit 181A) electrically connected to each of the scan signal lines 333 of the (n+2)th to kth rows receive the scan signals SC4(n+2) to SC4(k) supplied to each of the scan signal lines 333 of the (n+2)th to kth rows.

[0175] In the control circuit 120A shown in Figure 19, for example, n is 1 and k is 6. That is, multiple pixels 180A (pixel circuits 181A) electrically connected to scan signal lines 330, 331, and 334 from the first to the sixth row receive the scan signal SC1(1) supplied to the common scan signal line 330 at the same time, the scan signal SC2(1) supplied to the common scan signal line 331 at the same time, and the scan signal SC5(1) supplied to the common scan signal line 334 at the same time. Furthermore, multiple pixels 180A (pixel circuits 181A) electrically connected to the scan signal line 333 of the first row receive the scan signal SC4(1) supplied to the scan signal line 333 of the first row, and similarly, multiple pixels 180A (pixel circuits 181A) electrically connected to the scan signal line 333 of the second to sixth rows receive the scan signals SC4(n) (scan signals SC4(2) to SC4(6)) supplied to the scan signal line 333 of the corresponding row.

[0176] The multiple pixels 180A (pixel circuit 181A) in rows 7 to 12, which correspond to the six rows following the first six rows, receive scan signals SC1(2), SC2(2), and SC5(2) at the same timing, and receive scan signals SC4(7) to SC4(12) supplied to the scan signal line 333 of the corresponding row, respectively.

[0177] In the control circuit 120A shown in Figure 19, the scan signals SC1(n), SC2(n), and SC5(n) supplied to scan signal lines 330, 331, and 334 on lines 1 through 6 are described as scan signal SC1[1-6], scan signal SC2[1-6], and scan signal SC5[1-6], respectively, and the scan signals SC1(n), SC2(n), and SC5(n) supplied to scan signal lines 330, 331, and 334 on lines 7 through 12 are described as scan signal SC1[7-12], scan signal SC2[7-12], and scan signal SC5[7-12].

[0178] [2-2. Configuration of Pixel 180A] Referring to Figures 21 and 22, the outlines of pixel 180A and pixel circuit 181A will be explained.

[0179] As explained in (3) above, pixel 180A (pixel circuit 181A) does not include the scan signal SC3(n) and the scan signal line 332 to which the scan signal SC3(n) is supplied, and the first scan signal SC1(n) also serves as the scan signal SC3(n) included in pixel 180 (pixel circuit 181).

[0180] The gate electrode 662 of the sixth transistor T6 and the gate electrode 682 of the eighth transistor T8 are electrically connected to the scan signal line 330 to which the first scan signal SC1(n) is supplied. The switching of the sixth transistor T6 and the eighth transistor T8 is controlled using the first scan signal SC1(n). In other words, the conduction state (on state) and non-conduction state (off state) of the sixth transistor T6 and the eighth transistor T8 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the sixth transistor T6 and the eighth transistor T8 are in a non-conducting state, and when the signal supplied to the first scan signal SC1(n) is HI, the sixth transistor T6 and the eighth transistor T8 are in a conduction state.

[0181] Furthermore, as explained in (4) above, pixel 180A (pixel circuit 181A) includes a ninth transistor T9.

[0182] The ninth transistor T9 has the function of making the sixth node N6 and the third node N3 conductive. The ninth transistor T9 includes a gate electrode 692, a first electrode 694, and a second electrode 696. The gate electrode 692 is electrically connected to the scan signal line 334. The first electrode 694 is electrically connected to the second electrode 616 of the first transistor T1, the second electrode 54 of the capacitive element CD, and the sixth node N6. The second electrode 696 is electrically connected to the third node N3, the first electrode 624 of the second transistor T2, the second electrode 646 of the fourth transistor T4, and the second electrode 676 of the seventh transistor T7. The switching of the ninth transistor T9 is controlled using the fifth scan signal SC5(n). In other words, the conduction state (on state) and non-conduction state (off state) of the ninth transistor T9 are controlled by the fifth scan signal SC5(n). When the signal supplied to the fifth scan signal SC5(n) is LO, the ninth transistor T9 is in a non-conducting state, and when the signal supplied to the fifth scan signal SC5(n) is HI, the ninth transistor T9 is in a conducting state.

[0183] The first to ninth transistors T1 to T9 in the display device 20 are n-channel field-effect transistors, and the channel region of each of the first to ninth transistors T1 to T9 is formed using an oxide semiconductor layer having semiconductor properties.

[0184] The configuration and functions of pixel circuit 181A, other than those described in "2-2. Configuration of Pixel 180A," are the same as those of pixel circuit 181.

[0185] [2-3. Method for driving the display device 20] The method for driving the display device 20 will be explained with reference to Figures 23 to 28. The horizontal axis of the timing chart represents time.

[0186] For example, the method for driving the display device 20 based on the timing chart shown in Figure 23, compared to the method for driving the display device 10 based on the timing chart shown in Figure 4, includes executing the threshold voltage acquisition and hold period PVH (period PVH) after executing the initialization period PIN (period PIN), and executing the write period PWR (period PWR) in parallel with period PVH. In other words, period PWR overlaps with period PVH and is executed during period PVH. Note that period PWR may also be executed during period PIN.

[0187] For example, Figures 19, 20, and 24 illustrate the case where the period between the luminescence period PEM in the K-1stFRAME period and the luminescence period PEM in the KthFRAME period includes period PIN and period PVH, and the period between the luminescence period PEM in the K-1stFRAME period and the luminescence period PEM in the KthFRAME period is a 6-period horizontal period HRP (6 horizontal periods (6HRP)).

[0188] As explained in "2-1. Control Circuit 120A," output signals SR1 and SR2 (see Figure 24) are generated based on control signals such as the clock signal CLK (see Figure 19) and the start pulse STV (see Figure 19). Furthermore, output signals SR1 and SR2 are signals shifted at different timings. Specifically, output signal SR2 is a shifted version of output signal SR1. Also, the pulse widths of output signals SR1 and SR2 are equivalent.

[0189] As explained in "2-1. Control Circuit 120A", the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n) are generated based on the output signal SR1, the output signal SR2, and the enable signals EN1 to EN6.

[0190] For example, referring to Figures 19, 20, and 24, the first scan signal SC1(1), the second scan signal SC2(1), and the fifth scan signal SC5(1) are generated based on the rising and falling edges of the output signal SR1; the fourth scan signal SC4(1) is generated based on the output signal SR1 and the enable signal EN1; the fourth scan signal SC4(2) is generated based on the output signal SR1 and the enable signal EN2; the fourth scan signal SC4(3) is generated based on the output signal SR1 and the enable signal EN3; the fourth scan signal SC4(4) is generated based on the output signal SR1 and the enable signal EN4; the fourth scan signal SC4(5) is generated based on the output signal SR1 and the enable signal EN5; and the fourth scan signal SC4(6) is generated based on the output signal SR1 and the enable signal EN6.

[0191] The fourth scan signal SC4(1) is generated during period PIN, and the pixel 180A (pixel circuit 181A) electrically connected to the fourth scan signal SC4(1) receives the image data signal SL(m) during period HRP (period PWR), which overlaps with period PIN, before period PVH.

[0192] Furthermore, referring to Figures 19, 20, and 24, the first scan signal SC1(2), the second scan signal SC2(2), and the fifth scan signal SC5(2) are generated based on the rising and falling edges of the output signal SR2; the fourth scan signal SC4(7) is generated based on the output signal SR2 and the enable signal EN1; the fourth scan signal SC4(8) is generated based on the output signal SR2 and the enable signal EN2; the fourth scan signal SC4(9) is generated based on the output signal SR2 and the enable signal EN3; the fourth scan signal SC4(10) is generated based on the output signal SR2 and the enable signal EN4; the fourth scan signal SC4(11) is generated based on the output signal SR2 and the enable signal EN5; and the fourth scan signal SC4(12) is generated based on the output signal SR2 and the enable signal EN6.

[0193] To make Figure 24 easier to understand, the illustration is omitted, but similar to the fourth scan signal SC4(1), the fourth scan signal SC4(7) is generated in the period PIN, and the pixel 180A (pixel circuit 181A) electrically connected to the fourth scan signal SC4(7) receives the image data signal SL(m) in the period HRP (period PWR) which overlaps with the period PIN.

[0194] The driving method for the display device 20 includes using output signals SR1 and SR2 to shift the first scan signal SC1(n), the second scan signal SC2(n), the fifth scan signal SC5(n), and the fourth scan signals SC4(n) to SC4(n+k) by k rows, and driving the corresponding k rows of pixels 180A (pixel circuit 181A). Therefore, the control circuit 120A can drive the k rows of pixels 180A (pixel circuit 181A) at timings using a common control signal. As a result, the display device 20 includes a configuration that allows for a simpler control circuit than when driving pixels row by row. Furthermore, the display device 20 includes a configuration that enables lower power consumption due to the simplification of the control circuit, and includes a configuration that allows for a simpler control circuit than when driving pixels row by row.

[0195] Next, with reference to Figures 25 to 28, a horizontal period (horizontal period HRP) of the driving method for the pixels 180 (pixel circuit 181) of the display device 20 will be explained. The driving method for the pixels 180 (pixel circuit 181) of the display device 20 with reference to Figures 25 to 28 will be explained using the fourth scan signal SC4(n+3) from the fourth scan signals SC4(n) to SC4(n+k) as an example.

[0196] In the driving method of the display device 20, the horizontal period HRP includes the period PWR and the period PVH. Pixel 180A (pixel circuit 181A) receives the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n+3), and the image data signal SL(m) as inputs to the horizontal period HRP. For example, pixel 180A (pixel circuit 181A) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m) is input to the selected pixel 180A (pixel circuit 181A) according to the timing of each signal. The same operation is performed for all pixels 180A (pixel circuits 181A), and based on the image data signal SL(m) input to all pixels 180A (pixel circuits 181A), the image of the current frame corresponding to 1 FRAME is displayed in the display area 22 of the display device 20.

[0197] The voltages (potentials) supplied to each signal and each node during each period of each frame in the timing charts shown in Figures 23 to 28 are the same as those in Table 1.

[0198] [2-3-1. First example of a method for driving the display device 20] Referring to Figure 25, a first example of a method for driving the display device 20 will be described. The first example of a method for driving the display device 20 includes displaying images of different colors in consecutive frames, similar to the first example of a method for driving the display device 10 according to the first embodiment.

[0199] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m) including a data signal VDATA is input to each pixel 180 (pixel circuit 181) according to each period. The data signal VDATA is analog data including a voltage between VSIGL and VSIGH. For example, during the period PWR, a voltage between VSIGL and VSIGH is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, during periods other than the period PWR, the data signal VDATA is supplied to a voltage other than the selected pixel 180 (pixel circuit 181).

[0200] During the light emission period PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied to all pixels except the selected pixel 180A (pixel circuit 181A) at the voltage of the data signal VDATA. The first scan signal SC1(n) and the fourth scan signal SC4(n+3) are supplied with LO, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are in the off state, while the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 are in the on state. For example, the voltage supplied to the third node N3 and the sixth node N6 is voltage Vnd (-2V), the voltage supplied to the second node N2 is voltage Vnq (2V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the ON state, and a current Ion based on the potential difference Vgs and potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the K-1st FRAME can be supplied from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. The voltage supplied to the first node N1 is 0V due to capacitive coupling by the capacitive elements CV and CD. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels using a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180 emit white light.

[0201] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied to all pixels except the selected pixel 180A (pixel circuit 181A). Initially, the fifth scan signal SC5(n) changes from a HI state to a LO state. When the fifth scan signal SC5(n) is supplied with LO, the first scan signal SC1(n) changes from a LO state to a HI state. The second scan signal SC2(n) is supplied with HI, and the fourth scan signal SC4(n+3) is supplied with LO.

[0202] As a result, during the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the 7th transistor T7 and the 9th transistor T9 switch from the ON state to the OFF state, and the current Ion stops flowing from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. Also, the 6th node N6 becomes non-conductive with the 3rd node N3. The 3rd transistor T3, the 4th transistor T4, the 6th transistor T6, and the 8th transistor T8 switch from the OFF state to the ON state, the potential difference between the 1st electrode 32 and the 2nd electrode 34 of the light-emitting element OLED becomes 0V, the light emission of the light-emitting element OLED stops, and the voltage supplied to the 1st node N1 rises from 0V towards voltage Vnq (reference voltage VREF, 2V) until it reaches voltage Vnq. The sixth node N6 (the second electrode 616 of the first transistor T1) is in a floating state, and the voltage supplied to the sixth node N6 changes from voltage Vnd (-2V) to 0V so that the voltage supplied to the first node N1 remains elevated (2V-0V) due to the capacitive coupling between the first node N1 and the sixth node N6 via the capacitive element CD. The third transistor T3, the eighth transistor T8, and the fifth transistor T5 are in the ON state, the first transistor T1 remains in the OFF state, the second node N2 and the fourth node N4 are conducting, and the voltage Vnr (drive voltage VDDEL, 6V) is supplied to the second node N2 (the gate electrode 622 of the second transistor T2) and the fourth node N4 (the second electrode 626 of the second transistor T2). Furthermore, the fourth transistor T4 switches from the off state to the on state, supplying a voltage Vnp (initialization voltage VINI, 3V) to the third node N3 (the first electrode 624 of the second transistor T2). The potential difference Vgs is 3V (6V-3V), and the second transistor T2 is in the on state.

[0203] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, the first node N1 is initialized with the reference voltage VREF, and the third node N3 is initialized with the initialization voltage VINI.

[0204] During period PVH, following period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA that is supplied to all pixels except the selected pixel 180 (pixel circuit 181). The second scan signal SC2(n) changes from a HI state to a LO state. The other scan signals remain in the same state as during period PIN. The fifth transistor T5 changes from an ON state to an OFF state, and the other transistors remain in the same state as during period PIN.

[0205] As a result, during period PVH, the first node N1 maintains voltage Vnq, and the third node N3 maintains voltage Vnp. The second transistor T2 is ON, and electrode Ion flows, so the first node N1 maintains voltage Vnq, the third node N3 maintains voltage Vnp, and the sixth node N6 maintains 0V. Also, the fifth transistor T5 is OFF, so the voltage supplied to the second node N2 and the fourth node N4 is released and gradually decreases (discharges) from voltage Vnr. When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 reaches the threshold voltage VTH, the second transistor T2 turns OFF. At this time, the voltage supplied to the second node N2 and the fourth node N4 is voltage Vnl (e.g., 4V).

[0206] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0207] During the PWR period, which runs in parallel with the PVH period, the image data signal SL(m) (data signal VDATA) is supplied with voltage VSIGH (4V). The fourth scan signal SC4(n+3) changes from a LO state to a HI state. The first scan signal SC1(n) is supplied with HI, while the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with LO. The first transistor T1 changes from an off state to an on state. The other transistors are in the same state as during the PVH period. The voltage supplied to the first node N1 remains at voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 remains at voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 remains at voltage Vnp, and the voltage supplied to the sixth node N6 gradually increases from 0V to voltage Vnl (voltage VSIGH, e.g., 4V). At this time, the capacitive element CD maintains a potential difference (-2V with respect to the sixth node N6) by holding a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and the voltage Vnl (voltage VSIGH, e.g., 4V) supplied to the sixth node N6. The potential difference Vgs is 1V, which is the same as the threshold voltage VTH.

[0208] As described above, during the PWR period, the data signal VDATA is written to pixel 180A (pixel circuit 181A). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0209] During the PVH period following the PWR period, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA to all pixels except the selected pixel 180 (pixel circuit 181). The fourth scan signal SC4(n+3) changes from a HI state to a LO state. The first scan signal SC1(n) is HI, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are LO states. The first transistor T1 changes from an ON state to an OFF state. The other transistors are in the same state as during the PWR period. The voltage supplied to the first node N1 maintains voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 and the sixth node N6 maintains voltage Vnl (e.g., 4V), and the voltage supplied to the third node N3 maintains voltage Vnp. At this time, the capacitive element CD maintains a potential difference (-2V with respect to the sixth node N6) by holding a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and the voltage Vnl (voltage VSIGH, e.g., 4V) supplied to the sixth node N6. The potential difference Vgs is 1V, which is the same as the threshold voltage VTH.

[0210] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0211] During the period between the PVH period and the PEM period, the first scan signal SC1(n) changes from a HI state to a LO state. When the first scan signal SC1(n) is supplied with LO, the fifth scan signal SC5(n) changes from a LO state to a HI state. When the fifth scan signal SC5(n) is supplied with LO, the second scan signal SC2(n) changes from a LO state to a HI state. The third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 change from an ON state to an OFF state, and the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 change from an OFF state to an ON state. The other scan signals and other transistors remain in the same state as during the PVH period. The voltage supplied to the third node N3 drops from voltage Vnp to voltage Vnd (-2V), and due to the capacitive coupling of capacitive elements CD and CV, the voltage supplied to the second node N2 and the voltage supplied to the sixth node N6 drop from voltage Vnl to voltage Vnd (-2V). That is, the potential difference Vgs is 0V, and the second transistor T2 is in the off state. At this time, the voltage supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, drops from voltage Vnq to voltage Vnt (-4V).

[0212] During the light emission period PEM, the image data signal SL(m) (data signal VDATA) is supplied to all pixels except the selected pixel 180A (pixel circuit 181A). The scan signal and other transistors are in the same state as during the period between period PVH and the light emission period PEM. Since the potential difference Vgs is 0V and the second transistor T2 is in the off state, electrode Ion does not flow. Therefore, the light-emitting element OLED does not emit light. As a result, the red-emitting pixel 180A (pixel circuit 181A) becomes black. Also, similar to the red-emitting pixel 180A, the blue-emitting pixel 180A and the green-emitting pixel 180A also do not emit light, so the three pixels using the red-emitting pixel 180A, the blue-emitting pixel 180A and the green-emitting pixel 180A become black.

[0213] The display device 20 provides the same effects as the display device 10. Furthermore, each node can be controlled independently. The driving method for the display device 20 includes performing period PWR in parallel with period PIN, and also includes performing period PWR in parallel with period PVH. That is, the driving method for the display device 20 allows data voltage to be written to the pixel circuit at any timing. As a result, the driving method for the display device 20 allows for a longer emission period PEM than a driving method that does not include a dedicated period for performing period PWR. Therefore, the display device 20 can maintain the emission period for a long time and suppress brightness within a unit period, thus providing high reliability.

[0214] [2-3-2. Second example of a method for driving the display device 20] Referring to Figure 26, a second example of a method for driving the display device 20 will be described. The driving method shown in the second example of the display device 20 includes displaying images of the same color (white) in consecutive frames, similar to the second example of the driving method for the display device 10 according to the first embodiment.

[0215] The voltages (potentials) of each node during the period from the light emission period PEM of the K-1thFRAME to the period PWR, which runs in parallel with the period PVH of the KthFRAME, are the same as those described in "2-3-1. First Example of Driving Method of Display Device 20". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "2-3-1. First Example of Driving Method of Display Device 20". Therefore, configurations similar to those described in "2-3-1. First Example of Driving Method of Display Device 10" will be explained as needed. Note that during the PWR period of the KthFRAME, the image data signal SL(m) is supplied with a data signal VDATA including VSIGL(0V) corresponding to white, and during periods other than the PWR period of the KthFRAME, the same data signal VDATA as described in "2-3-1. First Example of Driving Method of Display Device 20" is supplied.

[0216] In the K-1stFRAME's light emission period PEM, similar to the configuration described in "2-3-1. First Example of Driving Method for Display Device 20," pixel 180A (pixel circuit 181A) emits red light, and three pixels using the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A emit white light.

[0217] In the KthFRAME period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, the first node N1 is initialized with the reference voltage VREF, and the third node N3 is initialized with the initialization voltage VINI, similar to the configuration described in "2-3-1. First Example of Driving Method of Display Device 20".

[0218] During the PVH period of the KthFRAME, similar to the configuration described in "2-3-1. First Example of Driving Method of Display Device 20," the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0219] During the KthFRAME period PWR, which runs in parallel with the KthFRAME period PVH, the image data signal SL(m) (data signal VDATA) is supplied with the voltage VSIGL (0V). The voltage supplied to the first node N1 maintains the voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 maintains the voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 maintains the voltage Vnp, and the sixth node N6 is supplied with the voltage VSIGL (0V), maintaining 0V. The capacitive element CD maintains this potential difference (2V) by holding a charge equivalent to the potential difference between the Vnq (reference voltage VREF, 2V) supplied to the first node N1 and the 0V supplied to the sixth node N6. The potential difference Vgs is 1V, which is the same as the threshold voltage VTH.

[0220] As described above, during the PWR period of the KthFRAME, the data signal VDATA is written to pixel 180A (pixel circuit 181A). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0221] During the PVH period of the KthFRAME, following the PWR period of the KthFRAME, the voltage supplied to the first node N1 remains at voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 remains at voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 remains at voltage Vnp, and the voltage supplied to the sixth node N6 remains at 0V. The capacitive element CD maintains this potential difference (2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between Vnq supplied to the first node N1 and 0V supplied to the sixth node N6. The potential difference Vgs is 1V, which is the same as the threshold voltage VTH.

[0222] As described above, during the PVH period of the KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0223] During the period between the KthFRAME's PVH phase and its light emission phase PEM phase, the voltage supplied to the third node N3 drops from voltage Vnp (3V) to voltage Vnd (-2V). Due to the capacitive coupling of capacitive elements CD and CV, the voltage supplied to the second node N2 drops from voltage Vnl (e.g., 4V) to voltage Vnq (2V). That is, the potential difference Vgs is 4V, and the second transistor T2 is in the ON state. At this time, the voltage supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, drops from voltage Vnq (2V) to 0V.

[0224] During the PEM emission period, the potential difference Vgs is 4V, and the second transistor T2 is ON, so electrode Ion flows. Therefore, the OLED light-emitting element emits light. For example, the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A each emit light, and the three pixels using the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A produce white light.

[0225] The second example of the driving method for the display device 20 produces the same effects as those described in "2-3-1. First Example of Driving Method for the Display Device 20".

[0226] [2-3-3. A third example of a method for driving the display device 20] Referring to Figure 27, a third example of a method for driving the display device 20 will be described. The driving method shown in the third example of a method for driving the pixel circuit 181A includes displaying images of the same color (black) in consecutive frames, similar to the third example of a method for driving the display device 10 according to the first embodiment.

[0227] The voltages (potentials) of each node during the PWR period and the PEM period of the KthFRAM, which run in parallel with the PVH period of the KthFRAME, are the same as those described in "2-3-2. Second Example of Driving Method for Display Device 20". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "2-3-1. First Example of Driving Method for Display Device 20". Therefore, configurations similar to those described in "2-3-1. First Example of Driving Method for Display Device 20" and "2-3-2. Second Example of Driving Method for Display Device 20" will be explained as needed.

[0228] In the K-1stFRAME's light-emitting period PEM, for example, the voltage supplied to the first node N1 is Vnt (-4V). Also, the voltage supplied to the second node N2, the third node N3, and the sixth node N6 is Vnd (-2V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, electrode Ion does not flow, and the light-emitting element OLED does not emit light.

[0229] As a result, the red-emitting pixel 180A (pixel circuit 181A) becomes black. Similarly, the blue-emitting pixel 180A and the green-emitting pixel 180A also do not emit light, so the three pixels using the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A all become black.

[0230] During the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, following the light emission period PEM of the K-1stFRAME, the voltage supplied to the first node N1 rises from voltage Vnt (-4V) towards voltage Vnq (reference voltage VREF, 2V) until it reaches voltage Vnq. The second node N2 and the fourth node N4 become conductive, and voltage Vnr (drive voltage VDDEL, 6V) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). Voltage Vnp (initialization voltage VINI, 3V) is supplied to the third node N3 (first electrode 624 of the second transistor T2). The sixth node N6 (the second electrode of the first transistor T1) is floating, and the capacitive coupling between the first node N1 and the sixth node N6 via the capacitive element CD causes the voltage supplied to the sixth node N6 to change from voltage Vnd (-2V) to voltage Vnl (e.g., 4V) so that the voltage supplied to the first node N1 remains elevated by the amount (2V - (-4V)). The potential difference Vgs is 3V (6V - 3V), and the second transistor T2 is ON.

[0231] As described above, during the KthFRAME's period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, the first node N1 is initialized with the reference voltage VREF, and the third node N3 is initialized with the initialization voltage VINI.

[0232] During the KthFRAME period PVH following the KthFRAME period PIN, the first node N1 maintains voltage Vnq, the third node N3 maintains voltage Vnp, and the sixth node N6 maintains voltage Vnl. With the second transistor T2 turned on and electrode Ion flowing, and the fifth transistor T5 turned off, the voltage supplied to the second node N2 and the fourth node N4 is released and gradually decreases (discharges) from voltage Vnr. When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 reaches the threshold voltage VTH, the second transistor T2 turns off. At this time, the voltage supplied to the second node N2 and the fourth node N4 is voltage Vnl (e.g., 4V).

[0233] As described above, during the PVH period of the KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0234] During the KthFRAME period PWR, which runs in parallel with the KthFRAME period PVH, the image data signal SL(m) (data signal VDATA) is supplied with the voltage VSIGH (4V). The voltage supplied to the first node N1 maintains voltage Vnq, the voltage supplied to the second node N2 maintains voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 maintains voltage Vnp, and the sixth node N6 is supplied with voltage VSIGH (4V), maintaining voltage Vnl (voltage VSIGH, e.g., 4V). At this time, the capacitive element CD maintains the potential difference (-2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and the voltage Vnl (voltage VSIGH, e.g., 4V) supplied to the sixth node N6. The potential difference Vgs is 1V, which is the same as the threshold voltage VTH.

[0235] As described above, during the PWR period, the data signal VDATA is written to pixel 180A (pixel circuit 181A). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0236] During the PVH period of the KthFRAME following the PWR period, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, similar to "2-3-1. First example of driving method of display device 20," and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0237] During the period between the KthFRAME period PVH and the KthFRAME light emission period PEM, similar to "2-3-1. First example of driving method of display device 20", the voltage supplied to the third node N3 drops from voltage Vnp to voltage Vnd(-2V), and due to the capacitive coupling of capacitive elements CD and CV, the voltage supplied to the second node N2 and the voltage supplied to the sixth node N6 drops from voltage Vnl to voltage Vnd(-2V). The potential difference Vgs is 0V, the second transistor T2 is in the off state, and the voltage supplied to the first node N1, capacitively coupled by capacitive elements CV and CD, drops from voltage Vnq to voltage Vnt(-4V).

[0238] In the KthFRAME's light emission period PEM, similar to "2-3-1. First example of driving method for display device 20," the potential difference Vgs is 0V and the second transistor T2 is in the off state, so electrode Ion does not flow. Therefore, the light-emitting element OLED does not emit light. As a result, the red-emitting pixel 180A (pixel circuit 181A) becomes black. Also, similar to the red-emitting pixel 180A, the blue-emitting pixel 180A and the green-emitting pixel 180A also do not emit light, so the three pixels using the red-emitting pixel 180A, the blue-emitting pixel 180A and the green-emitting pixel 180A become black.

[0239] The third example of the driving method for the display device 20 produces the same effects as those described in "2-3-1. First Example of Driving Method for the Display Device 20".

[0240] [2-3-4. A fourth example of a method for driving the display device 20] Referring to Figure 28, a fourth example of a method for driving the display device 20 will be described. The driving method shown in the fourth example of a method for driving the pixel circuit 181A includes displaying images of different colors in consecutive frames, similar to the fourth example of a method for driving the display device 10 according to the first embodiment.

[0241] The voltage (potential) of each node during the light emission period of K-1stFRAME (PEM) to the period before the PWR period, which is executed in parallel with the PVH period of KthFRAME, the configuration of each scan signal, and the operation of each transistor are the same as those described in "2-3-3. Third Example of Driving Method of Display Device 20". Also, the configuration of each scan signal and the operation of each transistor are the same as those described in "2-3-1. First Example of Driving Method of Display Device 20". Therefore, the same configurations as those described in "2-3-1. First Example of Driving Method of Display Device 20" and "2-3-3. Third Example of Driving Method of Display Device 20" will be explained as needed.

[0242] In the K-1stFRAME's light emission period PEM, similar to "2-3-3. Third Example of Driving Method for Display Device 20," the voltage supplied to the first node N1 is Vnt (-4V), the voltage supplied to the second node N2, the voltage supplied to the third node N3, and the voltage supplied to the sixth node N6 is Vnd (-2V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, electrode Ion does not flow, and the light-emitting element OLED does not emit light.

[0243] During the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, following the light emission period PEM of K-1stFRAME, the voltage supplied to the first node N1 becomes voltage Vnq, and voltage Vnr (drive voltage VDDEL, 6V) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). A voltage Vnp (initialization voltage VINI, 3V) is supplied to the third node N3 (the first electrode 624 of the second transistor T2), the sixth node N6 (the second electrode 616 of the first transistor T1) is floating, and the voltage supplied to the sixth node N6 changes from voltage Vnd (-2V) to voltage Vnl (e.g., 4V) so as to maintain the voltage supplied to the first node N1 by the amount of increase (2V - (-4V)) through the capacitive coupling between the first node N1 and the sixth node N6 via the capacitive element CD. Also, the potential difference Vgs is 3V (6V - 3V), and the second transistor T2 is in the ON state.

[0244] As described above, during the KthFRAME's period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, the first node N1 is initialized with the reference voltage VREF, and the third node N3 is initialized with the initialization voltage VINI.

[0245] During the KthFRAME period PVH following the KthFRAME period PIN, similar to "2-3-3. Third Example of Driving Method of Display Device 20", the first node N1 maintains voltage Vnq, the third node N3 maintains voltage Vnp, the sixth node N6 maintains voltage Vnl, and the voltage supplied to the second node N2 and the fourth node N4 becomes voltage Vnl (e.g., 4V).

[0246] As described above, during the PVH period of the KthFRAME, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0247] During the KthFRAME period PWR, which runs in parallel with the KthFRAME period PVH, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the first node N1 maintains voltage Vnq, the voltage supplied to the second node N2 maintains voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 maintains voltage Vnp, and the voltage supplied to the sixth node N6 drops from voltage Vnl to 0V (voltage VSIGL) and becomes 0V. At this time, the capacitive element CD maintains the potential difference (2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and 0V supplied to the sixth node N6. The potential difference Vgs is 1V, which is the same as the threshold voltage VTH.

[0248] As described above, during the PWR period, the data signal VDATA is written to pixel 180A (pixel circuit 181A). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0249] During the PVH period of the KthFRAME following the PWR period, the voltage supplied to the first node N1 remains at voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 remains at voltage Vnl (e.g., 4V), the voltage supplied to the third node N3 remains at voltage Vnp, and the voltage supplied to the second node N2 remains at 0V. At this time, the capacitive element CD maintains the potential difference (2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and 0V supplied to the sixth node N6. The potential difference Vgs is 1V, which is the same as the threshold voltage VTH.

[0250] As described above, in the period PVH of the Kth FRAME after the period PWR of the Kth FRAME, the threshold voltage VTH of the second transistor T2 is obtained by an operation in which the potential difference Vgs of the second transistor T2 becomes the same as the threshold voltage VTH, and a charge corresponding to the threshold voltage VTH is held in the capacitive element CV.

[0251] During the period between the period PVH of the Kth FRAME and the light emission period PEM of the Kth FRAME, the voltage supplied to the third node N3 drops from the voltage Vnp (3V) to the voltage Vnd (-2V). Due to the capacitive coupling of the capacitive element CD and the capacitive element CV, the voltage supplied to the second node N2 drops from the voltage Vnl to the voltage Vnq (2V). That is, the potential difference Vgs is 4V, and the second transistor T2 is in the on state. At this time, the voltage supplied to the first node N1 capacitively coupled by the capacitive element CV and the capacitive element CD drops from the voltage Vnq (2V) to 0V. The sixth node N6 (the second electrode 616 of the first transistor T1) is connected to the third node N3 because the ninth transistor T9 is in the on state, and the voltage supplied to the sixth node N6 becomes from 0V to the voltage Vnd (-2V).

[0252] During the light emission period PEM of the Kth FRAME, since the potential difference Vgs is 4V and the second transistor T2 is in the on state, current flows through the electrode Ion. Therefore, the pixel 180A (pixel circuit 181A) that emits red light emits light. Also, similar to the pixel 180A that emits red light, the pixel 180A that emits blue light and the pixel 180A that emits green light also emit light, and white light is emitted by three pixels using the pixel 180A that emits red light, the pixel 180A that emits blue light, and the pixel 180A that emits green light.

[0253] The fourth example of the driving method of the display device 20 has the same operational effects as those described in "2-3-1. The first example of the driving method of the display device 20".

[0254] [3. Third Embodiment] Referring to FIGS. 4, 29 to 35, the outline of the display device 30 according to the third embodiment will be described. FIG. 29 is a schematic diagram showing the configuration of the display device 30. FIG. 30 is a schematic diagram showing input signals to the pixel 180B (pixel circuit 181B) according to the third embodiment, FIG. 31 is a circuit diagram showing the configuration of the pixel circuit 181B, and FIGS. 32 to 35 are timing charts of the display device 30.

[0255] The display device 30 includes a control circuit 120B, pixels 180B, and pixel circuits 181B. The configurations of the control circuit 120B, pixels 180B, and pixel circuits 181B are different from the configurations of the control circuit 120, pixels 180, and pixel circuits 181 of the display device 10 according to the first embodiment. Specifically, the display device 30 includes the configurations shown in the following (7) to (15). Mainly, the configurations shown in (7) to (15) are different from the configuration of the display device 10 according to the first embodiment. (7) It has a configuration and function in which the control circuit 120 of the display device 10 according to the first embodiment is replaced by the control circuit 120B, and the configurations and functions related to the control circuit 120B are different from the configurations and functions related to the control circuit 120. (8) It has a configuration and function in which the pixel 180 (pixel circuit 181) of the display device 10 according to the first embodiment is replaced by the pixel 180B (pixel circuit 181B), and the configurations and functions related to the pixel 180B (pixel circuit 181B) are different from the configurations and functions related to the pixel 180 (pixel circuit 181). (9) The electrical connection between the control circuit 120B and the pixel 180B (pixel circuit 181B) is different from the electrical connection between the control circuit 120 and the pixel 180 (pixel circuit 181). (10) The second scan signal SC2(n) also serves as the scan signal SC5(n) according to the first embodiment. That is, the display device 30 does not include the scan signal SC5(n) and the scan signal line 334 to which the scan signal SC5(n) is supplied. The falling and rising timings of the second scan signal SC2(n) are different from the falling and rising timings of the second scan signal SC2(n) according to the first embodiment. (11) The scan signal line 335 and the sixth scan signal SC6(n) supplied to the scan signal line 335 are added. (12) Scan signal line 336 and a seventh scan signal SC7(n) supplied to scan signal line 336 are added. (13) A constant voltage VSH and a constant voltage power line SVS to which the constant voltage VSH is supplied are added. (14) Pixel 180A (pixel circuit 181A) includes a ninth transistor T9. The ninth transistor T9 is electrically connected between the fourth node N4 and the constant voltage power line SVS, and the gate electrode 692 of the ninth transistor T9 is electrically connected to the scan signal line 335. (15) The gate electrode 642 of the fourth transistor T4 is electrically connected to scan signal line 336, not to scan signal line 330.

[0256] Configurations of the display device 30 other than those shown in (7) to (15), and configurations of the display device 30 other than those related to those shown in (7) to (15), are the same as those of the display device 10 according to the first embodiment. When describing the configuration and functions of the display device 30, configurations and functions similar to those of the display device 10 will be described as necessary.

[0257] [3-1. Configuration of Control Circuit 120B] Referring to Figure 29, the outline of the control circuit 120B is described. Similar to the two control circuits 120, the two control circuits 120B are located adjacent to each other on both sides of the display area 22 along the second direction D2. Scan signal lines 330, 331, 332, 333, 335, and 336 extend from the control circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. As an example, each scan signal line of the display device 30 shown in Figure 29 is connected to both of the two control circuits 120B. Each scan signal line may be connected to one of the two control circuits 120B. That is, the nth scan signal line may be electrically connected to the control circuit 120 on the right side of the display area 22 along the second direction D2, and the (n+1)th scan signal line may be electrically connected to the control circuit 120 on the left side of the display area 22 along the second direction D2. The numerical value n is a positive integer.

[0258] The control circuit 120B includes a shift register circuit 130B and a scan driver circuit 160B. The scan driver circuit 160B includes multiple scan drivers. For example, multiple scan drivers are supplied with multiple output signals from the shift register circuit 130B, multiple enable signals as described in the first embodiment are supplied from the IC chip 110 via multiple connection lines 342, a drive voltage VDDEL is supplied via the drive power line PVDD, and a reference voltage VSSEL is supplied via the reference voltage line PVSS. Based on the multiple output signals and multiple enable signals, the multiple scan drivers sequentially supply scan signals with different timings (for example, a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a sixth scan signal SC6(n), and a seventh scan signal SC7(n)) to each scan signal line, and are responsible for driving pixels 180B (pixel circuit 181B) electrically connected to each scan signal line. For example, the fourth scan signal SC4(n) and the scan signal line 333 to which the fourth scan signal SC4(n) is supplied are so-called scan signal and scan signal line.

[0259] The configuration of control circuit 120B, other than that described in "3-1. Configuration of Control Circuit 120B," is the same as that of control circuit 120.

[0260] Constant voltage power lines (SVS) are sometimes called control voltage power lines, and constant voltage (VSH) are sometimes called control voltages.

[0261] [3-2. Pixel 180B configuration] Refer to Figures 29 to 31 to explain the outlines of pixel 180B and pixel circuit 181B.

[0262] The pixel circuit 181B is connected to scan signal lines 335 and 336, as well as the constant voltage power supply line SVS.

[0263] A constant voltage VSH is supplied to the constant voltage power line SVS. For example, the constant voltage power line SVS is electrically connected to a connection wiring 342 that is different from the initialization voltage power line SVI, the reference voltage power line SVR, the drive power line PVDD, and the reference voltage line PVSS among the connection wiring 342. Alternatively, the constant voltage power line SVS may be one of the connection wiring 342. For example, the constant voltage VSH may be supplied from an external device to the IC chip 110, and from the IC chip 110 to multiple pixels 180B (pixel circuits 181B) via the connection wiring 342 and the constant voltage power line SVS. Although not shown in the figures, the constant voltage VSH may be connected from an external device to the constant voltage power line SVS via the FPC 200, terminal section 150, and connection wiring 341, without going through the IC chip 110 and connection wiring 342, and supplied to multiple pixels 180B (pixel circuits 181B).

[0264] The gate electrode 642 of the fourth transistor T4 is electrically connected to the scan signal line 336. As described above, the seventh scan signal SC7(n) is supplied to the scan signal line 336. The switching of the fourth transistor T4 is controlled using the seventh scan signal SC7(n). In other words, the fourth transistor T4 is controlled to be either conducting (on) or not conducting (off) by the seventh scan signal SC7(n). When the signal supplied to the seventh scan signal SC7(n) is LO, the fourth transistor T4 is in a non-conducting state, and when the signal supplied to the seventh scan signal SC7(n) is HI, the fourth transistor T4 is in a conducting state. The seventh scan signal SC7(n) is sometimes called the seventh control signal.

[0265] The gate electrode 672 of the seventh transistor T7 is electrically connected to the scan signal line 331 to which the second scan signal SC2(n) is supplied. The switching of the seventh transistor T7 is controlled using the second scan signal SC2(n). In other words, the seventh transistor T7 is controlled to be either conducting (on) or not conducting (off) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the seventh transistor T7 is in a non-conducting state, and when the signal supplied to the second scan signal SC2(n) is HI, the seventh transistor T7 is in a conducting state.

[0266] The ninth transistor T9 has the function of supplying a constant voltage VSH to the fourth node N4 by conducting the fourth node N4 and the constant voltage power line SVS. The ninth transistor T9 includes a gate electrode 692, a first electrode 694, and a second electrode 696. The gate electrode 692 is electrically connected to the scan signal line 335. The first electrode 694 is electrically connected to the fourth node N4, the first electrode 654 of the fifth transistor T5, the second electrode 636 of the third transistor T3, and the second electrode 626 of the second transistor T2. The second electrode 696 is electrically connected to the constant voltage power line SVS. As described above, the sixth scan signal SC6(n) is supplied to the scan signal line 335. The switching of the ninth transistor T9 is controlled using the sixth scan signal SC6(n). In other words, the ninth transistor T9 is controlled by the sixth scan signal SC6(n) to be either conducting (on) or not conducting (off). When the signal supplied to the sixth scan signal SC6(n) is LO, the ninth transistor T9 is in a non-conducting state, and when the signal supplied to the sixth scan signal SC6(n) is HI, the ninth transistor T9 is in a conducting state. The sixth scan signal SC6(n) is sometimes referred to as the third control signal.

[0267] The configuration and functions of pixel circuit 181B, other than those described in "3-2. Configuration of Pixel 180B," are the same as those of pixel circuit 181.

[0268] [3-3. Driving method of pixel circuit 181B] The driving method of the display device 30 will be explained with reference to Figures 32 to 35. Configurations identical or similar to those in Figures 1 to 31 will be explained as necessary. The horizontal axis of the timing chart represents time.

[0269] The driving method for the display device 30 includes the same period as the driving method for the display device 10 according to the first embodiment shown in Figure 4.

[0270] In a horizontal period (horizontal period HRP) in the driving method of the display device 30, the pixel 180B (pixel circuit 181B) receives an image data signal SL(m) including the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the sixth scan signal SC6(n), the seventh scan signal SC7(n), and the data signal VDATA. For example, according to the timings of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the sixth scan signal SC6(n), and the seventh scan signal SC7(n), the pixel 180B (pixel circuit 181B) is selected. The image data signal SL(m) is input to the selected pixel 180B (pixel circuit 181B) according to the timings of the respective signals. The same operation is executed for all the pixels 180B (pixel circuits 181B), and an image of the current frame corresponding to 1 FRAME is displayed in the display area 22 of the display device 10 based on the image data signal SL(m) input to all the pixels 180B (pixel circuits 181B).

[0271] For example, the signals of each frame and the voltages (potentials) supplied to each node in the timing charts shown in FIGS. 32 to 35 are shown in Table 2.

[0272]

Table 2

[0273] For example, as shown in Table 2, the voltage VH(HI) is 10V, the voltage VL(LO) is -3V, the constant voltage VSH is 6V, the driving voltage VDDEL is 8V, the reference voltage VSSEL is 0V, the voltage VM is 5V, and the voltage VN is -5V. That is, the reference voltage VREF is different from the initialization voltage VINI, and the reference voltage VREF and the initialization voltage VINI are greater than the reference voltage VSSEL and less than the driving voltage VDDEL. The set values of the other voltages are the same as the set values shown in Table 1 described in "1-5. Driving Method of the Display Device 10".

[0274] [3-3-1. First example of a method for driving the display device 30] Referring to Figure 32 and Table 2, a first example of a method for driving the display device 30 will be described. The first example of a method for driving the display device 30 includes displaying images of different colors in consecutive frames, similar to the first example of a method for driving the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 31 will be described as necessary.

[0275] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m) including a data signal VDATA is input to each pixel 180B (pixel circuit 181B) according to each period. The data signal VDATA is analog data including a voltage between VSIGL and VSIGH. For example, in the period PWR, the voltage supplied to the selected pixel 180B (pixel circuit 181B) is supplied to the image data signal SL(m). For example, in periods other than the period PWR, the data signal VDATA is supplied with a voltage supplied to pixels other than the selected pixel 180B (pixel circuit 181B).

[0276] The light emission period PEM of the K-1stFRAME is the period during which pixel 180B (pixel circuit 181B) emits light in accordance with the potential difference Vgs of the second transistor T2 (voltage supplied to the second node N2 (voltage V(N2)) - voltage supplied to the third node N3 (voltage V(N3))). For example, pixel 180 (pixel circuit 181) emits red light, and three pixels using a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180 emit white light.

[0277] For example, during the emission period PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied to all pixels except the selected pixel 180B (pixel circuit 181B) at the voltage of the data signal VDATA. The first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the sixth scan signal SC6(n), and the seventh scan signal SC7(n) are supplied with LO, and the second scan signal SC2(n) is supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are in the off state, while the fifth transistor T5 and the seventh transistor T7 are in the on state. Also, for example, the voltage supplied to the third node N3 is 0V, the voltage supplied to the second node N2 is voltage Vnl (e.g., 4V), and the potential difference Vgs is 4V. Therefore, with the second transistor T2 in the ON state, a current Ion based on the potential difference Vgs and potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the K-1stFRAME can be supplied from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. The voltage supplied to the first node N1 is 2V due to capacitive coupling by the capacitive elements CV and CD. For example, pixel 180B (pixel circuit 181B) emits red light, and three pixels using a red-emitting pixel 180B, a blue-emitting pixel 180B, and a green-emitting pixel 180B emit white light.

[0278] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to all pixels except the selected pixel 180 (pixel circuit 181). Initially, the second scan signal SC2(n) changes from a HI state to a LO state. When the second scan signal SC2(n) is supplied with LO, the third scan signal SC3(n) changes from a LO state to a HI state. When the third scan signal SC3(n) is supplied with HI, the first scan signal SC1(n) and the sixth scan signal SC6(n) change from a LO state to a HI state. The fourth scan signal SC4(n) and the seventh scan signal SC7(n) are supplied with LO.

[0279] As a result, during the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, or during the period PIN of KthFRAME, the fifth transistor T5 and the seventh transistor T7 switch from the ON state to the OFF state, and the current Ion stops flowing from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. The eighth transistor T8 switches from the OFF state to the ON state, and the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, stopping the light emission of the light-emitting element OLED. Also, the sixth transistor T6 switches from the OFF state to the ON state, and the voltage supplied to the first node N1 is the reference voltage VREF (2V, voltage Vnq), which is maintained at voltage Vnq. The third transistor T3 and the ninth transistor T9 switch from the off state to the on state, the fourth transistor T4 and the first transistor T1 remain off, the second node N2 and the fourth node N4 become conductive, and a constant voltage VSH (6V, voltage Vnr) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). Also, the potential difference Vgs becomes 6V (6V-0V), the second transistor T2 is on, and the voltage supplied to the third node N3 (first electrode 624 of the second transistor T2) and the sixth node N6 (second electrode 616 of the first transistor T1) begins to rise. However, since the fourth transistor T4 is in the off state, current does not continue to flow, and the voltage supplied to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1) remains at approximately Vnp (3V), causing the operation of the display device 30 to transition from period PIN to period PVH.

[0280] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized with the constant voltage VSH, and the first node N1 is initialized with the reference voltage VREF. At this time, since the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in the off state, the constant voltage power line SVS and the initialization voltage power line SVI do not conduct, and the constant voltage power line SVS, the drive power line PVDD, and the reference voltage line PVSS do not conduct. Therefore, the current flowing between the power lines during the period PIN is interrupted, and the increase in power consumption of the display device 30 is suppressed.

[0281] During period PVH, following period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to all pixels except the selected pixel 180B (pixel circuit 181B). The sixth scan signal SC6(n) changes from a HI state to a LO state. When the sixth scan signal SC6(n) is supplied with LO, the seventh scan signal SC7(n) changes from a LO state to a HI state. The other scan signals remain in the same state as during period PIN. The ninth transistor T9 changes from an ON state to an OFF state, the fourth transistor T4 changes from an OFF state to an ON state, and the other transistors remain in the same state as during period PIN.

[0282] As a result, during period PVH, the third node N3 (sixth node N6) is supplied with an initialization voltage VINI (3V, voltage Vnp), the voltage supplied to the third node N3 (sixth node N6) is voltage Vnp, the second transistor T2 is ON and electrode Ion flows, and the voltage supplied to the first node N1 maintains voltage Vnq. Also, the fifth transistor T5 and the seventh transistor T7 are OFF, the fourth transistor T4 is ON, and the ninth transistor T9 is OFF, so the voltage supplied to the second node N2 and the fourth node N4 is released, current flows from the second node N2 and the fourth node N4 to the initialization voltage power line SVI, and the voltage supplied to the second node N2 and the fourth node N4 gradually decreases from voltage Vnr (discharges). When the potential difference Vgs between the voltages supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) reaches the threshold voltage VTH, the second transistor T2 turns off. At this time, the third node N3 (sixth node N6) is supplied with an initialization voltage VINI (3V), so the voltage supplied to the second node N2 and the fourth node N4 when the potential difference Vgs reaches the threshold voltage VTH is voltage Vnl (for example, 4V).

[0283] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0284] During the period between period PVH and period PWR, or during period PWR, the image data signal SL(m) (data signal VDATA) is supplied with voltage VSIGH (e.g., 4V, voltage Vnl). Initially, the first scan signal SC1(n) changes from a HI state to a LO state. When the first scan signal SC1(n) is supplied with LO, the seventh scan signal SC7(n) changes from a HI state to a LO state. When the seventh scan signal SC7(n) is supplied with LO, the fourth scan signal SC4(n) changes from a LO state to a HI state. The third scan signal SC3(n) is supplied with HI, and the second scan signal SC2(n) and the sixth scan signal SC6(n) are supplied with LO. The first transistor T1 changes from the off state to the on state, and the third transistor T3 and the fourth transistor T4 change from the on state to the off state. The other transistors remain in the same state as during period PVH. The second node N2 is supplied with voltage VSIGH (e.g., 4V, voltage Vnl) and maintains voltage Vnl (e.g., 4V), the voltage supplied to the first node N1 maintains voltage Vnq (reference voltage VREF, 2V), and the voltage supplied to the third node N3 (sixth node N6) rises from voltage Vnp towards voltage VSIGH (e.g., 4V, voltage Vnl) and becomes voltage Vnl (e.g., 4V). At this time, the capacitive element CD maintains the potential difference (2V with respect to the sixth node N6) by holding a charge equivalent to the potential difference between Vnq (reference voltage VREF, 2V) supplied to the first node N1 and voltage Vnl (e.g., 4V) supplied to the third node N3 (sixth node N6). The potential difference Vgs is 0V, and the second transistor T2 is in the off state.

[0285] As described above, during the PWR period, the data signal VDATA is written to pixel 180 (pixel circuit 181). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0286] During the period following the PWR, the third scan signal SC3(n) changes from a HI state to a LO state. The sixth transistor T6 and the eighth transistor T8 change from an ON state to an OFF state. Other scan signals and other transistors remain in the same state as during the PWR. The voltage supplied to the second node N2 and the voltage supplied to the third node N3 (sixth node N6) maintains the voltage Vnl, the potential difference Vgs maintains 0V, and the voltage supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, maintains the voltage Vnq.

[0287] During the KthFRAME emission period PEM, which follows the KthFRAME period PWR, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA to all pixels except the selected pixel 180 (pixel circuit 181). Also, the second scan signal SC2(n) changes from a LO state to a HI state. Thus, the fifth transistor T5 and the seventh transistor T7 turn on from the off state. Other scan signals and other transistors remain in the same state as during the KthFRAME period PWR. With the fifth transistor T5 and the seventh transistor T7 turned on, the first electrode 32 of the light-emitting element OLED conducts with the second electrode 626 of the second transistor T2 (fourth node N4). When the third node N3 is connected to the reference voltage VSSEL, the voltage supplied to the second node N2 and the voltage supplied to the third node N3 (the sixth node N6) drop from voltage Vnl to 0V, and the voltage supplied to the first node N1 drops from voltage Vnq to voltage Vnd (-2V). That is, the potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (initialization voltage VINI (3V) - voltage of data signal VDATA (voltage VSIGH, 4V) + threshold voltage VTH (1V) = 0V). For pixel 180B (pixel circuit 181B) where the data signal VDATA contains voltage VSIGH, the potential difference Vgs is 0V and the second transistor T2 is in the off state, so no current flows through the drain electrode Ion. Therefore, the light-emitting element OLED does not emit light. As a result, pixel 180 (pixel circuit 181) which emits red light becomes black. Furthermore, just like the red-emitting pixel 180, the blue-emitting pixel 180 and the green-emitting pixel 180 also do not emit light, so the three pixels using the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 result in black.

[0288] The reference voltage VSSEL in the display device 30 is 0V, which is a higher potential than the reference voltage VSSEL (-2V) in the display device 10, and the difference between the write potential of the display device 30 and the reference voltage VSSEL is smaller than that of the display device 10. As a result, the potential fluctuation during the transition from writing to illumination in the display device 30 is smaller than that of the display device 10, and the power consumption of the display device 30 can be reduced compared to the display device 10. The display device 30 also includes a configuration in which a constant voltage VSH is supplied to the second node N2 and the fourth node N4. As a result, the voltage rise of the first node N1, the second node N2 and the third node N3 (sixth node N6) in the period PIN can be lower in the display device 30 than the voltage rise of the first node N1, the second node N2 and the third node N3 (sixth node N6) in the display device 10. Furthermore, the display device 30 can make the voltage drop at the first node N1, the second node N2, and the third node N3 (sixth node N6) from the period PWR to the emission period PEM lower than the voltage drop at the first node N1, the second node N2, and the third node N3 (sixth node N6) in the display device 10. Therefore, the display device 30 can have lower power consumption during the period PIN and from the period PWR to the emission period PEM than the display device 10.

[0289] [3-3-2. Second example of a driving method for the display device 30] Referring to Figure 33, a second example of the driving method for the display device 30 will be described. The driving method shown in the second example of the display device 30 includes displaying images of the same color (white) in consecutive frames, similar to the second example of the driving method for the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 32 will be described as necessary.

[0290] The voltages (potentials) of each node during the light emission period PEM of the K-1thFRAME to the period PVH of the KthFRAME, and during the period between the KthFRAME's period PVH and the KthFRAME's period PWR, are the same as those described in "3-3-1. First Example of Driving Method of Display Device 30". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "3-3-1. First Example of Driving Method of Display Device 30". Therefore, configurations similar to those described in "3-3-1. First Example of Driving Method of Display Device 30" will be explained as needed. Note that during the KthFRAME's period PWR, the image data signal SL(m) is supplied with a data signal VDATA including VSIGL(0V) corresponding to white, and during periods other than the KthFRAME's period PWR, the same data signal VDATA as described in "3-3-1. First Example of Driving Method of Display Device 30" is supplied.

[0291] In the K-1stFRAME's light emission period PEM, similar to the configuration described in "3-3-1. First Example of Driving Method for Display Device 30," the pixel 180 (pixel circuit 181) emits red light, and three pixels, consisting of a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180, emit white light.

[0292] In the KthFRAME period PIN, the second node N2 and the fourth node N4 are initialized with a constant voltage VSH, and the first node N1 is initialized with a reference voltage VREF, similar to the configuration described in "3-3-1. First Example of Driving Method of Display Device 30".

[0293] During the period PVH following the period PIN, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, similar to the configuration described in "3-3-1. First Example of Driving Method of Display Device 30," and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0294] During the period between period PVH and period PWR, or during period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the second node N2 maintains a voltage Vnl (e.g., 4V), and the voltage supplied to the first node N1 maintains a voltage Vnq (reference voltage VREF, 2V). The voltage supplied to the third node N3 (sixth node N6) gradually decreases from a voltage Vnp (initialization voltage VINI, 3V) to 0V (voltage VSIGL). At this time, the capacitive element CD maintains the potential difference (2V) by holding a charge corresponding to the potential difference between the voltage Vnq (reference voltage VREF, 2V) supplied to the first node N1 and the 0V (voltage VSIGL) supplied to the third node N3 (sixth node N6). Furthermore, the capacitive element CV maintains a potential difference (2V relative to the first node N1) by holding a charge equivalent to the potential difference between the voltage Vnl (e.g., 4V) supplied to the second node N2 and the voltage Vnq (reference voltage VREF, 2V) supplied to the first node N1. In other words, the potential difference Vgs is the sum of the potential differences held by the series-connected capacitive elements CD and CV, which is 4V.

[0295] As described above, during the PWR period, the data signal VDATA is written to pixel 180 (pixel circuit 181). In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0296] In the period following the PWR period, the voltage supplied to the first node N1 remains at voltage Vnq (reference voltage VREF, 2V), the voltage supplied to the second node N2 remains at voltage Vnl (e.g., 4V), and the voltage supplied to the third node N3 (sixth node N6) remains at 0V. Also, similar to the PWR period, in the period following the PWR period, the capacitive element CD maintains the potential difference (2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the third node N3 (sixth node N6), and the capacitive element CV maintains the potential difference (2V relative to the first node N1) by holding a charge equivalent to the potential difference between the voltage supplied to the second node N2 (e.g., 4V) and the 2V supplied to the first node N1. In other words, the potential difference Vgs is the sum of the potential differences held by the series-connected capacitive elements CD and CV, which is 4V.

[0297] In the light emission period PEM of the KthFRAME, which follows the period PWR of the KthFRAME, the potential difference Vgs is held by two capacitive elements CD and CV, and is the sum of the potential difference held by capacitive element CD and the potential difference held by capacitive element CV (initialization voltage VINI (3V) - voltage included in the data signal VDATA (voltage VSIGL, 0V) + threshold voltage VTH (1V) = 4V). That is, based on the data signal VDATA and the corrected threshold voltage, pixel 180B (pixel circuit 181B) can display an image. When the data signal VDATA includes voltage VSIGL, the potential difference Vgs is 4V and the second transistor T2 is ON, so current Ion flows from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, a pixel 180B that emits red light, a pixel 180B that emits blue light, and a pixel 180B that emits green light each emit light, and the three pixels using the red-emitting pixel 180B, blue-emitting pixel 180B, and green-emitting pixel 180B become white.

[0298] The second example of the driving method for the display device 30 produces the same effects as those described in "3-3-1. First Example of Driving Method for the Display Device 30".

[0299] [3-3-3. A third example of a method for driving the display device 30] Referring to Figure 34, a third example of the driving method for the display device 30 will be described. The driving method shown in the third example of the driving method for the display device 30 includes displaying images of the same color (black) in consecutive frames, similar to the third example of the driving method for the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 33 will be described as necessary.

[0300] The voltages (potentials) of each node during the KthFRAME period PVH to the KthFRAM light emission period PEM are the same as those described in "3-3-1. First Example of Driving Method for Display Device 30". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "3-3-1. First Example of Driving Method for Display Device 30". Therefore, configurations similar to those described in "3-3-1. First Example of Driving Method for Display Device 30" will be explained as needed.

[0301] During the PEM emission period of the K-1stFRAME, for example, the voltage supplied to the first node N1 is Vnd (-2V). Also, the voltage supplied to the second node N2 and the third node N3 (sixth node N6) is 0V, and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, no ions flow through the drain electrode Ion, and the light-emitting element OLED does not emit light.

[0302] As a result, the red-emitting pixel 180B (pixel circuit 181B) becomes black. Similarly, the blue-emitting pixel 180B and the green-emitting pixel 180B also do not emit light, so the three pixels using the red-emitting pixel 180B, the blue-emitting pixel 180B, and the green-emitting pixel 180B all become black.

[0303] During the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, following the light emission period PEM of the K-1stFRAME, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, and the voltage supplied to the first node N1 rises from voltage Vnd (-2V) towards voltage Vnq (reference voltage VREF, 2V) to become voltage Vnq. The second node N2 and the fourth node N4 become conductive, and the voltages supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2) rise from 0V towards voltage VSH (6V, voltage Vnr) to become voltage Vnr. Furthermore, the voltage supplied to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1) begins to rise from voltage Vnd (-2V). However, since the fourth transistor T4 is in the off state, current does not continue to flow, and the voltage supplied to the third node N3 (the first electrode 624 of the second transistor T2) and the sixth node N6 (the second electrode 616 of the first transistor T1) remains at around voltage Vnp (3V), and the operation of the display device 30 transitions from period PIN to period PVH.

[0304] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized with the drive voltage VDDEL, and the first node N1 is initialized with the reference voltage VREF.

[0305] In the period PVH following period PIN, similar to the configuration described in "3-3-1. First Example of Driving Method of Display Device 30," the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0306] In the PWR period following the PVH period, the data signal VDATA is written to the pixel 180B (pixel circuit 181B), similar to the configuration described in "3-3-1. First Example of Driving Method of Display Device 30". In addition, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0307] During the period following the PWR period, and during the PEM period of the KthFRAME that follows the PWR period, the pixel circuit 181B operates in the same manner as described in "3-3-1. First Example of Driving Method of Display Device 30," where the potential difference Vgs is 0V and the second transistor T2 is in the off state, so no ion flows through the drain electrode Ion, and the light-emitting element OLED does not emit light. As a result, the three pixels using the red-emitting pixel 180B, the blue-emitting pixel 180B, and the green-emitting pixel 180B appear black.

[0308] The third example of the driving method for the display device 10 produces the same effects as those described in "3-3-1. First example of the driving method for the display device 30".

[0309] [3-3-4. A fourth example of a method for driving the display device 30] Referring to Figure 35, a fourth example of a method for driving the display device 30 will be described. The driving method shown in the fourth example of a method for driving the display device 30 includes displaying images of different colors in consecutive frames, similar to the fourth example of a method for driving the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 34 will be described as necessary.

[0310] The voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor during the light emission period PEM of K-1stFRAME to the light emission period PVH of KthFRAME are the same as those described in "3-3-3. Third Example of Driving Method of Display Device 30". Furthermore, the voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor during the period after the light emission period PVH of KthFRAME to the light emission period PEM of KthFRAME are the same as those described in "3-3-2. Second Example of Driving Method of Display Device 30". Therefore, further explanation is omitted here.

[0311] The fourth example of the driving method for the display device 30 produces the same effects as those described in "3-3-1. First Example of Driving Method for the Display Device 30".

[0312] [4. Fourth Embodiment] The overview of the display device according to the fourth embodiment will be described with reference to Figures 4, 29, and 36 to 41. Figure 36 is a schematic diagram showing the input signals to the pixel 180C (pixel circuit 181C) according to the fourth embodiment, Figure 37 is a circuit diagram showing the configuration of the pixel circuit 181C, and Figures 38 to 41 are timing charts of the display device 30.

[0313] The display device according to the fourth embodiment includes a configuration similar to that of the display device 30 according to the third embodiment shown in Figure 29. The display device according to the fourth embodiment includes a pixel 180C (pixel circuit 181C). Specifically, the display device according to the fourth embodiment includes the configurations shown in (16) to (21) below. The configurations shown in (16) to (21) mainly differ from the configuration of the display device 30 according to the third embodiment. (16) The display device 30 according to the third embodiment has a configuration and function in which the pixel 180B (pixel circuit 181B) is replaced by a pixel 180C (pixel circuit 181C), and the configuration and function related to the pixel 180C (pixel circuit 181C) are different from the configuration and function related to the pixel 180B (pixel circuit 181B). (17) The electrical connection between the control circuit 120 and the pixel 180C (pixel circuit 181C) is different from the electrical connection between the control circuit 120B and the pixel 180B (pixel circuit 181B). (18) The gate electrode 692 of the ninth transistor T9 is electrically connected to the scan signal line 330, and the first scan signal SC1(n) supplied to the scan signal line 330 is supplied to the gate electrode 692 of the ninth transistor T9. Furthermore, the falling and rising timings of the first scan signal SC1(n) are different from the falling and rising timings of the first scan signal SC1(n) in the third embodiment. (19) The gate electrode 642 of the fourth transistor T4 is electrically connected to the scan signal line 335, and the sixth scan signal SC6(n) supplied to the scan signal line 335 is supplied to the gate electrode 642 of the fourth transistor T4. Therefore, the display device according to the fourth embodiment does not include the scan signal line 336 and the seventh scan signal SC7(n) supplied to the scan signal line 336 according to the third embodiment. (20) A reset voltage VRES and a reset voltage power line SVRE to which the reset voltage VRES is supplied are added. The reset voltage power line SVRE is electrically connected to the second electrode 696 of the ninth transistor T9. Thus, the display device according to the fourth embodiment does not include the constant voltage VSH and the constant voltage power line SVS to which the constant voltage VSH is supplied according to the third embodiment. (21) The electrical connections between the first transistor T1, the capacitive element CV and the capacitive element CD and each transistor at each node are different from the electrical connections between the first transistor T1, the capacitive element CV and the capacitive element CD and each transistor at each node in pixel 180B (pixel circuit 181B).

[0314] Configurations in the display device according to the fourth embodiment other than those shown in (16) to (21), and configurations in the display device according to the fourth embodiment other than those related to those shown in (16) to (21), are the same as those of the display device 30 according to the third embodiment. When describing the configuration and functions of the display device according to the fourth embodiment, configurations and functions similar to those of the display device 30 according to the third embodiment will be described as necessary.

[0315] [4-1. Pixel 180C Configuration] Referring to Figures 29, 36, and 37, the outlines of pixel 180C and pixel circuit 181C will be described.

[0316] The pixel circuit 181C is connected to the reset voltage power line SVRE. The pixel circuit 181C is not connected to the scan signal line 336 or the constant voltage power supply SVS.

[0317] The reset voltage VRES is supplied to the reset voltage power line SVRE. For example, the reset voltage power line SVRE is electrically connected to a connection wiring 342 that is different from the initialization voltage power line SVI, the reference voltage power line SVR, the drive power line PVDD, and the reference voltage line PVSS among the connection wiring 342. Alternatively, the reset voltage power line SVRE may be one of the connection wiring 342. For example, the reset voltage VRES may be supplied from an external device to the IC chip 110, and from the IC chip 110 to a plurality of pixels 180C (pixel circuits 181C) via the connection wiring 342 and the reset voltage power line SVRE. Although not shown in the figures, the reset voltage VRES may be connected from an external device to the reset voltage power line SVRE via the FPC 200, terminal section 150, and connection wiring 341, without going through the IC chip 110 and connection wiring 342, and supplied to a plurality of pixels 180C (pixel circuits 181C).

[0318] For example, the first transistor T1 is a selection transistor. The first transistor T1 has the function of supplying an image data signal SL(m) to the second node N2. The first transistor T1 also includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, the first electrode 634 of the third transistor T3, and the second electrode 54 of the capacitive element CD. A fourth scan signal SC4(n) is supplied to the scan signal line 333. The switching of the first transistor T1 is controlled using the fourth scan signal SC4(n). In other words, the first transistor T1 is controlled by the fourth scan signal SC4(n) to be either conducting (on) or not conducting (off). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 is in a non-conducting state. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 is in a conducting state.

[0319] The gate electrode 642 of the fourth transistor T4 is electrically connected to the scan signal line 335. As described above, the sixth scan signal SC6(n) is supplied to the scan signal line 335. The switching of the fourth transistor T4 is controlled using the sixth scan signal SC6(n). In other words, the fourth transistor T4 is controlled to be either conducting (on) or not conducting (off) by the sixth scan signal SC6(n). When the signal supplied to the sixth scan signal SC6(n) is LO, the fourth transistor T4 is in a non-conducting state, and when the signal supplied to the sixth scan signal SC6(n) is HI, the fourth transistor T4 is in a conducting state.

[0320] The ninth transistor T9 has the function of supplying a reset voltage VRES to the fourth node N4 by conducting the fourth node N4 and the reset voltage power line SVRE. The ninth transistor T9 includes a gate electrode 692, a first electrode 694, and a second electrode 696. The gate electrode 692 is electrically connected to the scan signal line 330. The first electrode 694 is electrically connected to the fourth node N4, the first electrode 654 of the fifth transistor T5, the second electrode 636 of the third transistor T3, and the second electrode 626 of the second transistor T2. The second electrode 696 is electrically connected to the reset voltage power line SVRE. As described above, the first scan signal SC1(n) is supplied to the scan signal line 330. The switching of the ninth transistor T9 is controlled using the first scan signal SC1(n). In other words, the ninth transistor T9 is controlled by the first scan signal SC1(n) to be either conducting (on) or not conducting (off). When the signal supplied to the first scan signal SC1(n) is LO, the ninth transistor T9 is in a non-conducting state, and when the signal supplied to the first scan signal SC1(n) is HI, the ninth transistor T9 is in a conducting state.

[0321] The capacitive element CV has the function of holding (storing) a charge corresponding to the threshold voltage VTH of the second transistor T2. The sixth node N6 of the pixel circuit 181C is connected to the third node N3, and in the display device according to the fourth embodiment, the threshold voltage VTH is obtained from the first electrode 624 (source electrode) side of the second transistor T2. The capacitive element CV includes a first electrode 42 and a second electrode 44. The first electrode 42 is electrically connected to the third node N3 (sixth node N6), the first electrode 624 of the second transistor T2, the second electrode 646 of the fourth transistor T4, and the second electrode 676 of the seventh transistor T7. The second electrode 44 is electrically connected to the first node N1, the second electrode 666 of the sixth transistor T6, and the first electrode 52 of the capacitive element CD.

[0322] The capacitive element CD has the function of holding (storing) a charge corresponding to the data voltage (voltage between voltage VSIGL (see Figure 38) and voltage VSIGH (see Figure 38)) contained in the image data signal SL(m) supplied to the second node N2. The capacitive element CD includes a first electrode 52 and a second electrode 54.

[0323] The configuration and functions of pixel circuit 181C, other than those described in "4-1. Configuration of Pixel 180C," are the same as those of pixel circuit 181B.

[0324] [4-2. Driving method for the display device according to the fourth embodiment] Referring to Figures 38 to 41, the driving method of the display device (pixel circuit 181C) according to the fourth embodiment will be described. Configurations identical or similar to those in Figures 1 to 37 will be described as necessary. The horizontal axis of the timing chart is time.

[0325] The driving method for the display device according to the fourth embodiment includes the same period as the driving method for the display device 10 according to the first embodiment shown in Figure 4.

[0326] In the driving method of the display device according to the fourth embodiment, during one horizontal period (horizontal period HRP), the pixel 180C (pixel circuit 181C) is input an image data signal SL(m) which includes a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a sixth scan signal SC6(n), and a data signal VDATA. For example, the pixel 180C (pixel circuit 181C) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the sixth scan signal SC6(n). The image data signal SL(m) is input to the selected pixel 180C (pixel circuit 181C) according to the timing of each signal. The same operation is performed for all pixels 180C (pixel circuits 181C), and based on the image data signal SL(m) input to all pixels 180C (pixel circuits 181C), the image of the current frame corresponding to 1 FRAME is displayed in the display area 22 of the display device 10.

[0327] For example, the voltages (potentials) supplied to each signal and each node in each frame of the timing chart shown in Figures 38 to 41 are shown in Table 3.

[0328] [Table 3]

[0329] For example, as shown in Table 3, the voltage VSIGH is 4V, the voltage VSIGL is 0V, the initialization voltage VINI is -2V, the reference voltage VREF is 2.2V, and the reset voltage VRES is 1V. That is, the reset voltage VRES, the reference voltage VREF, and the initialization voltage VINI are different from each other, and the reset voltage VRES and the reference voltage VREF are greater than the reference voltage VSSEL and less than the drive voltage VDDEL. The initialization voltage VINI is less than the reference voltage VSSEL and the drive voltage VDDEL. The setting values ​​for the other voltages are the same as the setting values ​​shown in Table 1, which is explained in "1-5. Driving Method of Display Device 10".

[0330] [4-2-1. First example of a driving method for a display device according to the fourth embodiment] Referring to Figure 38 and Table 3, a first example of a driving method for the display device according to the fourth embodiment will be described. The first example of a driving method for the display device according to the fourth embodiment includes displaying images of different colors in consecutive frames, similar to the first example of a driving method for the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 37 will be described as necessary.

[0331] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m) including a data signal VDATA is input to each pixel 180C (pixel circuit 181C) according to each period. The data signal VDATA is analog data including a voltage between VSIGL and VSIGH. For example, in the period PWR, a voltage between VSIGL and VSIGH is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, in periods other than the period PWR, the data signal VDATA is supplied to a voltage other than the selected pixel 180C (pixel circuit 181C).

[0332] The PEM (Pigment Emission Mechanism) of the K-1stFRAME is the period during which pixel 180C (pixel circuit 181C) emits light in accordance with the potential difference Vgs of the second transistor T2 (voltage supplied to the second node N2 (voltage V(N2)) - voltage supplied to the third node N3 (voltage V(N3))). For example, pixel 180C (pixel circuit 181C) emits red light, and three pixels using a red-emitting pixel 180C, a blue-emitting pixel 180C, and a green-emitting pixel 180C emit white light.

[0333] For example, during the emission period PEM of the K-1stFRAME, the image data signal SL(m) (data signal VDATA) is supplied to all pixels except the selected pixel 180C (pixel circuit 181C) at the voltage of the data signal VDATA. The first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the sixth scan signal SC6(n) are supplied with LO, and the second scan signal SC2(n) is supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are in the off state, while the fifth transistor T5 and the seventh transistor T7 are in the on state. Also, for example, the voltage supplied to the third node N3 is 0V, the voltage supplied to the second node N2 is voltage Vnl (e.g., 4V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is ON, and a current Ion based on the potential difference Vgs and potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the K-1stFRAME can be supplied from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. The voltage supplied to the first node N1 is Vnu (2.2V, reference voltage VREF) due to capacitive coupling by the capacitive elements CV and CD. For example, pixel 180C (pixel circuit 181C) emits red light, and three pixels using a red-emitting pixel 180C, a blue-emitting pixel 180C, and a green-emitting pixel 180C emit white light.

[0334] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to all pixels except the selected pixel 180 (pixel circuit 181). Initially, the second scan signal SC2(n) changes from a HI state to a LO state. When the second scan signal SC2(n) is supplied with LO, the third scan signal SC3(n) changes from a LO state to a HI state. When the third scan signal SC3(n) is supplied with HI, the sixth scan signal SC6(n) changes from a LO state to a HI state. The first scan signal SC1(n) and the fourth scan signal SC4(n) are supplied with LO.

[0335] As a result, during the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, the fifth transistor T5 and the seventh transistor T7 turn from the ON state to the OFF state, and the current Ion stops flowing from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS. The eighth transistor T8 turns from the OFF state to the ON state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V, and the light emission of the light-emitting element OLED stops. The sixth transistor T6 turns from the OFF state to the ON state, and the first node N1 is supplied with a reference voltage VREF (2.2V, voltage Vnu) and maintains the voltage Vnu. The fourth transistor T4 turns from the OFF state to the ON state, and the third node N3 (sixth node N6) is supplied with an initialization voltage VINI (-2V, voltage Vnd) and becomes voltage Vnd. The first transistor T1, the third transistor T3, the fifth transistor T5, and the ninth transistor T9 remain in the off state. The voltage supplied to the second node N2 (gate electrode 622 of the second transistor T2) remains at voltage Vnl (e.g., 4V). Once the potential difference Vgs becomes 6V (4V - (-2V)), the second transistor T2 is in the on state, but no current continues to flow because the fifth transistor T5 is in the off state. Therefore, the voltage supplied to the fourth node N4 becomes voltage Vnd (-2V).

[0336] As described above, during the period PIN, the third node N3 (sixth node N6) and the fourth node N4 are initialized with the initialization voltage VINI, and the first node N1 is initialized with the reference voltage VREF.

[0337] During period PVH, following period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to all pixels except the selected pixel 180C (pixel circuit 181C). The sixth scan signal SC6(n) changes from a HI state to a LO state. When the sixth scan signal SC6(n) is supplied with LO, the first scan signal SC1(n) changes from a LO state to a HI state. The other scan signals remain in the same state as during period PIN. The third transistor T3 and the ninth transistor T9 change from the off state to the on state, the fourth transistor T4 changes from the on state to the off state, and the other transistors remain in the same state as during period PIN.

[0338] As a result, during period PVH, the third transistor T3 and the ninth transistor T9 are ON, the second node N2 and the fourth node N4 conduct to the reset voltage power line SVRE, the second node N2 and the fourth node N4 are supplied with the reset voltage VRES (1V, voltage Vno), and the voltage becomes Vno. The first node N1 maintains the voltage Vnq. Also, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are OFF, the second transistor T2 is ON and electrode Ion flows, and the fourth transistor T4 turns OFF, which opens the third node N3, current Ion flows to the third node N3 (sixth node N6), the third node N3 (sixth node N6) is charged, and the potential of the third node N3 (sixth node N6) rises. When the potential difference Vgs between the voltages supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) reaches the threshold voltage VTH, the second transistor T2 turns off. At this time, the second node N2 and the fourth node N4 are supplied with a reset voltage VRES (1V, voltage Vno), so the voltage supplied to the third node N3 (sixth node N6) when the potential difference Vgs is the threshold voltage VTH is 0V. That is, the potential of the third node N3 is reset voltage VRES (1V, voltage Vno) - threshold voltage VTH. The threshold voltage VTH varies during manufacturing; for example, if the threshold voltage VTH is 1.1V, the potential of the third node N3 will be -0.1V, and the threshold voltage VTH is corrected by the operation during period PVH.

[0339] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and at the same time, a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0340] During the period between period PVH and period PWR, or during period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). Initially, the first scan signal SC1(n) changes from a HI state to a LO state. When the first scan signal SC1(n) is supplied with LO, the fourth scan signal SC4(n) changes from a LO state to a HI state. The third scan signal SC3(n) is supplied with HI, and the second scan signal SC2(n) and the sixth scan signal SC6(n) are supplied with LO. The first transistor T1 changes from an off state to an on state, and the third transistor T3 and the ninth transistor T9 change from an on state to an off state. The other transistors remain in the same state as during period PVH. The voltage supplied to the second node N2 decreases from voltage Vno to voltage VSIGL(0V) upon application of the image data signal SL(m) (data signal VDATA) voltage VSIGL(0V), becoming 0V. The voltage supplied to the first node N1 remains at voltage Vnu (reference voltage VREF, 2.2V), and the voltage supplied to the third node N3 (sixth node N6) remains at 0V. At this time, the capacitive element CD maintains the potential difference (-2.2V relative to the first node N1) by holding a charge equivalent to the potential difference between Vnu (reference voltage VREF, 2.2V) supplied to the first node N1 and 0V supplied to the second node N2. The capacitive element CV also maintains the potential difference (2.2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between Vnu (reference voltage VREF, 2.2V) supplied to the first node N1 and 0V supplied to the third node N3 (sixth node N6). The sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (-2.2V + 2.2V) is 0V, and since BR > A, the potential difference Vgs is 0V, and the second transistor T2 is in the off state.

[0341] As described above, during the PWR period, the data signal VDATA is written to pixel 180C (pixel circuit 181C). Furthermore, the capacitive element CD maintains (holds) the voltage contained in the data signal VDATA.

[0342] In the period following the PWR period, the fourth scan signal SC4(n) changes from a HI state to a LO state. When the fourth scan signal SC4(n) is supplied with LO, the third scan signal SC3(n) changes from a HI state to a LO state. The first transistor T1, the sixth transistor T6, and the eighth transistor T8 change from the ON state to the OFF state. Other scan signals and other transistors remain in the same state as during the PWR period. The voltage supplied to the first node N1 remains at voltage Vnu (reference voltage VREF, 2.2V), and the voltages supplied to the second node N2 and the third node N3 (sixth node N6) remain at 0V. The combined potential difference between capacitive elements CD and CV (the potential difference between the second node N2 and the third node N3) remains at 0V. That is, the potential difference Vgs is 0V, and the second transistor T2 is in the OFF state.

[0343] In the KthFRAME emission period PEM that follows the KthFRAME period PWR, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to all pixels except the selected pixel 180C (pixel circuit 181C). Also, the second scan signal SC2(n) changes from a state where LO is supplied to a state where HI is supplied. Therefore, the fifth transistor T5 and the seventh transistor T7 turn from the off state to the on state. Other scan signals and other transistors remain in the same state as in the KthFRAME period PWR. With the fifth transistor T5 and the seventh transistor T7 turned on, the first electrode 32 of the light-emitting element OLED conducts with the second electrode 626 of the second transistor T2 (fourth node N4). When the seventh transistor T7 is turned on, the third node N3 (sixth node N6) is connected to the reference voltage VSSEL, and the voltage supplied to the third node N3 (sixth node N6) becomes 0V. At the same time, the second node N2 maintains 0V through the capacitive coupling of capacitive elements CD and CV. The first node N1 also maintains 2.2V through the capacitive coupling of capacitive elements CD and CV. For example, if the threshold voltage TVH is 1V (set value) due to manufacturing variations, the voltage supplied to the third node N3 (sixth node N6) remains 0V and does not change even when the seventh transistor T7 is turned on. If the threshold voltage TVH is 1.1V due to manufacturing variations, the voltage supplied to the third node N3 (sixth node N6) becomes -0.1V, and when the seventh transistor T7 is turned on, the voltage supplied to the third node N3 (sixth node N6) changes from -0.1V to 0V. The potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (voltage of data signal VDATA (voltage VSIGL, 0V) - reset voltage VRES (1V) + threshold voltage VTH (1V) = 0V). Pixel 180C (pixel circuit 181C) where the data signal VDATA contains voltage VSIGL has a potential difference Vgs of 0V, and the second transistor T2 is in the off state, so electrode Ion does not flow. Therefore, the light-emitting element OLED does not emit light. As a result, pixel 180C (pixel circuit 181C) that emits red light becomes black.Furthermore, just like the red-emitting pixel 180C, the blue-emitting pixel 180C and the green-emitting pixel 180C also do not emit light. Therefore, the three pixels using the red-emitting pixel 180C, the blue-emitting pixel 180C, and the green-emitting pixel 180C will appear black.

[0344] In the display device according to the fourth embodiment, the reference voltage VSSEL is 0V, and the display device according to the fourth embodiment includes a configuration in which a reset voltage VRES is supplied to the second node N2 and the fourth node N4. With the reset voltage VRES as a reference, the threshold voltage VTH information (data) is applied to the low potential side of the potential difference Vgs of the second transistor T2, the voltage (data) of the data signal VDATA is applied to the high potential side of the potential difference Vgs of the second transistor T2, and the light-emitting element OLED is placed on the drain side (drive voltage VDDEL side) opposite to the potential difference Vgs side of the second transistor T2, thereby minimizing voltage fluctuations (potential fluctuations) at the first node N1, the second node N2 and the third node N3 (sixth node N6) from the PWR period to the PEM period. Therefore, the display device according to the fourth embodiment can suppress power consumption from the period PWR to the light emission period PEM, and the charge redistribution caused by the gate capacitance of the second transistor T2 due to the potential fluctuation of the second node N2 is reduced, thereby minimizing the voltage loss that occurs when the writing voltage drops during light emission.

[0345] [4-2-2. A second example of a driving method for a display device according to the fourth embodiment] Referring to Figure 39, a second example of the driving method for the display device according to the fourth embodiment will be described. The driving method shown in the second example of the display device according to the fourth embodiment includes displaying images of the same color (white) in consecutive frames, similar to the second example of the driving method for the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 38 will be described as necessary.

[0346] The voltages (potentials) of each node during the light emission period PEM of the K-1thFRAME to the period PVH of the KthFRAME, and during the period between the KthFRAME's period PVH and the KthFRAME's period PWR, are the same as those described in "4-2-1. First Example of a Driving Method for a Display Device According to the Fourth Embodiment." Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "4-2-1. First Example of a Driving Method for a Display Device According to the Fourth Embodiment." Therefore, configurations similar to those described in "4-2-1. First Example of a Driving Method for a Display Device According to the Fourth Embodiment" will be explained as needed. Note that during the KthFRAME's period PWR, the image data signal SL(m) is supplied with a data signal VDATA including VSIGH (4V) corresponding to white, and during periods other than the KthFRAME's period PWR, the same data signal VDATA as described in "4-2-1. First Example of a Driving Method for a Display Device According to the Fourth Embodiment" is supplied.

[0347] In the light emission period PEM of the K-1stFRAME, similar to the configuration described in "4-2-1. First Example of a Driving Method for a Display Device According to the Fourth Embodiment," pixel 180C (pixel circuit 181C) emits red light, and three pixels using a red-emitting pixel 180C, a blue-emitting pixel 180C, and a green-emitting pixel 180C emit white light.

[0348] In the KthFRAME period PIN, the third node N3 (sixth node N6) is initialized with initialization voltage VINI, and the first node N1 is initialized with reference voltage VREF, similar to the configuration described in "4-2-1. First Example of Display Device According to the Fourth Embodiment".

[0349] During the period PVH following the period PIN, the threshold voltage VTH of the second transistor T2 is obtained by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, similar to the configuration described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment," and at the same time, a charge corresponding to the threshold voltage VTH is held in the capacitive element CV.

[0350] During the period between period PVH and period PWR, or during period PWR, the image data signal SL(m) (data signal VDATA) is supplied with voltage VSIGH (4V). The voltage supplied to the second node N2 increases from voltage Vno to voltage VSIGH (e.g., 4V, voltage Vnl) and becomes voltage Vnl, the voltage supplied to the first node N1 remains at voltage Vnu (reference voltage VREF, 2.2V), and the voltage supplied to the third node N3 (sixth node N6) remains at 0V. At this time, the capacitive element CD maintains the potential difference (1.8V relative to the first node N1) by holding a charge equivalent to the potential difference between the voltage Vnu (reference voltage VREF, 2.2V) supplied to the first node N1 and the voltage Vnl (e.g., 4V, voltage VSIGH) supplied to the second node N2. Furthermore, the capacitive element CV maintains the potential difference (2.2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between the voltage Vnu (reference voltage VREF, 2.2V) supplied to the first node N1 and the 0V supplied to the third node N3 (sixth node N6). In other words, the potential difference Vgs is 4V.

[0351] As described above, during the PWR period, the data signal VDATA is written to pixel 180C (pixel circuit 181C). Furthermore, the capacitive element CD maintains (holds) the voltage contained in the data signal VDATA.

[0352] In the period following the PWR period, the voltage supplied to the first node N1 remains at voltage Vnu (reference voltage VREF, 2.2V), the voltage supplied to the second node N2 remains at voltage Vnl (e.g., 4V), and the voltage supplied to the third node N3 (sixth node N6) remains at 0V. Also, similar to the PWR period, in the period following the PWR period, the capacitive element CD maintains a potential difference (1.8V relative to the first node N1) by holding a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the third node N3 (sixth node N6), and the capacitive element CV maintains a potential difference (2.2V relative to the sixth node N6) by holding a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the third node N3 (sixth node N6). That is, the potential difference Vgs is 4V.

[0353] In the KthFRAME emission period PEM that follows the KthFRAME period PWR, the potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (voltage of data signal VDATA (voltage VSIGH, 4V) - reset voltage VRES (1V) + threshold voltage VTH (1V) = 4V). For pixel 180C (pixel circuit 181C) where the data signal VDATA contains voltage VSIGH, the potential difference Vgs is 4V and the second transistor T2 is ON, so current Ion flows from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, the red-emitting pixel 180C, the blue-emitting pixel 180C, and the green-emitting pixel 180C each emit light, and the three pixels using the red-emitting pixel 180C, the blue-emitting pixel 180C, and the green-emitting pixel 180C will appear white.

[0354] A second example of the display device according to the fourth embodiment provides the same effects and advantages as described in "4-2-1. First Example of the Display Device According to the Fourth Embodiment".

[0355] [4-2-3. A third example of a display device according to the fourth embodiment] Referring to Figure 40, a third example of the display device according to the fourth embodiment will be described. The driving method shown in the third example of the display device according to the fourth embodiment includes displaying images of the same color (black) in consecutive frames, similar to the third example of the driving method for the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 39 will be described as necessary.

[0356] The voltage (potential) of each node during the KthFRAME period PVH to the KthFRAM light emission period PEM is the same as the configuration described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as the configuration described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment". Therefore, configurations similar to those described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment" will be explained as needed.

[0357] During the PEM emission period of the K-1stFRAME, the voltage supplied to the first node N1 is voltage Vnu (reference voltage VREF, 2.2V). The voltage supplied to the second node N2 and the third node N3 (sixth node N6) is 0V, and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, electrode Ion does not flow, and the light-emitting element OLED does not emit light.

[0358] As a result, the red-emitting pixel 180C (pixel circuit 181C) becomes black. Similarly, the blue-emitting pixel 180C and the green-emitting pixel 180C also do not emit light, so the three pixels using the red-emitting pixel 180C, the blue-emitting pixel 180C, and the green-emitting pixel 180C all become black.

[0359] During the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, or during the period PIN of the KthFRAME, following the light emission period PEM of the K-1stFRAME, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0V. The first node N1 is supplied with a reference voltage VREF (2.2V, voltage Vnu) and maintains voltage Vnu. The third node N3 (sixth node N6) is supplied with an initialization voltage VINI (-2V, voltage Vnd), and the voltage supplied to the third node N3 (sixth node N6) becomes voltage Vnd. The voltage supplied to the second node N2 (gate electrode 622 of the second transistor T2) remains 0V. Once the potential difference Vgs becomes 2V (0V - (-2V)), the second transistor T2 is in the ON state, and the voltage supplied to the fourth node N4 becomes voltage Vnd (-2V).

[0360] As described above, during the period PIN, the third node N3 (sixth node N6) and the fourth node N4 are initialized with the initialization voltage VINI, and the first node N1 is initialized with the reference voltage VREF.

[0361] During period PVH, following period PIN, the second node N2 and the fourth node N4 are supplied with a reset voltage VRES (1V, voltage Vno), and the voltage supplied to the second node N2 and the fourth node N4 becomes voltage Vno. The first node N1 maintains voltage Vnq. Also, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in the off state, the second transistor T2 is in the on state and electrode Ion flows, and the fourth transistor T4 turns off, which opens the third node N3, allowing current Ion to flow to the third node N3 (sixth node N6), charging the third node N3 (sixth node N6), and raising the potential of the third node N3 (sixth node N6). When the potential difference Vgs between the voltages supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 (sixth node N6) reaches the threshold voltage VTH, the second transistor T2 turns off. At this time, the second node N2 and the fourth node N4 are supplied with a reset voltage VRES (1V, voltage Vno), so the voltage supplied to the third node N3 (sixth node N6) when the potential difference Vgs reaches the threshold voltage VTH is 0V.

[0362] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, similar to the configuration described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment," and a charge corresponding to the threshold voltage VTH is held in the capacitive element CV.

[0363] In the PWR period following the PVH period, the data signal VDATA is written to the pixel 180C (pixel circuit 181C), similar to the configuration described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment". The capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0364] During the period following the PWR period, and during the PEM period of the KthFRAME that follows the PWR period, the pixel circuit 181C operates in the same manner as described in "4-2-1. First Example of a Display Device According to the Fourth Embodiment," where the potential difference Vgs is 0V and the second transistor T2 is in the off state, so no ions flow through the drain electrode Ion, and the light-emitting element OLED does not emit light. As a result, the three pixels, using the red-emitting pixel 180C, the blue-emitting pixel 180C, and the green-emitting pixel 180C, appear black.

[0365] A third example of the display device according to the fourth embodiment provides the same effects and advantages as described in "4-2-1. First Example of the Display Device According to the Fourth Embodiment".

[0366] [4-2-4. A fourth example of a display device according to the fourth embodiment] Referring to Figure 41, a fourth example of the display device according to the fourth embodiment will be described. The driving method shown in the fourth example of the display device according to the fourth embodiment includes displaying images of different colors in consecutive frames, similar to the fourth example of the driving method for the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 40 will be described as necessary.

[0367] The voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor during the light emission period PEM of K-1stFRAME to the light emission period PVH of KthFRAME are the same as those described in "4-2-3. Third Example of Display Device According to the Fourth Embodiment". Furthermore, the voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor during the period after the light emission period PVH of KthFRAME to the light emission period PEM of KthFRAME are the same as those described in "4-2-2. Second Example of Display Device According to the Fourth Embodiment". Therefore, further explanation is omitted here.

[0368] A fourth example of the display device according to the fourth embodiment provides the same effects and advantages as described in "4-2-1. First Example of the Display Device According to the Fourth Embodiment".

[0369] As embodiments of the present invention, each embodiment or part of each embodiment described above can be combined and implemented as appropriate, insofar as they do not contradict each other.

[0370] Any effects or benefits different from those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0371] 10: Display device, 20: Display device, 22: Display area, 24: Peripheral area, 26: Terminal area, 30: Display device, 32: First electrode, 34: Second electrode, 42: First electrode, 44: Second electrode, 52: First electrode, 54: Second electrode, 100: Array substrate, 101: Substrate, 101A: First surface, 101B: Second surface, 110: IC chip, 111: Shift register, 112: Shift register, 120: Control circuit, 120A: Control circuit, 120B: Control circuit, 121: Underlayer, 122: Semiconductor layer, 122A: Semiconductor layer, 122B: Semiconductor layer, 122C: Semiconductor layer , 122D: Semiconductor layer, 122E: Semiconductor layer, 122F: Semiconductor layer, 123: Channel region, 124A: Impurity region, 125: Gate insulating layer, 126: Conductive layer, 127A: Gate wiring, 127B: Gate wiring, 127C: Gate wiring, 127D: Gate wiring, 127E: Gate wiring, 127F: Gate wiring, 127G: Gate wiring, 128: Insulating layer, 130: Shift register circuit, 130A: Shift register circuit, 130B: Shift register circuit, 131: Insulating layer, 132: Conductive layer, 132A: First wiring, 132B: First wiring, 132C: First wiring Wire, 132D: First wiring, 132E: First wiring, 132F: First wiring, 132G: First wiring, 132H: First wiring, 132I: First wiring, 132J: First wiring, 132K: First wiring, 132L: First wiring, 135A: First contact hole opening, 135B: First contact hole opening, 135C: First contact hole opening, 135D: First contact hole opening, 135E: First contact hole opening, 135F: First contact hole opening, 135G: First contact hole opening, 135H: First Contact hole opening, 135I: First contact hole opening, 135J: First contact hole opening, 135K: First contact hole opening, 135L: First contact hole opening, 135M: First contact hole opening, 135N: First contact hole opening, 135O: First contact hole opening, 135P: First contact hole opening, 136: Insulating layer, 138: Second contact hole opening, 138A: Organic insulating film opening, 138B: Organic insulating film opening, 138C: Second contact hole opening,138D: Second contact hole opening, 138E: Second contact hole opening, 138F: Second contact hole opening, 138G: Second contact hole opening, 138H: Second contact hole opening, 138I: Second contact hole opening, 139: Conductive layer, 140A: Second wiring, 140B: Second wiring, 140C: Second wiring, 140D: Second wiring, 140E: Second wiring, 141: Insulating layer, 143: Cathode electrode, 144: First layer, 145: Second layer, 146: Third Layer, 147: Contact hole opening, 147A: Contact hole opening, 148: Functional layer, 149: Common electrode, 150: Terminal section, 152: First inorganic insulating layer, 154: Organic insulating layer, 156: Second inorganic insulating layer, 158: Cover film, 160: Scan driver circuit, 160A: Scan driver, 160B: Scan driver circuit, 165: Sealing film, 170: Array section, 180: Pixel, 180A: Pixel, 180B: Pixel, 180C: Pixel, 181: Pixel circuit, 181A: Pixel circuit, 181B: Pixel Circuit, 181C: Pixel circuit, 200: Flexible printed circuit board, 321: Image data signal line, 322: Image data signal line, 323: Image data signal line, 330: Scan signal line, 331: Scan signal line, 332: Scan signal line, 333: Scan signal line, 334: Scan signal line, 335: Scan signal line, 336: Scan signal line, 341: Connection wiring, 342: Connection wiring, 612: Gate electrode, 614: First electrode, 616: Second electrode, 622: Gate electrode, 622-: Gate electrode, 624 : First electrode, 626: Second electrode, 632: Gate electrode, 634: First electrode, 636: Second electrode, 642: Gate electrode, 644: First electrode, 646: Second electrode, 652: Gate electrode, 654: First electrode, 656: Second electrode, 662: Gate electrode, 664: First electrode, 666: Second electrode, 672: Gate electrode, 674: First electrode, 676: Second electrode, 682: Gate electrode, 684: First electrode, 686: Second electrode, 692: Gate electrode, 694: First electrode, 696: Second electrode,

Claims

1. A display device in which multiple pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction, Each of the aforementioned plurality of pixels is A first control signal is used to control the switching, and a first transistor is electrically connected between the image data signal line to which the data voltage is supplied and the sixth node, A second transistor has a gate electrode electrically connected to the second node, and is electrically connected between the third node and the fourth node, which are electrically connected to the sixth node, The switching is controlled using a second control signal, and a third transistor is electrically connected between the second node and the fourth node, A third control signal is used to control the switching, and a fourth transistor is electrically connected between the initialization voltage power line, which supplies the initialization voltage, and the third node. The switching is controlled using a fourth control signal, and a fifth transistor is electrically connected between the fourth node and the fifth node, The switching is controlled using a fifth control signal, and a sixth transistor is electrically connected between the reference voltage power line to which the reference voltage is supplied and the first node, The switching is controlled using a sixth control signal, and a seventh transistor is electrically connected between a reference voltage line to which a reference voltage is supplied and the third node, The switching is controlled using the fifth control signal, and an eighth transistor is electrically connected between the power line to which a constant voltage is supplied and the fifth node, A first capacitive element electrically connected between the first node and the second node, A second capacitive element electrically connected between the first node and the sixth node, A light-emitting element electrically connected between the power line and the fifth node, Display device.

2. The second control signal also serves as the third control signal. The display device according to claim 1.

3. The system further includes a control circuit that outputs the first control signal, the second control signal, the fourth control signal, the fifth control signal, and the sixth control signal. The control circuit is configured to be controllable to hold a potential difference in the first capacitive element that corresponds to the threshold voltage of the second transistor, and then to hold a potential difference in the second capacitive element that corresponds to the data voltage. The display device according to claim 2.

4. The switching is controlled using the sixth control signal, and the system further includes a ninth transistor electrically connected between the sixth node and the third node. The second control signal also serves as the third control signal and the fifth control signal. The display device according to claim 1.

5. The system further includes a control circuit that outputs the first control signal, the second control signal, the fourth control signal, and the sixth control signal. The control circuit is configured to control the simultaneous execution of holding a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor and holding a potential difference in the second capacitive element corresponding to the data voltage. The display device according to claim 4.

6. The control circuit is configured to be controllable to turn on the first transistor using the first control signal and supply the data voltage to the sixth node before the simultaneous execution. The display device according to claim 5.

7. The control circuit includes a shift register circuit and a scan driver circuit electrically connected to the shift register circuit. The scan driver circuit is configured to control the generation of a plurality of first control signals, a second control signal, a fourth control signal, and a sixth control signal, each with a different timing for each of the plurality of adjacent pixels in the second direction, in accordance with the output signal output by the shift register circuit. The display device according to claim 5.

8. The switching is controlled using a seventh control signal, and the system further includes a ninth transistor electrically connected between a control voltage power line, to which a control voltage different from the initialization voltage is supplied, and the fourth node. The fourth control signal also serves as the sixth control signal. The display device according to claim 1.

9. The system further includes a control circuit that outputs the first control signal, the second control signal, the third control signal, the fourth control signal, the fifth control signal, and the seventh control signal. The control circuit is configured to be controllable to hold a potential difference in the first capacitive element that corresponds to the threshold voltage of the second transistor, and then to hold a potential difference in the second capacitive element that corresponds to the data voltage. The display device according to claim 8.

10. The control circuit is configured to control the following before maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor: turning off the first transistor using the first control signal, turning off the fourth transistor using the third control signal, turning off the fifth and seventh transistors using the fourth control signal, turning on the sixth transistor using the fifth control signal and supplying the reference voltage to the first node, turning on the third transistor using the second control signal and turning on the ninth transistor using the seventh control signal and supplying the control voltage to the second and fourth nodes. The display device according to claim 9.

11. A display device in which multiple pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction, Each of the aforementioned plurality of pixels is A first transistor is electrically connected between a second node and an image data signal line to which a data voltage is supplied, and the switching is controlled using a first control signal, A second transistor having a gate electrode electrically connected to the second node and electrically connected between the third node and the fourth node, The switching is controlled using a second control signal, and a third transistor is electrically connected between the second node and the fourth node, A third control signal is used to control the switching, and a fourth transistor is electrically connected between the initialization voltage power line, which supplies the initialization voltage, and the third node. The switching is controlled using a fourth control signal, and a fifth transistor is electrically connected between the fourth node and the fifth node, The switching is controlled using a fifth control signal, and a sixth transistor is electrically connected between the reference voltage power line to which the reference voltage is supplied and the first node, The switching is controlled using the fourth control signal, and a seventh transistor is electrically connected between the reference voltage line to which the reference voltage is supplied and the third node, The switching is controlled using the fifth control signal, and an eighth transistor is electrically connected between the power line to which a constant voltage is supplied and the fifth node, The switching is controlled using the second control signal, and a ninth transistor is electrically connected between the reset voltage power line, which supplies the reset voltage, and the fourth node. A second capacitive element electrically connected between the first node and the second node, A first capacitive element electrically connected between the first node and the third node, A light-emitting element electrically connected between the power line and the fifth node, Display device.

12. The system further includes a control circuit that outputs the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal. The control circuit is configured to be controllable to hold a potential difference in the first capacitive element that corresponds to the threshold voltage of the second transistor, and then to hold a potential difference in the second capacitive element that corresponds to the data voltage. The display device according to claim 11.

13. The aforementioned reference voltage differs from the aforementioned initialization voltage, The aforementioned reference voltage and the aforementioned initialization voltage are greater than the aforementioned reference voltage and less than the aforementioned constant voltage. The display device according to claim 1 or claim 11.

14. The data voltage is an analog voltage that is greater than or equal to the first voltage and less than or equal to the second voltage which is greater than the first voltage. The reference voltage is the midpoint between the first voltage and the second voltage. The display device according to claim 1 or claim 11.

15. The capacitance value of the second capacitance element is greater than the capacitance value of the first capacitance element. The display device according to claim 1 or claim 11.

16. The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are n-channel field-effect transistors. The channel regions of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor each have an oxide semiconductor. The display device according to claim 1.

17. The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are n-channel field-effect transistors. The channel regions of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor each have an oxide semiconductor. The display device according to any one of claims 4, 8, and 11.

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